diff options
Diffstat (limited to 'arch/arm/kvm/interrupts.S')
-rw-r--r-- | arch/arm/kvm/interrupts.S | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S index 8ca87ab0919d..f7793df62f58 100644 --- a/arch/arm/kvm/interrupts.S +++ b/arch/arm/kvm/interrupts.S | |||
@@ -35,15 +35,18 @@ __kvm_hyp_code_start: | |||
35 | /******************************************************************** | 35 | /******************************************************************** |
36 | * Flush per-VMID TLBs | 36 | * Flush per-VMID TLBs |
37 | * | 37 | * |
38 | * void __kvm_tlb_flush_vmid(struct kvm *kvm); | 38 | * void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa); |
39 | * | 39 | * |
40 | * We rely on the hardware to broadcast the TLB invalidation to all CPUs | 40 | * We rely on the hardware to broadcast the TLB invalidation to all CPUs |
41 | * inside the inner-shareable domain (which is the case for all v7 | 41 | * inside the inner-shareable domain (which is the case for all v7 |
42 | * implementations). If we come across a non-IS SMP implementation, we'll | 42 | * implementations). If we come across a non-IS SMP implementation, we'll |
43 | * have to use an IPI based mechanism. Until then, we stick to the simple | 43 | * have to use an IPI based mechanism. Until then, we stick to the simple |
44 | * hardware assisted version. | 44 | * hardware assisted version. |
45 | * | ||
46 | * As v7 does not support flushing per IPA, just nuke the whole TLB | ||
47 | * instead, ignoring the ipa value. | ||
45 | */ | 48 | */ |
46 | ENTRY(__kvm_tlb_flush_vmid) | 49 | ENTRY(__kvm_tlb_flush_vmid_ipa) |
47 | push {r2, r3} | 50 | push {r2, r3} |
48 | 51 | ||
49 | add r0, r0, #KVM_VTTBR | 52 | add r0, r0, #KVM_VTTBR |
@@ -60,7 +63,7 @@ ENTRY(__kvm_tlb_flush_vmid) | |||
60 | 63 | ||
61 | pop {r2, r3} | 64 | pop {r2, r3} |
62 | bx lr | 65 | bx lr |
63 | ENDPROC(__kvm_tlb_flush_vmid) | 66 | ENDPROC(__kvm_tlb_flush_vmid_ipa) |
64 | 67 | ||
65 | /******************************************************************** | 68 | /******************************************************************** |
66 | * Flush TLBs and instruction caches of all CPUs inside the inner-shareable | 69 | * Flush TLBs and instruction caches of all CPUs inside the inner-shareable |
@@ -235,9 +238,9 @@ ENTRY(kvm_call_hyp) | |||
235 | * instruction is issued since all traps are disabled when running the host | 238 | * instruction is issued since all traps are disabled when running the host |
236 | * kernel as per the Hyp-mode initialization at boot time. | 239 | * kernel as per the Hyp-mode initialization at boot time. |
237 | * | 240 | * |
238 | * HVC instructions cause a trap to the vector page + offset 0x18 (see hyp_hvc | 241 | * HVC instructions cause a trap to the vector page + offset 0x14 (see hyp_hvc |
239 | * below) when the HVC instruction is called from SVC mode (i.e. a guest or the | 242 | * below) when the HVC instruction is called from SVC mode (i.e. a guest or the |
240 | * host kernel) and they cause a trap to the vector page + offset 0xc when HVC | 243 | * host kernel) and they cause a trap to the vector page + offset 0x8 when HVC |
241 | * instructions are called from within Hyp-mode. | 244 | * instructions are called from within Hyp-mode. |
242 | * | 245 | * |
243 | * Hyp-ABI: Calling HYP-mode functions from host (in SVC mode): | 246 | * Hyp-ABI: Calling HYP-mode functions from host (in SVC mode): |