1 files changed, 57 insertions, 6 deletions

diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 29dec080a604..a46d5b456765 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -11,8 +11,8 @@
  *
  *  Low-level vector interface routines
  *
- *  Note:  there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes
- *  it to save wrong values...  Be aware!
+ *  Note:  there is a StrongARM bug in the STMIA rn, {regs}^ instruction
+ *  that causes it to save wrong values...  Be aware!
  */
 
 #include <asm/memory.h>
@@ -58,6 +58,12 @@
 
         .endm
 
+#ifdef CONFIG_KPROBES
+        .section        .kprobes.text,"ax",%progbits
+#else
+        .text
+#endif
+
 /*
  * Invalid mode handlers
  */
@@ -112,8 +118,8 @@ common_invalid:
 #define SPFIX(code...)
 #endif
 
-        .macro  svc_entry
-        sub     sp, sp, #S_FRAME_SIZE
+        .macro  svc_entry, stack_hole=0
+        sub     sp, sp, #(S_FRAME_SIZE + \stack_hole)
  SPFIX( tst     sp, #4          )
  SPFIX( bicne   sp, sp, #4      )
         stmib   sp, {r1 - r12}
@@ -121,7 +127,7 @@ common_invalid:
         ldmia   r0, {r1 - r3}
         add     r5, sp, #S_SP           @ here for interlock avoidance
         mov     r4, #-1                 @  ""  ""      ""       ""
-        add     r0, sp, #S_FRAME_SIZE   @  ""  ""      ""       ""
+        add     r0, sp, #(S_FRAME_SIZE + \stack_hole)
  SPFIX( addne   r0, r0, #4      )
         str     r1, [sp]                @ save the "real" r0 copied
                                         @ from the exception stack
@@ -242,7 +248,14 @@ svc_preempt:
 
         .align  5
 __und_svc:
+#ifdef CONFIG_KPROBES
+        @ If a kprobe is about to simulate a "stmdb sp..." instruction,
+        @ it obviously needs free stack space which then will belong to
+        @ the saved context.
+        svc_entry 64
+#else
         svc_entry
+#endif
 
         @
         @ call emulation code, which returns using r9 if it has emulated
@@ -480,6 +493,13 @@ __und_usr:
  * co-processor instructions.  However, we have to watch out
  * for the ARM6/ARM7 SWI bug.
  *
+ * NEON is a special case that has to be handled here. Not all
+ * NEON instructions are co-processor instructions, so we have
+ * to make a special case of checking for them. Plus, there's
+ * five groups of them, so we have a table of mask/opcode pairs
+ * to check against, and if any match then we branch off into the
+ * NEON handler code.
+ *
  * Emulators may wish to make use of the following registers:
  *  r0  = instruction opcode.
  *  r2  = PC+4
@@ -488,6 +508,23 @@ __und_usr:
  *  lr  = unrecognised instruction return address
  */
 call_fpe:
+#ifdef CONFIG_NEON
+        adr     r6, .LCneon_opcodes
+2:
+        ldr     r7, [r6], #4                    @ mask value
+        cmp     r7, #0                          @ end mask?
+        beq     1f
+        and     r8, r0, r7
+        ldr     r7, [r6], #4                    @ opcode bits matching in mask
+        cmp     r8, r7                          @ NEON instruction?
+        bne     2b
+        get_thread_info r10
+        mov     r7, #1
+        strb    r7, [r10, #TI_USED_CP + 10]     @ mark CP#10 as used
+        strb    r7, [r10, #TI_USED_CP + 11]     @ mark CP#11 as used
+        b       do_vfp                          @ let VFP handler handle this
+1:
+#endif
         tst     r0, #0x08000000                 @ only CDP/CPRT/LDC/STC have bit 27
 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
         and     r8, r0, #0x0f000000             @ mask out op-code bits
@@ -537,6 +574,20 @@ call_fpe:
         mov     pc, lr                          @ CP#14 (Debug)
         mov     pc, lr                          @ CP#15 (Control)
 
+#ifdef CONFIG_NEON
+        .align  6
+
+.LCneon_opcodes:
+        .word   0xfe000000                      @ mask
+        .word   0xf2000000                      @ opcode
+
+        .word   0xff100000                      @ mask
+        .word   0xf4000000                      @ opcode
+
+        .word   0x00000000                      @ mask
+        .word   0x00000000                      @ opcode
+#endif
+
 do_fpe:
         enable_irq
         ldr     r4, .LCfp
@@ -555,7 +606,7 @@ do_fpe:
         .data
 ENTRY(fp_enter)
         .word   no_fp
-        .text
+        .previous
 
 no_fp:  mov     pc, lr