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-rw-r--r--arch/arm/include/asm/arch_timer.h109
-rw-r--r--arch/arm/include/asm/assembler.h10
-rw-r--r--arch/arm/include/asm/cputype.h33
-rw-r--r--arch/arm/include/asm/cti.h10
-rw-r--r--arch/arm/include/asm/delay.h1
-rw-r--r--arch/arm/include/asm/device.h6
-rw-r--r--arch/arm/include/asm/dma-iommu.h2
-rw-r--r--arch/arm/include/asm/dma.h2
-rw-r--r--arch/arm/include/asm/hardware/coresight.h6
-rw-r--r--arch/arm/include/asm/hardware/gic.h57
-rw-r--r--arch/arm/include/asm/hardware/pl080.h146
-rw-r--r--arch/arm/include/asm/hardware/sp810.h64
-rw-r--r--arch/arm/include/asm/hardware/vic.h57
-rw-r--r--arch/arm/include/asm/hw_breakpoint.h3
-rw-r--r--arch/arm/include/asm/idmap.h1
-rw-r--r--arch/arm/include/asm/kvm_arch_timer.h85
-rw-r--r--arch/arm/include/asm/kvm_arm.h214
-rw-r--r--arch/arm/include/asm/kvm_asm.h83
-rw-r--r--arch/arm/include/asm/kvm_coproc.h47
-rw-r--r--arch/arm/include/asm/kvm_emulate.h72
-rw-r--r--arch/arm/include/asm/kvm_host.h184
-rw-r--r--arch/arm/include/asm/kvm_mmio.h56
-rw-r--r--arch/arm/include/asm/kvm_mmu.h50
-rw-r--r--arch/arm/include/asm/kvm_psci.h23
-rw-r--r--arch/arm/include/asm/kvm_vgic.h221
-rw-r--r--arch/arm/include/asm/mach/arch.h3
-rw-r--r--arch/arm/include/asm/mach/irq.h1
-rw-r--r--arch/arm/include/asm/mach/pci.h1
-rw-r--r--arch/arm/include/asm/mach/time.h30
-rw-r--r--arch/arm/include/asm/memory.h12
-rw-r--r--arch/arm/include/asm/mmu.h8
-rw-r--r--arch/arm/include/asm/mmu_context.h2
-rw-r--r--arch/arm/include/asm/opcodes-sec.h24
-rw-r--r--arch/arm/include/asm/opcodes.h1
-rw-r--r--arch/arm/include/asm/outercache.h1
-rw-r--r--arch/arm/include/asm/pgtable-3level-hwdef.h5
-rw-r--r--arch/arm/include/asm/pgtable-3level.h18
-rw-r--r--arch/arm/include/asm/pgtable.h10
-rw-r--r--arch/arm/include/asm/psci.h36
-rw-r--r--arch/arm/include/asm/signal.h18
-rw-r--r--arch/arm/include/asm/smp_scu.h25
-rw-r--r--arch/arm/include/asm/spinlock.h16
-rw-r--r--arch/arm/include/asm/tlbflush.h34
-rw-r--r--arch/arm/include/asm/unistd.h2
-rw-r--r--arch/arm/include/asm/virt.h4
-rw-r--r--arch/arm/include/asm/xen/events.h5
-rw-r--r--arch/arm/include/asm/xen/page.h4
-rw-r--r--arch/arm/include/debug/imx-uart.h88
-rw-r--r--arch/arm/include/debug/imx.S29
-rw-r--r--arch/arm/include/debug/omap2plus.S190
-rw-r--r--arch/arm/include/debug/vt8500.S37
-rw-r--r--arch/arm/include/uapi/asm/kvm.h180
-rw-r--r--arch/arm/include/uapi/asm/unistd.h2
53 files changed, 1865 insertions, 463 deletions
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index d40229d9a1c9..7ade91d8cc6f 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -1,13 +1,115 @@
1#ifndef __ASMARM_ARCH_TIMER_H 1#ifndef __ASMARM_ARCH_TIMER_H
2#define __ASMARM_ARCH_TIMER_H 2#define __ASMARM_ARCH_TIMER_H
3 3
4#include <asm/barrier.h>
4#include <asm/errno.h> 5#include <asm/errno.h>
5#include <linux/clocksource.h> 6#include <linux/clocksource.h>
7#include <linux/init.h>
8#include <linux/types.h>
9
10#include <clocksource/arm_arch_timer.h>
6 11
7#ifdef CONFIG_ARM_ARCH_TIMER 12#ifdef CONFIG_ARM_ARCH_TIMER
8int arch_timer_of_register(void); 13int arch_timer_of_register(void);
9int arch_timer_sched_clock_init(void); 14int arch_timer_sched_clock_init(void);
10struct timecounter *arch_timer_get_timecounter(void); 15
16/*
17 * These register accessors are marked inline so the compiler can
18 * nicely work out which register we want, and chuck away the rest of
19 * the code. At least it does so with a recent GCC (4.6.3).
20 */
21static inline void arch_timer_reg_write(const int access, const int reg, u32 val)
22{
23 if (access == ARCH_TIMER_PHYS_ACCESS) {
24 switch (reg) {
25 case ARCH_TIMER_REG_CTRL:
26 asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
27 break;
28 case ARCH_TIMER_REG_TVAL:
29 asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
30 break;
31 }
32 }
33
34 if (access == ARCH_TIMER_VIRT_ACCESS) {
35 switch (reg) {
36 case ARCH_TIMER_REG_CTRL:
37 asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
38 break;
39 case ARCH_TIMER_REG_TVAL:
40 asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
41 break;
42 }
43 }
44
45 isb();
46}
47
48static inline u32 arch_timer_reg_read(const int access, const int reg)
49{
50 u32 val = 0;
51
52 if (access == ARCH_TIMER_PHYS_ACCESS) {
53 switch (reg) {
54 case ARCH_TIMER_REG_CTRL:
55 asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
56 break;
57 case ARCH_TIMER_REG_TVAL:
58 asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
59 break;
60 }
61 }
62
63 if (access == ARCH_TIMER_VIRT_ACCESS) {
64 switch (reg) {
65 case ARCH_TIMER_REG_CTRL:
66 asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
67 break;
68 case ARCH_TIMER_REG_TVAL:
69 asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
70 break;
71 }
72 }
73
74 return val;
75}
76
77static inline u32 arch_timer_get_cntfrq(void)
78{
79 u32 val;
80 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
81 return val;
82}
83
84static inline u64 arch_counter_get_cntpct(void)
85{
86 u64 cval;
87
88 isb();
89 asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
90 return cval;
91}
92
93static inline u64 arch_counter_get_cntvct(void)
94{
95 u64 cval;
96
97 isb();
98 asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
99 return cval;
100}
101
102static inline void __cpuinit arch_counter_set_user_access(void)
103{
104 u32 cntkctl;
105
106 asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl));
107
108 /* disable user access to everything */
109 cntkctl &= ~((3 << 8) | (7 << 0));
110
111 asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
112}
11#else 113#else
12static inline int arch_timer_of_register(void) 114static inline int arch_timer_of_register(void)
13{ 115{
@@ -18,11 +120,6 @@ static inline int arch_timer_sched_clock_init(void)
18{ 120{
19 return -ENXIO; 121 return -ENXIO;
20} 122}
21
22static inline struct timecounter *arch_timer_get_timecounter(void)
23{
24 return NULL;
25}
26#endif 123#endif
27 124
28#endif 125#endif
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index eb87200aa4b5..05ee9eebad6b 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -246,18 +246,14 @@
246 * 246 *
247 * This macro is intended for forcing the CPU into SVC mode at boot time. 247 * This macro is intended for forcing the CPU into SVC mode at boot time.
248 * you cannot return to the original mode. 248 * you cannot return to the original mode.
249 *
250 * Beware, it also clobers LR.
251 */ 249 */
252.macro safe_svcmode_maskall reg:req 250.macro safe_svcmode_maskall reg:req
253#if __LINUX_ARM_ARCH__ >= 6 251#if __LINUX_ARM_ARCH__ >= 6
254 mrs \reg , cpsr 252 mrs \reg , cpsr
255 mov lr , \reg 253 eor \reg, \reg, #HYP_MODE
256 and lr , lr , #MODE_MASK 254 tst \reg, #MODE_MASK
257 cmp lr , #HYP_MODE
258 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT
259 bic \reg , \reg , #MODE_MASK 255 bic \reg , \reg , #MODE_MASK
260 orr \reg , \reg , #SVC_MODE 256 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
261THUMB( orr \reg , \reg , #PSR_T_BIT ) 257THUMB( orr \reg , \reg , #PSR_T_BIT )
262 bne 1f 258 bne 1f
263 orr \reg, \reg, #PSR_A_BIT 259 orr \reg, \reg, #PSR_A_BIT
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index a59dcb5ab5fc..ad41ec2471e8 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -64,6 +64,24 @@ extern unsigned int processor_id;
64#define read_cpuid_ext(reg) 0 64#define read_cpuid_ext(reg) 0
65#endif 65#endif
66 66
67#define ARM_CPU_IMP_ARM 0x41
68#define ARM_CPU_IMP_INTEL 0x69
69
70#define ARM_CPU_PART_ARM1136 0xB360
71#define ARM_CPU_PART_ARM1156 0xB560
72#define ARM_CPU_PART_ARM1176 0xB760
73#define ARM_CPU_PART_ARM11MPCORE 0xB020
74#define ARM_CPU_PART_CORTEX_A8 0xC080
75#define ARM_CPU_PART_CORTEX_A9 0xC090
76#define ARM_CPU_PART_CORTEX_A5 0xC050
77#define ARM_CPU_PART_CORTEX_A15 0xC0F0
78#define ARM_CPU_PART_CORTEX_A7 0xC070
79
80#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
81#define ARM_CPU_XSCALE_ARCH_V1 0x2000
82#define ARM_CPU_XSCALE_ARCH_V2 0x4000
83#define ARM_CPU_XSCALE_ARCH_V3 0x6000
84
67/* 85/*
68 * The CPU ID never changes at run time, so we might as well tell the 86 * The CPU ID never changes at run time, so we might as well tell the
69 * compiler that it's constant. Use this function to read the CPU ID 87 * compiler that it's constant. Use this function to read the CPU ID
@@ -74,6 +92,21 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
74 return read_cpuid(CPUID_ID); 92 return read_cpuid(CPUID_ID);
75} 93}
76 94
95static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
96{
97 return (read_cpuid_id() & 0xFF000000) >> 24;
98}
99
100static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
101{
102 return read_cpuid_id() & 0xFFF0;
103}
104
105static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
106{
107 return read_cpuid_part_number() & ARM_CPU_XSCALE_ARCH_MASK;
108}
109
77static inline unsigned int __attribute_const__ read_cpuid_cachetype(void) 110static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
78{ 111{
79 return read_cpuid(CPUID_CACHETYPE); 112 return read_cpuid(CPUID_CACHETYPE);
diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h
index f2e5cad3f306..2381199acb7d 100644
--- a/arch/arm/include/asm/cti.h
+++ b/arch/arm/include/asm/cti.h
@@ -2,6 +2,7 @@
2#define __ASMARM_CTI_H 2#define __ASMARM_CTI_H
3 3
4#include <asm/io.h> 4#include <asm/io.h>
5#include <asm/hardware/coresight.h>
5 6
6/* The registers' definition is from section 3.2 of 7/* The registers' definition is from section 3.2 of
7 * Embedded Cross Trigger Revision: r0p0 8 * Embedded Cross Trigger Revision: r0p0
@@ -35,11 +36,6 @@
35#define LOCKACCESS 0xFB0 36#define LOCKACCESS 0xFB0
36#define LOCKSTATUS 0xFB4 37#define LOCKSTATUS 0xFB4
37 38
38/* write this value to LOCKACCESS will unlock the module, and
39 * other value will lock the module
40 */
41#define LOCKCODE 0xC5ACCE55
42
43/** 39/**
44 * struct cti - cross trigger interface struct 40 * struct cti - cross trigger interface struct
45 * @base: mapped virtual address for the cti base 41 * @base: mapped virtual address for the cti base
@@ -146,7 +142,7 @@ static inline void cti_irq_ack(struct cti *cti)
146 */ 142 */
147static inline void cti_unlock(struct cti *cti) 143static inline void cti_unlock(struct cti *cti)
148{ 144{
149 __raw_writel(LOCKCODE, cti->base + LOCKACCESS); 145 __raw_writel(CS_LAR_KEY, cti->base + LOCKACCESS);
150} 146}
151 147
152/** 148/**
@@ -158,6 +154,6 @@ static inline void cti_unlock(struct cti *cti)
158 */ 154 */
159static inline void cti_lock(struct cti *cti) 155static inline void cti_lock(struct cti *cti)
160{ 156{
161 __raw_writel(~LOCKCODE, cti->base + LOCKACCESS); 157 __raw_writel(~CS_LAR_KEY, cti->base + LOCKACCESS);
162} 158}
163#endif 159#endif
diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h
index ab98fdd083bd..720799fd3a81 100644
--- a/arch/arm/include/asm/delay.h
+++ b/arch/arm/include/asm/delay.h
@@ -24,6 +24,7 @@ extern struct arm_delay_ops {
24 void (*delay)(unsigned long); 24 void (*delay)(unsigned long);
25 void (*const_udelay)(unsigned long); 25 void (*const_udelay)(unsigned long);
26 void (*udelay)(unsigned long); 26 void (*udelay)(unsigned long);
27 bool const_clock;
27} arm_delay_ops; 28} arm_delay_ops;
28 29
29#define __delay(n) arm_delay_ops.delay(n) 30#define __delay(n) arm_delay_ops.delay(n)
diff --git a/arch/arm/include/asm/device.h b/arch/arm/include/asm/device.h
index b69c0d3285f8..dc662fca9230 100644
--- a/arch/arm/include/asm/device.h
+++ b/arch/arm/include/asm/device.h
@@ -27,4 +27,10 @@ struct pdev_archdata {
27#endif 27#endif
28}; 28};
29 29
30#ifdef CONFIG_ARM_DMA_USE_IOMMU
31#define to_dma_iommu_mapping(dev) ((dev)->archdata.mapping)
32#else
33#define to_dma_iommu_mapping(dev) NULL
34#endif
35
30#endif 36#endif
diff --git a/arch/arm/include/asm/dma-iommu.h b/arch/arm/include/asm/dma-iommu.h
index 799b09409fad..a8c56acc8c98 100644
--- a/arch/arm/include/asm/dma-iommu.h
+++ b/arch/arm/include/asm/dma-iommu.h
@@ -7,6 +7,7 @@
7#include <linux/scatterlist.h> 7#include <linux/scatterlist.h>
8#include <linux/dma-debug.h> 8#include <linux/dma-debug.h>
9#include <linux/kmemcheck.h> 9#include <linux/kmemcheck.h>
10#include <linux/kref.h>
10 11
11struct dma_iommu_mapping { 12struct dma_iommu_mapping {
12 /* iommu specific data */ 13 /* iommu specific data */
@@ -29,6 +30,7 @@ void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping);
29 30
30int arm_iommu_attach_device(struct device *dev, 31int arm_iommu_attach_device(struct device *dev,
31 struct dma_iommu_mapping *mapping); 32 struct dma_iommu_mapping *mapping);
33void arm_iommu_detach_device(struct device *dev);
32 34
33#endif /* __KERNEL__ */ 35#endif /* __KERNEL__ */
34#endif 36#endif
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index 5694a0d6576b..58b8c6a0ab1f 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -105,7 +105,7 @@ extern void set_dma_sg(unsigned int chan, struct scatterlist *sg, int nr_sg);
105 */ 105 */
106extern void __set_dma_addr(unsigned int chan, void *addr); 106extern void __set_dma_addr(unsigned int chan, void *addr);
107#define set_dma_addr(chan, addr) \ 107#define set_dma_addr(chan, addr) \
108 __set_dma_addr(chan, bus_to_virt(addr)) 108 __set_dma_addr(chan, (void *)__bus_to_virt(addr))
109 109
110/* Set the DMA byte count for this channel 110/* Set the DMA byte count for this channel
111 * 111 *
diff --git a/arch/arm/include/asm/hardware/coresight.h b/arch/arm/include/asm/hardware/coresight.h
index 7ecd793b8f5a..0cf7a6b842ff 100644
--- a/arch/arm/include/asm/hardware/coresight.h
+++ b/arch/arm/include/asm/hardware/coresight.h
@@ -36,7 +36,7 @@
36/* CoreSight Component Registers */ 36/* CoreSight Component Registers */
37#define CSCR_CLASS 0xff4 37#define CSCR_CLASS 0xff4
38 38
39#define UNLOCK_MAGIC 0xc5acce55 39#define CS_LAR_KEY 0xc5acce55
40 40
41/* ETM control register, "ETM Architecture", 3.3.1 */ 41/* ETM control register, "ETM Architecture", 3.3.1 */
42#define ETMR_CTRL 0 42#define ETMR_CTRL 0
@@ -147,11 +147,11 @@
147 147
148#define etm_lock(t) do { etm_writel((t), 0, CSMR_LOCKACCESS); } while (0) 148#define etm_lock(t) do { etm_writel((t), 0, CSMR_LOCKACCESS); } while (0)
149#define etm_unlock(t) \ 149#define etm_unlock(t) \
150 do { etm_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0) 150 do { etm_writel((t), CS_LAR_KEY, CSMR_LOCKACCESS); } while (0)
151 151
152#define etb_lock(t) do { etb_writel((t), 0, CSMR_LOCKACCESS); } while (0) 152#define etb_lock(t) do { etb_writel((t), 0, CSMR_LOCKACCESS); } while (0)
153#define etb_unlock(t) \ 153#define etb_unlock(t) \
154 do { etb_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0) 154 do { etb_writel((t), CS_LAR_KEY, CSMR_LOCKACCESS); } while (0)
155 155
156#endif /* __ASM_HARDWARE_CORESIGHT_H */ 156#endif /* __ASM_HARDWARE_CORESIGHT_H */
157 157
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
deleted file mode 100644
index 4b1ce6cd477f..000000000000
--- a/arch/arm/include/asm/hardware/gic.h
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * arch/arm/include/asm/hardware/gic.h
3 *
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ASM_ARM_HARDWARE_GIC_H
11#define __ASM_ARM_HARDWARE_GIC_H
12
13#include <linux/compiler.h>
14
15#define GIC_CPU_CTRL 0x00
16#define GIC_CPU_PRIMASK 0x04
17#define GIC_CPU_BINPOINT 0x08
18#define GIC_CPU_INTACK 0x0c
19#define GIC_CPU_EOI 0x10
20#define GIC_CPU_RUNNINGPRI 0x14
21#define GIC_CPU_HIGHPRI 0x18
22
23#define GIC_DIST_CTRL 0x000
24#define GIC_DIST_CTR 0x004
25#define GIC_DIST_ENABLE_SET 0x100
26#define GIC_DIST_ENABLE_CLEAR 0x180
27#define GIC_DIST_PENDING_SET 0x200
28#define GIC_DIST_PENDING_CLEAR 0x280
29#define GIC_DIST_ACTIVE_BIT 0x300
30#define GIC_DIST_PRI 0x400
31#define GIC_DIST_TARGET 0x800
32#define GIC_DIST_CONFIG 0xc00
33#define GIC_DIST_SOFTINT 0xf00
34
35#ifndef __ASSEMBLY__
36#include <linux/irqdomain.h>
37struct device_node;
38
39extern struct irq_chip gic_arch_extn;
40
41void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
42 u32 offset, struct device_node *);
43int gic_of_init(struct device_node *node, struct device_node *parent);
44void gic_secondary_init(unsigned int);
45void gic_handle_irq(struct pt_regs *regs);
46void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
47void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
48
49static inline void gic_init(unsigned int nr, int start,
50 void __iomem *dist , void __iomem *cpu)
51{
52 gic_init_bases(nr, start, dist, cpu, 0, NULL);
53}
54
55#endif
56
57#endif
diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h
deleted file mode 100644
index 4eea2107214b..000000000000
--- a/arch/arm/include/asm/hardware/pl080.h
+++ /dev/null
@@ -1,146 +0,0 @@
1/* arch/arm/include/asm/hardware/pl080.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * ARM PrimeCell PL080 DMA controller
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* Note, there are some Samsung updates to this controller block which
16 * make it not entierly compatible with the PL080 specification from
17 * ARM. When in doubt, check the Samsung documentation first.
18 *
19 * The Samsung defines are PL080S, and add an extra control register,
20 * the ability to move more than 2^11 counts of data and some extra
21 * OneNAND features.
22*/
23
24#ifndef ASM_PL080_H
25#define ASM_PL080_H
26
27#define PL080_INT_STATUS (0x00)
28#define PL080_TC_STATUS (0x04)
29#define PL080_TC_CLEAR (0x08)
30#define PL080_ERR_STATUS (0x0C)
31#define PL080_ERR_CLEAR (0x10)
32#define PL080_RAW_TC_STATUS (0x14)
33#define PL080_RAW_ERR_STATUS (0x18)
34#define PL080_EN_CHAN (0x1c)
35#define PL080_SOFT_BREQ (0x20)
36#define PL080_SOFT_SREQ (0x24)
37#define PL080_SOFT_LBREQ (0x28)
38#define PL080_SOFT_LSREQ (0x2C)
39
40#define PL080_CONFIG (0x30)
41#define PL080_CONFIG_M2_BE (1 << 2)
42#define PL080_CONFIG_M1_BE (1 << 1)
43#define PL080_CONFIG_ENABLE (1 << 0)
44
45#define PL080_SYNC (0x34)
46
47/* Per channel configuration registers */
48
49#define PL080_Cx_STRIDE (0x20)
50#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20)))
51#define PL080_Cx_SRC_ADDR(x) ((0x100 + (x * 0x20)))
52#define PL080_Cx_DST_ADDR(x) ((0x104 + (x * 0x20)))
53#define PL080_Cx_LLI(x) ((0x108 + (x * 0x20)))
54#define PL080_Cx_CONTROL(x) ((0x10C + (x * 0x20)))
55#define PL080_Cx_CONFIG(x) ((0x110 + (x * 0x20)))
56#define PL080S_Cx_CONTROL2(x) ((0x110 + (x * 0x20)))
57#define PL080S_Cx_CONFIG(x) ((0x114 + (x * 0x20)))
58
59#define PL080_CH_SRC_ADDR (0x00)
60#define PL080_CH_DST_ADDR (0x04)
61#define PL080_CH_LLI (0x08)
62#define PL080_CH_CONTROL (0x0C)
63#define PL080_CH_CONFIG (0x10)
64#define PL080S_CH_CONTROL2 (0x10)
65#define PL080S_CH_CONFIG (0x14)
66
67#define PL080_LLI_ADDR_MASK (0x3fffffff << 2)
68#define PL080_LLI_ADDR_SHIFT (2)
69#define PL080_LLI_LM_AHB2 (1 << 0)
70
71#define PL080_CONTROL_TC_IRQ_EN (1 << 31)
72#define PL080_CONTROL_PROT_MASK (0x7 << 28)
73#define PL080_CONTROL_PROT_SHIFT (28)
74#define PL080_CONTROL_PROT_CACHE (1 << 30)
75#define PL080_CONTROL_PROT_BUFF (1 << 29)
76#define PL080_CONTROL_PROT_SYS (1 << 28)
77#define PL080_CONTROL_DST_INCR (1 << 27)
78#define PL080_CONTROL_SRC_INCR (1 << 26)
79#define PL080_CONTROL_DST_AHB2 (1 << 25)
80#define PL080_CONTROL_SRC_AHB2 (1 << 24)
81#define PL080_CONTROL_DWIDTH_MASK (0x7 << 21)
82#define PL080_CONTROL_DWIDTH_SHIFT (21)
83#define PL080_CONTROL_SWIDTH_MASK (0x7 << 18)
84#define PL080_CONTROL_SWIDTH_SHIFT (18)
85#define PL080_CONTROL_DB_SIZE_MASK (0x7 << 15)
86#define PL080_CONTROL_DB_SIZE_SHIFT (15)
87#define PL080_CONTROL_SB_SIZE_MASK (0x7 << 12)
88#define PL080_CONTROL_SB_SIZE_SHIFT (12)
89#define PL080_CONTROL_TRANSFER_SIZE_MASK (0xfff << 0)
90#define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0)
91
92#define PL080_BSIZE_1 (0x0)
93#define PL080_BSIZE_4 (0x1)
94#define PL080_BSIZE_8 (0x2)
95#define PL080_BSIZE_16 (0x3)
96#define PL080_BSIZE_32 (0x4)
97#define PL080_BSIZE_64 (0x5)
98#define PL080_BSIZE_128 (0x6)
99#define PL080_BSIZE_256 (0x7)
100
101#define PL080_WIDTH_8BIT (0x0)
102#define PL080_WIDTH_16BIT (0x1)
103#define PL080_WIDTH_32BIT (0x2)
104
105#define PL080N_CONFIG_ITPROT (1 << 20)
106#define PL080N_CONFIG_SECPROT (1 << 19)
107#define PL080_CONFIG_HALT (1 << 18)
108#define PL080_CONFIG_ACTIVE (1 << 17) /* RO */
109#define PL080_CONFIG_LOCK (1 << 16)
110#define PL080_CONFIG_TC_IRQ_MASK (1 << 15)
111#define PL080_CONFIG_ERR_IRQ_MASK (1 << 14)
112#define PL080_CONFIG_FLOW_CONTROL_MASK (0x7 << 11)
113#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11)
114#define PL080_CONFIG_DST_SEL_MASK (0xf << 6)
115#define PL080_CONFIG_DST_SEL_SHIFT (6)
116#define PL080_CONFIG_SRC_SEL_MASK (0xf << 1)
117#define PL080_CONFIG_SRC_SEL_SHIFT (1)
118#define PL080_CONFIG_ENABLE (1 << 0)
119
120#define PL080_FLOW_MEM2MEM (0x0)
121#define PL080_FLOW_MEM2PER (0x1)
122#define PL080_FLOW_PER2MEM (0x2)
123#define PL080_FLOW_SRC2DST (0x3)
124#define PL080_FLOW_SRC2DST_DST (0x4)
125#define PL080_FLOW_MEM2PER_PER (0x5)
126#define PL080_FLOW_PER2MEM_PER (0x6)
127#define PL080_FLOW_SRC2DST_SRC (0x7)
128
129/* DMA linked list chain structure */
130
131struct pl080_lli {
132 u32 src_addr;
133 u32 dst_addr;
134 u32 next_lli;
135 u32 control0;
136};
137
138struct pl080s_lli {
139 u32 src_addr;
140 u32 dst_addr;
141 u32 next_lli;
142 u32 control0;
143 u32 control1;
144};
145
146#endif /* ASM_PL080_H */
diff --git a/arch/arm/include/asm/hardware/sp810.h b/arch/arm/include/asm/hardware/sp810.h
deleted file mode 100644
index 6636430dd0e6..000000000000
--- a/arch/arm/include/asm/hardware/sp810.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * arch/arm/include/asm/hardware/sp810.h
3 *
4 * ARM PrimeXsys System Controller SP810 header file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar <viresh.linux@gmail.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __ASM_ARM_SP810_H
15#define __ASM_ARM_SP810_H
16
17#include <linux/io.h>
18
19/* sysctl registers offset */
20#define SCCTRL 0x000
21#define SCSYSSTAT 0x004
22#define SCIMCTRL 0x008
23#define SCIMSTAT 0x00C
24#define SCXTALCTRL 0x010
25#define SCPLLCTRL 0x014
26#define SCPLLFCTRL 0x018
27#define SCPERCTRL0 0x01C
28#define SCPERCTRL1 0x020
29#define SCPEREN 0x024
30#define SCPERDIS 0x028
31#define SCPERCLKEN 0x02C
32#define SCPERSTAT 0x030
33#define SCSYSID0 0xEE0
34#define SCSYSID1 0xEE4
35#define SCSYSID2 0xEE8
36#define SCSYSID3 0xEEC
37#define SCITCR 0xF00
38#define SCITIR0 0xF04
39#define SCITIR1 0xF08
40#define SCITOR 0xF0C
41#define SCCNTCTRL 0xF10
42#define SCCNTDATA 0xF14
43#define SCCNTSTEP 0xF18
44#define SCPERIPHID0 0xFE0
45#define SCPERIPHID1 0xFE4
46#define SCPERIPHID2 0xFE8
47#define SCPERIPHID3 0xFEC
48#define SCPCELLID0 0xFF0
49#define SCPCELLID1 0xFF4
50#define SCPCELLID2 0xFF8
51#define SCPCELLID3 0xFFC
52
53#define SCCTRL_TIMERENnSEL_SHIFT(n) (15 + ((n) * 2))
54
55static inline void sysctl_soft_reset(void __iomem *base)
56{
57 /* switch to slow mode */
58 writel(0x2, base + SCCTRL);
59
60 /* writing any value to SCSYSSTAT reg will reset system */
61 writel(0, base + SCSYSSTAT);
62}
63
64#endif /* __ASM_ARM_SP810_H */
diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h
deleted file mode 100644
index 2bebad36fc83..000000000000
--- a/arch/arm/include/asm/hardware/vic.h
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * arch/arm/include/asm/hardware/vic.h
3 *
4 * Copyright (c) ARM Limited 2003. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARM_HARDWARE_VIC_H
21#define __ASM_ARM_HARDWARE_VIC_H
22
23#define VIC_IRQ_STATUS 0x00
24#define VIC_FIQ_STATUS 0x04
25#define VIC_RAW_STATUS 0x08
26#define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */
27#define VIC_INT_ENABLE 0x10 /* 1 = enable, 0 = disable */
28#define VIC_INT_ENABLE_CLEAR 0x14
29#define VIC_INT_SOFT 0x18
30#define VIC_INT_SOFT_CLEAR 0x1c
31#define VIC_PROTECT 0x20
32#define VIC_PL190_VECT_ADDR 0x30 /* PL190 only */
33#define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */
34
35#define VIC_VECT_ADDR0 0x100 /* 0 to 15 (0..31 PL192) */
36#define VIC_VECT_CNTL0 0x200 /* 0 to 15 (0..31 PL192) */
37#define VIC_ITCR 0x300 /* VIC test control register */
38
39#define VIC_VECT_CNTL_ENABLE (1 << 5)
40
41#define VIC_PL192_VECT_ADDR 0xF00
42
43#ifndef __ASSEMBLY__
44#include <linux/compiler.h>
45#include <linux/types.h>
46
47struct device_node;
48struct pt_regs;
49
50void __vic_init(void __iomem *base, int irq_start, u32 vic_sources,
51 u32 resume_sources, struct device_node *node);
52void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
53int vic_of_init(struct device_node *node, struct device_node *parent);
54void vic_handle_irq(struct pt_regs *regs);
55
56#endif /* __ASSEMBLY__ */
57#endif
diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h
index 01169dd723f1..eef55ea9ef00 100644
--- a/arch/arm/include/asm/hw_breakpoint.h
+++ b/arch/arm/include/asm/hw_breakpoint.h
@@ -85,6 +85,9 @@ static inline void decode_ctrl_reg(u32 reg,
85#define ARM_DSCR_HDBGEN (1 << 14) 85#define ARM_DSCR_HDBGEN (1 << 14)
86#define ARM_DSCR_MDBGEN (1 << 15) 86#define ARM_DSCR_MDBGEN (1 << 15)
87 87
88/* OSLSR os lock model bits */
89#define ARM_OSLSR_OSLM0 (1 << 0)
90
88/* opcode2 numbers for the co-processor instructions. */ 91/* opcode2 numbers for the co-processor instructions. */
89#define ARM_OP2_BVR 4 92#define ARM_OP2_BVR 4
90#define ARM_OP2_BCR 5 93#define ARM_OP2_BCR 5
diff --git a/arch/arm/include/asm/idmap.h b/arch/arm/include/asm/idmap.h
index bf863edb517d..1a66f907e5cc 100644
--- a/arch/arm/include/asm/idmap.h
+++ b/arch/arm/include/asm/idmap.h
@@ -8,6 +8,7 @@
8#define __idmap __section(.idmap.text) noinline notrace 8#define __idmap __section(.idmap.text) noinline notrace
9 9
10extern pgd_t *idmap_pgd; 10extern pgd_t *idmap_pgd;
11extern pgd_t *hyp_pgd;
11 12
12void setup_mm_for_reboot(void); 13void setup_mm_for_reboot(void);
13 14
diff --git a/arch/arm/include/asm/kvm_arch_timer.h b/arch/arm/include/asm/kvm_arch_timer.h
new file mode 100644
index 000000000000..68cb9e1dfb81
--- /dev/null
+++ b/arch/arm/include/asm/kvm_arch_timer.h
@@ -0,0 +1,85 @@
1/*
2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef __ASM_ARM_KVM_ARCH_TIMER_H
20#define __ASM_ARM_KVM_ARCH_TIMER_H
21
22#include <linux/clocksource.h>
23#include <linux/hrtimer.h>
24#include <linux/workqueue.h>
25
26struct arch_timer_kvm {
27#ifdef CONFIG_KVM_ARM_TIMER
28 /* Is the timer enabled */
29 bool enabled;
30
31 /* Virtual offset */
32 cycle_t cntvoff;
33#endif
34};
35
36struct arch_timer_cpu {
37#ifdef CONFIG_KVM_ARM_TIMER
38 /* Registers: control register, timer value */
39 u32 cntv_ctl; /* Saved/restored */
40 cycle_t cntv_cval; /* Saved/restored */
41
42 /*
43 * Anything that is not used directly from assembly code goes
44 * here.
45 */
46
47 /* Background timer used when the guest is not running */
48 struct hrtimer timer;
49
50 /* Work queued with the above timer expires */
51 struct work_struct expired;
52
53 /* Background timer active */
54 bool armed;
55
56 /* Timer IRQ */
57 const struct kvm_irq_level *irq;
58#endif
59};
60
61#ifdef CONFIG_KVM_ARM_TIMER
62int kvm_timer_hyp_init(void);
63int kvm_timer_init(struct kvm *kvm);
64void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu);
65void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu);
66void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu);
67void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu);
68#else
69static inline int kvm_timer_hyp_init(void)
70{
71 return 0;
72};
73
74static inline int kvm_timer_init(struct kvm *kvm)
75{
76 return 0;
77}
78
79static inline void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu) {}
80static inline void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu) {}
81static inline void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu) {}
82static inline void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu) {}
83#endif
84
85#endif
diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h
new file mode 100644
index 000000000000..7c3d813e15df
--- /dev/null
+++ b/arch/arm/include/asm/kvm_arm.h
@@ -0,0 +1,214 @@
1/*
2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
3 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19#ifndef __ARM_KVM_ARM_H__
20#define __ARM_KVM_ARM_H__
21
22#include <linux/types.h>
23
24/* Hyp Configuration Register (HCR) bits */
25#define HCR_TGE (1 << 27)
26#define HCR_TVM (1 << 26)
27#define HCR_TTLB (1 << 25)
28#define HCR_TPU (1 << 24)
29#define HCR_TPC (1 << 23)
30#define HCR_TSW (1 << 22)
31#define HCR_TAC (1 << 21)
32#define HCR_TIDCP (1 << 20)
33#define HCR_TSC (1 << 19)
34#define HCR_TID3 (1 << 18)
35#define HCR_TID2 (1 << 17)
36#define HCR_TID1 (1 << 16)
37#define HCR_TID0 (1 << 15)
38#define HCR_TWE (1 << 14)
39#define HCR_TWI (1 << 13)
40#define HCR_DC (1 << 12)
41#define HCR_BSU (3 << 10)
42#define HCR_BSU_IS (1 << 10)
43#define HCR_FB (1 << 9)
44#define HCR_VA (1 << 8)
45#define HCR_VI (1 << 7)
46#define HCR_VF (1 << 6)
47#define HCR_AMO (1 << 5)
48#define HCR_IMO (1 << 4)
49#define HCR_FMO (1 << 3)
50#define HCR_PTW (1 << 2)
51#define HCR_SWIO (1 << 1)
52#define HCR_VM 1
53
54/*
55 * The bits we set in HCR:
56 * TAC: Trap ACTLR
57 * TSC: Trap SMC
58 * TSW: Trap cache operations by set/way
59 * TWI: Trap WFI
60 * TIDCP: Trap L2CTLR/L2ECTLR
61 * BSU_IS: Upgrade barriers to the inner shareable domain
62 * FB: Force broadcast of all maintainance operations
63 * AMO: Override CPSR.A and enable signaling with VA
64 * IMO: Override CPSR.I and enable signaling with VI
65 * FMO: Override CPSR.F and enable signaling with VF
66 * SWIO: Turn set/way invalidates into set/way clean+invalidate
67 */
68#define HCR_GUEST_MASK (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS | \
69 HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \
70 HCR_SWIO | HCR_TIDCP)
71#define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF)
72
73/* System Control Register (SCTLR) bits */
74#define SCTLR_TE (1 << 30)
75#define SCTLR_EE (1 << 25)
76#define SCTLR_V (1 << 13)
77
78/* Hyp System Control Register (HSCTLR) bits */
79#define HSCTLR_TE (1 << 30)
80#define HSCTLR_EE (1 << 25)
81#define HSCTLR_FI (1 << 21)
82#define HSCTLR_WXN (1 << 19)
83#define HSCTLR_I (1 << 12)
84#define HSCTLR_C (1 << 2)
85#define HSCTLR_A (1 << 1)
86#define HSCTLR_M 1
87#define HSCTLR_MASK (HSCTLR_M | HSCTLR_A | HSCTLR_C | HSCTLR_I | \
88 HSCTLR_WXN | HSCTLR_FI | HSCTLR_EE | HSCTLR_TE)
89
90/* TTBCR and HTCR Registers bits */
91#define TTBCR_EAE (1 << 31)
92#define TTBCR_IMP (1 << 30)
93#define TTBCR_SH1 (3 << 28)
94#define TTBCR_ORGN1 (3 << 26)
95#define TTBCR_IRGN1 (3 << 24)
96#define TTBCR_EPD1 (1 << 23)
97#define TTBCR_A1 (1 << 22)
98#define TTBCR_T1SZ (3 << 16)
99#define TTBCR_SH0 (3 << 12)
100#define TTBCR_ORGN0 (3 << 10)
101#define TTBCR_IRGN0 (3 << 8)
102#define TTBCR_EPD0 (1 << 7)
103#define TTBCR_T0SZ 3
104#define HTCR_MASK (TTBCR_T0SZ | TTBCR_IRGN0 | TTBCR_ORGN0 | TTBCR_SH0)
105
106/* Hyp System Trap Register */
107#define HSTR_T(x) (1 << x)
108#define HSTR_TTEE (1 << 16)
109#define HSTR_TJDBX (1 << 17)
110
111/* Hyp Coprocessor Trap Register */
112#define HCPTR_TCP(x) (1 << x)
113#define HCPTR_TCP_MASK (0x3fff)
114#define HCPTR_TASE (1 << 15)
115#define HCPTR_TTA (1 << 20)
116#define HCPTR_TCPAC (1 << 31)
117
118/* Hyp Debug Configuration Register bits */
119#define HDCR_TDRA (1 << 11)
120#define HDCR_TDOSA (1 << 10)
121#define HDCR_TDA (1 << 9)
122#define HDCR_TDE (1 << 8)
123#define HDCR_HPME (1 << 7)
124#define HDCR_TPM (1 << 6)
125#define HDCR_TPMCR (1 << 5)
126#define HDCR_HPMN_MASK (0x1F)
127
128/*
129 * The architecture supports 40-bit IPA as input to the 2nd stage translations
130 * and PTRS_PER_S2_PGD becomes 1024, because each entry covers 1GB of address
131 * space.
132 */
133#define KVM_PHYS_SHIFT (40)
134#define KVM_PHYS_SIZE (1ULL << KVM_PHYS_SHIFT)
135#define KVM_PHYS_MASK (KVM_PHYS_SIZE - 1ULL)
136#define PTRS_PER_S2_PGD (1ULL << (KVM_PHYS_SHIFT - 30))
137#define S2_PGD_ORDER get_order(PTRS_PER_S2_PGD * sizeof(pgd_t))
138#define S2_PGD_SIZE (1 << S2_PGD_ORDER)
139
140/* Virtualization Translation Control Register (VTCR) bits */
141#define VTCR_SH0 (3 << 12)
142#define VTCR_ORGN0 (3 << 10)
143#define VTCR_IRGN0 (3 << 8)
144#define VTCR_SL0 (3 << 6)
145#define VTCR_S (1 << 4)
146#define VTCR_T0SZ (0xf)
147#define VTCR_MASK (VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0 | VTCR_SL0 | \
148 VTCR_S | VTCR_T0SZ)
149#define VTCR_HTCR_SH (VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0)
150#define VTCR_SL_L2 (0 << 6) /* Starting-level: 2 */
151#define VTCR_SL_L1 (1 << 6) /* Starting-level: 1 */
152#define KVM_VTCR_SL0 VTCR_SL_L1
153/* stage-2 input address range defined as 2^(32-T0SZ) */
154#define KVM_T0SZ (32 - KVM_PHYS_SHIFT)
155#define KVM_VTCR_T0SZ (KVM_T0SZ & VTCR_T0SZ)
156#define KVM_VTCR_S ((KVM_VTCR_T0SZ << 1) & VTCR_S)
157
158/* Virtualization Translation Table Base Register (VTTBR) bits */
159#if KVM_VTCR_SL0 == VTCR_SL_L2 /* see ARM DDI 0406C: B4-1720 */
160#define VTTBR_X (14 - KVM_T0SZ)
161#else
162#define VTTBR_X (5 - KVM_T0SZ)
163#endif
164#define VTTBR_BADDR_SHIFT (VTTBR_X - 1)
165#define VTTBR_BADDR_MASK (((1LLU << (40 - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT)
166#define VTTBR_VMID_SHIFT (48LLU)
167#define VTTBR_VMID_MASK (0xffLLU << VTTBR_VMID_SHIFT)
168
169/* Hyp Syndrome Register (HSR) bits */
170#define HSR_EC_SHIFT (26)
171#define HSR_EC (0x3fU << HSR_EC_SHIFT)
172#define HSR_IL (1U << 25)
173#define HSR_ISS (HSR_IL - 1)
174#define HSR_ISV_SHIFT (24)
175#define HSR_ISV (1U << HSR_ISV_SHIFT)
176#define HSR_SRT_SHIFT (16)
177#define HSR_SRT_MASK (0xf << HSR_SRT_SHIFT)
178#define HSR_FSC (0x3f)
179#define HSR_FSC_TYPE (0x3c)
180#define HSR_SSE (1 << 21)
181#define HSR_WNR (1 << 6)
182#define HSR_CV_SHIFT (24)
183#define HSR_CV (1U << HSR_CV_SHIFT)
184#define HSR_COND_SHIFT (20)
185#define HSR_COND (0xfU << HSR_COND_SHIFT)
186
187#define FSC_FAULT (0x04)
188#define FSC_PERM (0x0c)
189
190/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
191#define HPFAR_MASK (~0xf)
192
193#define HSR_EC_UNKNOWN (0x00)
194#define HSR_EC_WFI (0x01)
195#define HSR_EC_CP15_32 (0x03)
196#define HSR_EC_CP15_64 (0x04)
197#define HSR_EC_CP14_MR (0x05)
198#define HSR_EC_CP14_LS (0x06)
199#define HSR_EC_CP_0_13 (0x07)
200#define HSR_EC_CP10_ID (0x08)
201#define HSR_EC_JAZELLE (0x09)
202#define HSR_EC_BXJ (0x0A)
203#define HSR_EC_CP14_64 (0x0C)
204#define HSR_EC_SVC_HYP (0x11)
205#define HSR_EC_HVC (0x12)
206#define HSR_EC_SMC (0x13)
207#define HSR_EC_IABT (0x20)
208#define HSR_EC_IABT_HYP (0x21)
209#define HSR_EC_DABT (0x24)
210#define HSR_EC_DABT_HYP (0x25)
211
212#define HSR_HVC_IMM_MASK ((1UL << 16) - 1)
213
214#endif /* __ARM_KVM_ARM_H__ */
diff --git a/arch/arm/include/asm/kvm_asm.h b/arch/arm/include/asm/kvm_asm.h
new file mode 100644
index 000000000000..e4956f4e23e1
--- /dev/null
+++ b/arch/arm/include/asm/kvm_asm.h
@@ -0,0 +1,83 @@
1/*
2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
3 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19#ifndef __ARM_KVM_ASM_H__
20#define __ARM_KVM_ASM_H__
21
22/* 0 is reserved as an invalid value. */
23#define c0_MPIDR 1 /* MultiProcessor ID Register */
24#define c0_CSSELR 2 /* Cache Size Selection Register */
25#define c1_SCTLR 3 /* System Control Register */
26#define c1_ACTLR 4 /* Auxilliary Control Register */
27#define c1_CPACR 5 /* Coprocessor Access Control */
28#define c2_TTBR0 6 /* Translation Table Base Register 0 */
29#define c2_TTBR0_high 7 /* TTBR0 top 32 bits */
30#define c2_TTBR1 8 /* Translation Table Base Register 1 */
31#define c2_TTBR1_high 9 /* TTBR1 top 32 bits */
32#define c2_TTBCR 10 /* Translation Table Base Control R. */
33#define c3_DACR 11 /* Domain Access Control Register */
34#define c5_DFSR 12 /* Data Fault Status Register */
35#define c5_IFSR 13 /* Instruction Fault Status Register */
36#define c5_ADFSR 14 /* Auxilary Data Fault Status R */
37#define c5_AIFSR 15 /* Auxilary Instrunction Fault Status R */
38#define c6_DFAR 16 /* Data Fault Address Register */
39#define c6_IFAR 17 /* Instruction Fault Address Register */
40#define c9_L2CTLR 18 /* Cortex A15 L2 Control Register */
41#define c10_PRRR 19 /* Primary Region Remap Register */
42#define c10_NMRR 20 /* Normal Memory Remap Register */
43#define c12_VBAR 21 /* Vector Base Address Register */
44#define c13_CID 22 /* Context ID Register */
45#define c13_TID_URW 23 /* Thread ID, User R/W */
46#define c13_TID_URO 24 /* Thread ID, User R/O */
47#define c13_TID_PRIV 25 /* Thread ID, Privileged */
48#define c14_CNTKCTL 26 /* Timer Control Register (PL1) */
49#define NR_CP15_REGS 27 /* Number of regs (incl. invalid) */
50
51#define ARM_EXCEPTION_RESET 0
52#define ARM_EXCEPTION_UNDEFINED 1
53#define ARM_EXCEPTION_SOFTWARE 2
54#define ARM_EXCEPTION_PREF_ABORT 3
55#define ARM_EXCEPTION_DATA_ABORT 4
56#define ARM_EXCEPTION_IRQ 5
57#define ARM_EXCEPTION_FIQ 6
58#define ARM_EXCEPTION_HVC 7
59
60#ifndef __ASSEMBLY__
61struct kvm;
62struct kvm_vcpu;
63
64extern char __kvm_hyp_init[];
65extern char __kvm_hyp_init_end[];
66
67extern char __kvm_hyp_exit[];
68extern char __kvm_hyp_exit_end[];
69
70extern char __kvm_hyp_vector[];
71
72extern char __kvm_hyp_code_start[];
73extern char __kvm_hyp_code_end[];
74
75extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
76
77extern void __kvm_flush_vm_context(void);
78extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
79
80extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
81#endif
82
83#endif /* __ARM_KVM_ASM_H__ */
diff --git a/arch/arm/include/asm/kvm_coproc.h b/arch/arm/include/asm/kvm_coproc.h
new file mode 100644
index 000000000000..4917c2f7e459
--- /dev/null
+++ b/arch/arm/include/asm/kvm_coproc.h
@@ -0,0 +1,47 @@
1/*
2 * Copyright (C) 2012 Rusty Russell IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License, version 2, as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
16 */
17
18#ifndef __ARM_KVM_COPROC_H__
19#define __ARM_KVM_COPROC_H__
20#include <linux/kvm_host.h>
21
22void kvm_reset_coprocs(struct kvm_vcpu *vcpu);
23
24struct kvm_coproc_target_table {
25 unsigned target;
26 const struct coproc_reg *table;
27 size_t num;
28};
29void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table);
30
31int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run);
32int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run);
33int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run);
34int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run);
35int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run);
36int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run);
37
38unsigned long kvm_arm_num_guest_msrs(struct kvm_vcpu *vcpu);
39int kvm_arm_copy_msrindices(struct kvm_vcpu *vcpu, u64 __user *uindices);
40void kvm_coproc_table_init(void);
41
42struct kvm_one_reg;
43int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
44int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
45int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
46unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu);
47#endif /* __ARM_KVM_COPROC_H__ */
diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h
new file mode 100644
index 000000000000..fd611996bfb5
--- /dev/null
+++ b/arch/arm/include/asm/kvm_emulate.h
@@ -0,0 +1,72 @@
1/*
2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
3 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19#ifndef __ARM_KVM_EMULATE_H__
20#define __ARM_KVM_EMULATE_H__
21
22#include <linux/kvm_host.h>
23#include <asm/kvm_asm.h>
24#include <asm/kvm_mmio.h>
25
26u32 *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num);
27u32 *vcpu_spsr(struct kvm_vcpu *vcpu);
28
29int kvm_handle_wfi(struct kvm_vcpu *vcpu, struct kvm_run *run);
30void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr);
31void kvm_inject_undefined(struct kvm_vcpu *vcpu);
32void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
33void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
34
35static inline bool vcpu_mode_is_32bit(struct kvm_vcpu *vcpu)
36{
37 return 1;
38}
39
40static inline u32 *vcpu_pc(struct kvm_vcpu *vcpu)
41{
42 return (u32 *)&vcpu->arch.regs.usr_regs.ARM_pc;
43}
44
45static inline u32 *vcpu_cpsr(struct kvm_vcpu *vcpu)
46{
47 return (u32 *)&vcpu->arch.regs.usr_regs.ARM_cpsr;
48}
49
50static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
51{
52 *vcpu_cpsr(vcpu) |= PSR_T_BIT;
53}
54
55static inline bool mode_has_spsr(struct kvm_vcpu *vcpu)
56{
57 unsigned long cpsr_mode = vcpu->arch.regs.usr_regs.ARM_cpsr & MODE_MASK;
58 return (cpsr_mode > USR_MODE && cpsr_mode < SYSTEM_MODE);
59}
60
61static inline bool vcpu_mode_priv(struct kvm_vcpu *vcpu)
62{
63 unsigned long cpsr_mode = vcpu->arch.regs.usr_regs.ARM_cpsr & MODE_MASK;
64 return cpsr_mode > USR_MODE;;
65}
66
67static inline bool kvm_vcpu_reg_is_pc(struct kvm_vcpu *vcpu, int reg)
68{
69 return reg == 15;
70}
71
72#endif /* __ARM_KVM_EMULATE_H__ */
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
new file mode 100644
index 000000000000..d1736a53b12d
--- /dev/null
+++ b/arch/arm/include/asm/kvm_host.h
@@ -0,0 +1,184 @@
1/*
2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
3 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19#ifndef __ARM_KVM_HOST_H__
20#define __ARM_KVM_HOST_H__
21
22#include <asm/kvm.h>
23#include <asm/kvm_asm.h>
24#include <asm/kvm_mmio.h>
25#include <asm/fpstate.h>
26#include <asm/kvm_arch_timer.h>
27
28#define KVM_MAX_VCPUS CONFIG_KVM_ARM_MAX_VCPUS
29#define KVM_USER_MEM_SLOTS 32
30#define KVM_PRIVATE_MEM_SLOTS 4
31#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
32#define KVM_HAVE_ONE_REG
33
34#define KVM_VCPU_MAX_FEATURES 1
35
36/* We don't currently support large pages. */
37#define KVM_HPAGE_GFN_SHIFT(x) 0
38#define KVM_NR_PAGE_SIZES 1
39#define KVM_PAGES_PER_HPAGE(x) (1UL<<31)
40
41#include <asm/kvm_vgic.h>
42
43struct kvm_vcpu;
44u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode);
45int kvm_target_cpu(void);
46int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
47void kvm_reset_coprocs(struct kvm_vcpu *vcpu);
48
49struct kvm_arch {
50 /* VTTBR value associated with below pgd and vmid */
51 u64 vttbr;
52
53 /* Timer */
54 struct arch_timer_kvm timer;
55
56 /*
57 * Anything that is not used directly from assembly code goes
58 * here.
59 */
60
61 /* The VMID generation used for the virt. memory system */
62 u64 vmid_gen;
63 u32 vmid;
64
65 /* Stage-2 page table */
66 pgd_t *pgd;
67
68 /* Interrupt controller */
69 struct vgic_dist vgic;
70};
71
72#define KVM_NR_MEM_OBJS 40
73
74/*
75 * We don't want allocation failures within the mmu code, so we preallocate
76 * enough memory for a single page fault in a cache.
77 */
78struct kvm_mmu_memory_cache {
79 int nobjs;
80 void *objects[KVM_NR_MEM_OBJS];
81};
82
83struct kvm_vcpu_arch {
84 struct kvm_regs regs;
85
86 int target; /* Processor target */
87 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
88
89 /* System control coprocessor (cp15) */
90 u32 cp15[NR_CP15_REGS];
91
92 /* The CPU type we expose to the VM */
93 u32 midr;
94
95 /* Exception Information */
96 u32 hsr; /* Hyp Syndrome Register */
97 u32 hxfar; /* Hyp Data/Inst Fault Address Register */
98 u32 hpfar; /* Hyp IPA Fault Address Register */
99
100 /* Floating point registers (VFP and Advanced SIMD/NEON) */
101 struct vfp_hard_struct vfp_guest;
102 struct vfp_hard_struct *vfp_host;
103
104 /* VGIC state */
105 struct vgic_cpu vgic_cpu;
106 struct arch_timer_cpu timer_cpu;
107
108 /*
109 * Anything that is not used directly from assembly code goes
110 * here.
111 */
112 /* dcache set/way operation pending */
113 int last_pcpu;
114 cpumask_t require_dcache_flush;
115
116 /* Don't run the guest on this vcpu */
117 bool pause;
118
119 /* IO related fields */
120 struct kvm_decode mmio_decode;
121
122 /* Interrupt related fields */
123 u32 irq_lines; /* IRQ and FIQ levels */
124
125 /* Hyp exception information */
126 u32 hyp_pc; /* PC when exception was taken from Hyp mode */
127
128 /* Cache some mmu pages needed inside spinlock regions */
129 struct kvm_mmu_memory_cache mmu_page_cache;
130
131 /* Detect first run of a vcpu */
132 bool has_run_once;
133};
134
135struct kvm_vm_stat {
136 u32 remote_tlb_flush;
137};
138
139struct kvm_vcpu_stat {
140 u32 halt_wakeup;
141};
142
143struct kvm_vcpu_init;
144int kvm_vcpu_set_target(struct kvm_vcpu *vcpu,
145 const struct kvm_vcpu_init *init);
146unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
147int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
148struct kvm_one_reg;
149int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
150int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
151u64 kvm_call_hyp(void *hypfn, ...);
152void force_vm_exit(const cpumask_t *mask);
153
154#define KVM_ARCH_WANT_MMU_NOTIFIER
155struct kvm;
156int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
157int kvm_unmap_hva_range(struct kvm *kvm,
158 unsigned long start, unsigned long end);
159void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
160
161unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
162int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
163
164/* We do not have shadow page tables, hence the empty hooks */
165static inline int kvm_age_hva(struct kvm *kvm, unsigned long hva)
166{
167 return 0;
168}
169
170static inline int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
171{
172 return 0;
173}
174
175struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
176struct kvm_vcpu __percpu **kvm_get_running_vcpus(void);
177
178int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
179unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu);
180struct kvm_one_reg;
181int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
182int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
183
184#endif /* __ARM_KVM_HOST_H__ */
diff --git a/arch/arm/include/asm/kvm_mmio.h b/arch/arm/include/asm/kvm_mmio.h
new file mode 100644
index 000000000000..adcc0d7d3175
--- /dev/null
+++ b/arch/arm/include/asm/kvm_mmio.h
@@ -0,0 +1,56 @@
1/*
2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
3 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19#ifndef __ARM_KVM_MMIO_H__
20#define __ARM_KVM_MMIO_H__
21
22#include <linux/kvm_host.h>
23#include <asm/kvm_asm.h>
24#include <asm/kvm_arm.h>
25
26struct kvm_decode {
27 unsigned long rt;
28 bool sign_extend;
29};
30
31/*
32 * The in-kernel MMIO emulation code wants to use a copy of run->mmio,
33 * which is an anonymous type. Use our own type instead.
34 */
35struct kvm_exit_mmio {
36 phys_addr_t phys_addr;
37 u8 data[8];
38 u32 len;
39 bool is_write;
40};
41
42static inline void kvm_prepare_mmio(struct kvm_run *run,
43 struct kvm_exit_mmio *mmio)
44{
45 run->mmio.phys_addr = mmio->phys_addr;
46 run->mmio.len = mmio->len;
47 run->mmio.is_write = mmio->is_write;
48 memcpy(run->mmio.data, mmio->data, mmio->len);
49 run->exit_reason = KVM_EXIT_MMIO;
50}
51
52int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
53int io_mem_abort(struct kvm_vcpu *vcpu, struct kvm_run *run,
54 phys_addr_t fault_ipa);
55
56#endif /* __ARM_KVM_MMIO_H__ */
diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
new file mode 100644
index 000000000000..421a20b34874
--- /dev/null
+++ b/arch/arm/include/asm/kvm_mmu.h
@@ -0,0 +1,50 @@
1/*
2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
3 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19#ifndef __ARM_KVM_MMU_H__
20#define __ARM_KVM_MMU_H__
21
22int create_hyp_mappings(void *from, void *to);
23int create_hyp_io_mappings(void *from, void *to, phys_addr_t);
24void free_hyp_pmds(void);
25
26int kvm_alloc_stage2_pgd(struct kvm *kvm);
27void kvm_free_stage2_pgd(struct kvm *kvm);
28int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
29 phys_addr_t pa, unsigned long size);
30
31int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
32
33void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
34
35phys_addr_t kvm_mmu_get_httbr(void);
36int kvm_mmu_init(void);
37void kvm_clear_hyp_idmap(void);
38
39static inline bool kvm_is_write_fault(unsigned long hsr)
40{
41 unsigned long hsr_ec = hsr >> HSR_EC_SHIFT;
42 if (hsr_ec == HSR_EC_IABT)
43 return false;
44 else if ((hsr & HSR_ISV) && !(hsr & HSR_WNR))
45 return false;
46 else
47 return true;
48}
49
50#endif /* __ARM_KVM_MMU_H__ */
diff --git a/arch/arm/include/asm/kvm_psci.h b/arch/arm/include/asm/kvm_psci.h
new file mode 100644
index 000000000000..9a83d98bf170
--- /dev/null
+++ b/arch/arm/include/asm/kvm_psci.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright (C) 2012 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __ARM_KVM_PSCI_H__
19#define __ARM_KVM_PSCI_H__
20
21bool kvm_psci_call(struct kvm_vcpu *vcpu);
22
23#endif /* __ARM_KVM_PSCI_H__ */
diff --git a/arch/arm/include/asm/kvm_vgic.h b/arch/arm/include/asm/kvm_vgic.h
new file mode 100644
index 000000000000..ab97207d9cd3
--- /dev/null
+++ b/arch/arm/include/asm/kvm_vgic.h
@@ -0,0 +1,221 @@
1/*
2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef __ASM_ARM_KVM_VGIC_H
20#define __ASM_ARM_KVM_VGIC_H
21
22#include <linux/kernel.h>
23#include <linux/kvm.h>
24#include <linux/kvm_host.h>
25#include <linux/irqreturn.h>
26#include <linux/spinlock.h>
27#include <linux/types.h>
28#include <linux/irqchip/arm-gic.h>
29
30#define VGIC_NR_IRQS 128
31#define VGIC_NR_SGIS 16
32#define VGIC_NR_PPIS 16
33#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
34#define VGIC_NR_SHARED_IRQS (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
35#define VGIC_MAX_CPUS KVM_MAX_VCPUS
36#define VGIC_MAX_LRS (1 << 6)
37
38/* Sanity checks... */
39#if (VGIC_MAX_CPUS > 8)
40#error Invalid number of CPU interfaces
41#endif
42
43#if (VGIC_NR_IRQS & 31)
44#error "VGIC_NR_IRQS must be a multiple of 32"
45#endif
46
47#if (VGIC_NR_IRQS > 1024)
48#error "VGIC_NR_IRQS must be <= 1024"
49#endif
50
51/*
52 * The GIC distributor registers describing interrupts have two parts:
53 * - 32 per-CPU interrupts (SGI + PPI)
54 * - a bunch of shared interrupts (SPI)
55 */
56struct vgic_bitmap {
57 union {
58 u32 reg[VGIC_NR_PRIVATE_IRQS / 32];
59 DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS);
60 } percpu[VGIC_MAX_CPUS];
61 union {
62 u32 reg[VGIC_NR_SHARED_IRQS / 32];
63 DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS);
64 } shared;
65};
66
67struct vgic_bytemap {
68 u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4];
69 u32 shared[VGIC_NR_SHARED_IRQS / 4];
70};
71
72struct vgic_dist {
73#ifdef CONFIG_KVM_ARM_VGIC
74 spinlock_t lock;
75 bool ready;
76
77 /* Virtual control interface mapping */
78 void __iomem *vctrl_base;
79
80 /* Distributor and vcpu interface mapping in the guest */
81 phys_addr_t vgic_dist_base;
82 phys_addr_t vgic_cpu_base;
83
84 /* Distributor enabled */
85 u32 enabled;
86
87 /* Interrupt enabled (one bit per IRQ) */
88 struct vgic_bitmap irq_enabled;
89
90 /* Interrupt 'pin' level */
91 struct vgic_bitmap irq_state;
92
93 /* Level-triggered interrupt in progress */
94 struct vgic_bitmap irq_active;
95
96 /* Interrupt priority. Not used yet. */
97 struct vgic_bytemap irq_priority;
98
99 /* Level/edge triggered */
100 struct vgic_bitmap irq_cfg;
101
102 /* Source CPU per SGI and target CPU */
103 u8 irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS];
104
105 /* Target CPU for each IRQ */
106 u8 irq_spi_cpu[VGIC_NR_SHARED_IRQS];
107 struct vgic_bitmap irq_spi_target[VGIC_MAX_CPUS];
108
109 /* Bitmap indicating which CPU has something pending */
110 unsigned long irq_pending_on_cpu;
111#endif
112};
113
114struct vgic_cpu {
115#ifdef CONFIG_KVM_ARM_VGIC
116 /* per IRQ to LR mapping */
117 u8 vgic_irq_lr_map[VGIC_NR_IRQS];
118
119 /* Pending interrupts on this VCPU */
120 DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
121 DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS);
122
123 /* Bitmap of used/free list registers */
124 DECLARE_BITMAP( lr_used, VGIC_MAX_LRS);
125
126 /* Number of list registers on this CPU */
127 int nr_lr;
128
129 /* CPU vif control registers for world switch */
130 u32 vgic_hcr;
131 u32 vgic_vmcr;
132 u32 vgic_misr; /* Saved only */
133 u32 vgic_eisr[2]; /* Saved only */
134 u32 vgic_elrsr[2]; /* Saved only */
135 u32 vgic_apr;
136 u32 vgic_lr[VGIC_MAX_LRS];
137#endif
138};
139
140#define LR_EMPTY 0xff
141
142struct kvm;
143struct kvm_vcpu;
144struct kvm_run;
145struct kvm_exit_mmio;
146
147#ifdef CONFIG_KVM_ARM_VGIC
148int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr);
149int kvm_vgic_hyp_init(void);
150int kvm_vgic_init(struct kvm *kvm);
151int kvm_vgic_create(struct kvm *kvm);
152int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
153void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
154void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
155int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
156 bool level);
157int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
158bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
159 struct kvm_exit_mmio *mmio);
160
161#define irqchip_in_kernel(k) (!!((k)->arch.vgic.vctrl_base))
162#define vgic_initialized(k) ((k)->arch.vgic.ready)
163
164#else
165static inline int kvm_vgic_hyp_init(void)
166{
167 return 0;
168}
169
170static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
171{
172 return 0;
173}
174
175static inline int kvm_vgic_init(struct kvm *kvm)
176{
177 return 0;
178}
179
180static inline int kvm_vgic_create(struct kvm *kvm)
181{
182 return 0;
183}
184
185static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
186{
187 return 0;
188}
189
190static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
191static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}
192
193static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
194 unsigned int irq_num, bool level)
195{
196 return 0;
197}
198
199static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
200{
201 return 0;
202}
203
204static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
205 struct kvm_exit_mmio *mmio)
206{
207 return false;
208}
209
210static inline int irqchip_in_kernel(struct kvm *kvm)
211{
212 return 0;
213}
214
215static inline bool vgic_initialized(struct kvm *kvm)
216{
217 return true;
218}
219#endif
220
221#endif
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 917d4fcfd9b4..308ad7d6f98b 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -12,7 +12,6 @@
12 12
13struct tag; 13struct tag;
14struct meminfo; 14struct meminfo;
15struct sys_timer;
16struct pt_regs; 15struct pt_regs;
17struct smp_operations; 16struct smp_operations;
18#ifdef CONFIG_SMP 17#ifdef CONFIG_SMP
@@ -48,7 +47,7 @@ struct machine_desc {
48 void (*map_io)(void);/* IO mapping function */ 47 void (*map_io)(void);/* IO mapping function */
49 void (*init_early)(void); 48 void (*init_early)(void);
50 void (*init_irq)(void); 49 void (*init_irq)(void);
51 struct sys_timer *timer; /* system tick timer */ 50 void (*init_time)(void);
52 void (*init_machine)(void); 51 void (*init_machine)(void);
53 void (*init_late)(void); 52 void (*init_late)(void);
54#ifdef CONFIG_MULTI_IRQ_HANDLER 53#ifdef CONFIG_MULTI_IRQ_HANDLER
diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h
index 15cb035309f7..18c883023339 100644
--- a/arch/arm/include/asm/mach/irq.h
+++ b/arch/arm/include/asm/mach/irq.h
@@ -22,6 +22,7 @@ extern int show_fiq_list(struct seq_file *, int);
22 22
23#ifdef CONFIG_MULTI_IRQ_HANDLER 23#ifdef CONFIG_MULTI_IRQ_HANDLER
24extern void (*handle_arch_irq)(struct pt_regs *); 24extern void (*handle_arch_irq)(struct pt_regs *);
25extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
25#endif 26#endif
26 27
27/* 28/*
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index db9fedb57f2c..5cf2e979b4be 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -23,6 +23,7 @@ struct hw_pci {
23#endif 23#endif
24 struct pci_ops *ops; 24 struct pci_ops *ops;
25 int nr_controllers; 25 int nr_controllers;
26 void **private_data;
26 int (*setup)(int nr, struct pci_sys_data *); 27 int (*setup)(int nr, struct pci_sys_data *);
27 struct pci_bus *(*scan)(int nr, struct pci_sys_data *); 28 struct pci_bus *(*scan)(int nr, struct pci_sys_data *);
28 void (*preinit)(void); 29 void (*preinit)(void);
diff --git a/arch/arm/include/asm/mach/time.h b/arch/arm/include/asm/mach/time.h
index 6ca945f534ab..90c12e1e695c 100644
--- a/arch/arm/include/asm/mach/time.h
+++ b/arch/arm/include/asm/mach/time.h
@@ -10,36 +10,6 @@
10#ifndef __ASM_ARM_MACH_TIME_H 10#ifndef __ASM_ARM_MACH_TIME_H
11#define __ASM_ARM_MACH_TIME_H 11#define __ASM_ARM_MACH_TIME_H
12 12
13/*
14 * This is our kernel timer structure.
15 *
16 * - init
17 * Initialise the kernels jiffy timer source, claim interrupt
18 * using setup_irq. This is called early on during initialisation
19 * while interrupts are still disabled on the local CPU.
20 * - suspend
21 * Suspend the kernel jiffy timer source, if necessary. This
22 * is called with interrupts disabled, after all normal devices
23 * have been suspended. If no action is required, set this to
24 * NULL.
25 * - resume
26 * Resume the kernel jiffy timer source, if necessary. This
27 * is called with interrupts disabled before any normal devices
28 * are resumed. If no action is required, set this to NULL.
29 * - offset
30 * Return the timer offset in microseconds since the last timer
31 * interrupt. Note: this must take account of any unprocessed
32 * timer interrupt which may be pending.
33 */
34struct sys_timer {
35 void (*init)(void);
36 void (*suspend)(void);
37 void (*resume)(void);
38#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
39 unsigned long (*offset)(void);
40#endif
41};
42
43extern void timer_tick(void); 13extern void timer_tick(void);
44 14
45struct timespec; 15struct timespec;
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 73cf03aa981e..57870ab313c5 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -36,23 +36,23 @@
36 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area 36 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
37 */ 37 */
38#define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET) 38#define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET)
39#define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(0x01000000)) 39#define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(SZ_16M))
40#define TASK_UNMAPPED_BASE (UL(CONFIG_PAGE_OFFSET) / 3) 40#define TASK_UNMAPPED_BASE ALIGN(TASK_SIZE / 3, SZ_16M)
41 41
42/* 42/*
43 * The maximum size of a 26-bit user space task. 43 * The maximum size of a 26-bit user space task.
44 */ 44 */
45#define TASK_SIZE_26 UL(0x04000000) 45#define TASK_SIZE_26 (UL(1) << 26)
46 46
47/* 47/*
48 * The module space lives between the addresses given by TASK_SIZE 48 * The module space lives between the addresses given by TASK_SIZE
49 * and PAGE_OFFSET - it must be within 32MB of the kernel text. 49 * and PAGE_OFFSET - it must be within 32MB of the kernel text.
50 */ 50 */
51#ifndef CONFIG_THUMB2_KERNEL 51#ifndef CONFIG_THUMB2_KERNEL
52#define MODULES_VADDR (PAGE_OFFSET - 16*1024*1024) 52#define MODULES_VADDR (PAGE_OFFSET - SZ_16M)
53#else 53#else
54/* smaller range for Thumb-2 symbols relocation (2^24)*/ 54/* smaller range for Thumb-2 symbols relocation (2^24)*/
55#define MODULES_VADDR (PAGE_OFFSET - 8*1024*1024) 55#define MODULES_VADDR (PAGE_OFFSET - SZ_8M)
56#endif 56#endif
57 57
58#if TASK_SIZE > MODULES_VADDR 58#if TASK_SIZE > MODULES_VADDR
@@ -245,6 +245,7 @@ static inline void *phys_to_virt(phys_addr_t x)
245#define __bus_to_pfn(x) __phys_to_pfn(x) 245#define __bus_to_pfn(x) __phys_to_pfn(x)
246#endif 246#endif
247 247
248#ifdef CONFIG_VIRT_TO_BUS
248static inline __deprecated unsigned long virt_to_bus(void *x) 249static inline __deprecated unsigned long virt_to_bus(void *x)
249{ 250{
250 return __virt_to_bus((unsigned long)x); 251 return __virt_to_bus((unsigned long)x);
@@ -254,6 +255,7 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
254{ 255{
255 return (void *)__bus_to_virt(x); 256 return (void *)__bus_to_virt(x);
256} 257}
258#endif
257 259
258/* 260/*
259 * Conversion between a struct page and a physical address. 261 * Conversion between a struct page and a physical address.
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index 9f77e7804f3b..e3d55547e755 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -5,15 +5,15 @@
5 5
6typedef struct { 6typedef struct {
7#ifdef CONFIG_CPU_HAS_ASID 7#ifdef CONFIG_CPU_HAS_ASID
8 u64 id; 8 atomic64_t id;
9#endif 9#endif
10 unsigned int vmalloc_seq; 10 unsigned int vmalloc_seq;
11} mm_context_t; 11} mm_context_t;
12 12
13#ifdef CONFIG_CPU_HAS_ASID 13#ifdef CONFIG_CPU_HAS_ASID
14#define ASID_BITS 8 14#define ASID_BITS 8
15#define ASID_MASK ((~0ULL) << ASID_BITS) 15#define ASID_MASK ((~0ULL) << ASID_BITS)
16#define ASID(mm) ((mm)->context.id & ~ASID_MASK) 16#define ASID(mm) ((mm)->context.id.counter & ~ASID_MASK)
17#else 17#else
18#define ASID(mm) (0) 18#define ASID(mm) (0)
19#endif 19#endif
@@ -26,7 +26,7 @@ typedef struct {
26 * modified for 2.6 by Hyok S. Choi <hyok.choi@samsung.com> 26 * modified for 2.6 by Hyok S. Choi <hyok.choi@samsung.com>
27 */ 27 */
28typedef struct { 28typedef struct {
29 unsigned long end_brk; 29 unsigned long end_brk;
30} mm_context_t; 30} mm_context_t;
31 31
32#endif 32#endif
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index e1f644bc7cc5..863a6611323c 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -25,7 +25,7 @@ void __check_vmalloc_seq(struct mm_struct *mm);
25#ifdef CONFIG_CPU_HAS_ASID 25#ifdef CONFIG_CPU_HAS_ASID
26 26
27void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk); 27void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk);
28#define init_new_context(tsk,mm) ({ mm->context.id = 0; }) 28#define init_new_context(tsk,mm) ({ atomic64_set(&mm->context.id, 0); 0; })
29 29
30#else /* !CONFIG_CPU_HAS_ASID */ 30#else /* !CONFIG_CPU_HAS_ASID */
31 31
diff --git a/arch/arm/include/asm/opcodes-sec.h b/arch/arm/include/asm/opcodes-sec.h
new file mode 100644
index 000000000000..bc3a9174417c
--- /dev/null
+++ b/arch/arm/include/asm/opcodes-sec.h
@@ -0,0 +1,24 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * Copyright (C) 2012 ARM Limited
12 */
13
14#ifndef __ASM_ARM_OPCODES_SEC_H
15#define __ASM_ARM_OPCODES_SEC_H
16
17#include <asm/opcodes.h>
18
19#define __SMC(imm4) __inst_arm_thumb32( \
20 0xE1600070 | (((imm4) & 0xF) << 0), \
21 0xF7F08000 | (((imm4) & 0xF) << 16) \
22)
23
24#endif /* __ASM_ARM_OPCODES_SEC_H */
diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
index 74e211a6fb24..e796c598513b 100644
--- a/arch/arm/include/asm/opcodes.h
+++ b/arch/arm/include/asm/opcodes.h
@@ -10,6 +10,7 @@
10#define __ASM_ARM_OPCODES_H 10#define __ASM_ARM_OPCODES_H
11 11
12#ifndef __ASSEMBLY__ 12#ifndef __ASSEMBLY__
13#include <linux/linkage.h>
13extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr); 14extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
14#endif 15#endif
15 16
diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h
index 53426c66352a..12f71a190422 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -92,6 +92,7 @@ static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
92static inline void outer_flush_all(void) { } 92static inline void outer_flush_all(void) { }
93static inline void outer_inv_all(void) { } 93static inline void outer_inv_all(void) { }
94static inline void outer_disable(void) { } 94static inline void outer_disable(void) { }
95static inline void outer_resume(void) { }
95 96
96#endif 97#endif
97 98
diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h
index d7952824c5c4..18f5cef82ad5 100644
--- a/arch/arm/include/asm/pgtable-3level-hwdef.h
+++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
@@ -32,6 +32,9 @@
32#define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) 32#define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0)
33#define PMD_BIT4 (_AT(pmdval_t, 0)) 33#define PMD_BIT4 (_AT(pmdval_t, 0))
34#define PMD_DOMAIN(x) (_AT(pmdval_t, 0)) 34#define PMD_DOMAIN(x) (_AT(pmdval_t, 0))
35#define PMD_APTABLE_SHIFT (61)
36#define PMD_APTABLE (_AT(pgdval_t, 3) << PGD_APTABLE_SHIFT)
37#define PMD_PXNTABLE (_AT(pgdval_t, 1) << 59)
35 38
36/* 39/*
37 * - section 40 * - section
@@ -41,9 +44,11 @@
41#define PMD_SECT_S (_AT(pmdval_t, 3) << 8) 44#define PMD_SECT_S (_AT(pmdval_t, 3) << 8)
42#define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) 45#define PMD_SECT_AF (_AT(pmdval_t, 1) << 10)
43#define PMD_SECT_nG (_AT(pmdval_t, 1) << 11) 46#define PMD_SECT_nG (_AT(pmdval_t, 1) << 11)
47#define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53)
44#define PMD_SECT_XN (_AT(pmdval_t, 1) << 54) 48#define PMD_SECT_XN (_AT(pmdval_t, 1) << 54)
45#define PMD_SECT_AP_WRITE (_AT(pmdval_t, 0)) 49#define PMD_SECT_AP_WRITE (_AT(pmdval_t, 0))
46#define PMD_SECT_AP_READ (_AT(pmdval_t, 0)) 50#define PMD_SECT_AP_READ (_AT(pmdval_t, 0))
51#define PMD_SECT_AP1 (_AT(pmdval_t, 1) << 6)
47#define PMD_SECT_TEX(x) (_AT(pmdval_t, 0)) 52#define PMD_SECT_TEX(x) (_AT(pmdval_t, 0))
48 53
49/* 54/*
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index a3f37929940a..6ef8afd1b64c 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -104,11 +104,29 @@
104 */ 104 */
105#define L_PGD_SWAPPER (_AT(pgdval_t, 1) << 55) /* swapper_pg_dir entry */ 105#define L_PGD_SWAPPER (_AT(pgdval_t, 1) << 55) /* swapper_pg_dir entry */
106 106
107/*
108 * 2nd stage PTE definitions for LPAE.
109 */
110#define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */
111#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */
112#define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */
113#define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */
114#define L_PTE_S2_RDWR (_AT(pteval_t, 2) << 6) /* HAP[2:1] */
115
116/*
117 * Hyp-mode PL2 PTE definitions for LPAE.
118 */
119#define L_PTE_HYP L_PTE_USER
120
107#ifndef __ASSEMBLY__ 121#ifndef __ASSEMBLY__
108 122
109#define pud_none(pud) (!pud_val(pud)) 123#define pud_none(pud) (!pud_val(pud))
110#define pud_bad(pud) (!(pud_val(pud) & 2)) 124#define pud_bad(pud) (!(pud_val(pud) & 2))
111#define pud_present(pud) (pud_val(pud)) 125#define pud_present(pud) (pud_val(pud))
126#define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
127 PMD_TYPE_TABLE)
128#define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
129 PMD_TYPE_SECT)
112 130
113#define pud_clear(pudp) \ 131#define pud_clear(pudp) \
114 do { \ 132 do { \
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 9c82f988c0e3..80d6fc4dbe4a 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -70,6 +70,9 @@ extern void __pgd_error(const char *file, int line, pgd_t);
70 70
71extern pgprot_t pgprot_user; 71extern pgprot_t pgprot_user;
72extern pgprot_t pgprot_kernel; 72extern pgprot_t pgprot_kernel;
73extern pgprot_t pgprot_hyp_device;
74extern pgprot_t pgprot_s2;
75extern pgprot_t pgprot_s2_device;
73 76
74#define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b)) 77#define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b))
75 78
@@ -82,6 +85,10 @@ extern pgprot_t pgprot_kernel;
82#define PAGE_READONLY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY) 85#define PAGE_READONLY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
83#define PAGE_KERNEL _MOD_PROT(pgprot_kernel, L_PTE_XN) 86#define PAGE_KERNEL _MOD_PROT(pgprot_kernel, L_PTE_XN)
84#define PAGE_KERNEL_EXEC pgprot_kernel 87#define PAGE_KERNEL_EXEC pgprot_kernel
88#define PAGE_HYP _MOD_PROT(pgprot_kernel, L_PTE_HYP)
89#define PAGE_HYP_DEVICE _MOD_PROT(pgprot_hyp_device, L_PTE_HYP)
90#define PAGE_S2 _MOD_PROT(pgprot_s2, L_PTE_S2_RDONLY)
91#define PAGE_S2_DEVICE _MOD_PROT(pgprot_s2_device, L_PTE_USER | L_PTE_S2_RDONLY)
85 92
86#define __PAGE_NONE __pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE) 93#define __PAGE_NONE __pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE)
87#define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN) 94#define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)
@@ -240,7 +247,8 @@ static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
240 247
241static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 248static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
242{ 249{
243 const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER | L_PTE_NONE; 250 const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER |
251 L_PTE_NONE | L_PTE_VALID;
244 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 252 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
245 return pte; 253 return pte;
246} 254}
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
new file mode 100644
index 000000000000..ce0dbe7c1625
--- /dev/null
+++ b/arch/arm/include/asm/psci.h
@@ -0,0 +1,36 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * Copyright (C) 2012 ARM Limited
12 */
13
14#ifndef __ASM_ARM_PSCI_H
15#define __ASM_ARM_PSCI_H
16
17#define PSCI_POWER_STATE_TYPE_STANDBY 0
18#define PSCI_POWER_STATE_TYPE_POWER_DOWN 1
19
20struct psci_power_state {
21 u16 id;
22 u8 type;
23 u8 affinity_level;
24};
25
26struct psci_operations {
27 int (*cpu_suspend)(struct psci_power_state state,
28 unsigned long entry_point);
29 int (*cpu_off)(struct psci_power_state state);
30 int (*cpu_on)(unsigned long cpuid, unsigned long entry_point);
31 int (*migrate)(unsigned long cpuid);
32};
33
34extern struct psci_operations psci_ops;
35
36#endif /* __ASM_ARM_PSCI_H */
diff --git a/arch/arm/include/asm/signal.h b/arch/arm/include/asm/signal.h
index 9a0ea6ab988f..c0eb412aff04 100644
--- a/arch/arm/include/asm/signal.h
+++ b/arch/arm/include/asm/signal.h
@@ -16,23 +16,7 @@ typedef struct {
16 unsigned long sig[_NSIG_WORDS]; 16 unsigned long sig[_NSIG_WORDS];
17} sigset_t; 17} sigset_t;
18 18
19struct old_sigaction { 19#define __ARCH_HAS_SA_RESTORER
20 __sighandler_t sa_handler;
21 old_sigset_t sa_mask;
22 unsigned long sa_flags;
23 __sigrestore_t sa_restorer;
24};
25
26struct sigaction {
27 __sighandler_t sa_handler;
28 unsigned long sa_flags;
29 __sigrestore_t sa_restorer;
30 sigset_t sa_mask; /* mask last for extensibility */
31};
32
33struct k_sigaction {
34 struct sigaction sa;
35};
36 20
37#include <asm/sigcontext.h> 21#include <asm/sigcontext.h>
38#endif 22#endif
diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h
index 4eb6d005ffaa..18d169373612 100644
--- a/arch/arm/include/asm/smp_scu.h
+++ b/arch/arm/include/asm/smp_scu.h
@@ -6,9 +6,32 @@
6#define SCU_PM_POWEROFF 3 6#define SCU_PM_POWEROFF 3
7 7
8#ifndef __ASSEMBLER__ 8#ifndef __ASSEMBLER__
9
10#include <asm/cputype.h>
11
12static inline bool scu_a9_has_base(void)
13{
14 return read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9;
15}
16
17static inline unsigned long scu_a9_get_base(void)
18{
19 unsigned long pa;
20
21 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (pa));
22
23 return pa;
24}
25
9unsigned int scu_get_core_count(void __iomem *); 26unsigned int scu_get_core_count(void __iomem *);
10void scu_enable(void __iomem *);
11int scu_power_mode(void __iomem *, unsigned int); 27int scu_power_mode(void __iomem *, unsigned int);
28
29#ifdef CONFIG_SMP
30void scu_enable(void __iomem *scu_base);
31#else
32static inline void scu_enable(void __iomem *scu_base) {}
33#endif
34
12#endif 35#endif
13 36
14#endif 37#endif
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index b4ca707d0a69..6220e9fdf4c7 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -119,22 +119,8 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
119 119
120static inline void arch_spin_unlock(arch_spinlock_t *lock) 120static inline void arch_spin_unlock(arch_spinlock_t *lock)
121{ 121{
122 unsigned long tmp;
123 u32 slock;
124
125 smp_mb(); 122 smp_mb();
126 123 lock->tickets.owner++;
127 __asm__ __volatile__(
128" mov %1, #1\n"
129"1: ldrex %0, [%2]\n"
130" uadd16 %0, %0, %1\n"
131" strex %1, %0, [%2]\n"
132" teq %1, #0\n"
133" bne 1b"
134 : "=&r" (slock), "=&r" (tmp)
135 : "r" (&lock->slock)
136 : "cc");
137
138 dsb_sev(); 124 dsb_sev();
139} 125}
140 126
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 6e924d3a77eb..4db8c8820f0d 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -34,10 +34,13 @@
34#define TLB_V6_D_ASID (1 << 17) 34#define TLB_V6_D_ASID (1 << 17)
35#define TLB_V6_I_ASID (1 << 18) 35#define TLB_V6_I_ASID (1 << 18)
36 36
37#define TLB_V6_BP (1 << 19)
38
37/* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */ 39/* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */
38#define TLB_V7_UIS_PAGE (1 << 19) 40#define TLB_V7_UIS_PAGE (1 << 20)
39#define TLB_V7_UIS_FULL (1 << 20) 41#define TLB_V7_UIS_FULL (1 << 21)
40#define TLB_V7_UIS_ASID (1 << 21) 42#define TLB_V7_UIS_ASID (1 << 22)
43#define TLB_V7_UIS_BP (1 << 23)
41 44
42#define TLB_BARRIER (1 << 28) 45#define TLB_BARRIER (1 << 28)
43#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */ 46#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */
@@ -150,7 +153,8 @@
150#define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \ 153#define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
151 TLB_V6_I_FULL | TLB_V6_D_FULL | \ 154 TLB_V6_I_FULL | TLB_V6_D_FULL | \
152 TLB_V6_I_PAGE | TLB_V6_D_PAGE | \ 155 TLB_V6_I_PAGE | TLB_V6_D_PAGE | \
153 TLB_V6_I_ASID | TLB_V6_D_ASID) 156 TLB_V6_I_ASID | TLB_V6_D_ASID | \
157 TLB_V6_BP)
154 158
155#ifdef CONFIG_CPU_TLB_V6 159#ifdef CONFIG_CPU_TLB_V6
156# define v6wbi_possible_flags v6wbi_tlb_flags 160# define v6wbi_possible_flags v6wbi_tlb_flags
@@ -166,9 +170,11 @@
166#endif 170#endif
167 171
168#define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \ 172#define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
169 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID) 173 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | \
174 TLB_V7_UIS_ASID | TLB_V7_UIS_BP)
170#define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \ 175#define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
171 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID) 176 TLB_V6_U_FULL | TLB_V6_U_PAGE | \
177 TLB_V6_U_ASID | TLB_V6_BP)
172 178
173#ifdef CONFIG_CPU_TLB_V7 179#ifdef CONFIG_CPU_TLB_V7
174 180
@@ -430,6 +436,20 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
430 } 436 }
431} 437}
432 438
439static inline void local_flush_bp_all(void)
440{
441 const int zero = 0;
442 const unsigned int __tlb_flag = __cpu_tlb_flags;
443
444 if (tlb_flag(TLB_V7_UIS_BP))
445 asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero));
446 else if (tlb_flag(TLB_V6_BP))
447 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero));
448
449 if (tlb_flag(TLB_BARRIER))
450 isb();
451}
452
433/* 453/*
434 * flush_pmd_entry 454 * flush_pmd_entry
435 * 455 *
@@ -480,6 +500,7 @@ static inline void clean_pmd_entry(void *pmd)
480#define flush_tlb_kernel_page local_flush_tlb_kernel_page 500#define flush_tlb_kernel_page local_flush_tlb_kernel_page
481#define flush_tlb_range local_flush_tlb_range 501#define flush_tlb_range local_flush_tlb_range
482#define flush_tlb_kernel_range local_flush_tlb_kernel_range 502#define flush_tlb_kernel_range local_flush_tlb_kernel_range
503#define flush_bp_all local_flush_bp_all
483#else 504#else
484extern void flush_tlb_all(void); 505extern void flush_tlb_all(void);
485extern void flush_tlb_mm(struct mm_struct *mm); 506extern void flush_tlb_mm(struct mm_struct *mm);
@@ -487,6 +508,7 @@ extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
487extern void flush_tlb_kernel_page(unsigned long kaddr); 508extern void flush_tlb_kernel_page(unsigned long kaddr);
488extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); 509extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
489extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); 510extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
511extern void flush_bp_all(void);
490#endif 512#endif
491 513
492/* 514/*
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 21a2700d2957..e4ddfb39ca34 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -26,8 +26,6 @@
26#define __ARCH_WANT_SYS_NICE 26#define __ARCH_WANT_SYS_NICE
27#define __ARCH_WANT_SYS_SIGPENDING 27#define __ARCH_WANT_SYS_SIGPENDING
28#define __ARCH_WANT_SYS_SIGPROCMASK 28#define __ARCH_WANT_SYS_SIGPROCMASK
29#define __ARCH_WANT_SYS_RT_SIGACTION
30#define __ARCH_WANT_SYS_RT_SIGSUSPEND
31#define __ARCH_WANT_SYS_OLD_MMAP 29#define __ARCH_WANT_SYS_OLD_MMAP
32#define __ARCH_WANT_SYS_OLD_SELECT 30#define __ARCH_WANT_SYS_OLD_SELECT
33 31
diff --git a/arch/arm/include/asm/virt.h b/arch/arm/include/asm/virt.h
index 86164df86cb4..50af92bac737 100644
--- a/arch/arm/include/asm/virt.h
+++ b/arch/arm/include/asm/virt.h
@@ -24,9 +24,9 @@
24/* 24/*
25 * Flag indicating that the kernel was not entered in the same mode on every 25 * Flag indicating that the kernel was not entered in the same mode on every
26 * CPU. The zImage loader stashes this value in an SPSR, so we need an 26 * CPU. The zImage loader stashes this value in an SPSR, so we need an
27 * architecturally defined flag bit here (the N flag, as it happens) 27 * architecturally defined flag bit here.
28 */ 28 */
29#define BOOT_CPU_MODE_MISMATCH (1<<31) 29#define BOOT_CPU_MODE_MISMATCH PSR_N_BIT
30 30
31#ifndef __ASSEMBLY__ 31#ifndef __ASSEMBLY__
32 32
diff --git a/arch/arm/include/asm/xen/events.h b/arch/arm/include/asm/xen/events.h
index 94b4e9020b02..8b1f37bfeeec 100644
--- a/arch/arm/include/asm/xen/events.h
+++ b/arch/arm/include/asm/xen/events.h
@@ -2,6 +2,7 @@
2#define _ASM_ARM_XEN_EVENTS_H 2#define _ASM_ARM_XEN_EVENTS_H
3 3
4#include <asm/ptrace.h> 4#include <asm/ptrace.h>
5#include <asm/atomic.h>
5 6
6enum ipi_vector { 7enum ipi_vector {
7 XEN_PLACEHOLDER_VECTOR, 8 XEN_PLACEHOLDER_VECTOR,
@@ -15,4 +16,8 @@ static inline int xen_irqs_disabled(struct pt_regs *regs)
15 return raw_irqs_disabled_flags(regs->ARM_cpsr); 16 return raw_irqs_disabled_flags(regs->ARM_cpsr);
16} 17}
17 18
19#define xchg_xen_ulong(ptr, val) atomic64_xchg(container_of((ptr), \
20 atomic64_t, \
21 counter), (val))
22
18#endif /* _ASM_ARM_XEN_EVENTS_H */ 23#endif /* _ASM_ARM_XEN_EVENTS_H */
diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
index c6b9096cef95..30cdacb675af 100644
--- a/arch/arm/include/asm/xen/page.h
+++ b/arch/arm/include/asm/xen/page.h
@@ -1,6 +1,7 @@
1#ifndef _ASM_ARM_XEN_PAGE_H 1#ifndef _ASM_ARM_XEN_PAGE_H
2#define _ASM_ARM_XEN_PAGE_H 2#define _ASM_ARM_XEN_PAGE_H
3 3
4#include <asm/mach/map.h>
4#include <asm/page.h> 5#include <asm/page.h>
5#include <asm/pgtable.h> 6#include <asm/pgtable.h>
6 7
@@ -86,4 +87,7 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
86{ 87{
87 return __set_phys_to_machine(pfn, mfn); 88 return __set_phys_to_machine(pfn, mfn);
88} 89}
90
91#define xen_remap(cookie, size) __arm_ioremap((cookie), (size), MT_MEMORY);
92
89#endif /* _ASM_ARM_XEN_PAGE_H */ 93#endif /* _ASM_ARM_XEN_PAGE_H */
diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h
new file mode 100644
index 000000000000..91d38e38a0b4
--- /dev/null
+++ b/arch/arm/include/debug/imx-uart.h
@@ -0,0 +1,88 @@
1/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __DEBUG_IMX_UART_H
10#define __DEBUG_IMX_UART_H
11
12#define IMX1_UART1_BASE_ADDR 0x00206000
13#define IMX1_UART2_BASE_ADDR 0x00207000
14#define IMX1_UART_BASE_ADDR(n) IMX1_UART##n##_BASE_ADDR
15#define IMX1_UART_BASE(n) IMX1_UART_BASE_ADDR(n)
16
17#define IMX21_UART1_BASE_ADDR 0x1000a000
18#define IMX21_UART2_BASE_ADDR 0x1000b000
19#define IMX21_UART3_BASE_ADDR 0x1000c000
20#define IMX21_UART4_BASE_ADDR 0x1000d000
21#define IMX21_UART_BASE_ADDR(n) IMX21_UART##n##_BASE_ADDR
22#define IMX21_UART_BASE(n) IMX21_UART_BASE_ADDR(n)
23
24#define IMX25_UART1_BASE_ADDR 0x43f90000
25#define IMX25_UART2_BASE_ADDR 0x43f94000
26#define IMX25_UART3_BASE_ADDR 0x5000c000
27#define IMX25_UART4_BASE_ADDR 0x50008000
28#define IMX25_UART5_BASE_ADDR 0x5002c000
29#define IMX25_UART_BASE_ADDR(n) IMX25_UART##n##_BASE_ADDR
30#define IMX25_UART_BASE(n) IMX25_UART_BASE_ADDR(n)
31
32#define IMX31_UART1_BASE_ADDR 0x43f90000
33#define IMX31_UART2_BASE_ADDR 0x43f94000
34#define IMX31_UART3_BASE_ADDR 0x5000c000
35#define IMX31_UART4_BASE_ADDR 0x43fb0000
36#define IMX31_UART5_BASE_ADDR 0x43fb4000
37#define IMX31_UART_BASE_ADDR(n) IMX31_UART##n##_BASE_ADDR
38#define IMX31_UART_BASE(n) IMX31_UART_BASE_ADDR(n)
39
40#define IMX35_UART1_BASE_ADDR 0x43f90000
41#define IMX35_UART2_BASE_ADDR 0x43f94000
42#define IMX35_UART3_BASE_ADDR 0x5000c000
43#define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR
44#define IMX35_UART_BASE(n) IMX35_UART_BASE_ADDR(n)
45
46#define IMX51_UART1_BASE_ADDR 0x73fbc000
47#define IMX51_UART2_BASE_ADDR 0x73fc0000
48#define IMX51_UART3_BASE_ADDR 0x7000c000
49#define IMX51_UART_BASE_ADDR(n) IMX51_UART##n##_BASE_ADDR
50#define IMX51_UART_BASE(n) IMX51_UART_BASE_ADDR(n)
51
52#define IMX53_UART1_BASE_ADDR 0x53fbc000
53#define IMX53_UART2_BASE_ADDR 0x53fc0000
54#define IMX53_UART3_BASE_ADDR 0x5000c000
55#define IMX53_UART4_BASE_ADDR 0x53ff0000
56#define IMX53_UART5_BASE_ADDR 0x63f90000
57#define IMX53_UART_BASE_ADDR(n) IMX53_UART##n##_BASE_ADDR
58#define IMX53_UART_BASE(n) IMX53_UART_BASE_ADDR(n)
59
60#define IMX6Q_UART1_BASE_ADDR 0x02020000
61#define IMX6Q_UART2_BASE_ADDR 0x021e8000
62#define IMX6Q_UART3_BASE_ADDR 0x021ec000
63#define IMX6Q_UART4_BASE_ADDR 0x021f0000
64#define IMX6Q_UART5_BASE_ADDR 0x021f4000
65#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
66#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n)
67
68#define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT)
69
70#ifdef CONFIG_DEBUG_IMX1_UART
71#define UART_PADDR IMX_DEBUG_UART_BASE(IMX1)
72#elif defined(CONFIG_DEBUG_IMX21_IMX27_UART)
73#define UART_PADDR IMX_DEBUG_UART_BASE(IMX21)
74#elif defined(CONFIG_DEBUG_IMX25_UART)
75#define UART_PADDR IMX_DEBUG_UART_BASE(IMX25)
76#elif defined(CONFIG_DEBUG_IMX31_UART)
77#define UART_PADDR IMX_DEBUG_UART_BASE(IMX31)
78#elif defined(CONFIG_DEBUG_IMX35_UART)
79#define UART_PADDR IMX_DEBUG_UART_BASE(IMX35)
80#elif defined(CONFIG_DEBUG_IMX51_UART)
81#define UART_PADDR IMX_DEBUG_UART_BASE(IMX51)
82#elif defined(CONFIG_DEBUG_IMX53_UART)
83#define UART_PADDR IMX_DEBUG_UART_BASE(IMX53)
84#elif defined(CONFIG_DEBUG_IMX6Q_UART)
85#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q)
86#endif
87
88#endif /* __DEBUG_IMX_UART_H */
diff --git a/arch/arm/include/debug/imx.S b/arch/arm/include/debug/imx.S
index 0c4e17d4d359..619d8cc1ac12 100644
--- a/arch/arm/include/debug/imx.S
+++ b/arch/arm/include/debug/imx.S
@@ -10,35 +10,8 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 * 11 *
12 */ 12 */
13#define IMX6Q_UART1_BASE_ADDR 0x02020000
14#define IMX6Q_UART2_BASE_ADDR 0x021e8000
15#define IMX6Q_UART3_BASE_ADDR 0x021ec000
16#define IMX6Q_UART4_BASE_ADDR 0x021f0000
17#define IMX6Q_UART5_BASE_ADDR 0x021f4000
18 13
19/* 14#include "imx-uart.h"
20 * IMX6Q_UART_BASE_ADDR is put in the middle to force the expansion
21 * of IMX6Q_UART##n##_BASE_ADDR.
22 */
23#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
24#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n)
25#define IMX6Q_DEBUG_UART_BASE IMX6Q_UART_BASE(CONFIG_DEBUG_IMX6Q_UART_PORT)
26
27#ifdef CONFIG_DEBUG_IMX1_UART
28#define UART_PADDR 0x00206000
29#elif defined (CONFIG_DEBUG_IMX25_UART)
30#define UART_PADDR 0x43f90000
31#elif defined (CONFIG_DEBUG_IMX21_IMX27_UART)
32#define UART_PADDR 0x1000a000
33#elif defined (CONFIG_DEBUG_IMX31_IMX35_UART)
34#define UART_PADDR 0x43f90000
35#elif defined (CONFIG_DEBUG_IMX51_UART)
36#define UART_PADDR 0x73fbc000
37#elif defined (CONFIG_DEBUG_IMX50_IMX53_UART)
38#define UART_PADDR 0x53fbc000
39#elif defined (CONFIG_DEBUG_IMX6Q_UART)
40#define UART_PADDR IMX6Q_DEBUG_UART_BASE
41#endif
42 15
43/* 16/*
44 * FIXME: This is a copy of IMX_IO_P2V in hardware.h, and needs to 17 * FIXME: This is a copy of IMX_IO_P2V in hardware.h, and needs to
diff --git a/arch/arm/include/debug/omap2plus.S b/arch/arm/include/debug/omap2plus.S
new file mode 100644
index 000000000000..6d867aef18eb
--- /dev/null
+++ b/arch/arm/include/debug/omap2plus.S
@@ -0,0 +1,190 @@
1/*
2 * Debugging macro include header
3 *
4 * Copyright (C) 1994-1999 Russell King
5 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11*/
12
13#include <linux/serial_reg.h>
14
15/* OMAP2 serial ports */
16#define OMAP2_UART1_BASE 0x4806a000
17#define OMAP2_UART2_BASE 0x4806c000
18#define OMAP2_UART3_BASE 0x4806e000
19
20/* OMAP3 serial ports */
21#define OMAP3_UART1_BASE OMAP2_UART1_BASE
22#define OMAP3_UART2_BASE OMAP2_UART2_BASE
23#define OMAP3_UART3_BASE 0x49020000
24#define OMAP3_UART4_BASE 0x49042000 /* Only on 36xx */
25#define OMAP3_UART4_AM35XX_BASE 0x4809E000 /* Only on AM35xx */
26
27/* OMAP4 serial ports */
28#define OMAP4_UART1_BASE OMAP2_UART1_BASE
29#define OMAP4_UART2_BASE OMAP2_UART2_BASE
30#define OMAP4_UART3_BASE 0x48020000
31#define OMAP4_UART4_BASE 0x4806e000
32
33/* TI81XX serial ports */
34#define TI81XX_UART1_BASE 0x48020000
35#define TI81XX_UART2_BASE 0x48022000
36#define TI81XX_UART3_BASE 0x48024000
37
38/* AM3505/3517 UART4 */
39#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
40
41/* AM33XX serial port */
42#define AM33XX_UART1_BASE 0x44E09000
43
44/* OMAP5 serial ports */
45#define OMAP5_UART1_BASE OMAP2_UART1_BASE
46#define OMAP5_UART2_BASE OMAP2_UART2_BASE
47#define OMAP5_UART3_BASE OMAP4_UART3_BASE
48#define OMAP5_UART4_BASE OMAP4_UART4_BASE
49#define OMAP5_UART5_BASE 0x48066000
50#define OMAP5_UART6_BASE 0x48068000
51
52/* External port on Zoom2/3 */
53#define ZOOM_UART_BASE 0x10000000
54#define ZOOM_UART_VIRT 0xfa400000
55
56#define OMAP_PORT_SHIFT 2
57#define ZOOM_PORT_SHIFT 1
58
59#define UART_OFFSET(addr) ((addr) & 0x00ffffff)
60
61 .pushsection .data
62omap_uart_phys: .word 0
63omap_uart_virt: .word 0
64omap_uart_lsr: .word 0
65 .popsection
66
67 .macro addruart, rp, rv, tmp
68
69 /* Use omap_uart_phys/virt if already configured */
7010: adr \rp, 99f @ get effective addr of 99f
71 ldr \rv, [\rp] @ get absolute addr of 99f
72 sub \rv, \rv, \rp @ offset between the two
73 ldr \rp, [\rp, #4] @ abs addr of omap_uart_phys
74 sub \tmp, \rp, \rv @ make it effective
75 ldr \rp, [\tmp, #0] @ omap_uart_phys
76 ldr \rv, [\tmp, #4] @ omap_uart_virt
77 cmp \rp, #0 @ is port configured?
78 cmpne \rv, #0
79 bne 100f @ already configured
80
81 /* Configure the UART offset from the phys/virt base */
82#ifdef CONFIG_DEBUG_OMAP2UART1
83 mov \rp, #UART_OFFSET(OMAP2_UART1_BASE) @ omap2/3/4
84 b 98f
85#endif
86#ifdef CONFIG_DEBUG_OMAP2UART2
87 mov \rp, #UART_OFFSET(OMAP2_UART2_BASE) @ omap2/3/4
88 b 98f
89#endif
90#ifdef CONFIG_DEBUG_OMAP2UART3
91 mov \rp, #UART_OFFSET(OMAP2_UART3_BASE)
92 b 98f
93#endif
94#ifdef CONFIG_DEBUG_OMAP3UART3
95 mov \rp, #UART_OFFSET(OMAP3_UART1_BASE)
96 add \rp, \rp, #0x00fb0000
97 add \rp, \rp, #0x00006000 @ OMAP3_UART3_BASE
98 b 98f
99#endif
100#ifdef CONFIG_DEBUG_OMAP4UART3
101 mov \rp, #UART_OFFSET(OMAP4_UART3_BASE)
102 b 98f
103#endif
104#ifdef CONFIG_DEBUG_OMAP3UART4
105 mov \rp, #UART_OFFSET(OMAP3_UART1_BASE)
106 add \rp, \rp, #0x00fb0000
107 add \rp, \rp, #0x00028000 @ OMAP3_UART4_BASE
108 b 98f
109#endif
110#ifdef CONFIG_DEBUG_OMAP4UART4
111 mov \rp, #UART_OFFSET(OMAP4_UART4_BASE)
112 b 98f
113#endif
114#ifdef CONFIG_DEBUG_TI81XXUART1
115 mov \rp, #UART_OFFSET(TI81XX_UART1_BASE)
116 b 98f
117#endif
118#ifdef CONFIG_DEBUG_TI81XXUART2
119 mov \rp, #UART_OFFSET(TI81XX_UART2_BASE)
120 b 98f
121#endif
122#ifdef CONFIG_DEBUG_TI81XXUART3
123 mov \rp, #UART_OFFSET(TI81XX_UART3_BASE)
124 b 98f
125#endif
126#ifdef CONFIG_DEBUG_AM33XXUART1
127 ldr \rp, =AM33XX_UART1_BASE
128 and \rp, \rp, #0x00ffffff
129 b 97f
130#endif
131#ifdef CONFIG_DEBUG_ZOOM_UART
132 ldr \rp, =ZOOM_UART_BASE
133 str \rp, [\tmp, #0] @ omap_uart_phys
134 ldr \rp, =ZOOM_UART_VIRT
135 str \rp, [\tmp, #4] @ omap_uart_virt
136 mov \rp, #(UART_LSR << ZOOM_PORT_SHIFT)
137 str \rp, [\tmp, #8] @ omap_uart_lsr
138#endif
139 b 10b
140
141 /* AM33XX: Store both phys and virt address for the uart */
14297: add \rp, \rp, #0x44000000 @ phys base
143 str \rp, [\tmp, #0] @ omap_uart_phys
144 sub \rp, \rp, #0x44000000 @ phys base
145 add \rp, \rp, #0xf9000000 @ virt base
146 str \rp, [\tmp, #4] @ omap_uart_virt
147 mov \rp, #(UART_LSR << OMAP_PORT_SHIFT)
148 str \rp, [\tmp, #8] @ omap_uart_lsr
149
150 b 10b
151
152 /* Store both phys and virt address for the uart */
15398: add \rp, \rp, #0x48000000 @ phys base
154 str \rp, [\tmp, #0] @ omap_uart_phys
155 sub \rp, \rp, #0x48000000 @ phys base
156 add \rp, \rp, #0xfa000000 @ virt base
157 str \rp, [\tmp, #4] @ omap_uart_virt
158 mov \rp, #(UART_LSR << OMAP_PORT_SHIFT)
159 str \rp, [\tmp, #8] @ omap_uart_lsr
160
161 b 10b
162
163 .align
16499: .word .
165 .word omap_uart_phys
166 .ltorg
167
168100: /* Pass the UART_LSR reg address */
169 ldr \tmp, [\tmp, #8] @ omap_uart_lsr
170 add \rp, \rp, \tmp
171 add \rv, \rv, \tmp
172 .endm
173
174 .macro senduart,rd,rx
175 orr \rd, \rd, \rx, lsl #24 @ preserve LSR reg offset
176 bic \rx, \rx, #0xff @ get base (THR) reg address
177 strb \rd, [\rx] @ send lower byte of rd
178 orr \rx, \rx, \rd, lsr #24 @ restore original rx (LSR)
179 bic \rd, \rd, #(0xff << 24) @ restore original rd
180 .endm
181
182 .macro busyuart,rd,rx
1831001: ldrb \rd, [\rx] @ rx contains UART_LSR address
184 and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
185 teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
186 bne 1001b
187 .endm
188
189 .macro waituart,rd,rx
190 .endm
diff --git a/arch/arm/include/debug/vt8500.S b/arch/arm/include/debug/vt8500.S
new file mode 100644
index 000000000000..0e0ca0869da7
--- /dev/null
+++ b/arch/arm/include/debug/vt8500.S
@@ -0,0 +1,37 @@
1/*
2 * Debugging macro include header
3 *
4 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
5 * Moved from arch/arm/mach-vt8500/include/mach/debug-macro.S
6 * Minor changes for readability.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#define DEBUG_LL_PHYS_BASE 0xD8000000
14#define DEBUG_LL_VIRT_BASE 0xF8000000
15#define DEBUG_LL_UART_OFFSET 0x00200000
16
17#if defined(CONFIG_DEBUG_VT8500_UART0)
18 .macro addruart, rp, rv, tmp
19 mov \rp, #DEBUG_LL_UART_OFFSET
20 orr \rv, \rp, #DEBUG_LL_VIRT_BASE
21 orr \rp, \rp, #DEBUG_LL_PHYS_BASE
22 .endm
23
24 .macro senduart,rd,rx
25 strb \rd, [\rx, #0]
26 .endm
27
28 .macro busyuart,rd,rx
291001: ldr \rd, [\rx, #0x1c]
30 ands \rd, \rd, #0x2
31 bne 1001b
32 .endm
33
34 .macro waituart,rd,rx
35 .endm
36
37#endif
diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h
new file mode 100644
index 000000000000..023bfeb367bf
--- /dev/null
+++ b/arch/arm/include/uapi/asm/kvm.h
@@ -0,0 +1,180 @@
1/*
2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
3 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19#ifndef __ARM_KVM_H__
20#define __ARM_KVM_H__
21
22#include <linux/types.h>
23#include <asm/ptrace.h>
24
25#define __KVM_HAVE_GUEST_DEBUG
26#define __KVM_HAVE_IRQ_LINE
27
28#define KVM_REG_SIZE(id) \
29 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
30
31/* Valid for svc_regs, abt_regs, und_regs, irq_regs in struct kvm_regs */
32#define KVM_ARM_SVC_sp svc_regs[0]
33#define KVM_ARM_SVC_lr svc_regs[1]
34#define KVM_ARM_SVC_spsr svc_regs[2]
35#define KVM_ARM_ABT_sp abt_regs[0]
36#define KVM_ARM_ABT_lr abt_regs[1]
37#define KVM_ARM_ABT_spsr abt_regs[2]
38#define KVM_ARM_UND_sp und_regs[0]
39#define KVM_ARM_UND_lr und_regs[1]
40#define KVM_ARM_UND_spsr und_regs[2]
41#define KVM_ARM_IRQ_sp irq_regs[0]
42#define KVM_ARM_IRQ_lr irq_regs[1]
43#define KVM_ARM_IRQ_spsr irq_regs[2]
44
45/* Valid only for fiq_regs in struct kvm_regs */
46#define KVM_ARM_FIQ_r8 fiq_regs[0]
47#define KVM_ARM_FIQ_r9 fiq_regs[1]
48#define KVM_ARM_FIQ_r10 fiq_regs[2]
49#define KVM_ARM_FIQ_fp fiq_regs[3]
50#define KVM_ARM_FIQ_ip fiq_regs[4]
51#define KVM_ARM_FIQ_sp fiq_regs[5]
52#define KVM_ARM_FIQ_lr fiq_regs[6]
53#define KVM_ARM_FIQ_spsr fiq_regs[7]
54
55struct kvm_regs {
56 struct pt_regs usr_regs;/* R0_usr - R14_usr, PC, CPSR */
57 __u32 svc_regs[3]; /* SP_svc, LR_svc, SPSR_svc */
58 __u32 abt_regs[3]; /* SP_abt, LR_abt, SPSR_abt */
59 __u32 und_regs[3]; /* SP_und, LR_und, SPSR_und */
60 __u32 irq_regs[3]; /* SP_irq, LR_irq, SPSR_irq */
61 __u32 fiq_regs[8]; /* R8_fiq - R14_fiq, SPSR_fiq */
62};
63
64/* Supported Processor Types */
65#define KVM_ARM_TARGET_CORTEX_A15 0
66#define KVM_ARM_NUM_TARGETS 1
67
68/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
69#define KVM_ARM_DEVICE_TYPE_SHIFT 0
70#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
71#define KVM_ARM_DEVICE_ID_SHIFT 16
72#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
73
74/* Supported device IDs */
75#define KVM_ARM_DEVICE_VGIC_V2 0
76
77/* Supported VGIC address types */
78#define KVM_VGIC_V2_ADDR_TYPE_DIST 0
79#define KVM_VGIC_V2_ADDR_TYPE_CPU 1
80
81#define KVM_VGIC_V2_DIST_SIZE 0x1000
82#define KVM_VGIC_V2_CPU_SIZE 0x2000
83
84#define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
85
86struct kvm_vcpu_init {
87 __u32 target;
88 __u32 features[7];
89};
90
91struct kvm_sregs {
92};
93
94struct kvm_fpu {
95};
96
97struct kvm_guest_debug_arch {
98};
99
100struct kvm_debug_exit_arch {
101};
102
103struct kvm_sync_regs {
104};
105
106struct kvm_arch_memory_slot {
107};
108
109/* If you need to interpret the index values, here is the key: */
110#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
111#define KVM_REG_ARM_COPROC_SHIFT 16
112#define KVM_REG_ARM_32_OPC2_MASK 0x0000000000000007
113#define KVM_REG_ARM_32_OPC2_SHIFT 0
114#define KVM_REG_ARM_OPC1_MASK 0x0000000000000078
115#define KVM_REG_ARM_OPC1_SHIFT 3
116#define KVM_REG_ARM_CRM_MASK 0x0000000000000780
117#define KVM_REG_ARM_CRM_SHIFT 7
118#define KVM_REG_ARM_32_CRN_MASK 0x0000000000007800
119#define KVM_REG_ARM_32_CRN_SHIFT 11
120
121/* Normal registers are mapped as coprocessor 16. */
122#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
123#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / 4)
124
125/* Some registers need more space to represent values. */
126#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
127#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
128#define KVM_REG_ARM_DEMUX_ID_SHIFT 8
129#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
130#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
131#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
132
133/* VFP registers: we could overload CP10 like ARM does, but that's ugly. */
134#define KVM_REG_ARM_VFP (0x0012 << KVM_REG_ARM_COPROC_SHIFT)
135#define KVM_REG_ARM_VFP_MASK 0x000000000000FFFF
136#define KVM_REG_ARM_VFP_BASE_REG 0x0
137#define KVM_REG_ARM_VFP_FPSID 0x1000
138#define KVM_REG_ARM_VFP_FPSCR 0x1001
139#define KVM_REG_ARM_VFP_MVFR1 0x1006
140#define KVM_REG_ARM_VFP_MVFR0 0x1007
141#define KVM_REG_ARM_VFP_FPEXC 0x1008
142#define KVM_REG_ARM_VFP_FPINST 0x1009
143#define KVM_REG_ARM_VFP_FPINST2 0x100A
144
145
146/* KVM_IRQ_LINE irq field index values */
147#define KVM_ARM_IRQ_TYPE_SHIFT 24
148#define KVM_ARM_IRQ_TYPE_MASK 0xff
149#define KVM_ARM_IRQ_VCPU_SHIFT 16
150#define KVM_ARM_IRQ_VCPU_MASK 0xff
151#define KVM_ARM_IRQ_NUM_SHIFT 0
152#define KVM_ARM_IRQ_NUM_MASK 0xffff
153
154/* irq_type field */
155#define KVM_ARM_IRQ_TYPE_CPU 0
156#define KVM_ARM_IRQ_TYPE_SPI 1
157#define KVM_ARM_IRQ_TYPE_PPI 2
158
159/* out-of-kernel GIC cpu interrupt injection irq_number field */
160#define KVM_ARM_IRQ_CPU_IRQ 0
161#define KVM_ARM_IRQ_CPU_FIQ 1
162
163/* Highest supported SPI, from VGIC_NR_IRQS */
164#define KVM_ARM_IRQ_GIC_MAX 127
165
166/* PSCI interface */
167#define KVM_PSCI_FN_BASE 0x95c1ba5e
168#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
169
170#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
171#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
172#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
173#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
174
175#define KVM_PSCI_RET_SUCCESS 0
176#define KVM_PSCI_RET_NI ((unsigned long)-1)
177#define KVM_PSCI_RET_INVAL ((unsigned long)-2)
178#define KVM_PSCI_RET_DENIED ((unsigned long)-3)
179
180#endif /* __ARM_KVM_H__ */
diff --git a/arch/arm/include/uapi/asm/unistd.h b/arch/arm/include/uapi/asm/unistd.h
index 4da7cde70b5d..af33b44990ed 100644
--- a/arch/arm/include/uapi/asm/unistd.h
+++ b/arch/arm/include/uapi/asm/unistd.h
@@ -404,7 +404,7 @@
404#define __NR_setns (__NR_SYSCALL_BASE+375) 404#define __NR_setns (__NR_SYSCALL_BASE+375)
405#define __NR_process_vm_readv (__NR_SYSCALL_BASE+376) 405#define __NR_process_vm_readv (__NR_SYSCALL_BASE+376)
406#define __NR_process_vm_writev (__NR_SYSCALL_BASE+377) 406#define __NR_process_vm_writev (__NR_SYSCALL_BASE+377)
407 /* 378 for kcmp */ 407#define __NR_kcmp (__NR_SYSCALL_BASE+378)
408#define __NR_finit_module (__NR_SYSCALL_BASE+379) 408#define __NR_finit_module (__NR_SYSCALL_BASE+379)
409 409
410/* 410/*
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