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-rw-r--r--arch/arm/include/asm/Kbuild1
-rw-r--r--arch/arm/include/asm/assembler.h2
-rw-r--r--arch/arm/include/asm/cacheflush.h4
-rw-r--r--arch/arm/include/asm/cp15.h25
-rw-r--r--arch/arm/include/asm/cputype.h1
-rw-r--r--arch/arm/include/asm/dma-mapping.h25
-rw-r--r--arch/arm/include/asm/fixmap.h21
-rw-r--r--arch/arm/include/asm/glue-df.h8
-rw-r--r--arch/arm/include/asm/hardware/cache-l2x0.h104
-rw-r--r--arch/arm/include/asm/highmem.h1
-rw-r--r--arch/arm/include/asm/io.h6
-rw-r--r--arch/arm/include/asm/mach/arch.h7
-rw-r--r--arch/arm/include/asm/mcpm.h8
-rw-r--r--arch/arm/include/asm/memblock.h3
-rw-r--r--arch/arm/include/asm/memory.h2
-rw-r--r--arch/arm/include/asm/outercache.h66
-rw-r--r--arch/arm/include/asm/setup.h28
17 files changed, 185 insertions, 127 deletions
diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild
index 23e728ecf8ab..f5a357601983 100644
--- a/arch/arm/include/asm/Kbuild
+++ b/arch/arm/include/asm/Kbuild
@@ -21,6 +21,7 @@ generic-y += parport.h
21generic-y += poll.h 21generic-y += poll.h
22generic-y += preempt.h 22generic-y += preempt.h
23generic-y += resource.h 23generic-y += resource.h
24generic-y += rwsem.h
24generic-y += sections.h 25generic-y += sections.h
25generic-y += segment.h 26generic-y += segment.h
26generic-y += sembuf.h 27generic-y += sembuf.h
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index b974184f9941..57f0584e8d97 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -312,7 +312,7 @@
312 * you cannot return to the original mode. 312 * you cannot return to the original mode.
313 */ 313 */
314.macro safe_svcmode_maskall reg:req 314.macro safe_svcmode_maskall reg:req
315#if __LINUX_ARM_ARCH__ >= 6 315#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
316 mrs \reg , cpsr 316 mrs \reg , cpsr
317 eor \reg, \reg, #HYP_MODE 317 eor \reg, \reg, #HYP_MODE
318 tst \reg, #MODE_MASK 318 tst \reg, #MODE_MASK
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 8b8b61685a34..fd43f7f55b70 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -212,7 +212,7 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *,
212static inline void __flush_icache_all(void) 212static inline void __flush_icache_all(void)
213{ 213{
214 __flush_icache_preferred(); 214 __flush_icache_preferred();
215 dsb(); 215 dsb(ishst);
216} 216}
217 217
218/* 218/*
@@ -487,4 +487,6 @@ int set_memory_rw(unsigned long addr, int numpages);
487int set_memory_x(unsigned long addr, int numpages); 487int set_memory_x(unsigned long addr, int numpages);
488int set_memory_nx(unsigned long addr, int numpages); 488int set_memory_nx(unsigned long addr, int numpages);
489 489
490void flush_uprobe_xol_access(struct page *page, unsigned long uaddr,
491 void *kaddr, unsigned long len);
490#endif 492#endif
diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
index 6493802f880a..c3f11524f10c 100644
--- a/arch/arm/include/asm/cp15.h
+++ b/arch/arm/include/asm/cp15.h
@@ -42,24 +42,23 @@
42#ifndef __ASSEMBLY__ 42#ifndef __ASSEMBLY__
43 43
44#if __LINUX_ARM_ARCH__ >= 4 44#if __LINUX_ARM_ARCH__ >= 4
45#define vectors_high() (cr_alignment & CR_V) 45#define vectors_high() (get_cr() & CR_V)
46#else 46#else
47#define vectors_high() (0) 47#define vectors_high() (0)
48#endif 48#endif
49 49
50#ifdef CONFIG_CPU_CP15 50#ifdef CONFIG_CPU_CP15
51 51
52extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
53extern unsigned long cr_alignment; /* defined in entry-armv.S */ 52extern unsigned long cr_alignment; /* defined in entry-armv.S */
54 53
55static inline unsigned int get_cr(void) 54static inline unsigned long get_cr(void)
56{ 55{
57 unsigned int val; 56 unsigned long val;
58 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); 57 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
59 return val; 58 return val;
60} 59}
61 60
62static inline void set_cr(unsigned int val) 61static inline void set_cr(unsigned long val)
63{ 62{
64 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" 63 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
65 : : "r" (val) : "cc"); 64 : : "r" (val) : "cc");
@@ -80,10 +79,6 @@ static inline void set_auxcr(unsigned int val)
80 isb(); 79 isb();
81} 80}
82 81
83#ifndef CONFIG_SMP
84extern void adjust_cr(unsigned long mask, unsigned long set);
85#endif
86
87#define CPACC_FULL(n) (3 << (n * 2)) 82#define CPACC_FULL(n) (3 << (n * 2))
88#define CPACC_SVC(n) (1 << (n * 2)) 83#define CPACC_SVC(n) (1 << (n * 2))
89#define CPACC_DISABLE(n) (0 << (n * 2)) 84#define CPACC_DISABLE(n) (0 << (n * 2))
@@ -106,13 +101,17 @@ static inline void set_copro_access(unsigned int val)
106#else /* ifdef CONFIG_CPU_CP15 */ 101#else /* ifdef CONFIG_CPU_CP15 */
107 102
108/* 103/*
109 * cr_alignment and cr_no_alignment are tightly coupled to cp15 (at least in the 104 * cr_alignment is tightly coupled to cp15 (at least in the minds of the
110 * minds of the developers). Yielding 0 for machines without a cp15 (and making 105 * developers). Yielding 0 for machines without a cp15 (and making it
111 * it read-only) is fine for most cases and saves quite some #ifdeffery. 106 * read-only) is fine for most cases and saves quite some #ifdeffery.
112 */ 107 */
113#define cr_no_alignment UL(0)
114#define cr_alignment UL(0) 108#define cr_alignment UL(0)
115 109
110static inline unsigned long get_cr(void)
111{
112 return 0;
113}
114
116#endif /* ifdef CONFIG_CPU_CP15 / else */ 115#endif /* ifdef CONFIG_CPU_CP15 / else */
117 116
118#endif /* ifndef __ASSEMBLY__ */ 117#endif /* ifndef __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 4764344367d4..8c2b7321a478 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -72,6 +72,7 @@
72#define ARM_CPU_PART_CORTEX_A15 0xC0F0 72#define ARM_CPU_PART_CORTEX_A15 0xC0F0
73#define ARM_CPU_PART_CORTEX_A7 0xC070 73#define ARM_CPU_PART_CORTEX_A7 0xC070
74#define ARM_CPU_PART_CORTEX_A12 0xC0D0 74#define ARM_CPU_PART_CORTEX_A12 0xC0D0
75#define ARM_CPU_PART_CORTEX_A17 0xC0E0
75 76
76#define ARM_CPU_XSCALE_ARCH_MASK 0xe000 77#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
77#define ARM_CPU_XSCALE_ARCH_V1 0x2000 78#define ARM_CPU_XSCALE_ARCH_V1 0x2000
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index e701a4d9aa59..c45b61a4b4a5 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -58,21 +58,37 @@ static inline int dma_set_mask(struct device *dev, u64 mask)
58#ifndef __arch_pfn_to_dma 58#ifndef __arch_pfn_to_dma
59static inline dma_addr_t pfn_to_dma(struct device *dev, unsigned long pfn) 59static inline dma_addr_t pfn_to_dma(struct device *dev, unsigned long pfn)
60{ 60{
61 if (dev)
62 pfn -= dev->dma_pfn_offset;
61 return (dma_addr_t)__pfn_to_bus(pfn); 63 return (dma_addr_t)__pfn_to_bus(pfn);
62} 64}
63 65
64static inline unsigned long dma_to_pfn(struct device *dev, dma_addr_t addr) 66static inline unsigned long dma_to_pfn(struct device *dev, dma_addr_t addr)
65{ 67{
66 return __bus_to_pfn(addr); 68 unsigned long pfn = __bus_to_pfn(addr);
69
70 if (dev)
71 pfn += dev->dma_pfn_offset;
72
73 return pfn;
67} 74}
68 75
69static inline void *dma_to_virt(struct device *dev, dma_addr_t addr) 76static inline void *dma_to_virt(struct device *dev, dma_addr_t addr)
70{ 77{
78 if (dev) {
79 unsigned long pfn = dma_to_pfn(dev, addr);
80
81 return phys_to_virt(__pfn_to_phys(pfn));
82 }
83
71 return (void *)__bus_to_virt((unsigned long)addr); 84 return (void *)__bus_to_virt((unsigned long)addr);
72} 85}
73 86
74static inline dma_addr_t virt_to_dma(struct device *dev, void *addr) 87static inline dma_addr_t virt_to_dma(struct device *dev, void *addr)
75{ 88{
89 if (dev)
90 return pfn_to_dma(dev, virt_to_pfn(addr));
91
76 return (dma_addr_t)__virt_to_bus((unsigned long)(addr)); 92 return (dma_addr_t)__virt_to_bus((unsigned long)(addr));
77} 93}
78 94
@@ -105,6 +121,13 @@ static inline unsigned long dma_max_pfn(struct device *dev)
105} 121}
106#define dma_max_pfn(dev) dma_max_pfn(dev) 122#define dma_max_pfn(dev) dma_max_pfn(dev)
107 123
124static inline int set_arch_dma_coherent_ops(struct device *dev)
125{
126 set_dma_ops(dev, &arm_coherent_dma_ops);
127 return 0;
128}
129#define set_arch_dma_coherent_ops(dev) set_arch_dma_coherent_ops(dev)
130
108static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) 131static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
109{ 132{
110 unsigned int offset = paddr & ~PAGE_MASK; 133 unsigned int offset = paddr & ~PAGE_MASK;
diff --git a/arch/arm/include/asm/fixmap.h b/arch/arm/include/asm/fixmap.h
index bbae919bceb4..74124b0d0d79 100644
--- a/arch/arm/include/asm/fixmap.h
+++ b/arch/arm/include/asm/fixmap.h
@@ -1,24 +1,11 @@
1#ifndef _ASM_FIXMAP_H 1#ifndef _ASM_FIXMAP_H
2#define _ASM_FIXMAP_H 2#define _ASM_FIXMAP_H
3 3
4/* 4#define FIXADDR_START 0xffc00000UL
5 * Nothing too fancy for now. 5#define FIXADDR_TOP 0xffe00000UL
6 *
7 * On ARM we already have well known fixed virtual addresses imposed by
8 * the architecture such as the vector page which is located at 0xffff0000,
9 * therefore a second level page table is already allocated covering
10 * 0xfff00000 upwards.
11 *
12 * The cache flushing code in proc-xscale.S uses the virtual area between
13 * 0xfffe0000 and 0xfffeffff.
14 */
15
16#define FIXADDR_START 0xfff00000UL
17#define FIXADDR_TOP 0xfffe0000UL
18#define FIXADDR_SIZE (FIXADDR_TOP - FIXADDR_START) 6#define FIXADDR_SIZE (FIXADDR_TOP - FIXADDR_START)
19 7
20#define FIX_KMAP_BEGIN 0 8#define FIX_KMAP_NR_PTES (FIXADDR_SIZE >> PAGE_SHIFT)
21#define FIX_KMAP_END (FIXADDR_SIZE >> PAGE_SHIFT)
22 9
23#define __fix_to_virt(x) (FIXADDR_START + ((x) << PAGE_SHIFT)) 10#define __fix_to_virt(x) (FIXADDR_START + ((x) << PAGE_SHIFT))
24#define __virt_to_fix(x) (((x) - FIXADDR_START) >> PAGE_SHIFT) 11#define __virt_to_fix(x) (((x) - FIXADDR_START) >> PAGE_SHIFT)
@@ -27,7 +14,7 @@ extern void __this_fixmap_does_not_exist(void);
27 14
28static inline unsigned long fix_to_virt(const unsigned int idx) 15static inline unsigned long fix_to_virt(const unsigned int idx)
29{ 16{
30 if (idx >= FIX_KMAP_END) 17 if (idx >= FIX_KMAP_NR_PTES)
31 __this_fixmap_does_not_exist(); 18 __this_fixmap_does_not_exist();
32 return __fix_to_virt(idx); 19 return __fix_to_virt(idx);
33} 20}
diff --git a/arch/arm/include/asm/glue-df.h b/arch/arm/include/asm/glue-df.h
index 6b70f1b46a6e..04e18b656659 100644
--- a/arch/arm/include/asm/glue-df.h
+++ b/arch/arm/include/asm/glue-df.h
@@ -31,14 +31,6 @@
31#undef CPU_DABORT_HANDLER 31#undef CPU_DABORT_HANDLER
32#undef MULTI_DABORT 32#undef MULTI_DABORT
33 33
34#if defined(CONFIG_CPU_ARM710)
35# ifdef CPU_DABORT_HANDLER
36# define MULTI_DABORT 1
37# else
38# define CPU_DABORT_HANDLER cpu_arm7_data_abort
39# endif
40#endif
41
42#ifdef CONFIG_CPU_ABRT_EV4 34#ifdef CONFIG_CPU_ABRT_EV4
43# ifdef CPU_DABORT_HANDLER 35# ifdef CPU_DABORT_HANDLER
44# define MULTI_DABORT 1 36# define MULTI_DABORT 1
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 6795ff743b3d..3a5ec1c25659 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -26,8 +26,8 @@
26#define L2X0_CACHE_TYPE 0x004 26#define L2X0_CACHE_TYPE 0x004
27#define L2X0_CTRL 0x100 27#define L2X0_CTRL 0x100
28#define L2X0_AUX_CTRL 0x104 28#define L2X0_AUX_CTRL 0x104
29#define L2X0_TAG_LATENCY_CTRL 0x108 29#define L310_TAG_LATENCY_CTRL 0x108
30#define L2X0_DATA_LATENCY_CTRL 0x10C 30#define L310_DATA_LATENCY_CTRL 0x10C
31#define L2X0_EVENT_CNT_CTRL 0x200 31#define L2X0_EVENT_CNT_CTRL 0x200
32#define L2X0_EVENT_CNT1_CFG 0x204 32#define L2X0_EVENT_CNT1_CFG 0x204
33#define L2X0_EVENT_CNT0_CFG 0x208 33#define L2X0_EVENT_CNT0_CFG 0x208
@@ -54,53 +54,93 @@
54#define L2X0_LOCKDOWN_WAY_D_BASE 0x900 54#define L2X0_LOCKDOWN_WAY_D_BASE 0x900
55#define L2X0_LOCKDOWN_WAY_I_BASE 0x904 55#define L2X0_LOCKDOWN_WAY_I_BASE 0x904
56#define L2X0_LOCKDOWN_STRIDE 0x08 56#define L2X0_LOCKDOWN_STRIDE 0x08
57#define L2X0_ADDR_FILTER_START 0xC00 57#define L310_ADDR_FILTER_START 0xC00
58#define L2X0_ADDR_FILTER_END 0xC04 58#define L310_ADDR_FILTER_END 0xC04
59#define L2X0_TEST_OPERATION 0xF00 59#define L2X0_TEST_OPERATION 0xF00
60#define L2X0_LINE_DATA 0xF10 60#define L2X0_LINE_DATA 0xF10
61#define L2X0_LINE_TAG 0xF30 61#define L2X0_LINE_TAG 0xF30
62#define L2X0_DEBUG_CTRL 0xF40 62#define L2X0_DEBUG_CTRL 0xF40
63#define L2X0_PREFETCH_CTRL 0xF60 63#define L310_PREFETCH_CTRL 0xF60
64#define L2X0_POWER_CTRL 0xF80 64#define L310_POWER_CTRL 0xF80
65#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1) 65#define L310_DYNAMIC_CLK_GATING_EN (1 << 1)
66#define L2X0_STNDBY_MODE_EN (1 << 0) 66#define L310_STNDBY_MODE_EN (1 << 0)
67 67
68/* Registers shifts and masks */ 68/* Registers shifts and masks */
69#define L2X0_CACHE_ID_PART_MASK (0xf << 6) 69#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
70#define L2X0_CACHE_ID_PART_L210 (1 << 6) 70#define L2X0_CACHE_ID_PART_L210 (1 << 6)
71#define L2X0_CACHE_ID_PART_L220 (2 << 6)
71#define L2X0_CACHE_ID_PART_L310 (3 << 6) 72#define L2X0_CACHE_ID_PART_L310 (3 << 6)
72#define L2X0_CACHE_ID_RTL_MASK 0x3f 73#define L2X0_CACHE_ID_RTL_MASK 0x3f
73#define L2X0_CACHE_ID_RTL_R0P0 0x0 74#define L210_CACHE_ID_RTL_R0P2_02 0x00
74#define L2X0_CACHE_ID_RTL_R1P0 0x2 75#define L210_CACHE_ID_RTL_R0P1 0x01
75#define L2X0_CACHE_ID_RTL_R2P0 0x4 76#define L210_CACHE_ID_RTL_R0P2_01 0x02
76#define L2X0_CACHE_ID_RTL_R3P0 0x5 77#define L210_CACHE_ID_RTL_R0P3 0x03
77#define L2X0_CACHE_ID_RTL_R3P1 0x6 78#define L210_CACHE_ID_RTL_R0P4 0x0b
78#define L2X0_CACHE_ID_RTL_R3P2 0x8 79#define L210_CACHE_ID_RTL_R0P5 0x0f
80#define L220_CACHE_ID_RTL_R1P7_01REL0 0x06
81#define L310_CACHE_ID_RTL_R0P0 0x00
82#define L310_CACHE_ID_RTL_R1P0 0x02
83#define L310_CACHE_ID_RTL_R2P0 0x04
84#define L310_CACHE_ID_RTL_R3P0 0x05
85#define L310_CACHE_ID_RTL_R3P1 0x06
86#define L310_CACHE_ID_RTL_R3P1_50REL0 0x07
87#define L310_CACHE_ID_RTL_R3P2 0x08
88#define L310_CACHE_ID_RTL_R3P3 0x09
79 89
80#define L2X0_AUX_CTRL_MASK 0xc0000fff 90/* L2C auxiliary control register - bits common to L2C-210/220/310 */
91#define L2C_AUX_CTRL_WAY_SIZE_SHIFT 17
92#define L2C_AUX_CTRL_WAY_SIZE_MASK (7 << 17)
93#define L2C_AUX_CTRL_WAY_SIZE(n) ((n) << 17)
94#define L2C_AUX_CTRL_EVTMON_ENABLE BIT(20)
95#define L2C_AUX_CTRL_PARITY_ENABLE BIT(21)
96#define L2C_AUX_CTRL_SHARED_OVERRIDE BIT(22)
97/* L2C-210/220 common bits */
81#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0 98#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0
82#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK 0x7 99#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK (7 << 0)
83#define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3 100#define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3
84#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (0x7 << 3) 101#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (7 << 3)
85#define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6 102#define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6
86#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (0x7 << 6) 103#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (7 << 6)
87#define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9 104#define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9
88#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (0x7 << 9) 105#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (7 << 9)
89#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16 106#define L2X0_AUX_CTRL_ASSOC_SHIFT 13
90#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17 107#define L2X0_AUX_CTRL_ASSOC_MASK (15 << 13)
91#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17) 108/* L2C-210 specific bits */
92#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22 109#define L210_AUX_CTRL_WRAP_DISABLE BIT(12)
93#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26 110#define L210_AUX_CTRL_WA_OVERRIDE BIT(23)
94#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27 111#define L210_AUX_CTRL_EXCLUSIVE_ABORT BIT(24)
95#define L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT 28 112/* L2C-220 specific bits */
96#define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29 113#define L220_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
97#define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30 114#define L220_AUX_CTRL_FWA_SHIFT 23
115#define L220_AUX_CTRL_FWA_MASK (3 << 23)
116#define L220_AUX_CTRL_NS_LOCKDOWN BIT(26)
117#define L220_AUX_CTRL_NS_INT_CTRL BIT(27)
118/* L2C-310 specific bits */
119#define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */
120#define L310_AUX_CTRL_HIGHPRIO_SO_DEV BIT(10) /* R2P0+ */
121#define L310_AUX_CTRL_STORE_LIMITATION BIT(11) /* R2P0+ */
122#define L310_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
123#define L310_AUX_CTRL_ASSOCIATIVITY_16 BIT(16)
124#define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */
125#define L310_AUX_CTRL_NS_LOCKDOWN BIT(26)
126#define L310_AUX_CTRL_NS_INT_CTRL BIT(27)
127#define L310_AUX_CTRL_DATA_PREFETCH BIT(28)
128#define L310_AUX_CTRL_INSTR_PREFETCH BIT(29)
129#define L310_AUX_CTRL_EARLY_BRESP BIT(30) /* R2P0+ */
98 130
99#define L2X0_LATENCY_CTRL_SETUP_SHIFT 0 131#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0)
100#define L2X0_LATENCY_CTRL_RD_SHIFT 4 132#define L310_LATENCY_CTRL_RD(n) ((n) << 4)
101#define L2X0_LATENCY_CTRL_WR_SHIFT 8 133#define L310_LATENCY_CTRL_WR(n) ((n) << 8)
102 134
103#define L2X0_ADDR_FILTER_EN 1 135#define L310_ADDR_FILTER_EN 1
136
137#define L310_PREFETCH_CTRL_OFFSET_MASK 0x1f
138#define L310_PREFETCH_CTRL_DBL_LINEFILL_INCR BIT(23)
139#define L310_PREFETCH_CTRL_PREFETCH_DROP BIT(24)
140#define L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP BIT(27)
141#define L310_PREFETCH_CTRL_DATA_PREFETCH BIT(28)
142#define L310_PREFETCH_CTRL_INSTR_PREFETCH BIT(29)
143#define L310_PREFETCH_CTRL_DBL_LINEFILL BIT(30)
104 144
105#define L2X0_CTRL_EN 1 145#define L2X0_CTRL_EN 1
106 146
diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h
index 91b99abe7a95..535579511ed0 100644
--- a/arch/arm/include/asm/highmem.h
+++ b/arch/arm/include/asm/highmem.h
@@ -18,6 +18,7 @@
18 } while (0) 18 } while (0)
19 19
20extern pte_t *pkmap_page_table; 20extern pte_t *pkmap_page_table;
21extern pte_t *fixmap_page_table;
21 22
22extern void *kmap_high(struct page *page); 23extern void *kmap_high(struct page *page);
23extern void kunmap_high(struct page *page); 24extern void kunmap_high(struct page *page);
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 8aa4cca74501..3d23418cbddd 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -179,6 +179,12 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
179/* PCI fixed i/o mapping */ 179/* PCI fixed i/o mapping */
180#define PCI_IO_VIRT_BASE 0xfee00000 180#define PCI_IO_VIRT_BASE 0xfee00000
181 181
182#if defined(CONFIG_PCI)
183void pci_ioremap_set_mem_type(int mem_type);
184#else
185static inline void pci_ioremap_set_mem_type(int mem_type) {}
186#endif
187
182extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr); 188extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
183 189
184/* 190/*
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 17a3fa2979e8..060a75e99263 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -14,7 +14,6 @@
14#include <linux/reboot.h> 14#include <linux/reboot.h>
15 15
16struct tag; 16struct tag;
17struct meminfo;
18struct pt_regs; 17struct pt_regs;
19struct smp_operations; 18struct smp_operations;
20#ifdef CONFIG_SMP 19#ifdef CONFIG_SMP
@@ -45,10 +44,12 @@ struct machine_desc {
45 unsigned char reserve_lp1 :1; /* never has lp1 */ 44 unsigned char reserve_lp1 :1; /* never has lp1 */
46 unsigned char reserve_lp2 :1; /* never has lp2 */ 45 unsigned char reserve_lp2 :1; /* never has lp2 */
47 enum reboot_mode reboot_mode; /* default restart mode */ 46 enum reboot_mode reboot_mode; /* default restart mode */
47 unsigned l2c_aux_val; /* L2 cache aux value */
48 unsigned l2c_aux_mask; /* L2 cache aux mask */
49 void (*l2c_write_sec)(unsigned long, unsigned);
48 struct smp_operations *smp; /* SMP operations */ 50 struct smp_operations *smp; /* SMP operations */
49 bool (*smp_init)(void); 51 bool (*smp_init)(void);
50 void (*fixup)(struct tag *, char **, 52 void (*fixup)(struct tag *, char **);
51 struct meminfo *);
52 void (*init_meminfo)(void); 53 void (*init_meminfo)(void);
53 void (*reserve)(void);/* reserve mem blocks */ 54 void (*reserve)(void);/* reserve mem blocks */
54 void (*map_io)(void);/* IO mapping function */ 55 void (*map_io)(void);/* IO mapping function */
diff --git a/arch/arm/include/asm/mcpm.h b/arch/arm/include/asm/mcpm.h
index a5ff410dcdb6..d9702eb0b02b 100644
--- a/arch/arm/include/asm/mcpm.h
+++ b/arch/arm/include/asm/mcpm.h
@@ -98,14 +98,14 @@ int mcpm_cpu_power_up(unsigned int cpu, unsigned int cluster);
98 * previously in which case the caller should take appropriate action. 98 * previously in which case the caller should take appropriate action.
99 * 99 *
100 * On success, the CPU is not guaranteed to be truly halted until 100 * On success, the CPU is not guaranteed to be truly halted until
101 * mcpm_cpu_power_down_finish() subsequently returns non-zero for the 101 * mcpm_wait_for_cpu_powerdown() subsequently returns non-zero for the
102 * specified cpu. Until then, other CPUs should make sure they do not 102 * specified cpu. Until then, other CPUs should make sure they do not
103 * trash memory the target CPU might be executing/accessing. 103 * trash memory the target CPU might be executing/accessing.
104 */ 104 */
105void mcpm_cpu_power_down(void); 105void mcpm_cpu_power_down(void);
106 106
107/** 107/**
108 * mcpm_cpu_power_down_finish - wait for a specified CPU to halt, and 108 * mcpm_wait_for_cpu_powerdown - wait for a specified CPU to halt, and
109 * make sure it is powered off 109 * make sure it is powered off
110 * 110 *
111 * @cpu: CPU number within given cluster 111 * @cpu: CPU number within given cluster
@@ -127,7 +127,7 @@ void mcpm_cpu_power_down(void);
127 * - zero if the CPU is in a safely parked state 127 * - zero if the CPU is in a safely parked state
128 * - nonzero otherwise (e.g., timeout) 128 * - nonzero otherwise (e.g., timeout)
129 */ 129 */
130int mcpm_cpu_power_down_finish(unsigned int cpu, unsigned int cluster); 130int mcpm_wait_for_cpu_powerdown(unsigned int cpu, unsigned int cluster);
131 131
132/** 132/**
133 * mcpm_cpu_suspend - bring the calling CPU in a suspended state 133 * mcpm_cpu_suspend - bring the calling CPU in a suspended state
@@ -171,7 +171,7 @@ int mcpm_cpu_powered_up(void);
171struct mcpm_platform_ops { 171struct mcpm_platform_ops {
172 int (*power_up)(unsigned int cpu, unsigned int cluster); 172 int (*power_up)(unsigned int cpu, unsigned int cluster);
173 void (*power_down)(void); 173 void (*power_down)(void);
174 int (*power_down_finish)(unsigned int cpu, unsigned int cluster); 174 int (*wait_for_powerdown)(unsigned int cpu, unsigned int cluster);
175 void (*suspend)(u64); 175 void (*suspend)(u64);
176 void (*powered_up)(void); 176 void (*powered_up)(void);
177}; 177};
diff --git a/arch/arm/include/asm/memblock.h b/arch/arm/include/asm/memblock.h
index c2f5102ae659..bf47a6c110a2 100644
--- a/arch/arm/include/asm/memblock.h
+++ b/arch/arm/include/asm/memblock.h
@@ -1,10 +1,9 @@
1#ifndef _ASM_ARM_MEMBLOCK_H 1#ifndef _ASM_ARM_MEMBLOCK_H
2#define _ASM_ARM_MEMBLOCK_H 2#define _ASM_ARM_MEMBLOCK_H
3 3
4struct meminfo;
5struct machine_desc; 4struct machine_desc;
6 5
7void arm_memblock_init(struct meminfo *, const struct machine_desc *); 6void arm_memblock_init(const struct machine_desc *);
8phys_addr_t arm_memblock_steal(phys_addr_t size, phys_addr_t align); 7phys_addr_t arm_memblock_steal(phys_addr_t size, phys_addr_t align);
9 8
10#endif 9#endif
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 02fa2558f662..2b751464d6ff 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -83,8 +83,6 @@
83 */ 83 */
84#define IOREMAP_MAX_ORDER 24 84#define IOREMAP_MAX_ORDER 24
85 85
86#define CONSISTENT_END (0xffe00000UL)
87
88#else /* CONFIG_MMU */ 86#else /* CONFIG_MMU */
89 87
90/* 88/*
diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h
index f94784f0e3a6..891a56b35bcf 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -28,53 +28,84 @@ struct outer_cache_fns {
28 void (*clean_range)(unsigned long, unsigned long); 28 void (*clean_range)(unsigned long, unsigned long);
29 void (*flush_range)(unsigned long, unsigned long); 29 void (*flush_range)(unsigned long, unsigned long);
30 void (*flush_all)(void); 30 void (*flush_all)(void);
31 void (*inv_all)(void);
32 void (*disable)(void); 31 void (*disable)(void);
33#ifdef CONFIG_OUTER_CACHE_SYNC 32#ifdef CONFIG_OUTER_CACHE_SYNC
34 void (*sync)(void); 33 void (*sync)(void);
35#endif 34#endif
36 void (*set_debug)(unsigned long);
37 void (*resume)(void); 35 void (*resume)(void);
36
37 /* This is an ARM L2C thing */
38 void (*write_sec)(unsigned long, unsigned);
38}; 39};
39 40
40extern struct outer_cache_fns outer_cache; 41extern struct outer_cache_fns outer_cache;
41 42
42#ifdef CONFIG_OUTER_CACHE 43#ifdef CONFIG_OUTER_CACHE
43 44/**
45 * outer_inv_range - invalidate range of outer cache lines
46 * @start: starting physical address, inclusive
47 * @end: end physical address, exclusive
48 */
44static inline void outer_inv_range(phys_addr_t start, phys_addr_t end) 49static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
45{ 50{
46 if (outer_cache.inv_range) 51 if (outer_cache.inv_range)
47 outer_cache.inv_range(start, end); 52 outer_cache.inv_range(start, end);
48} 53}
54
55/**
56 * outer_clean_range - clean dirty outer cache lines
57 * @start: starting physical address, inclusive
58 * @end: end physical address, exclusive
59 */
49static inline void outer_clean_range(phys_addr_t start, phys_addr_t end) 60static inline void outer_clean_range(phys_addr_t start, phys_addr_t end)
50{ 61{
51 if (outer_cache.clean_range) 62 if (outer_cache.clean_range)
52 outer_cache.clean_range(start, end); 63 outer_cache.clean_range(start, end);
53} 64}
65
66/**
67 * outer_flush_range - clean and invalidate outer cache lines
68 * @start: starting physical address, inclusive
69 * @end: end physical address, exclusive
70 */
54static inline void outer_flush_range(phys_addr_t start, phys_addr_t end) 71static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
55{ 72{
56 if (outer_cache.flush_range) 73 if (outer_cache.flush_range)
57 outer_cache.flush_range(start, end); 74 outer_cache.flush_range(start, end);
58} 75}
59 76
77/**
78 * outer_flush_all - clean and invalidate all cache lines in the outer cache
79 *
80 * Note: depending on implementation, this may not be atomic - it must
81 * only be called with interrupts disabled and no other active outer
82 * cache masters.
83 *
84 * It is intended that this function is only used by implementations
85 * needing to override the outer_cache.disable() method due to security.
86 * (Some implementations perform this as a clean followed by an invalidate.)
87 */
60static inline void outer_flush_all(void) 88static inline void outer_flush_all(void)
61{ 89{
62 if (outer_cache.flush_all) 90 if (outer_cache.flush_all)
63 outer_cache.flush_all(); 91 outer_cache.flush_all();
64} 92}
65 93
66static inline void outer_inv_all(void) 94/**
67{ 95 * outer_disable - clean, invalidate and disable the outer cache
68 if (outer_cache.inv_all) 96 *
69 outer_cache.inv_all(); 97 * Disable the outer cache, ensuring that any data contained in the outer
70} 98 * cache is pushed out to lower levels of system memory. The note and
71 99 * conditions above concerning outer_flush_all() applies here.
72static inline void outer_disable(void) 100 */
73{ 101extern void outer_disable(void);
74 if (outer_cache.disable)
75 outer_cache.disable();
76}
77 102
103/**
104 * outer_resume - restore the cache configuration and re-enable outer cache
105 *
106 * Restore any configuration that the cache had when previously enabled,
107 * and re-enable the outer cache.
108 */
78static inline void outer_resume(void) 109static inline void outer_resume(void)
79{ 110{
80 if (outer_cache.resume) 111 if (outer_cache.resume)
@@ -90,13 +121,18 @@ static inline void outer_clean_range(phys_addr_t start, phys_addr_t end)
90static inline void outer_flush_range(phys_addr_t start, phys_addr_t end) 121static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
91{ } 122{ }
92static inline void outer_flush_all(void) { } 123static inline void outer_flush_all(void) { }
93static inline void outer_inv_all(void) { }
94static inline void outer_disable(void) { } 124static inline void outer_disable(void) { }
95static inline void outer_resume(void) { } 125static inline void outer_resume(void) { }
96 126
97#endif 127#endif
98 128
99#ifdef CONFIG_OUTER_CACHE_SYNC 129#ifdef CONFIG_OUTER_CACHE_SYNC
130/**
131 * outer_sync - perform a sync point for outer cache
132 *
133 * Ensure that all outer cache operations are complete and any store
134 * buffers are drained.
135 */
100static inline void outer_sync(void) 136static inline void outer_sync(void)
101{ 137{
102 if (outer_cache.sync) 138 if (outer_cache.sync)
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index 8d6a089dfb76..e0adb9f1bf94 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -21,34 +21,6 @@
21#define __tagtable(tag, fn) \ 21#define __tagtable(tag, fn) \
22static const struct tagtable __tagtable_##fn __tag = { tag, fn } 22static const struct tagtable __tagtable_##fn __tag = { tag, fn }
23 23
24/*
25 * Memory map description
26 */
27#define NR_BANKS CONFIG_ARM_NR_BANKS
28
29struct membank {
30 phys_addr_t start;
31 phys_addr_t size;
32 unsigned int highmem;
33};
34
35struct meminfo {
36 int nr_banks;
37 struct membank bank[NR_BANKS];
38};
39
40extern struct meminfo meminfo;
41
42#define for_each_bank(iter,mi) \
43 for (iter = 0; iter < (mi)->nr_banks; iter++)
44
45#define bank_pfn_start(bank) __phys_to_pfn((bank)->start)
46#define bank_pfn_end(bank) __phys_to_pfn((bank)->start + (bank)->size)
47#define bank_pfn_size(bank) ((bank)->size >> PAGE_SHIFT)
48#define bank_phys_start(bank) (bank)->start
49#define bank_phys_end(bank) ((bank)->start + (bank)->size)
50#define bank_phys_size(bank) (bank)->size
51
52extern int arm_add_memory(u64 start, u64 size); 24extern int arm_add_memory(u64 start, u64 size);
53extern void early_print(const char *str, ...); 25extern void early_print(const char *str, ...);
54extern void dump_machine_table(void); 26extern void dump_machine_table(void);
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-24 02:31:52 -0400