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Diffstat (limited to 'arch/arm/include/asm/hardware/entry-macro-gic.S')
| -rw-r--r-- | arch/arm/include/asm/hardware/entry-macro-gic.S | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S deleted file mode 100644 index 74ebc803904d..000000000000 --- a/arch/arm/include/asm/hardware/entry-macro-gic.S +++ /dev/null | |||
| @@ -1,60 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/include/asm/hardware/entry-macro-gic.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for GIC | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <asm/hardware/gic.h> | ||
| 12 | |||
| 13 | #ifndef HAVE_GET_IRQNR_PREAMBLE | ||
| 14 | .macro get_irqnr_preamble, base, tmp | ||
| 15 | ldr \base, =gic_cpu_base_addr | ||
| 16 | ldr \base, [\base] | ||
| 17 | .endm | ||
| 18 | #endif | ||
| 19 | |||
| 20 | /* | ||
| 21 | * The interrupt numbering scheme is defined in the | ||
| 22 | * interrupt controller spec. To wit: | ||
| 23 | * | ||
| 24 | * Interrupts 0-15 are IPI | ||
| 25 | * 16-31 are local. We allow 30 to be used for the watchdog. | ||
| 26 | * 32-1020 are global | ||
| 27 | * 1021-1022 are reserved | ||
| 28 | * 1023 is "spurious" (no interrupt) | ||
| 29 | * | ||
| 30 | * A simple read from the controller will tell us the number of the highest | ||
| 31 | * priority enabled interrupt. We then just need to check whether it is in the | ||
| 32 | * valid range for an IRQ (30-1020 inclusive). | ||
| 33 | */ | ||
| 34 | |||
| 35 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 36 | |||
| 37 | ldr \irqstat, [\base, #GIC_CPU_INTACK] | ||
| 38 | /* bits 12-10 = src CPU, 9-0 = int # */ | ||
| 39 | |||
| 40 | ldr \tmp, =1021 | ||
| 41 | bic \irqnr, \irqstat, #0x1c00 | ||
| 42 | cmp \irqnr, #15 | ||
| 43 | cmpcc \irqnr, \irqnr | ||
| 44 | cmpne \irqnr, \tmp | ||
| 45 | cmpcs \irqnr, \irqnr | ||
| 46 | .endm | ||
| 47 | |||
| 48 | /* We assume that irqstat (the raw value of the IRQ acknowledge | ||
| 49 | * register) is preserved from the macro above. | ||
| 50 | * If there is an IPI, we immediately signal end of interrupt on the | ||
| 51 | * controller, since this requires the original irqstat value which | ||
| 52 | * we won't easily be able to recreate later. | ||
| 53 | */ | ||
| 54 | |||
| 55 | .macro test_for_ipi, irqnr, irqstat, base, tmp | ||
| 56 | bic \irqnr, \irqstat, #0x1c00 | ||
| 57 | cmp \irqnr, #16 | ||
| 58 | strcc \irqstat, [\base, #GIC_CPU_EOI] | ||
| 59 | cmpcs \irqnr, \irqnr | ||
| 60 | .endm | ||