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-rw-r--r--arch/arm/boot/dts/Makefile2
-rw-r--r--arch/arm/boot/dts/imx27-apf27dev.dts21
-rw-r--r--arch/arm/boot/dts/imx27.dtsi2
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts1
-rw-r--r--arch/arm/boot/dts/imx51-apf51dev.dts14
-rw-r--r--arch/arm/boot/dts/imx53.dtsi11
-rw-r--r--arch/arm/boot/dts/imx6dl-udoo.dts18
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6q-udoo.dts124
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi4
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabrelite.dtsi33
-rw-r--r--arch/arm/boot/dts/imx6qdl-udoo.dtsi134
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi5
-rw-r--r--arch/arm/boot/dts/imx6sx-sabreauto.dts146
-rw-r--r--arch/arm/boot/dts/imx6sx-sdb.dts39
-rw-r--r--arch/arm/boot/dts/vf-colibri-eval-v3.dtsi2
-rw-r--r--arch/arm/boot/dts/vf-colibri.dtsi3
-rw-r--r--arch/arm/boot/dts/vf500.dtsi23
-rw-r--r--arch/arm/boot/dts/vf610-twr.dts2
-rw-r--r--arch/arm/boot/dts/vfxxx.dtsi48
20 files changed, 484 insertions, 150 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 89b732b6d6cf..38e1ec7a81ff 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -273,6 +273,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
273 imx6dl-tx6dl-comtft.dtb \ 273 imx6dl-tx6dl-comtft.dtb \
274 imx6dl-tx6u-801x.dtb \ 274 imx6dl-tx6u-801x.dtb \
275 imx6dl-tx6u-811x.dtb \ 275 imx6dl-tx6u-811x.dtb \
276 imx6dl-udoo.dtb \
276 imx6dl-wandboard.dtb \ 277 imx6dl-wandboard.dtb \
277 imx6dl-wandboard-revb1.dtb \ 278 imx6dl-wandboard-revb1.dtb \
278 imx6q-arm2.dtb \ 279 imx6q-arm2.dtb \
@@ -307,6 +308,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
307dtb-$(CONFIG_SOC_IMX6SL) += \ 308dtb-$(CONFIG_SOC_IMX6SL) += \
308 imx6sl-evk.dtb 309 imx6sl-evk.dtb
309dtb-$(CONFIG_SOC_IMX6SX) += \ 310dtb-$(CONFIG_SOC_IMX6SX) += \
311 imx6sx-sabreauto.dtb \
310 imx6sx-sdb.dtb 312 imx6sx-sdb.dtb
311dtb-$(CONFIG_SOC_LS1021A) += \ 313dtb-$(CONFIG_SOC_LS1021A) += \
312 ls1021a-qds.dtb \ 314 ls1021a-qds.dtb \
diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts
index da306c5dd678..bba3f41b89ef 100644
--- a/arch/arm/boot/dts/imx27-apf27dev.dts
+++ b/arch/arm/boot/dts/imx27-apf27dev.dts
@@ -59,6 +59,21 @@
59 linux,default-trigger = "heartbeat"; 59 linux,default-trigger = "heartbeat";
60 }; 60 };
61 }; 61 };
62
63 regulators {
64 compatible = "simple-bus";
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 reg_max5821: regulator@0 {
69 compatible = "regulator-fixed";
70 reg = <0>;
71 regulator-name = "max5821-reg";
72 regulator-min-microvolt = <2500000>;
73 regulator-max-microvolt = <2500000>;
74 regulator-always-on;
75 };
76 };
62}; 77};
63 78
64&cspi1 { 79&cspi1 {
@@ -107,6 +122,12 @@
107 compatible = "dallas,ds1374"; 122 compatible = "dallas,ds1374";
108 reg = <0x68>; 123 reg = <0x68>;
109 }; 124 };
125
126 max5821@38 {
127 compatible = "maxim,max5821";
128 reg = <0x38>;
129 vref-supply = <&reg_max5821>;
130 };
110}; 131};
111 132
112&i2c2 { 133&i2c2 {
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 107d713e1cbe..4b063b68db44 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -464,7 +464,7 @@
464 }; 464 };
465 465
466 coda: coda@10023000 { 466 coda: coda@10023000 {
467 compatible = "fsl,imx27-vpu"; 467 compatible = "fsl,imx27-vpu", "cnm,codadx6";
468 reg = <0x10023000 0x0200>; 468 reg = <0x10023000 0x0200>;
469 interrupts = <53>; 469 interrupts = <53>;
470 clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>, 470 clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 0e13b4b10a92..279249b8c3f3 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -182,7 +182,6 @@
182 }; 182 };
183 183
184 lradc@80050000 { 184 lradc@80050000 {
185 fsl,lradc-touchscreen-wires = <4>;
186 status = "okay"; 185 status = "okay";
187 fsl,lradc-touchscreen-wires = <4>; 186 fsl,lradc-touchscreen-wires = <4>;
188 fsl,ave-ctrl = <4>; 187 fsl,ave-ctrl = <4>;
diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts
index c5a9a24c280a..93d3ea12328c 100644
--- a/arch/arm/boot/dts/imx51-apf51dev.dts
+++ b/arch/arm/boot/dts/imx51-apf51dev.dts
@@ -16,6 +16,14 @@
16 model = "Armadeus Systems APF51Dev docking/development board"; 16 model = "Armadeus Systems APF51Dev docking/development board";
17 compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51"; 17 compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51";
18 18
19 backlight@bl1{
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_backlight>;
22 compatible = "gpio-backlight";
23 gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
24 default-on;
25 };
26
19 display@di1 { 27 display@di1 {
20 compatible = "fsl,imx-parallel-display"; 28 compatible = "fsl,imx-parallel-display";
21 interface-pix-fmt = "bgr666"; 29 interface-pix-fmt = "bgr666";
@@ -114,6 +122,12 @@
114 pinctrl-0 = <&pinctrl_hog>; 122 pinctrl-0 = <&pinctrl_hog>;
115 123
116 imx51-apf51dev { 124 imx51-apf51dev {
125 pinctrl_backlight: bl1grp {
126 fsl,pins = <
127 MX51_PAD_DI1_D1_CS__GPIO3_4 0x1F5
128 >;
129 };
130
117 pinctrl_hog: hoggrp { 131 pinctrl_hog: hoggrp {
118 fsl,pins = < 132 fsl,pins = <
119 MX51_PAD_EIM_EB2__GPIO2_22 0x0C5 133 MX51_PAD_EIM_EB2__GPIO2_22 0x0C5
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index a30bddfdbdb6..ff4fa7ecacd8 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -756,7 +756,7 @@
756 }; 756 };
757 757
758 vpu: vpu@63ff4000 { 758 vpu: vpu@63ff4000 {
759 compatible = "fsl,imx53-vpu"; 759 compatible = "fsl,imx53-vpu", "cnm,coda7541";
760 reg = <0x63ff4000 0x1000>; 760 reg = <0x63ff4000 0x1000>;
761 interrupts = <9>; 761 interrupts = <9>;
762 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, 762 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
@@ -765,6 +765,15 @@
765 resets = <&src 1>; 765 resets = <&src 1>;
766 iram = <&ocram>; 766 iram = <&ocram>;
767 }; 767 };
768
769 sahara: crypto@63ff8000 {
770 compatible = "fsl,imx53-sahara";
771 reg = <0x63ff8000 0x4000>;
772 interrupts = <19 20>;
773 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
774 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
775 clock-names = "ipg", "ahb";
776 };
768 }; 777 };
769 778
770 ocram: sram@f8000000 { 779 ocram: sram@f8000000 {
diff --git a/arch/arm/boot/dts/imx6dl-udoo.dts b/arch/arm/boot/dts/imx6dl-udoo.dts
new file mode 100644
index 000000000000..e3713f00e819
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-udoo.dts
@@ -0,0 +1,18 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11/dts-v1/;
12#include "imx6dl.dtsi"
13#include "imx6qdl-udoo.dtsi"
14
15/ {
16 model = "Udoo i.MX6 Dual-lite Board";
17 compatible = "udoo,imx6dl-udoo", "fsl,imx6dl";
18};
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 1ac2fe732867..f94bf72832af 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -28,7 +28,7 @@
28 next-level-cache = <&L2>; 28 next-level-cache = <&L2>;
29 operating-points = < 29 operating-points = <
30 /* kHz uV */ 30 /* kHz uV */
31 996000 1275000 31 996000 1250000
32 792000 1175000 32 792000 1175000
33 396000 1075000 33 396000 1075000
34 >; 34 >;
diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/imx6q-udoo.dts
index e3bff2ac00db..c3e64ff3d544 100644
--- a/arch/arm/boot/dts/imx6q-udoo.dts
+++ b/arch/arm/boot/dts/imx6q-udoo.dts
@@ -8,137 +8,15 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 * 9 *
10 */ 10 */
11
12/dts-v1/; 11/dts-v1/;
13#include "imx6q.dtsi" 12#include "imx6q.dtsi"
13#include "imx6qdl-udoo.dtsi"
14 14
15/ { 15/ {
16 model = "Udoo i.MX6 Quad Board"; 16 model = "Udoo i.MX6 Quad Board";
17 compatible = "udoo,imx6q-udoo", "fsl,imx6q"; 17 compatible = "udoo,imx6q-udoo", "fsl,imx6q";
18
19 chosen {
20 stdout-path = &uart2;
21 };
22
23 memory {
24 reg = <0x10000000 0x40000000>;
25 };
26
27 regulators {
28 compatible = "simple-bus";
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 reg_usb_h1_vbus: regulator@0 {
33 compatible = "regulator-fixed";
34 reg = <0>;
35 regulator-name = "usb_h1_vbus";
36 regulator-min-microvolt = <5000000>;
37 regulator-max-microvolt = <5000000>;
38 enable-active-high;
39 startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */
40 gpio = <&gpio7 12 0>;
41 };
42 };
43};
44
45&fec {
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_enet>;
48 phy-mode = "rgmii";
49 status = "okay";
50};
51
52&hdmi {
53 ddc-i2c-bus = <&i2c2>;
54 status = "okay";
55};
56
57&i2c2 {
58 clock-frequency = <100000>;
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_i2c2>;
61 status = "okay";
62};
63
64&iomuxc {
65 imx6q-udoo {
66 pinctrl_enet: enetgrp {
67 fsl,pins = <
68 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
69 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
70 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
71 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
72 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
73 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
74 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
75 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
76 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
77 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
78 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
79 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
80 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
81 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
82 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
83 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
84 >;
85 };
86
87 pinctrl_i2c2: i2c2grp {
88 fsl,pins = <
89 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
90 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
91 >;
92 };
93
94 pinctrl_uart2: uart2grp {
95 fsl,pins = <
96 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
97 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
98 >;
99 };
100
101 pinctrl_usbh: usbhgrp {
102 fsl,pins = <
103 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
104 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0
105 >;
106 };
107
108 pinctrl_usdhc3: usdhc3grp {
109 fsl,pins = <
110 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
111 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
112 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
113 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
114 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
115 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
116 >;
117 };
118 };
119}; 18};
120 19
121&sata { 20&sata {
122 status = "okay"; 21 status = "okay";
123}; 22};
124
125&uart2 {
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_uart2>;
128 status = "okay";
129};
130
131&usbh1 {
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_usbh>;
134 vbus-supply = <&reg_usb_h1_vbus>;
135 clocks = <&clks 201>;
136 status = "okay";
137};
138
139&usdhc3 {
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_usdhc3>;
142 non-removable;
143 status = "okay";
144};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 85f72e6b5bad..93ec79bb6b35 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -31,7 +31,7 @@
31 1200000 1275000 31 1200000 1275000
32 996000 1250000 32 996000 1250000
33 852000 1250000 33 852000 1250000
34 792000 1150000 34 792000 1175000
35 396000 975000 35 396000 975000
36 >; 36 >;
37 fsl,soc-operating-points = < 37 fsl,soc-operating-points = <
@@ -95,6 +95,8 @@
95 clocks = <&clks IMX6Q_CLK_ECSPI5>, 95 clocks = <&clks IMX6Q_CLK_ECSPI5>,
96 <&clks IMX6Q_CLK_ECSPI5>; 96 <&clks IMX6Q_CLK_ECSPI5>;
97 clock-names = "ipg", "per"; 97 clock-names = "ipg", "per";
98 dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
99 dma-names = "rx", "tx";
98 status = "disabled"; 100 status = "disabled";
99 }; 101 };
100 }; 102 };
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index 0a36129152e0..0b28a9d5241e 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -173,6 +173,11 @@
173 status = "okay"; 173 status = "okay";
174}; 174};
175 175
176&hdmi {
177 ddc-i2c-bus = <&i2c2>;
178 status = "okay";
179};
180
176&i2c1 { 181&i2c1 {
177 clock-frequency = <100000>; 182 clock-frequency = <100000>;
178 pinctrl-names = "default"; 183 pinctrl-names = "default";
@@ -188,6 +193,20 @@
188 }; 193 };
189}; 194};
190 195
196&i2c2 {
197 clock-frequency = <100000>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_i2c2>;
200 status = "okay";
201};
202
203&i2c3 {
204 clock-frequency = <100000>;
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_i2c3>;
207 status = "okay";
208};
209
191&iomuxc { 210&iomuxc {
192 pinctrl-names = "default"; 211 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_hog>; 212 pinctrl-0 = <&pinctrl_hog>;
@@ -265,6 +284,20 @@
265 >; 284 >;
266 }; 285 };
267 286
287 pinctrl_i2c2: i2c2grp {
288 fsl,pins = <
289 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
290 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
291 >;
292 };
293
294 pinctrl_i2c3: i2c3grp {
295 fsl,pins = <
296 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
297 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
298 >;
299 };
300
268 pinctrl_pwm1: pwm1grp { 301 pinctrl_pwm1: pwm1grp {
269 fsl,pins = < 302 fsl,pins = <
270 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 303 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
new file mode 100644
index 000000000000..1211da894ee9
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
@@ -0,0 +1,134 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12/ {
13 chosen {
14 stdout-path = &uart2;
15 };
16
17 memory {
18 reg = <0x10000000 0x40000000>;
19 };
20
21 regulators {
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 reg_usb_h1_vbus: regulator@0 {
27 compatible = "regulator-fixed";
28 reg = <0>;
29 regulator-name = "usb_h1_vbus";
30 regulator-min-microvolt = <5000000>;
31 regulator-max-microvolt = <5000000>;
32 enable-active-high;
33 startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */
34 gpio = <&gpio7 12 0>;
35 };
36 };
37};
38
39&fec {
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_enet>;
42 phy-mode = "rgmii";
43 status = "okay";
44};
45
46&hdmi {
47 ddc-i2c-bus = <&i2c2>;
48 status = "okay";
49};
50
51&i2c2 {
52 clock-frequency = <100000>;
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_i2c2>;
55 status = "okay";
56};
57
58&iomuxc {
59 imx6q-udoo {
60 pinctrl_enet: enetgrp {
61 fsl,pins = <
62 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
63 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
64 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
65 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
66 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
67 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
68 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
69 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
70 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
71 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
72 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
73 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
74 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
75 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
76 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
77 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
78 >;
79 };
80
81 pinctrl_i2c2: i2c2grp {
82 fsl,pins = <
83 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
84 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
85 >;
86 };
87
88 pinctrl_uart2: uart2grp {
89 fsl,pins = <
90 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
91 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
92 >;
93 };
94
95 pinctrl_usbh: usbhgrp {
96 fsl,pins = <
97 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
98 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0
99 >;
100 };
101
102 pinctrl_usdhc3: usdhc3grp {
103 fsl,pins = <
104 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
105 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
106 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
107 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
108 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
109 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
110 >;
111 };
112 };
113};
114
115&uart2 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_uart2>;
118 status = "okay";
119};
120
121&usbh1 {
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_usbh>;
124 vbus-supply = <&reg_usb_h1_vbus>;
125 clocks = <&clks 201>;
126 status = "okay";
127};
128
129&usdhc3 {
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_usdhc3>;
132 non-removable;
133 status = "okay";
134};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 4fc03b7f1cee..f6c6a6e1cf3d 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -339,9 +339,8 @@
339 <0 12 IRQ_TYPE_LEVEL_HIGH>; 339 <0 12 IRQ_TYPE_LEVEL_HIGH>;
340 interrupt-names = "bit", "jpeg"; 340 interrupt-names = "bit", "jpeg";
341 clocks = <&clks IMX6QDL_CLK_VPU_AXI>, 341 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
342 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>, 342 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
343 <&clks IMX6QDL_CLK_OCRAM>; 343 clock-names = "per", "ahb";
344 clock-names = "per", "ahb", "ocram";
345 resets = <&src 1>; 344 resets = <&src 1>;
346 iram = <&ocram>; 345 iram = <&ocram>;
347 }; 346 };
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts
new file mode 100644
index 000000000000..e3c0b63c2205
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -0,0 +1,146 @@
1/*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
11#include "imx6sx.dtsi"
12
13/ {
14 model = "Freescale i.MX6 SoloX Sabre Auto Board";
15 compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
16
17 memory {
18 reg = <0x80000000 0x80000000>;
19 };
20
21 regulators {
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 vcc_sd3: regulator@0 {
27 compatible = "regulator-fixed";
28 reg = <0>;
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_vcc_sd3>;
31 regulator-name = "VCC_SD3";
32 regulator-min-microvolt = <3000000>;
33 regulator-max-microvolt = <3000000>;
34 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
35 enable-active-high;
36 };
37 };
38};
39
40&uart1 {
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_uart1>;
43 status = "okay";
44};
45
46&usdhc3 {
47 pinctrl-names = "default", "state_100mhz", "state_200mhz";
48 pinctrl-0 = <&pinctrl_usdhc3>;
49 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
50 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
51 bus-width = <8>;
52 cd-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>;
53 wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
54 keep-power-in-suspend;
55 enable-sdio-wakeup;
56 vmmc-supply = <&vcc_sd3>;
57 status = "okay";
58};
59
60&usdhc4 {
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_usdhc4>;
63 bus-width = <8>;
64 cd-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
65 no-1-8-v;
66 keep-power-in-suspend;
67 enable-sdio-wakup;
68 status = "okay";
69};
70
71&iomuxc {
72 imx6x-sabreauto {
73 pinctrl_uart1: uart1grp {
74 fsl,pins = <
75 MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
76 MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
77 >;
78 };
79
80 pinctrl_usdhc3: usdhc3grp {
81 fsl,pins = <
82 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
83 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
84 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
85 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
86 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
87 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
88 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
89 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
90 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
91 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
92 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
93 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
94 >;
95 };
96
97 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
98 fsl,pins = <
99 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
100 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
101 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
102 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
103 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
104 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
105 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
106 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
107 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
108 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
109 >;
110 };
111
112 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
113 fsl,pins = <
114 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
115 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
116 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
117 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
118 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
119 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
120 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
121 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
122 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
123 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
124 >;
125 };
126
127 pinctrl_usdhc4: usdhc4grp {
128 fsl,pins = <
129 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
130 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
131 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
132 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
133 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
134 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
135 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
136 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
137 >;
138 };
139
140 pinctrl_vcc_sd3: vccsd3grp {
141 fsl,pins = <
142 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
143 >;
144 };
145 };
146};
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 1e6e5cc1c14c..cdffe8465c46 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -340,6 +340,28 @@
340 status = "okay"; 340 status = "okay";
341}; 341};
342 342
343&qspi2 {
344 pinctrl-names = "default";
345 pinctrl-0 = <&pinctrl_qspi2>;
346 status = "okay";
347
348 flash0: s25fl128s@0 {
349 reg = <0>;
350 #address-cells = <1>;
351 #size-cells = <1>;
352 compatible = "spansion,s25fl128s";
353 spi-max-frequency = <66000000>;
354 };
355
356 flash1: s25fl128s@1 {
357 reg = <1>;
358 #address-cells = <1>;
359 #size-cells = <1>;
360 compatible = "spansion,s25fl128s";
361 spi-max-frequency = <66000000>;
362 };
363};
364
343&ssi2 { 365&ssi2 {
344 status = "okay"; 366 status = "okay";
345}; 367};
@@ -524,6 +546,23 @@
524 >; 546 >;
525 }; 547 };
526 548
549 pinctrl_qspi2: qspi2grp {
550 fsl,pins = <
551 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1
552 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1
553 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1
554 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1
555 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1
556 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1
557 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1
558 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1
559 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1
560 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1
561 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1
562 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1
563 >;
564 };
565
527 pinctrl_vcc_sd3: vccsd3grp { 566 pinctrl_vcc_sd3: vccsd3grp {
528 fsl,pins = < 567 fsl,pins = <
529 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 568 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
index 56a452bc326c..36cafbfa1bfa 100644
--- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
@@ -35,7 +35,7 @@
35 regulator-name = "usbh_vbus"; 35 regulator-name = "usbh_vbus";
36 regulator-min-microvolt = <5000000>; 36 regulator-min-microvolt = <5000000>;
37 regulator-max-microvolt = <5000000>; 37 regulator-max-microvolt = <5000000>;
38 gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; 38 gpio = <&gpio2 19 GPIO_ACTIVE_LOW>;
39 vin-supply = <&sys_5v0_reg>; 39 vin-supply = <&sys_5v0_reg>;
40 }; 40 };
41 }; 41 };
diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi
index 82f5728be5c9..5c2b7320856d 100644
--- a/arch/arm/boot/dts/vf-colibri.dtsi
+++ b/arch/arm/boot/dts/vf-colibri.dtsi
@@ -31,7 +31,7 @@
31 pinctrl-names = "default"; 31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_esdhc1>; 32 pinctrl-0 = <&pinctrl_esdhc1>;
33 bus-width = <4>; 33 bus-width = <4>;
34 cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 34 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
35}; 35};
36 36
37&fec1 { 37&fec1 {
@@ -121,6 +121,7 @@
121 121
122 pinctrl_fec1: fec1grp { 122 pinctrl_fec1: fec1grp {
123 fsl,pins = < 123 fsl,pins = <
124 VF610_PAD_PTA6__RMII_CLKOUT 0x30d2
124 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 125 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
125 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 126 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
126 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 127 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index de6700542714..1dbf8d2d1ddf 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -94,23 +94,23 @@
94 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 94 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
95}; 95};
96 96
97&gpio1 { 97&gpio0 {
98 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 98 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
99}; 99};
100 100
101&gpio2 { 101&gpio1 {
102 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 102 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
103}; 103};
104 104
105&gpio3 { 105&gpio2 {
106 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 106 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
107}; 107};
108 108
109&gpio4 { 109&gpio3 {
110 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 110 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
111}; 111};
112 112
113&gpio5 { 113&gpio4 {
114 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 114 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
115}; 115};
116 116
@@ -130,6 +130,14 @@
130 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 130 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
131}; 131};
132 132
133&snvsrtc {
134 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
135};
136
137&src {
138 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
139};
140
133&uart0 { 141&uart0 {
134 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 142 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
135}; 143};
@@ -169,3 +177,8 @@
169&usbphy1 { 177&usbphy1 {
170 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 178 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
171}; 179};
180
181&wdoga5 {
182 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
183 status = "okay";
184};
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index a0f762159cb2..289fef20cd83 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -123,7 +123,7 @@
123 pinctrl-names = "default"; 123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_esdhc1>; 124 pinctrl-0 = <&pinctrl_esdhc1>;
125 bus-width = <4>; 125 bus-width = <4>;
126 cd-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; 126 cd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
127 status = "okay"; 127 status = "okay";
128}; 128};
129 129
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index 505969ae8093..a29c7ce15eaf 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -22,11 +22,11 @@
22 serial3 = &uart3; 22 serial3 = &uart3;
23 serial4 = &uart4; 23 serial4 = &uart4;
24 serial5 = &uart5; 24 serial5 = &uart5;
25 gpio0 = &gpio1; 25 gpio0 = &gpio0;
26 gpio1 = &gpio2; 26 gpio1 = &gpio1;
27 gpio2 = &gpio3; 27 gpio2 = &gpio2;
28 gpio3 = &gpio4; 28 gpio3 = &gpio3;
29 gpio4 = &gpio5; 29 gpio4 = &gpio4;
30 usbphy0 = &usbphy0; 30 usbphy0 = &usbphy0;
31 usbphy1 = &usbphy1; 31 usbphy1 = &usbphy1;
32 }; 32 };
@@ -43,6 +43,13 @@
43 clock-frequency = <32768>; 43 clock-frequency = <32768>;
44 }; 44 };
45 45
46 reboot: syscon-reboot {
47 compatible = "syscon-reboot";
48 regmap = <&src>;
49 offset = <0x0>;
50 mask = <0x1000>;
51 };
52
46 soc { 53 soc {
47 #address-cells = <1>; 54 #address-cells = <1>;
48 #size-cells = <1>; 55 #size-cells = <1>;
@@ -184,7 +191,7 @@
184 status = "disabled"; 191 status = "disabled";
185 }; 192 };
186 193
187 wdog@4003e000 { 194 wdoga5: wdog@4003e000 {
188 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; 195 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
189 reg = <0x4003e000 0x1000>; 196 reg = <0x4003e000 0x1000>;
190 clocks = <&clks VF610_CLK_WDT>; 197 clocks = <&clks VF610_CLK_WDT>;
@@ -209,7 +216,7 @@
209 #gpio-range-cells = <3>; 216 #gpio-range-cells = <3>;
210 }; 217 };
211 218
212 gpio1: gpio@40049000 { 219 gpio0: gpio@40049000 {
213 compatible = "fsl,vf610-gpio"; 220 compatible = "fsl,vf610-gpio";
214 reg = <0x40049000 0x1000 0x400ff000 0x40>; 221 reg = <0x40049000 0x1000 0x400ff000 0x40>;
215 gpio-controller; 222 gpio-controller;
@@ -219,7 +226,7 @@
219 gpio-ranges = <&iomuxc 0 0 32>; 226 gpio-ranges = <&iomuxc 0 0 32>;
220 }; 227 };
221 228
222 gpio2: gpio@4004a000 { 229 gpio1: gpio@4004a000 {
223 compatible = "fsl,vf610-gpio"; 230 compatible = "fsl,vf610-gpio";
224 reg = <0x4004a000 0x1000 0x400ff040 0x40>; 231 reg = <0x4004a000 0x1000 0x400ff040 0x40>;
225 gpio-controller; 232 gpio-controller;
@@ -229,7 +236,7 @@
229 gpio-ranges = <&iomuxc 0 32 32>; 236 gpio-ranges = <&iomuxc 0 32 32>;
230 }; 237 };
231 238
232 gpio3: gpio@4004b000 { 239 gpio2: gpio@4004b000 {
233 compatible = "fsl,vf610-gpio"; 240 compatible = "fsl,vf610-gpio";
234 reg = <0x4004b000 0x1000 0x400ff080 0x40>; 241 reg = <0x4004b000 0x1000 0x400ff080 0x40>;
235 gpio-controller; 242 gpio-controller;
@@ -239,7 +246,7 @@
239 gpio-ranges = <&iomuxc 0 64 32>; 246 gpio-ranges = <&iomuxc 0 64 32>;
240 }; 247 };
241 248
242 gpio4: gpio@4004c000 { 249 gpio3: gpio@4004c000 {
243 compatible = "fsl,vf610-gpio"; 250 compatible = "fsl,vf610-gpio";
244 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; 251 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
245 gpio-controller; 252 gpio-controller;
@@ -249,7 +256,7 @@
249 gpio-ranges = <&iomuxc 0 96 32>; 256 gpio-ranges = <&iomuxc 0 96 32>;
250 }; 257 };
251 258
252 gpio5: gpio@4004d000 { 259 gpio4: gpio@4004d000 {
253 compatible = "fsl,vf610-gpio"; 260 compatible = "fsl,vf610-gpio";
254 reg = <0x4004d000 0x1000 0x400ff100 0x40>; 261 reg = <0x4004d000 0x1000 0x400ff100 0x40>;
255 gpio-controller; 262 gpio-controller;
@@ -318,6 +325,11 @@
318 clocks = <&clks VF610_CLK_USBC0>; 325 clocks = <&clks VF610_CLK_USBC0>;
319 status = "disabled"; 326 status = "disabled";
320 }; 327 };
328
329 src: src@4006e000 {
330 compatible = "fsl,vf610-src", "syscon";
331 reg = <0x4006e000 0x1000>;
332 };
321 }; 333 };
322 334
323 aips1: aips-bus@40080000 { 335 aips1: aips-bus@40080000 {
@@ -339,6 +351,20 @@
339 status = "disabled"; 351 status = "disabled";
340 }; 352 };
341 353
354 snvs0: snvs@400a7000 {
355 compatible = "fsl,sec-v4.0-mon", "simple-bus";
356 #address-cells = <1>;
357 #size-cells = <1>;
358 ranges = <0 0x400a7000 0x2000>;
359
360 snvsrtc: snvs-rtc-lp@34 {
361 compatible = "fsl,sec-v4.0-mon-rtc-lp";
362 reg = <0x34 0x58>;
363 clocks = <&clks VF610_CLK_SNVS>;
364 clock-names = "snvs-rtc";
365 };
366 };
367
342 uart4: serial@400a9000 { 368 uart4: serial@400a9000 {
343 compatible = "fsl,vf610-lpuart"; 369 compatible = "fsl,vf610-lpuart";
344 reg = <0x400a9000 0x1000>; 370 reg = <0x400a9000 0x1000>;
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-12 14:23:55 -0400