3 files changed, 42 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts
index d42ff1dcd89f..7ce798be5e01 100644
--- a/arch/arm/boot/dts/stih416-b2020.dts
+++ b/arch/arm/boot/dts/stih416-b2020.dts
@@ -19,5 +19,15 @@
                         bus-width    = <8>;
                         non-removable;
                 };
+
+                miphy365x_phy: miphy365x@fe382000 {
+                        phy_port0: port@fe382000 {
+                                st,sata-gen = <3>;
+                        };
+
+                        phy_port1: port@fe38a000 {
+                                st,pcie-tx-pol-inv;
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/stih416-b2020e.dts b/arch/arm/boot/dts/stih416-b2020e.dts
index a0434b6ae772..fa59224115bb 100644
--- a/arch/arm/boot/dts/stih416-b2020e.dts
+++ b/arch/arm/boot/dts/stih416-b2020e.dts
@@ -37,5 +37,15 @@
                         bus-width    = <8>;
                         non-removable;
                 };
+
+                miphy365x_phy: miphy365x@fe382000 {
+                        phy_port0: port@fe382000 {
+                                st,sata-gen = <3>;
+                        };
+
+                        phy_port1: port@fe38a000 {
+                                st,pcie-tx-pol-inv;
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 28091548d915..a54f6832a9ac 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -9,6 +9,8 @@
 #include "stih41x.dtsi"
 #include "stih416-clock.dtsi"
 #include "stih416-pinctrl.dtsi"
+
+#include <dt-bindings/phy/phy-miphy365x.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset-controller/stih416-resets.h>
 / {
@@ -278,5 +280,25 @@
                         clock-names     = "mmc";
                         clocks          = <&clk_s_a1_ls 8>;
                 };
+
+                miphy365x_phy: miphy365x@fe382000 {
+                        compatible      = "st,miphy365x-phy";
+                        st,syscfg       = <&syscfg_rear>;
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        ranges;
+
+                        phy_port0: port@fe382000 {
+                                #phy-cells = <1>;
+                                reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
+                                reg-names = "sata", "pcie", "syscfg";
+                        };
+
+                        phy_port1: port@fe38a000 {
+                                #phy-cells = <1>;
+                                reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
+                                reg-names = "sata", "pcie", "syscfg";
+                        };
+                };
         };
 };