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-rw-r--r--arch/arm/boot/dts/Makefile6
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi5
-rw-r--r--arch/arm/boot/dts/am4372.dtsi5
-rw-r--r--arch/arm/boot/dts/at91-sama5d4ek.dts260
-rw-r--r--arch/arm/boot/dts/bcm63138.dtsi134
-rw-r--r--arch/arm/boot/dts/bcm963138dvt.dts30
-rw-r--r--arch/arm/boot/dts/dra7.dtsi1
-rw-r--r--arch/arm/boot/dts/hip04-d01.dts32
-rw-r--r--arch/arm/boot/dts/hip04.dtsi267
-rw-r--r--arch/arm/boot/dts/omap3.dtsi1
-rw-r--r--arch/arm/boot/dts/omap4.dtsi7
-rw-r--r--arch/arm/boot/dts/omap5.dtsi9
-rw-r--r--arch/arm/boot/dts/r7s72100-genmai.dts4
-rw-r--r--arch/arm/boot/dts/r7s72100.dtsi10
-rw-r--r--arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts283
-rw-r--r--arch/arm/boot/dts/r8a7740-armadillo800eva.dts276
-rw-r--r--arch/arm/boot/dts/r8a7740.dtsi220
-rw-r--r--arch/arm/boot/dts/r8a7778.dtsi6
-rw-r--r--arch/arm/boot/dts/r8a7779-marzen.dts4
-rw-r--r--arch/arm/boot/dts/r8a7779.dtsi42
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts4
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi32
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch.dts4
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi32
-rw-r--r--arch/arm/boot/dts/sama5d4.dtsi1240
-rw-r--r--arch/arm/boot/dts/sh7372.dtsi1
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g-reference.dts4
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi12
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi5
29 files changed, 2646 insertions, 290 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e6aa6e77a3ec..d3e687ecfc95 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -48,11 +48,14 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb
48dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb 48dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb
49dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb 49dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb
50dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb 50dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb
51# sama5d4
52dtb-$(CONFIG_ARCH_AT91) += at91-sama5d4ek.dtb
51 53
52dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb 54dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
53dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb 55dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
54dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb 56dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
55dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb 57dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
58dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
56dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \ 59dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
57 bcm21664-garnet.dtb 60 bcm21664-garnet.dtb
58dtb-$(CONFIG_ARCH_BERLIN) += \ 61dtb-$(CONFIG_ARCH_BERLIN) += \
@@ -90,6 +93,7 @@ dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb
90dtb-$(CONFIG_ARCH_HIX5HD2) += hisi-x5hd2-dkb.dtb 93dtb-$(CONFIG_ARCH_HIX5HD2) += hisi-x5hd2-dkb.dtb
91dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ 94dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
92 ecx-2000.dtb 95 ecx-2000.dtb
96dtb-$(CONFIG_ARCH_HIP04) += hip04-d01.dtb
93dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ 97dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
94 integratorcp.dtb 98 integratorcp.dtb
95dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \ 99dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \
@@ -361,7 +365,6 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
361 r8a7740-armadillo800eva.dtb \ 365 r8a7740-armadillo800eva.dtb \
362 r8a7778-bockw.dtb \ 366 r8a7778-bockw.dtb \
363 r8a7778-bockw-reference.dtb \ 367 r8a7778-bockw-reference.dtb \
364 r8a7740-armadillo800eva-reference.dtb \
365 r8a7779-marzen.dtb \ 368 r8a7779-marzen.dtb \
366 r8a7791-koelsch.dtb \ 369 r8a7791-koelsch.dtb \
367 r8a7790-lager.dtb \ 370 r8a7790-lager.dtb \
@@ -372,6 +375,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
372 sh7372-mackerel.dtb 375 sh7372-mackerel.dtb
373dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \ 376dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
374 r7s72100-genmai.dtb \ 377 r7s72100-genmai.dtb \
378 r8a7740-armadillo800eva.dtb \
375 r8a7791-henninger.dtb \ 379 r8a7791-henninger.dtb \
376 r8a7791-koelsch.dtb \ 380 r8a7791-koelsch.dtb \
377 r8a7790-lager.dtb \ 381 r8a7790-lager.dtb \
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 3a0a161342ba..c8238c467acf 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -726,9 +726,8 @@
726 }; 726 };
727 727
728 ocmcram: ocmcram@40300000 { 728 ocmcram: ocmcram@40300000 {
729 compatible = "ti,am3352-ocmcram"; 729 compatible = "mmio-sram";
730 reg = <0x40300000 0x10000>; 730 reg = <0x40300000 0x10000>; /* 64k */
731 ti,hwmods = "ocmcram";
732 }; 731 };
733 732
734 wkup_m3: wkup_m3@44d00000 { 733 wkup_m3: wkup_m3@44d00000 {
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 8689949bdba3..24531de979f2 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -885,6 +885,11 @@
885 clock-names = "fck"; 885 clock-names = "fck";
886 }; 886 };
887 }; 887 };
888
889 ocmcram: ocmcram@40300000 {
890 compatible = "mmio-sram";
891 reg = <0x40300000 0x40000>; /* 256k */
892 };
888 }; 893 };
889}; 894};
890 895
diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts
new file mode 100644
index 000000000000..b5b84006469e
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sama5d4ek.dts
@@ -0,0 +1,260 @@
1/*
2 * at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit
3 *
4 * Copyright (C) 2014 Atmel,
5 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This library is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This library is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45/dts-v1/;
46#include "sama5d4.dtsi"
47
48/ {
49 model = "Atmel SAMA5D4-EK";
50 compatible = "atmel,sama5d4ek", "atmel,sama5d4", "atmel,sama5";
51
52 chosen {
53 bootargs = "console=ttyS0,115200 ignore_loglevel earlyprintk";
54 };
55
56 memory {
57 reg = <0x20000000 0x20000000>;
58 };
59
60 clocks {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 ranges;
64
65 main_clock: clock@0 {
66 compatible = "atmel,osc", "fixed-clock";
67 clock-frequency = <12000000>;
68 };
69
70 slow_xtal {
71 clock-frequency = <32768>;
72 };
73
74 main_xtal {
75 clock-frequency = <12000000>;
76 };
77 };
78
79 ahb {
80 apb {
81 lcd_bus@f0000000 {
82 status = "okay";
83
84 lcd@f0000000 {
85 status = "okay";
86 };
87
88 lcdovl1@f0000140 {
89 status = "okay";
90 };
91
92 lcdovl2@f0000240 {
93 status = "okay";
94 };
95
96 lcdheo1@f0000340 {
97 status = "okay";
98 };
99 };
100
101 adc0: adc@fc034000 {
102 /* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */
103 atmel,adc-vref = <3300>;
104 /*atmel,adc-ts-wires = <4>;*/ /* Set up ADC touch screen */
105 status = "okay"; /* Enable ADC IIO support */
106 };
107
108 mmc0: mmc@f8000000 {
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
111 slot@1 {
112 reg = <1>;
113 bus-width = <4>;
114 cd-gpios = <&pioE 5 0>;
115 };
116 };
117
118 spi0: spi@f8010000 {
119 cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
120 status = "okay";
121 m25p80@0 {
122 compatible = "atmel,at25df321a";
123 spi-max-frequency = <50000000>;
124 reg = <0>;
125 };
126 };
127
128 i2c0: i2c@f8014000 {
129 status = "okay";
130 };
131
132 macb0: ethernet@f8020000 {
133 phy-mode = "rmii";
134 status = "okay";
135 };
136
137 mmc1: mmc@fc000000 {
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
140 status = "okay";
141 slot@0 {
142 reg = <0>;
143 bus-width = <4>;
144 cd-gpios = <&pioE 6 0>;
145 };
146 };
147
148 usart2: serial@fc008000 {
149 status = "okay";
150 };
151
152 usart3: serial@fc00c000 {
153 status = "okay";
154 };
155
156 usart4: serial@fc010000 {
157 status = "okay";
158 };
159
160 watchdog@fc068640 {
161 status = "okay";
162 };
163
164 pinctrl@fc06a000 {
165 board {
166 pinctrl_mmc0_cd: mmc0_cd {
167 atmel,pins =
168 <AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
169 };
170 pinctrl_mmc1_cd: mmc1_cd {
171 atmel,pins =
172 <AT91_PIOE 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
173 };
174 pinctrl_usba_vbus: usba_vbus {
175 atmel,pins =
176 <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
177 };
178 pinctrl_key_gpio: key_gpio_0 {
179 atmel,pins =
180 <AT91_PIOE 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PE13 gpio */
181 };
182 };
183 };
184 };
185
186 usb0: gadget@00400000 {
187 atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_usba_vbus>;
190 status = "okay";
191 };
192
193 usb1: ohci@00500000 {
194 num-ports = <3>;
195 atmel,vbus-gpio = <0 /* &pioE 10 GPIO_ACTIVE_LOW */
196 &pioE 11 GPIO_ACTIVE_LOW
197 &pioE 12 GPIO_ACTIVE_LOW
198 >;
199 status = "okay";
200 };
201
202 usb2: ehci@00600000 {
203 status = "okay";
204 };
205
206 nand0: nand@80000000 {
207 nand-bus-width = <8>;
208 nand-ecc-mode = "hw";
209 nand-on-flash-bbt;
210 atmel,has-pmecc;
211 status = "okay";
212
213 at91bootstrap@0 {
214 label = "at91bootstrap";
215 reg = <0x0 0x40000>;
216 };
217
218 bootloader@40000 {
219 label = "bootloader";
220 reg = <0x40000 0x80000>;
221 };
222
223 bootloaderenv@c0000 {
224 label = "bootloader env";
225 reg = <0xc0000 0xc0000>;
226 };
227
228 dtb@180000 {
229 label = "device tree";
230 reg = <0x180000 0x80000>;
231 };
232
233 kernel@200000 {
234 label = "kernel";
235 reg = <0x200000 0x600000>;
236 };
237
238 rootfs@800000 {
239 label = "rootfs";
240 reg = <0x800000 0x0f800000>;
241 };
242 };
243 };
244
245 gpio_keys {
246 compatible = "gpio-keys";
247 #address-cells = <1>;
248 #size-cells = <0>;
249
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_key_gpio>;
252
253 pb_user1 {
254 label = "pb_user1";
255 gpios = <&pioE 13 GPIO_ACTIVE_HIGH>;
256 linux,code = <0x100>;
257 gpio-key,wakeup;
258 };
259 };
260};
diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi
new file mode 100644
index 000000000000..f3bb2dd6269e
--- /dev/null
+++ b/arch/arm/boot/dts/bcm63138.dtsi
@@ -0,0 +1,134 @@
1/*
2 * Broadcom BCM63138 DSL SoCs Device Tree
3 */
4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/interrupt-controller/irq.h>
7
8#include "skeleton.dtsi"
9
10/ {
11 compatible = "brcm,bcm63138";
12 model = "Broadcom BCM63138 DSL SoC";
13 interrupt-parent = <&gic>;
14
15 aliases {
16 uart0 = &serial0;
17 uart1 = &serial1;
18 };
19
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 cpu@0 {
25 device_type = "cpu";
26 compatible = "arm,cortex-a9";
27 next-level-cache = <&L2>;
28 reg = <0>;
29 };
30
31 cpu@1 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a9";
34 next-level-cache = <&L2>;
35 reg = <1>;
36 };
37 };
38
39 clocks {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 arm_timer_clk: arm_timer_clk {
44 #clock-cells = <0>;
45 compatible = "fixed-clock";
46 clock-frequency = <500000000>;
47 };
48
49 periph_clk: periph_clk {
50 #clock-cells = <0>;
51 compatible = "fixed-clock";
52 clock-frequency = <50000000>;
53 clock-output-names = "periph";
54 };
55 };
56
57 /* ARM bus */
58 axi@80000000 {
59 compatible = "simple-bus";
60 ranges = <0 0x80000000 0x784000>;
61 #address-cells = <1>;
62 #size-cells = <1>;
63
64 L2: cache-controller@1d000 {
65 compatible = "arm,pl310-cache";
66 reg = <0x1d000 0x1000>;
67 cache-unified;
68 cache-level = <2>;
69 cache-sets = <16>;
70 cache-size = <0x80000>;
71 interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
72 };
73
74 scu: scu@1e000 {
75 compatible = "arm,cortex-a9-scu";
76 reg = <0x1e000 0x100>;
77 };
78
79 gic: interrupt-controller@1e100 {
80 compatible = "arm,cortex-a9-gic";
81 reg = <0x1f000 0x1000
82 0x1e100 0x100>;
83 #interrupt-cells = <3>;
84 #address-cells = <0>;
85 interrupt-controller;
86 };
87
88 global_timer: timer@1e200 {
89 compatible = "arm,cortex-a9-global-timer";
90 reg = <0x1e200 0x20>;
91 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
92 clocks = <&arm_timer_clk>;
93 };
94
95 local_timer: local-timer@1e600 {
96 compatible = "arm,cortex-a9-twd-timer";
97 reg = <0x1e600 0x20>;
98 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
99 clocks = <&arm_timer_clk>;
100 };
101
102 twd_watchdog: watchdog@1e620 {
103 compatible = "arm,cortex-a9-twd-wdt";
104 reg = <0x1e620 0x20>;
105 interupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>;
106 };
107 };
108
109 /* Legacy UBUS base */
110 ubus@fffe8000 {
111 compatible = "simple-bus";
112 #address-cells = <1>;
113 #size-cells = <1>;
114 ranges = <0 0xfffe8000 0x8100>;
115
116 serial0: serial@600 {
117 compatible = "brcm,bcm6345-uart";
118 reg = <0x600 0x1b>;
119 interrupts = <GIC_SPI 32 0>;
120 clocks = <&periph_clk>;
121 clock-names = "periph";
122 status = "disabled";
123 };
124
125 serial1: serial@620 {
126 compatible = "brcm,bcm6345-uart";
127 reg = <0x620 0x1b>;
128 interrupts = <GIC_SPI 33 0>;
129 clocks = <&periph_clk>;
130 clock-names = "periph";
131 status = "disabled";
132 };
133 };
134};
diff --git a/arch/arm/boot/dts/bcm963138dvt.dts b/arch/arm/boot/dts/bcm963138dvt.dts
new file mode 100644
index 000000000000..69c93395ecd2
--- /dev/null
+++ b/arch/arm/boot/dts/bcm963138dvt.dts
@@ -0,0 +1,30 @@
1/*
2 * Broadcom BCM63138 Reference Board DTS
3 */
4
5/dts-v1/;
6
7#include "bcm63138.dtsi"
8
9/ {
10 compatible = "brcm,BCM963138DVT", "brcm,bcm63138";
11 model = "Broadcom BCM963138DVT";
12
13 chosen {
14 bootargs = "console=ttyS0,115200";
15 stdout-path = &serial0;
16 };
17
18 memory {
19 reg = <0x0 0x08000000>;
20 };
21
22};
23
24&serial0 {
25 status = "okay";
26};
27
28&serial1 {
29 status = "okay";
30};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d678152db4cb..e09b1afdaef2 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -89,6 +89,7 @@
89 prm: prm@4ae06000 { 89 prm: prm@4ae06000 {
90 compatible = "ti,dra7-prm"; 90 compatible = "ti,dra7-prm";
91 reg = <0x4ae06000 0x3000>; 91 reg = <0x4ae06000 0x3000>;
92 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
92 93
93 prm_clocks: clocks { 94 prm_clocks: clocks {
94 #address-cells = <1>; 95 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/hip04-d01.dts b/arch/arm/boot/dts/hip04-d01.dts
new file mode 100644
index 000000000000..40a9e33c2654
--- /dev/null
+++ b/arch/arm/boot/dts/hip04-d01.dts
@@ -0,0 +1,32 @@
1/*
2 * Copyright (C) 2013-2014 Linaro Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/dts-v1/;
11
12#include "hip04.dtsi"
13
14/ {
15 /* memory bus is 64-bit */
16 #address-cells = <2>;
17 #size-cells = <2>;
18 model = "Hisilicon D01 Development Board";
19 compatible = "hisilicon,hip04-d01";
20
21 memory@00000000,10000000 {
22 device_type = "memory";
23 reg = <0x00000000 0x10000000 0x00000000 0xc0000000>,
24 <0x00000004 0xc0000000 0x00000003 0x40000000>;
25 };
26
27 soc {
28 uart0: uart@4007000 {
29 status = "ok";
30 };
31 };
32};
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
new file mode 100644
index 000000000000..93b6c909e991
--- /dev/null
+++ b/arch/arm/boot/dts/hip04.dtsi
@@ -0,0 +1,267 @@
1/*
2 * Hisilicon Ltd. HiP04 SoC
3 *
4 * Copyright (C) 2013-2014 Hisilicon Ltd.
5 * Copyright (C) 2013-2014 Linaro Ltd.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14/ {
15 /* memory bus is 64-bit */
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 serial0 = &uart0;
21 };
22
23 bootwrapper {
24 compatible = "hisilicon,hip04-bootwrapper";
25 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 cpu-map {
33 cluster0 {
34 core0 {
35 cpu = <&CPU0>;
36 };
37 core1 {
38 cpu = <&CPU1>;
39 };
40 core2 {
41 cpu = <&CPU2>;
42 };
43 core3 {
44 cpu = <&CPU3>;
45 };
46 };
47 cluster1 {
48 core0 {
49 cpu = <&CPU4>;
50 };
51 core1 {
52 cpu = <&CPU5>;
53 };
54 core2 {
55 cpu = <&CPU6>;
56 };
57 core3 {
58 cpu = <&CPU7>;
59 };
60 };
61 cluster2 {
62 core0 {
63 cpu = <&CPU8>;
64 };
65 core1 {
66 cpu = <&CPU9>;
67 };
68 core2 {
69 cpu = <&CPU10>;
70 };
71 core3 {
72 cpu = <&CPU11>;
73 };
74 };
75 cluster3 {
76 core0 {
77 cpu = <&CPU12>;
78 };
79 core1 {
80 cpu = <&CPU13>;
81 };
82 core2 {
83 cpu = <&CPU14>;
84 };
85 core3 {
86 cpu = <&CPU15>;
87 };
88 };
89 };
90 CPU0: cpu@0 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a15";
93 reg = <0>;
94 };
95 CPU1: cpu@1 {
96 device_type = "cpu";
97 compatible = "arm,cortex-a15";
98 reg = <1>;
99 };
100 CPU2: cpu@2 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a15";
103 reg = <2>;
104 };
105 CPU3: cpu@3 {
106 device_type = "cpu";
107 compatible = "arm,cortex-a15";
108 reg = <3>;
109 };
110 CPU4: cpu@100 {
111 device_type = "cpu";
112 compatible = "arm,cortex-a15";
113 reg = <0x100>;
114 };
115 CPU5: cpu@101 {
116 device_type = "cpu";
117 compatible = "arm,cortex-a15";
118 reg = <0x101>;
119 };
120 CPU6: cpu@102 {
121 device_type = "cpu";
122 compatible = "arm,cortex-a15";
123 reg = <0x102>;
124 };
125 CPU7: cpu@103 {
126 device_type = "cpu";
127 compatible = "arm,cortex-a15";
128 reg = <0x103>;
129 };
130 CPU8: cpu@200 {
131 device_type = "cpu";
132 compatible = "arm,cortex-a15";
133 reg = <0x200>;
134 };
135 CPU9: cpu@201 {
136 device_type = "cpu";
137 compatible = "arm,cortex-a15";
138 reg = <0x201>;
139 };
140 CPU10: cpu@202 {
141 device_type = "cpu";
142 compatible = "arm,cortex-a15";
143 reg = <0x202>;
144 };
145 CPU11: cpu@203 {
146 device_type = "cpu";
147 compatible = "arm,cortex-a15";
148 reg = <0x203>;
149 };
150 CPU12: cpu@300 {
151 device_type = "cpu";
152 compatible = "arm,cortex-a15";
153 reg = <0x300>;
154 };
155 CPU13: cpu@301 {
156 device_type = "cpu";
157 compatible = "arm,cortex-a15";
158 reg = <0x301>;
159 };
160 CPU14: cpu@302 {
161 device_type = "cpu";
162 compatible = "arm,cortex-a15";
163 reg = <0x302>;
164 };
165 CPU15: cpu@303 {
166 device_type = "cpu";
167 compatible = "arm,cortex-a15";
168 reg = <0x303>;
169 };
170 };
171
172 timer {
173 compatible = "arm,armv7-timer";
174 interrupt-parent = <&gic>;
175 interrupts = <1 13 0xf08>,
176 <1 14 0xf08>,
177 <1 11 0xf08>,
178 <1 10 0xf08>;
179 };
180
181 clk_50m: clk_50m {
182 #clock-cells = <0>;
183 compatible = "fixed-clock";
184 clock-frequency = <50000000>;
185 };
186
187 clk_168m: clk_168m {
188 #clock-cells = <0>;
189 compatible = "fixed-clock";
190 clock-frequency = <168000000>;
191 };
192
193 soc {
194 /* It's a 32-bit SoC. */
195 #address-cells = <1>;
196 #size-cells = <1>;
197 compatible = "simple-bus";
198 interrupt-parent = <&gic>;
199 ranges = <0 0 0xe0000000 0x10000000>;
200
201 gic: interrupt-controller@c01000 {
202 compatible = "hisilicon,hip04-intc";
203 #interrupt-cells = <3>;
204 #address-cells = <0>;
205 interrupt-controller;
206 interrupts = <1 9 0xf04>;
207
208 reg = <0xc01000 0x1000>, <0xc02000 0x1000>,
209 <0xc04000 0x2000>, <0xc06000 0x2000>;
210 };
211
212 sysctrl: sysctrl {
213 compatible = "hisilicon,sysctrl";
214 reg = <0x3e00000 0x00100000>;
215 };
216
217 fabric: fabric {
218 compatible = "hisilicon,hip04-fabric";
219 reg = <0x302a000 0x1000>;
220 };
221
222 dual_timer0: dual_timer@3000000 {
223 compatible = "arm,sp804", "arm,primecell";
224 reg = <0x3000000 0x1000>;
225 interrupts = <0 224 4>;
226 clocks = <&clk_50m>, <&clk_50m>;
227 clock-names = "apb_pclk";
228 };
229
230 arm-pmu {
231 compatible = "arm,cortex-a15-pmu";
232 interrupts = <0 64 4>,
233 <0 65 4>,
234 <0 66 4>,
235 <0 67 4>,
236 <0 68 4>,
237 <0 69 4>,
238 <0 70 4>,
239 <0 71 4>,
240 <0 72 4>,
241 <0 73 4>,
242 <0 74 4>,
243 <0 75 4>,
244 <0 76 4>,
245 <0 77 4>,
246 <0 78 4>,
247 <0 79 4>;
248 };
249
250 uart0: uart@4007000 {
251 compatible = "snps,dw-apb-uart";
252 reg = <0x4007000 0x1000>;
253 interrupts = <0 381 4>;
254 clocks = <&clk_168m>;
255 clock-names = "uartclk";
256 reg-shift = <2>;
257 status = "disabled";
258 };
259
260 sata0: sata@a000000 {
261 compatible = "hisilicon,hisi-ahci";
262 reg = <0xa000000 0x1000000>;
263 interrupts = <0 372 4>;
264 };
265
266 };
267};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 575a49bf968d..3136ed1a04ba 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -97,6 +97,7 @@
97 prm: prm@48306000 { 97 prm: prm@48306000 {
98 compatible = "ti,omap3-prm"; 98 compatible = "ti,omap3-prm";
99 reg = <0x48306000 0x4000>; 99 reg = <0x48306000 0x4000>;
100 interrupts = <11>;
100 101
101 prm_clocks: clocks { 102 prm_clocks: clocks {
102 #address-cells = <1>; 103 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 69408b53200d..8a944974d72e 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -81,6 +81,7 @@
81 mpu { 81 mpu {
82 compatible = "ti,omap4-mpu"; 82 compatible = "ti,omap4-mpu";
83 ti,hwmods = "mpu"; 83 ti,hwmods = "mpu";
84 sram = <&ocmcram>;
84 }; 85 };
85 86
86 dsp { 87 dsp {
@@ -129,6 +130,7 @@
129 prm: prm@4a306000 { 130 prm: prm@4a306000 {
130 compatible = "ti,omap4-prm"; 131 compatible = "ti,omap4-prm";
131 reg = <0x4a306000 0x3000>; 132 reg = <0x4a306000 0x3000>;
133 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
132 134
133 prm_clocks: clocks { 135 prm_clocks: clocks {
134 #address-cells = <1>; 136 #address-cells = <1>;
@@ -208,6 +210,11 @@
208 }; 210 };
209 }; 211 };
210 212
213 ocmcram: ocmcram@40304000 {
214 compatible = "mmio-sram";
215 reg = <0x40304000 0xa000>; /* 40k */
216 };
217
211 sdma: dma-controller@4a056000 { 218 sdma: dma-controller@4a056000 {
212 compatible = "ti,omap4430-sdma"; 219 compatible = "ti,omap4430-sdma";
213 reg = <0x4a056000 0x1000>; 220 reg = <0x4a056000 0x1000>;
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index fc8df1739f39..4a6091d717b5 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -104,8 +104,9 @@
104 soc { 104 soc {
105 compatible = "ti,omap-infra"; 105 compatible = "ti,omap-infra";
106 mpu { 106 mpu {
107 compatible = "ti,omap5-mpu"; 107 compatible = "ti,omap4-mpu";
108 ti,hwmods = "mpu"; 108 ti,hwmods = "mpu";
109 sram = <&ocmcram>;
109 }; 110 };
110 }; 111 };
111 112
@@ -131,6 +132,7 @@
131 prm: prm@4ae06000 { 132 prm: prm@4ae06000 {
132 compatible = "ti,omap5-prm"; 133 compatible = "ti,omap5-prm";
133 reg = <0x4ae06000 0x3000>; 134 reg = <0x4ae06000 0x3000>;
135 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
134 136
135 prm_clocks: clocks { 137 prm_clocks: clocks {
136 #address-cells = <1>; 138 #address-cells = <1>;
@@ -219,6 +221,11 @@
219 }; 221 };
220 }; 222 };
221 223
224 ocmcram: ocmcram@40300000 {
225 compatible = "mmio-sram";
226 reg = <0x40300000 0x20000>; /* 128k */
227 };
228
222 sdma: dma-controller@4a056000 { 229 sdma: dma-controller@4a056000 {
223 compatible = "ti,omap4430-sdma"; 230 compatible = "ti,omap4430-sdma";
224 reg = <0x4a056000 0x1000>; 231 reg = <0x4a056000 0x1000>;
diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index 20705467f4c9..a3ed23c0a8f5 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -43,6 +43,10 @@
43 clock-frequency = <48000000>; 43 clock-frequency = <48000000>;
44}; 44};
45 45
46&mtu2 {
47 status = "ok";
48};
49
46&i2c2 { 50&i2c2 {
47 status = "okay"; 51 status = "okay";
48 clock-frequency = <400000>; 52 clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index bdee22541189..801a556e264b 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -229,6 +229,16 @@
229 status = "disabled"; 229 status = "disabled";
230 }; 230 };
231 231
232 mtu2: timer@fcff0000 {
233 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
234 reg = <0xfcff0000 0x400>;
235 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
236 interrupt-names = "tgi0a";
237 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
238 clock-names = "fck";
239 status = "disabled";
240 };
241
232 scif0: serial@e8007000 { 242 scif0: serial@e8007000 {
233 compatible = "renesas,scif-r7s72100", "renesas,scif"; 243 compatible = "renesas,scif-r7s72100", "renesas,scif";
234 reg = <0xe8007000 64>; 244 reg = <0xe8007000 64>;
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
deleted file mode 100644
index ee9e7d5c97a9..000000000000
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
+++ /dev/null
@@ -1,283 +0,0 @@
1/*
2 * Reference Device Tree Source for the armadillo 800 eva board
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12#include "r8a7740.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/pwm/pwm.h>
17
18/ {
19 model = "armadillo 800 eva reference";
20 compatible = "renesas,armadillo800eva-reference", "renesas,r8a7740";
21
22 aliases {
23 serial1 = &scifa1;
24 };
25
26 chosen {
27 bootargs = "console=tty0 console=ttySC1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
28 };
29
30 memory {
31 device_type = "memory";
32 reg = <0x40000000 0x20000000>;
33 };
34
35 reg_3p3v: regulator@0 {
36 compatible = "regulator-fixed";
37 regulator-name = "fixed-3.3V";
38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>;
40 regulator-always-on;
41 regulator-boot-on;
42 };
43
44 vcc_sdhi0: regulator@1 {
45 compatible = "regulator-fixed";
46
47 regulator-name = "SDHI0 Vcc";
48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <3300000>;
50
51 gpio = <&pfc 75 GPIO_ACTIVE_HIGH>;
52 enable-active-high;
53 };
54
55 vccq_sdhi0: regulator@2 {
56 compatible = "regulator-gpio";
57
58 regulator-name = "SDHI0 VccQ";
59 regulator-min-microvolt = <1800000>;
60 regulator-max-microvolt = <3300000>;
61 vin-supply = <&vcc_sdhi0>;
62
63 enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>;
64 gpios = <&pfc 17 GPIO_ACTIVE_HIGH>;
65 states = <3300000 0
66 1800000 1>;
67
68 enable-active-high;
69 };
70
71 reg_5p0v: regulator@3 {
72 compatible = "regulator-fixed";
73 regulator-name = "fixed-5.0V";
74 regulator-min-microvolt = <5000000>;
75 regulator-max-microvolt = <5000000>;
76 regulator-always-on;
77 regulator-boot-on;
78 };
79
80 gpio-keys {
81 compatible = "gpio-keys";
82
83 power-key {
84 gpios = <&pfc 99 GPIO_ACTIVE_LOW>;
85 linux,code = <KEY_POWER>;
86 label = "SW3";
87 gpio-key,wakeup;
88 };
89
90 back-key {
91 gpios = <&pfc 100 GPIO_ACTIVE_LOW>;
92 linux,code = <KEY_BACK>;
93 label = "SW4";
94 };
95
96 menu-key {
97 gpios = <&pfc 97 GPIO_ACTIVE_LOW>;
98 linux,code = <KEY_MENU>;
99 label = "SW5";
100 };
101
102 home-key {
103 gpios = <&pfc 98 GPIO_ACTIVE_LOW>;
104 linux,code = <KEY_HOME>;
105 label = "SW6";
106 };
107 };
108
109 leds {
110 compatible = "gpio-leds";
111 led3 {
112 gpios = <&pfc 102 GPIO_ACTIVE_HIGH>;
113 label = "LED3";
114 };
115 led4 {
116 gpios = <&pfc 111 GPIO_ACTIVE_HIGH>;
117 label = "LED4";
118 };
119 led5 {
120 gpios = <&pfc 110 GPIO_ACTIVE_HIGH>;
121 label = "LED5";
122 };
123 led6 {
124 gpios = <&pfc 177 GPIO_ACTIVE_HIGH>;
125 label = "LED6";
126 };
127 };
128
129 i2c2: i2c@2 {
130 #address-cells = <1>;
131 #size-cells = <0>;
132 compatible = "i2c-gpio";
133 gpios = <&pfc 208 GPIO_ACTIVE_HIGH /* sda */
134 &pfc 91 GPIO_ACTIVE_HIGH /* scl */
135 >;
136 i2c-gpio,delay-us = <5>;
137 };
138
139 backlight {
140 compatible = "pwm-backlight";
141 pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>;
142 brightness-levels = <0 1 2 4 8 16 32 64 128 255>;
143 default-brightness-level = <9>;
144 pinctrl-0 = <&backlight_pins>;
145 pinctrl-names = "default";
146 power-supply = <&reg_5p0v>;
147 enable-gpios = <&pfc 61 GPIO_ACTIVE_HIGH>;
148 };
149
150 sound {
151 compatible = "simple-audio-card";
152
153 simple-audio-card,format = "i2s";
154
155 simple-audio-card,cpu {
156 sound-dai = <&sh_fsi2 0>;
157 bitclock-inversion;
158 };
159
160 simple-audio-card,codec {
161 sound-dai = <&wm8978>;
162 bitclock-master;
163 frame-master;
164 system-clock-frequency = <12288000>;
165 };
166 };
167};
168
169&ether {
170 pinctrl-0 = <&ether_pins>;
171 pinctrl-names = "default";
172
173 phy-handle = <&phy0>;
174 status = "ok";
175
176 phy0: ethernet-phy@0 {
177 reg = <0>;
178 };
179};
180
181&i2c0 {
182 status = "okay";
183 touchscreen@55 {
184 compatible = "sitronix,st1232";
185 reg = <0x55>;
186 interrupt-parent = <&irqpin1>;
187 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
188 pinctrl-0 = <&st1232_pins>;
189 pinctrl-names = "default";
190 gpios = <&pfc 166 GPIO_ACTIVE_LOW>;
191 };
192
193 wm8978: wm8978@1a {
194 #sound-dai-cells = <0>;
195 compatible = "wlf,wm8978";
196 reg = <0x1a>;
197 };
198};
199
200&i2c2 {
201 status = "okay";
202 rtc@30 {
203 compatible = "sii,s35390a";
204 reg = <0x30>;
205 };
206};
207
208&pfc {
209 ether_pins: ether {
210 renesas,groups = "gether_mii", "gether_int";
211 renesas,function = "gether";
212 };
213
214 scifa1_pins: serial1 {
215 renesas,groups = "scifa1_data";
216 renesas,function = "scifa1";
217 };
218
219 st1232_pins: touchscreen {
220 renesas,groups = "intc_irq10";
221 renesas,function = "intc";
222 };
223
224 backlight_pins: backlight {
225 renesas,groups = "tpu0_to2_1";
226 renesas,function = "tpu0";
227 };
228
229 mmc0_pins: mmc0 {
230 renesas,groups = "mmc0_data8_1", "mmc0_ctrl_1";
231 renesas,function = "mmc0";
232 };
233
234 sdhi0_pins: sd0 {
235 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
236 renesas,function = "sdhi0";
237 };
238
239 fsia_pins: sounda {
240 renesas,groups = "fsia_sclk_in", "fsia_mclk_out",
241 "fsia_data_in_1", "fsia_data_out_0";
242 renesas,function = "fsia";
243 };
244};
245
246&tpu {
247 status = "okay";
248};
249
250&mmcif0 {
251 pinctrl-0 = <&mmc0_pins>;
252 pinctrl-names = "default";
253
254 vmmc-supply = <&reg_3p3v>;
255 bus-width = <8>;
256 non-removable;
257 status = "okay";
258};
259
260&scifa1 {
261 pinctrl-0 = <&scifa1_pins>;
262 pinctrl-names = "default";
263
264 status = "okay";
265};
266
267&sdhi0 {
268 pinctrl-0 = <&sdhi0_pins>;
269 pinctrl-names = "default";
270
271 vmmc-supply = <&vcc_sdhi0>;
272 vqmmc-supply = <&vccq_sdhi0>;
273 bus-width = <4>;
274 cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>;
275 status = "okay";
276};
277
278&sh_fsi2 {
279 pinctrl-0 = <&fsia_pins>;
280 pinctrl-names = "default";
281
282 status = "okay";
283};
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
index a06a11e1a840..effb7b46f131 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -10,10 +10,18 @@
10 10
11/dts-v1/; 11/dts-v1/;
12#include "r8a7740.dtsi" 12#include "r8a7740.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/pwm/pwm.h>
13 17
14/ { 18/ {
15 model = "armadillo 800 eva"; 19 model = "armadillo 800 eva";
16 compatible = "renesas,armadillo800eva"; 20 compatible = "renesas,armadillo800eva", "renesas,r8a7740";
21
22 aliases {
23 serial1 = &scifa1;
24 };
17 25
18 chosen { 26 chosen {
19 bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; 27 bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
@@ -23,4 +31,270 @@
23 device_type = "memory"; 31 device_type = "memory";
24 reg = <0x40000000 0x20000000>; 32 reg = <0x40000000 0x20000000>;
25 }; 33 };
34
35 reg_3p3v: regulator@0 {
36 compatible = "regulator-fixed";
37 regulator-name = "fixed-3.3V";
38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>;
40 regulator-always-on;
41 regulator-boot-on;
42 };
43
44 vcc_sdhi0: regulator@1 {
45 compatible = "regulator-fixed";
46
47 regulator-name = "SDHI0 Vcc";
48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <3300000>;
50
51 gpio = <&pfc 75 GPIO_ACTIVE_HIGH>;
52 enable-active-high;
53 };
54
55 vccq_sdhi0: regulator@2 {
56 compatible = "regulator-gpio";
57
58 regulator-name = "SDHI0 VccQ";
59 regulator-min-microvolt = <1800000>;
60 regulator-max-microvolt = <3300000>;
61 vin-supply = <&vcc_sdhi0>;
62
63 enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>;
64 gpios = <&pfc 17 GPIO_ACTIVE_HIGH>;
65 states = <3300000 0
66 1800000 1>;
67
68 enable-active-high;
69 };
70
71 reg_5p0v: regulator@3 {
72 compatible = "regulator-fixed";
73 regulator-name = "fixed-5.0V";
74 regulator-min-microvolt = <5000000>;
75 regulator-max-microvolt = <5000000>;
76 regulator-always-on;
77 regulator-boot-on;
78 };
79
80 gpio-keys {
81 compatible = "gpio-keys";
82
83 power-key {
84 gpios = <&pfc 99 GPIO_ACTIVE_LOW>;
85 linux,code = <KEY_POWER>;
86 label = "SW3";
87 gpio-key,wakeup;
88 };
89
90 back-key {
91 gpios = <&pfc 100 GPIO_ACTIVE_LOW>;
92 linux,code = <KEY_BACK>;
93 label = "SW4";
94 };
95
96 menu-key {
97 gpios = <&pfc 97 GPIO_ACTIVE_LOW>;
98 linux,code = <KEY_MENU>;
99 label = "SW5";
100 };
101
102 home-key {
103 gpios = <&pfc 98 GPIO_ACTIVE_LOW>;
104 linux,code = <KEY_HOME>;
105 label = "SW6";
106 };
107 };
108
109 leds {
110 compatible = "gpio-leds";
111 led3 {
112 gpios = <&pfc 102 GPIO_ACTIVE_HIGH>;
113 label = "LED3";
114 };
115 led4 {
116 gpios = <&pfc 111 GPIO_ACTIVE_HIGH>;
117 label = "LED4";
118 };
119 led5 {
120 gpios = <&pfc 110 GPIO_ACTIVE_HIGH>;
121 label = "LED5";
122 };
123 led6 {
124 gpios = <&pfc 177 GPIO_ACTIVE_HIGH>;
125 label = "LED6";
126 };
127 };
128
129 i2c2: i2c@2 {
130 #address-cells = <1>;
131 #size-cells = <0>;
132 compatible = "i2c-gpio";
133 gpios = <&pfc 208 GPIO_ACTIVE_HIGH /* sda */
134 &pfc 91 GPIO_ACTIVE_HIGH /* scl */
135 >;
136 i2c-gpio,delay-us = <5>;
137 };
138
139 backlight {
140 compatible = "pwm-backlight";
141 pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>;
142 brightness-levels = <0 1 2 4 8 16 32 64 128 255>;
143 default-brightness-level = <9>;
144 pinctrl-0 = <&backlight_pins>;
145 pinctrl-names = "default";
146 power-supply = <&reg_5p0v>;
147 enable-gpios = <&pfc 61 GPIO_ACTIVE_HIGH>;
148 };
149
150 sound {
151 compatible = "simple-audio-card";
152
153 simple-audio-card,format = "i2s";
154
155 simple-audio-card,cpu {
156 sound-dai = <&sh_fsi2 0>;
157 bitclock-inversion;
158 };
159
160 simple-audio-card,codec {
161 sound-dai = <&wm8978>;
162 bitclock-master;
163 frame-master;
164 system-clock-frequency = <12288000>;
165 };
166 };
167};
168
169&ether {
170 pinctrl-0 = <&ether_pins>;
171 pinctrl-names = "default";
172
173 phy-handle = <&phy0>;
174 status = "ok";
175
176 phy0: ethernet-phy@0 {
177 reg = <0>;
178 };
179};
180
181&extal1_clk {
182 clock-frequency = <25000000>;
183};
184&extal2_clk {
185 clock-frequency = <48000000>;
186};
187&fsibck_clk {
188 clock-frequency = <12288000>;
189};
190&cpg_clocks {
191 renesas,mode = <0x05>; /* MD_CK0 | MD_CK2 */
192};
193
194&cmt1 {
195 status = "ok";
196};
197
198&i2c0 {
199 status = "okay";
200 touchscreen@55 {
201 compatible = "sitronix,st1232";
202 reg = <0x55>;
203 interrupt-parent = <&irqpin1>;
204 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
205 pinctrl-0 = <&st1232_pins>;
206 pinctrl-names = "default";
207 gpios = <&pfc 166 GPIO_ACTIVE_LOW>;
208 };
209
210 wm8978: wm8978@1a {
211 #sound-dai-cells = <0>;
212 compatible = "wlf,wm8978";
213 reg = <0x1a>;
214 };
215};
216
217&i2c2 {
218 status = "okay";
219 rtc@30 {
220 compatible = "sii,s35390a";
221 reg = <0x30>;
222 };
223};
224
225&pfc {
226 ether_pins: ether {
227 renesas,groups = "gether_mii", "gether_int";
228 renesas,function = "gether";
229 };
230
231 scifa1_pins: serial1 {
232 renesas,groups = "scifa1_data";
233 renesas,function = "scifa1";
234 };
235
236 st1232_pins: touchscreen {
237 renesas,groups = "intc_irq10";
238 renesas,function = "intc";
239 };
240
241 backlight_pins: backlight {
242 renesas,groups = "tpu0_to2_1";
243 renesas,function = "tpu0";
244 };
245
246 mmc0_pins: mmc0 {
247 renesas,groups = "mmc0_data8_1", "mmc0_ctrl_1";
248 renesas,function = "mmc0";
249 };
250
251 sdhi0_pins: sd0 {
252 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
253 renesas,function = "sdhi0";
254 };
255
256 fsia_pins: sounda {
257 renesas,groups = "fsia_sclk_in", "fsia_mclk_out",
258 "fsia_data_in_1", "fsia_data_out_0";
259 renesas,function = "fsia";
260 };
261};
262
263&tpu {
264 status = "okay";
265};
266
267&mmcif0 {
268 pinctrl-0 = <&mmc0_pins>;
269 pinctrl-names = "default";
270
271 vmmc-supply = <&reg_3p3v>;
272 bus-width = <8>;
273 non-removable;
274 status = "okay";
275};
276
277&scifa1 {
278 pinctrl-0 = <&scifa1_pins>;
279 pinctrl-names = "default";
280
281 status = "okay";
282};
283
284&sdhi0 {
285 pinctrl-0 = <&sdhi0_pins>;
286 pinctrl-names = "default";
287
288 vmmc-supply = <&vcc_sdhi0>;
289 vqmmc-supply = <&vccq_sdhi0>;
290 bus-width = <4>;
291 cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>;
292 status = "okay";
293};
294
295&sh_fsi2 {
296 pinctrl-0 = <&fsia_pins>;
297 pinctrl-names = "default";
298
299 status = "okay";
26}; 300};
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index bda18fb3d9e5..d46c213a17ad 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -10,6 +10,7 @@
10 10
11/include/ "skeleton.dtsi" 11/include/ "skeleton.dtsi"
12 12
13#include <dt-bindings/clock/r8a7740-clock.h>
13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/irq.h>
14 15
15/ { 16/ {
@@ -40,6 +41,18 @@
40 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; 41 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
41 }; 42 };
42 43
44 cmt1: timer@e6138000 {
45 compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
46 reg = <0xe6138000 0x170>;
47 interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
48 clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
49 clock-names = "fck";
50
51 renesas,channels-mask = <0x3f>;
52
53 status = "disabled";
54 };
55
43 /* irqpin0: IRQ0 - IRQ7 */ 56 /* irqpin0: IRQ0 - IRQ7 */
44 irqpin0: irqpin@e6900000 { 57 irqpin0: irqpin@e6900000 {
45 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; 58 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
@@ -125,7 +138,7 @@
125 reg = <0xe9a00000 0x800>, 138 reg = <0xe9a00000 0x800>,
126 <0xe9a01800 0x800>; 139 <0xe9a01800 0x800>;
127 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; 140 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
128 /* clocks = <&mstp3_clks R8A7740_CLK_GETHER>; */ 141 clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
129 phy-mode = "mii"; 142 phy-mode = "mii";
130 #address-cells = <1>; 143 #address-cells = <1>;
131 #size-cells = <0>; 144 #size-cells = <0>;
@@ -141,6 +154,7 @@
141 0 202 IRQ_TYPE_LEVEL_HIGH 154 0 202 IRQ_TYPE_LEVEL_HIGH
142 0 203 IRQ_TYPE_LEVEL_HIGH 155 0 203 IRQ_TYPE_LEVEL_HIGH
143 0 204 IRQ_TYPE_LEVEL_HIGH>; 156 0 204 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
144 status = "disabled"; 158 status = "disabled";
145 }; 159 };
146 160
@@ -153,6 +167,7 @@
153 0 71 IRQ_TYPE_LEVEL_HIGH 167 0 71 IRQ_TYPE_LEVEL_HIGH
154 0 72 IRQ_TYPE_LEVEL_HIGH 168 0 72 IRQ_TYPE_LEVEL_HIGH
155 0 73 IRQ_TYPE_LEVEL_HIGH>; 169 0 73 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
156 status = "disabled"; 171 status = "disabled";
157 }; 172 };
158 173
@@ -160,6 +175,8 @@
160 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 175 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
161 reg = <0xe6c40000 0x100>; 176 reg = <0xe6c40000 0x100>;
162 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; 177 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
179 clock-names = "sci_ick";
163 status = "disabled"; 180 status = "disabled";
164 }; 181 };
165 182
@@ -167,6 +184,8 @@
167 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 184 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
168 reg = <0xe6c50000 0x100>; 185 reg = <0xe6c50000 0x100>;
169 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; 186 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
188 clock-names = "sci_ick";
170 status = "disabled"; 189 status = "disabled";
171 }; 190 };
172 191
@@ -174,6 +193,8 @@
174 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 193 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
175 reg = <0xe6c60000 0x100>; 194 reg = <0xe6c60000 0x100>;
176 interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; 195 interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
197 clock-names = "sci_ick";
177 status = "disabled"; 198 status = "disabled";
178 }; 199 };
179 200
@@ -181,6 +202,8 @@
181 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 202 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
182 reg = <0xe6c70000 0x100>; 203 reg = <0xe6c70000 0x100>;
183 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; 204 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
206 clock-names = "sci_ick";
184 status = "disabled"; 207 status = "disabled";
185 }; 208 };
186 209
@@ -188,6 +211,8 @@
188 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 211 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
189 reg = <0xe6c80000 0x100>; 212 reg = <0xe6c80000 0x100>;
190 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; 213 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
215 clock-names = "sci_ick";
191 status = "disabled"; 216 status = "disabled";
192 }; 217 };
193 218
@@ -195,6 +220,8 @@
195 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 220 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
196 reg = <0xe6cb0000 0x100>; 221 reg = <0xe6cb0000 0x100>;
197 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; 222 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
224 clock-names = "sci_ick";
198 status = "disabled"; 225 status = "disabled";
199 }; 226 };
200 227
@@ -202,6 +229,8 @@
202 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 229 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
203 reg = <0xe6cc0000 0x100>; 230 reg = <0xe6cc0000 0x100>;
204 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 231 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
233 clock-names = "sci_ick";
205 status = "disabled"; 234 status = "disabled";
206 }; 235 };
207 236
@@ -209,6 +238,8 @@
209 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 238 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
210 reg = <0xe6cd0000 0x100>; 239 reg = <0xe6cd0000 0x100>;
211 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; 240 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
242 clock-names = "sci_ick";
212 status = "disabled"; 243 status = "disabled";
213 }; 244 };
214 245
@@ -216,6 +247,8 @@
216 compatible = "renesas,scifb-r8a7740", "renesas,scifb"; 247 compatible = "renesas,scifb-r8a7740", "renesas,scifb";
217 reg = <0xe6c30000 0x100>; 248 reg = <0xe6c30000 0x100>;
218 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; 249 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
251 clock-names = "sci_ick";
219 status = "disabled"; 252 status = "disabled";
220 }; 253 };
221 254
@@ -239,6 +272,7 @@
239 tpu: pwm@e6600000 { 272 tpu: pwm@e6600000 {
240 compatible = "renesas,tpu-r8a7740", "renesas,tpu"; 273 compatible = "renesas,tpu-r8a7740", "renesas,tpu";
241 reg = <0xe6600000 0x100>; 274 reg = <0xe6600000 0x100>;
275 clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
242 status = "disabled"; 276 status = "disabled";
243 #pwm-cells = <3>; 277 #pwm-cells = <3>;
244 }; 278 };
@@ -248,6 +282,7 @@
248 reg = <0xe6bd0000 0x100>; 282 reg = <0xe6bd0000 0x100>;
249 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH 283 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
250 0 57 IRQ_TYPE_LEVEL_HIGH>; 284 0 57 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&mstp3_clks R8A7740_CLK_MMC>;
251 status = "disabled"; 286 status = "disabled";
252 }; 287 };
253 288
@@ -257,6 +292,7 @@
257 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH 292 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH
258 0 118 IRQ_TYPE_LEVEL_HIGH 293 0 118 IRQ_TYPE_LEVEL_HIGH
259 0 119 IRQ_TYPE_LEVEL_HIGH>; 294 0 119 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
260 cap-sd-highspeed; 296 cap-sd-highspeed;
261 cap-sdio-irq; 297 cap-sdio-irq;
262 status = "disabled"; 298 status = "disabled";
@@ -268,6 +304,7 @@
268 interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH 304 interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH
269 0 122 IRQ_TYPE_LEVEL_HIGH 305 0 122 IRQ_TYPE_LEVEL_HIGH
270 0 123 IRQ_TYPE_LEVEL_HIGH>; 306 0 123 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
271 cap-sd-highspeed; 308 cap-sd-highspeed;
272 cap-sdio-irq; 309 cap-sdio-irq;
273 status = "disabled"; 310 status = "disabled";
@@ -279,6 +316,7 @@
279 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH 316 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH
280 0 126 IRQ_TYPE_LEVEL_HIGH 317 0 126 IRQ_TYPE_LEVEL_HIGH
281 0 127 IRQ_TYPE_LEVEL_HIGH>; 318 0 127 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
282 cap-sd-highspeed; 320 cap-sd-highspeed;
283 cap-sdio-irq; 321 cap-sdio-irq;
284 status = "disabled"; 322 status = "disabled";
@@ -289,6 +327,186 @@
289 compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; 327 compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
290 reg = <0xfe1f0000 0x400>; 328 reg = <0xfe1f0000 0x400>;
291 interrupts = <0 9 0x4>; 329 interrupts = <0 9 0x4>;
330 clocks = <&mstp3_clks R8A7740_CLK_FSI>;
292 status = "disabled"; 331 status = "disabled";
293 }; 332 };
333
334 clocks {
335 #address-cells = <1>;
336 #size-cells = <1>;
337 ranges;
338
339 /* External root clock */
340 extalr_clk: extalr_clk {
341 compatible = "fixed-clock";
342 #clock-cells = <0>;
343 clock-frequency = <32768>;
344 clock-output-names = "extalr";
345 };
346 extal1_clk: extal1_clk {
347 compatible = "fixed-clock";
348 #clock-cells = <0>;
349 clock-frequency = <0>;
350 clock-output-names = "extal1";
351 };
352 extal2_clk: extal2_clk {
353 compatible = "fixed-clock";
354 #clock-cells = <0>;
355 clock-frequency = <0>;
356 clock-output-names = "extal2";
357 };
358 dv_clk: dv_clk {
359 compatible = "fixed-clock";
360 #clock-cells = <0>;
361 clock-frequency = <27000000>;
362 clock-output-names = "dv";
363 };
364 fsiack_clk: fsiack_clk {
365 compatible = "fixed-clock";
366 #clock-cells = <0>;
367 clock-frequency = <0>;
368 clock-output-names = "fsiack";
369 };
370 fsibck_clk: fsibck_clk {
371 compatible = "fixed-clock";
372 #clock-cells = <0>;
373 clock-frequency = <0>;
374 clock-output-names = "fsibck";
375 };
376
377 /* Special CPG clocks */
378 cpg_clocks: cpg_clocks@e6150000 {
379 compatible = "renesas,r8a7740-cpg-clocks";
380 reg = <0xe6150000 0x10000>;
381 clocks = <&extal1_clk>, <&extalr_clk>;
382 #clock-cells = <1>;
383 clock-output-names = "system", "pllc0", "pllc1",
384 "pllc2", "r",
385 "usb24s",
386 "i", "zg", "b", "m1", "hp",
387 "hpp", "usbp", "s", "zb", "m3",
388 "cp";
389 };
390
391 /* Variable factor clocks (DIV6) */
392 sub_clk: sub_clk@e6150080 {
393 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
394 reg = <0xe6150080 4>;
395 clocks = <&pllc1_div2_clk>;
396 #clock-cells = <0>;
397 clock-output-names = "sub";
398 };
399
400 /* Fixed factor clocks */
401 pllc1_div2_clk: pllc1_div2_clk {
402 compatible = "fixed-factor-clock";
403 clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
404 #clock-cells = <0>;
405 clock-div = <2>;
406 clock-mult = <1>;
407 clock-output-names = "pllc1_div2";
408 };
409 extal1_div2_clk: extal1_div2_clk {
410 compatible = "fixed-factor-clock";
411 clocks = <&extal1_clk>;
412 #clock-cells = <0>;
413 clock-div = <2>;
414 clock-mult = <1>;
415 clock-output-names = "extal1_div2";
416 };
417
418 /* Gate clocks */
419 subck_clks: subck_clks@e6150080 {
420 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
421 reg = <0xe6150080 4>;
422 clocks = <&sub_clk>, <&sub_clk>;
423 #clock-cells = <1>;
424 renesas,clock-indices = <
425 R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
426 >;
427 clock-output-names =
428 "subck", "subck2";
429 };
430 mstp1_clks: mstp1_clks@e6150134 {
431 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
432 reg = <0xe6150134 4>, <0xe6150038 4>;
433 clocks = <&cpg_clocks R8A7740_CLK_S>,
434 <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
435 <&cpg_clocks R8A7740_CLK_B>,
436 <&sub_clk>, <&sub_clk>,
437 <&cpg_clocks R8A7740_CLK_B>;
438 #clock-cells = <1>;
439 renesas,clock-indices = <
440 R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
441 R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
442 R8A7740_CLK_LCDC0
443 >;
444 clock-output-names =
445 "ceu21", "ceu20", "tmu0", "lcdc1", "iic0",
446 "tmu1", "lcdc0";
447 };
448 mstp2_clks: mstp2_clks@e6150138 {
449 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
450 reg = <0xe6150138 4>, <0xe6150040 4>;
451 clocks = <&sub_clk>, <&sub_clk>,
452 <&cpg_clocks R8A7740_CLK_HP>,
453 <&cpg_clocks R8A7740_CLK_HP>,
454 <&cpg_clocks R8A7740_CLK_HP>,
455 <&cpg_clocks R8A7740_CLK_HP>,
456 <&sub_clk>, <&sub_clk>, <&sub_clk>,
457 <&sub_clk>, <&sub_clk>, <&sub_clk>,
458 <&sub_clk>;
459 #clock-cells = <1>;
460 renesas,clock-indices = <
461 R8A7740_CLK_SCIFA6 R8A7740_CLK_SCIFA7
462 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
463 R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
464 R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
465 R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1
466 R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3
467 R8A7740_CLK_SCIFA4
468 >;
469 clock-output-names =
470 "scifa6", "scifa7", "dmac1", "dmac2", "dmac3",
471 "usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
472 "scifa2", "scifa3", "scifa4";
473 };
474 mstp3_clks: mstp3_clks@e615013c {
475 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
476 reg = <0xe615013c 4>, <0xe6150048 4>;
477 clocks = <&cpg_clocks R8A7740_CLK_R>,
478 <&cpg_clocks R8A7740_CLK_HP>,
479 <&sub_clk>,
480 <&cpg_clocks R8A7740_CLK_HP>,
481 <&cpg_clocks R8A7740_CLK_HP>,
482 <&cpg_clocks R8A7740_CLK_HP>,
483 <&cpg_clocks R8A7740_CLK_HP>,
484 <&cpg_clocks R8A7740_CLK_HP>,
485 <&cpg_clocks R8A7740_CLK_HP>;
486 #clock-cells = <1>;
487 renesas,clock-indices = <
488 R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
489 R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
490 R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
491 >;
492 clock-output-names =
493 "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1",
494 "mmc", "gether", "tpu0";
495 };
496 mstp4_clks: mstp4_clks@e6150140 {
497 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
498 reg = <0xe6150140 4>, <0xe615004c 4>;
499 clocks = <&cpg_clocks R8A7740_CLK_HP>,
500 <&cpg_clocks R8A7740_CLK_HP>,
501 <&cpg_clocks R8A7740_CLK_HP>,
502 <&cpg_clocks R8A7740_CLK_HP>;
503 #clock-cells = <1>;
504 renesas,clock-indices = <
505 R8A7740_CLK_USBH R8A7740_CLK_SDHI2
506 R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
507 >;
508 clock-output-names =
509 "usbhost", "sdhi2", "usbfunc", "usphy";
510 };
511 };
294}; 512};
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index ecfdf4b01b5a..315ec62cb96b 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -23,8 +23,14 @@
23 interrupt-parent = <&gic>; 23 interrupt-parent = <&gic>;
24 24
25 cpus { 25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
26 cpu@0 { 29 cpu@0 {
30 device_type = "cpu";
27 compatible = "arm,cortex-a9"; 31 compatible = "arm,cortex-a9";
32 reg = <0>;
33 clock-frequency = <800000000>;
28 }; 34 };
29 }; 35 };
30 36
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index 5745555df943..c160404e4d40 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -78,6 +78,10 @@
78 clock-frequency = <31250000>; 78 clock-frequency = <31250000>;
79}; 79};
80 80
81&tmu0 {
82 status = "okay";
83};
84
81&pfc { 85&pfc {
82 lan0_pins: lan0 { 86 lan0_pins: lan0 {
83 intc { 87 intc {
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 58d0d952d60e..72891e5f0f1b 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -266,6 +266,48 @@
266 reg = <0xffc48000 0x38>; 266 reg = <0xffc48000 0x38>;
267 }; 267 };
268 268
269 tmu0: timer@ffd80000 {
270 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
271 reg = <0xffd80000 0x30>;
272 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
273 <0 33 IRQ_TYPE_LEVEL_HIGH>,
274 <0 34 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
276 clock-names = "fck";
277
278 #renesas,channels = <3>;
279
280 status = "disabled";
281 };
282
283 tmu1: timer@ffd81000 {
284 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
285 reg = <0xffd81000 0x30>;
286 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
287 <0 37 IRQ_TYPE_LEVEL_HIGH>,
288 <0 38 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
290 clock-names = "fck";
291
292 #renesas,channels = <3>;
293
294 status = "disabled";
295 };
296
297 tmu2: timer@ffd82000 {
298 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
299 reg = <0xffd82000 0x30>;
300 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
301 <0 41 IRQ_TYPE_LEVEL_HIGH>,
302 <0 42 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
304 clock-names = "fck";
305
306 #renesas,channels = <3>;
307
308 status = "disabled";
309 };
310
269 sata: sata@fc600000 { 311 sata: sata@fc600000 {
270 compatible = "renesas,rcar-sata"; 312 compatible = "renesas,rcar-sata";
271 reg = <0xfc600000 0x2000>; 313 reg = <0xfc600000 0x2000>;
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 856b4236b674..7853c2c15ce6 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -252,6 +252,10 @@
252 }; 252 };
253}; 253};
254 254
255&cmt0 {
256 status = "ok";
257};
258
255&mmcif1 { 259&mmcif1 {
256 pinctrl-0 = <&mmc1_pins>; 260 pinctrl-0 = <&mmc1_pins>;
257 pinctrl-names = "default"; 261 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index d9ddecbb859c..aa146d2d1022 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -206,6 +206,38 @@
206 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 206 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
207 }; 207 };
208 208
209 cmt0: timer@ffca0000 {
210 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
211 reg = <0 0xffca0000 0 0x1004>;
212 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
213 <0 143 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
215 clock-names = "fck";
216
217 renesas,channels-mask = <0x60>;
218
219 status = "disabled";
220 };
221
222 cmt1: timer@e6130000 {
223 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
224 reg = <0 0xe6130000 0 0x1004>;
225 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
226 <0 121 IRQ_TYPE_LEVEL_HIGH>,
227 <0 122 IRQ_TYPE_LEVEL_HIGH>,
228 <0 123 IRQ_TYPE_LEVEL_HIGH>,
229 <0 124 IRQ_TYPE_LEVEL_HIGH>,
230 <0 125 IRQ_TYPE_LEVEL_HIGH>,
231 <0 126 IRQ_TYPE_LEVEL_HIGH>,
232 <0 127 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
234 clock-names = "fck";
235
236 renesas,channels-mask = <0xff>;
237
238 status = "disabled";
239 };
240
209 irqc0: interrupt-controller@e61c0000 { 241 irqc0: interrupt-controller@e61c0000 {
210 compatible = "renesas,irqc-r8a7790", "renesas,irqc"; 242 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
211 #interrupt-cells = <2>; 243 #interrupt-cells = <2>;
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index be59014474b2..740308e09457 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -302,6 +302,10 @@
302 }; 302 };
303}; 303};
304 304
305&cmt0 {
306 status = "ok";
307};
308
305&sata0 { 309&sata0 {
306 status = "okay"; 310 status = "okay";
307}; 311};
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 0d82a4b3c650..e270f38d827f 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -189,6 +189,38 @@
189 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 189 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
190 }; 190 };
191 191
192 cmt0: timer@ffca0000 {
193 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
194 reg = <0 0xffca0000 0 0x1004>;
195 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
196 <0 143 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
198 clock-names = "fck";
199
200 renesas,channels-mask = <0x60>;
201
202 status = "disabled";
203 };
204
205 cmt1: timer@e6130000 {
206 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
207 reg = <0 0xe6130000 0 0x1004>;
208 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
209 <0 121 IRQ_TYPE_LEVEL_HIGH>,
210 <0 122 IRQ_TYPE_LEVEL_HIGH>,
211 <0 123 IRQ_TYPE_LEVEL_HIGH>,
212 <0 124 IRQ_TYPE_LEVEL_HIGH>,
213 <0 125 IRQ_TYPE_LEVEL_HIGH>,
214 <0 126 IRQ_TYPE_LEVEL_HIGH>,
215 <0 127 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
217 clock-names = "fck";
218
219 renesas,channels-mask = <0xff>;
220
221 status = "disabled";
222 };
223
192 irqc0: interrupt-controller@e61c0000 { 224 irqc0: interrupt-controller@e61c0000 {
193 compatible = "renesas,irqc-r8a7791", "renesas,irqc"; 225 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
194 #interrupt-cells = <2>; 226 #interrupt-cells = <2>;
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
new file mode 100644
index 000000000000..e0157b0f075c
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -0,0 +1,1240 @@
1/*
2 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
3 *
4 * Copyright (C) 2014 Atmel,
5 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This library is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This library is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46#include "skeleton.dtsi"
47#include <dt-bindings/clock/at91.h>
48#include <dt-bindings/pinctrl/at91.h>
49#include <dt-bindings/interrupt-controller/irq.h>
50#include <dt-bindings/gpio/gpio.h>
51
52/ {
53 model = "Atmel SAMA5D4 family SoC";
54 compatible = "atmel,sama5d4";
55 interrupt-parent = <&aic>;
56
57 aliases {
58 serial0 = &usart3;
59 serial1 = &usart4;
60 serial2 = &usart2;
61 gpio0 = &pioA;
62 gpio1 = &pioB;
63 gpio2 = &pioC;
64 gpio4 = &pioE;
65 tcb0 = &tcb0;
66 tcb1 = &tcb1;
67 i2c2 = &i2c2;
68 };
69 cpus {
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 cpu@0 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a5";
76 reg = <0>;
77 next-level-cache = <&L2>;
78 };
79 };
80
81 memory {
82 reg = <0x20000000 0x20000000>;
83 };
84
85 clocks {
86 slow_xtal: slow_xtal {
87 compatible = "fixed-clock";
88 #clock-cells = <0>;
89 clock-frequency = <0>;
90 };
91
92 main_xtal: main_xtal {
93 compatible = "fixed-clock";
94 #clock-cells = <0>;
95 clock-frequency = <0>;
96 };
97
98 adc_op_clk: adc_op_clk{
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <1000000>;
102 };
103 };
104
105 ahb {
106 compatible = "simple-bus";
107 #address-cells = <1>;
108 #size-cells = <1>;
109 ranges;
110
111 usb0: gadget@00400000 {
112 #address-cells = <1>;
113 #size-cells = <0>;
114 compatible = "atmel,at91sam9rl-udc";
115 reg = <0x00400000 0x100000
116 0xfc02c000 0x4000>;
117 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
118 clocks = <&udphs_clk>, <&utmi>;
119 clock-names = "pclk", "hclk";
120 status = "disabled";
121
122 ep0 {
123 reg = <0>;
124 atmel,fifo-size = <64>;
125 atmel,nb-banks = <1>;
126 };
127
128 ep1 {
129 reg = <1>;
130 atmel,fifo-size = <1024>;
131 atmel,nb-banks = <3>;
132 atmel,can-dma;
133 atmel,can-isoc;
134 };
135
136 ep2 {
137 reg = <2>;
138 atmel,fifo-size = <1024>;
139 atmel,nb-banks = <3>;
140 atmel,can-dma;
141 atmel,can-isoc;
142 };
143
144 ep3 {
145 reg = <3>;
146 atmel,fifo-size = <1024>;
147 atmel,nb-banks = <2>;
148 atmel,can-dma;
149 atmel,can-isoc;
150 };
151
152 ep4 {
153 reg = <4>;
154 atmel,fifo-size = <1024>;
155 atmel,nb-banks = <2>;
156 atmel,can-dma;
157 atmel,can-isoc;
158 };
159
160 ep5 {
161 reg = <5>;
162 atmel,fifo-size = <1024>;
163 atmel,nb-banks = <2>;
164 atmel,can-dma;
165 atmel,can-isoc;
166 };
167
168 ep6 {
169 reg = <6>;
170 atmel,fifo-size = <1024>;
171 atmel,nb-banks = <2>;
172 atmel,can-dma;
173 atmel,can-isoc;
174 };
175
176 ep7 {
177 reg = <7>;
178 atmel,fifo-size = <1024>;
179 atmel,nb-banks = <2>;
180 atmel,can-dma;
181 atmel,can-isoc;
182 };
183
184 ep8 {
185 reg = <8>;
186 atmel,fifo-size = <1024>;
187 atmel,nb-banks = <2>;
188 atmel,can-isoc;
189 };
190
191 ep9 {
192 reg = <9>;
193 atmel,fifo-size = <1024>;
194 atmel,nb-banks = <2>;
195 atmel,can-isoc;
196 };
197
198 ep10 {
199 reg = <10>;
200 atmel,fifo-size = <1024>;
201 atmel,nb-banks = <2>;
202 atmel,can-isoc;
203 };
204
205 ep11 {
206 reg = <11>;
207 atmel,fifo-size = <1024>;
208 atmel,nb-banks = <2>;
209 atmel,can-isoc;
210 };
211
212 ep12 {
213 reg = <12>;
214 atmel,fifo-size = <1024>;
215 atmel,nb-banks = <2>;
216 atmel,can-isoc;
217 };
218
219 ep13 {
220 reg = <13>;
221 atmel,fifo-size = <1024>;
222 atmel,nb-banks = <2>;
223 atmel,can-isoc;
224 };
225
226 ep14 {
227 reg = <14>;
228 atmel,fifo-size = <1024>;
229 atmel,nb-banks = <2>;
230 atmel,can-isoc;
231 };
232
233 ep15 {
234 reg = <15>;
235 atmel,fifo-size = <1024>;
236 atmel,nb-banks = <2>;
237 atmel,can-isoc;
238 };
239 };
240
241 usb1: ohci@00500000 {
242 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
243 reg = <0x00500000 0x100000>;
244 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
245 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
246 <&uhpck>;
247 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
248 status = "disabled";
249 };
250
251 usb2: ehci@00600000 {
252 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
253 reg = <0x00600000 0x100000>;
254 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
255 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
256 clock-names = "usb_clk", "ehci_clk", "uhpck";
257 status = "disabled";
258 };
259
260 L2: cache-controller@00a00000 {
261 compatible = "arm,pl310-cache";
262 reg = <0x00a00000 0x1000>;
263 interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
264 cache-unified;
265 cache-level = <2>;
266 };
267
268 nand0: nand@80000000 {
269 compatible = "atmel,at91rm9200-nand";
270 #address-cells = <1>;
271 #size-cells = <1>;
272 ranges;
273 reg = < 0x80000000 0x08000000 /* EBI CS3 */
274 0xfc05c070 0x00000490 /* SMC PMECC regs */
275 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */
276 >;
277 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
278 atmel,nand-addr-offset = <21>;
279 atmel,nand-cmd-offset = <22>;
280 atmel,nand-has-dma;
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_nand>;
283 status = "disabled";
284
285 nfc@90000000 {
286 compatible = "atmel,sama5d3-nfc";
287 #address-cells = <1>;
288 #size-cells = <1>;
289 reg = <
290 0x90000000 0x10000000 /* NFC Command Registers */
291 0xfc05c000 0x00000070 /* NFC HSMC regs */
292 0x00100000 0x00100000 /* NFC SRAM banks */
293 >;
294 clocks = <&hsmc_clk>;
295 atmel,write-by-sram;
296 };
297 };
298
299 apb {
300 compatible = "simple-bus";
301 #address-cells = <1>;
302 #size-cells = <1>;
303 ranges;
304
305 ramc0: ramc@f0010000 {
306 compatible = "atmel,sama5d3-ddramc";
307 reg = <0xf0010000 0x200>;
308 clocks = <&ddrck>, <&mpddr_clk>;
309 clock-names = "ddrck", "mpddr";
310 };
311
312 pmc: pmc@f0018000 {
313 compatible = "atmel,sama5d3-pmc";
314 reg = <0xf0018000 0x120>;
315 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
316 interrupt-controller;
317 #address-cells = <1>;
318 #size-cells = <0>;
319 #interrupt-cells = <1>;
320
321 main_rc_osc: main_rc_osc {
322 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
323 #clock-cells = <0>;
324 interrupt-parent = <&pmc>;
325 interrupts = <AT91_PMC_MOSCRCS>;
326 clock-frequency = <12000000>;
327 clock-accuracy = <100000000>;
328 };
329
330 main_osc: main_osc {
331 compatible = "atmel,at91rm9200-clk-main-osc";
332 #clock-cells = <0>;
333 interrupt-parent = <&pmc>;
334 interrupts = <AT91_PMC_MOSCS>;
335 clocks = <&main_xtal>;
336 };
337
338 main: mainck {
339 compatible = "atmel,at91sam9x5-clk-main";
340 #clock-cells = <0>;
341 interrupt-parent = <&pmc>;
342 interrupts = <AT91_PMC_MOSCSELS>;
343 clocks = <&main_rc_osc &main_osc>;
344 };
345
346 plla: pllack {
347 compatible = "atmel,sama5d3-clk-pll";
348 #clock-cells = <0>;
349 interrupt-parent = <&pmc>;
350 interrupts = <AT91_PMC_LOCKA>;
351 clocks = <&main>;
352 reg = <0>;
353 atmel,clk-input-range = <12000000 12000000>;
354 #atmel,pll-clk-output-range-cells = <4>;
355 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
356 };
357
358 plladiv: plladivck {
359 compatible = "atmel,at91sam9x5-clk-plldiv";
360 #clock-cells = <0>;
361 clocks = <&plla>;
362 };
363
364 utmi: utmick {
365 compatible = "atmel,at91sam9x5-clk-utmi";
366 #clock-cells = <0>;
367 interrupt-parent = <&pmc>;
368 interrupts = <AT91_PMC_LOCKU>;
369 clocks = <&main>;
370 };
371
372 mck: masterck {
373 compatible = "atmel,at91sam9x5-clk-master";
374 #clock-cells = <0>;
375 interrupt-parent = <&pmc>;
376 interrupts = <AT91_PMC_MCKRDY>;
377 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
378 atmel,clk-output-range = <125000000 177000000>;
379 atmel,clk-divisors = <1 2 4 3>;
380 };
381
382 h32ck: h32mxck {
383 #clock-cells = <0>;
384 compatible = "atmel,sama5d4-clk-h32mx";
385 clocks = <&mck>;
386 };
387
388 usb: usbck {
389 compatible = "atmel,at91sam9x5-clk-usb";
390 #clock-cells = <0>;
391 clocks = <&plladiv>, <&utmi>;
392 };
393
394 prog: progck {
395 compatible = "atmel,at91sam9x5-clk-programmable";
396 #address-cells = <1>;
397 #size-cells = <0>;
398 interrupt-parent = <&pmc>;
399 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
400
401 prog0: prog0 {
402 #clock-cells = <0>;
403 reg = <0>;
404 interrupts = <AT91_PMC_PCKRDY(0)>;
405 };
406
407 prog1: prog1 {
408 #clock-cells = <0>;
409 reg = <1>;
410 interrupts = <AT91_PMC_PCKRDY(1)>;
411 };
412
413 prog2: prog2 {
414 #clock-cells = <0>;
415 reg = <2>;
416 interrupts = <AT91_PMC_PCKRDY(2)>;
417 };
418 };
419
420 smd: smdclk {
421 compatible = "atmel,at91sam9x5-clk-smd";
422 #clock-cells = <0>;
423 clocks = <&plladiv>, <&utmi>;
424 };
425
426 systemck {
427 compatible = "atmel,at91rm9200-clk-system";
428 #address-cells = <1>;
429 #size-cells = <0>;
430
431 ddrck: ddrck {
432 #clock-cells = <0>;
433 reg = <2>;
434 clocks = <&mck>;
435 };
436
437 lcdck: lcdck {
438 #clock-cells = <0>;
439 reg = <4>;
440 clocks = <&smd>;
441 };
442
443 smdck: smdck {
444 #clock-cells = <0>;
445 reg = <4>;
446 clocks = <&smd>;
447 };
448
449 uhpck: uhpck {
450 #clock-cells = <0>;
451 reg = <6>;
452 clocks = <&usb>;
453 };
454
455 udpck: udpck {
456 #clock-cells = <0>;
457 reg = <7>;
458 clocks = <&usb>;
459 };
460
461 pck0: pck0 {
462 #clock-cells = <0>;
463 reg = <8>;
464 clocks = <&prog0>;
465 };
466
467 pck1: pck1 {
468 #clock-cells = <0>;
469 reg = <9>;
470 clocks = <&prog1>;
471 };
472
473 pck2: pck2 {
474 #clock-cells = <0>;
475 reg = <10>;
476 clocks = <&prog2>;
477 };
478 };
479
480 periph32ck {
481 compatible = "atmel,at91sam9x5-clk-peripheral";
482 #address-cells = <1>;
483 #size-cells = <0>;
484 clocks = <&h32ck>;
485
486 pioD_clk: pioD_clk {
487 #clock-cells = <0>;
488 reg = <5>;
489 };
490
491 usart0_clk: usart0_clk {
492 #clock-cells = <0>;
493 reg = <6>;
494 };
495
496 usart1_clk: usart1_clk {
497 #clock-cells = <0>;
498 reg = <7>;
499 };
500
501 icm_clk: icm_clk {
502 #clock-cells = <0>;
503 reg = <9>;
504 };
505
506 aes_clk: aes_clk {
507 #clock-cells = <0>;
508 reg = <12>;
509 };
510
511 tdes_clk: tdes_clk {
512 #clock-cells = <0>;
513 reg = <14>;
514 };
515
516 sha_clk: sha_clk {
517 #clock-cells = <0>;
518 reg = <15>;
519 };
520
521 matrix1_clk: matrix1_clk {
522 #clock-cells = <0>;
523 reg = <17>;
524 };
525
526 hsmc_clk: hsmc_clk {
527 #clock-cells = <0>;
528 reg = <22>;
529 };
530
531 pioA_clk: pioA_clk {
532 #clock-cells = <0>;
533 reg = <23>;
534 };
535
536 pioB_clk: pioB_clk {
537 #clock-cells = <0>;
538 reg = <24>;
539 };
540
541 pioC_clk: pioC_clk {
542 #clock-cells = <0>;
543 reg = <25>;
544 };
545
546 pioE_clk: pioE_clk {
547 #clock-cells = <0>;
548 reg = <26>;
549 };
550
551 uart0_clk: uart0_clk {
552 #clock-cells = <0>;
553 reg = <27>;
554 };
555
556 uart1_clk: uart1_clk {
557 #clock-cells = <0>;
558 reg = <28>;
559 };
560
561 usart2_clk: usart2_clk {
562 #clock-cells = <0>;
563 reg = <29>;
564 };
565
566 usart3_clk: usart3_clk {
567 #clock-cells = <0>;
568 reg = <30>;
569 };
570
571 usart4_clk: usart4_clk {
572 #clock-cells = <0>;
573 reg = <31>;
574 };
575
576 twi0_clk: twi0_clk {
577 reg = <32>;
578 #clock-cells = <0>;
579 };
580
581 twi1_clk: twi1_clk {
582 #clock-cells = <0>;
583 reg = <33>;
584 };
585
586 twi2_clk: twi2_clk {
587 #clock-cells = <0>;
588 reg = <34>;
589 };
590
591 mci0_clk: mci0_clk {
592 #clock-cells = <0>;
593 reg = <35>;
594 };
595
596 mci1_clk: mci1_clk {
597 #clock-cells = <0>;
598 reg = <36>;
599 };
600
601 spi0_clk: spi0_clk {
602 #clock-cells = <0>;
603 reg = <37>;
604 };
605
606 spi1_clk: spi1_clk {
607 #clock-cells = <0>;
608 reg = <38>;
609 };
610
611 spi2_clk: spi2_clk {
612 #clock-cells = <0>;
613 reg = <39>;
614 };
615
616 tcb0_clk: tcb0_clk {
617 #clock-cells = <0>;
618 reg = <40>;
619 };
620
621 tcb1_clk: tcb1_clk {
622 #clock-cells = <0>;
623 reg = <41>;
624 };
625
626 tcb2_clk: tcb2_clk {
627 #clock-cells = <0>;
628 reg = <42>;
629 };
630
631 pwm_clk: pwm_clk {
632 #clock-cells = <0>;
633 reg = <43>;
634 };
635
636 adc_clk: adc_clk {
637 #clock-cells = <0>;
638 reg = <44>;
639 };
640
641 dbgu_clk: dbgu_clk {
642 #clock-cells = <0>;
643 reg = <45>;
644 };
645
646 uhphs_clk: uhphs_clk {
647 #clock-cells = <0>;
648 reg = <46>;
649 };
650
651 udphs_clk: udphs_clk {
652 #clock-cells = <0>;
653 reg = <47>;
654 };
655
656 ssc0_clk: ssc0_clk {
657 #clock-cells = <0>;
658 reg = <48>;
659 };
660
661 ssc1_clk: ssc1_clk {
662 #clock-cells = <0>;
663 reg = <49>;
664 };
665
666 trng_clk: trng_clk {
667 #clock-cells = <0>;
668 reg = <53>;
669 };
670
671 macb0_clk: macb0_clk {
672 #clock-cells = <0>;
673 reg = <54>;
674 };
675
676 macb1_clk: macb1_clk {
677 #clock-cells = <0>;
678 reg = <55>;
679 };
680
681 fuse_clk: fuse_clk {
682 #clock-cells = <0>;
683 reg = <57>;
684 };
685
686 securam_clk: securam_clk {
687 #clock-cells = <0>;
688 reg = <59>;
689 };
690
691 smd_clk: smd_clk {
692 #clock-cells = <0>;
693 reg = <61>;
694 };
695
696 twi3_clk: twi3_clk {
697 #clock-cells = <0>;
698 reg = <62>;
699 };
700
701 catb_clk: catb_clk {
702 #clock-cells = <0>;
703 reg = <63>;
704 };
705 };
706
707 periph64ck {
708 compatible = "atmel,at91sam9x5-clk-peripheral";
709 #address-cells = <1>;
710 #size-cells = <0>;
711 clocks = <&mck>;
712
713 dma0_clk: dma0_clk {
714 #clock-cells = <0>;
715 reg = <8>;
716 };
717
718 cpkcc_clk: cpkcc_clk {
719 #clock-cells = <0>;
720 reg = <10>;
721 };
722
723 aesb_clk: aesb_clk {
724 #clock-cells = <0>;
725 reg = <13>;
726 };
727
728 mpddr_clk: mpddr_clk {
729 #clock-cells = <0>;
730 reg = <16>;
731 };
732
733 matrix0_clk: matrix0_clk {
734 #clock-cells = <0>;
735 reg = <18>;
736 };
737
738 vdec_clk: vdec_clk {
739 #clock-cells = <0>;
740 reg = <19>;
741 };
742
743 dma1_clk: dma1_clk {
744 #clock-cells = <0>;
745 reg = <50>;
746 };
747
748 lcd_clk: lcd_clk {
749 #clock-cells = <0>;
750 reg = <51>;
751 };
752
753 isi_clk: isi_clk {
754 #clock-cells = <0>;
755 reg = <52>;
756 };
757 };
758 };
759
760 mmc0: mmc@f8000000 {
761 compatible = "atmel,hsmci";
762 reg = <0xf8000000 0x600>;
763 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
764 pinctrl-names = "default";
765 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
766 status = "disabled";
767 #address-cells = <1>;
768 #size-cells = <0>;
769 clocks = <&mci0_clk>;
770 clock-names = "mci_clk";
771 };
772
773 spi0: spi@f8010000 {
774 #address-cells = <1>;
775 #size-cells = <0>;
776 compatible = "atmel,at91rm9200-spi";
777 reg = <0xf8010000 0x100>;
778 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
779 pinctrl-names = "default";
780 pinctrl-0 = <&pinctrl_spi0>;
781 clocks = <&spi0_clk>;
782 clock-names = "spi_clk";
783 status = "disabled";
784 };
785
786 i2c0: i2c@f8014000 {
787 compatible = "atmel,at91sam9x5-i2c";
788 reg = <0xf8014000 0x4000>;
789 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
790 pinctrl-names = "default";
791 pinctrl-0 = <&pinctrl_i2c0>;
792 #address-cells = <1>;
793 #size-cells = <0>;
794 clocks = <&twi0_clk>;
795 status = "disabled";
796 };
797
798 tcb0: timer@f801c000 {
799 compatible = "atmel,at91sam9x5-tcb";
800 reg = <0xf801c000 0x100>;
801 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
802 clocks = <&tcb0_clk>;
803 clock-names = "t0_clk";
804 };
805
806 macb0: ethernet@f8020000 {
807 compatible = "atmel,sama5d4-gem";
808 reg = <0xf8020000 0x100>;
809 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
810 pinctrl-names = "default";
811 pinctrl-0 = <&pinctrl_macb0_rmii>;
812 clocks = <&macb0_clk>, <&macb0_clk>;
813 clock-names = "hclk", "pclk";
814 status = "disabled";
815 };
816
817 i2c2: i2c@f8024000 {
818 compatible = "atmel,at91sam9x5-i2c";
819 reg = <0xf8024000 0x4000>;
820 interrupts = <34 4 6>;
821 pinctrl-names = "default";
822 pinctrl-0 = <&pinctrl_i2c2>;
823 #address-cells = <1>;
824 #size-cells = <0>;
825 clocks = <&twi2_clk>;
826 status = "disabled";
827 };
828
829 mmc1: mmc@fc000000 {
830 compatible = "atmel,hsmci";
831 reg = <0xfc000000 0x600>;
832 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
833 pinctrl-names = "default";
834 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
835 status = "disabled";
836 #address-cells = <1>;
837 #size-cells = <0>;
838 clocks = <&mci1_clk>;
839 clock-names = "mci_clk";
840 };
841
842 usart2: serial@fc008000 {
843 compatible = "atmel,at91sam9260-usart";
844 reg = <0xfc008000 0x100>;
845 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
846 pinctrl-names = "default";
847 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
848 clocks = <&usart2_clk>;
849 clock-names = "usart";
850 status = "disabled";
851 };
852
853 usart3: serial@fc00c000 {
854 compatible = "atmel,at91sam9260-usart";
855 reg = <0xfc00c000 0x100>;
856 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
857 pinctrl-names = "default";
858 pinctrl-0 = <&pinctrl_usart3>;
859 clocks = <&usart3_clk>;
860 clock-names = "usart";
861 status = "disabled";
862 };
863
864 usart4: serial@fc010000 {
865 compatible = "atmel,at91sam9260-usart";
866 reg = <0xfc010000 0x100>;
867 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
868 pinctrl-names = "default";
869 pinctrl-0 = <&pinctrl_usart4>;
870 clocks = <&usart4_clk>;
871 clock-names = "usart";
872 status = "disabled";
873 };
874
875 tcb1: timer@fc020000 {
876 compatible = "atmel,at91sam9x5-tcb";
877 reg = <0xfc020000 0x100>;
878 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
879 clocks = <&tcb1_clk>;
880 clock-names = "t0_clk";
881 };
882
883 adc0: adc@fc034000 {
884 compatible = "atmel,at91sam9x5-adc";
885 reg = <0xfc034000 0x100>;
886 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
887 pinctrl-names = "default";
888 pinctrl-0 = <
889 /* external trigger is conflict with USBA_VBUS */
890 &pinctrl_adc0_ad0
891 &pinctrl_adc0_ad1
892 &pinctrl_adc0_ad2
893 &pinctrl_adc0_ad3
894 &pinctrl_adc0_ad4
895 >;
896 clocks = <&adc_clk>,
897 <&adc_op_clk>;
898 clock-names = "adc_clk", "adc_op_clk";
899 atmel,adc-channels-used = <0x01f>;
900 atmel,adc-startup-time = <40>;
901 atmel,adc-use-external;
902 atmel,adc-vref = <3000>;
903 atmel,adc-res = <8 10>;
904 atmel,adc-sample-hold-time = <11>;
905 atmel,adc-res-names = "lowres", "highres";
906 atmel,adc-ts-pressure-threshold = <10000>;
907 status = "disabled";
908
909 trigger@0 {
910 trigger-name = "external-rising";
911 trigger-value = <0x1>;
912 trigger-external;
913 };
914 trigger@1 {
915 trigger-name = "external-falling";
916 trigger-value = <0x2>;
917 trigger-external;
918 };
919 trigger@2 {
920 trigger-name = "external-any";
921 trigger-value = <0x3>;
922 trigger-external;
923 };
924 trigger@3 {
925 trigger-name = "continuous";
926 trigger-value = <0x6>;
927 };
928 };
929
930 rstc@fc068600 {
931 compatible = "atmel,at91sam9g45-rstc";
932 reg = <0xfc068600 0x10>;
933 };
934
935 shdwc@fc068610 {
936 compatible = "atmel,at91sam9x5-shdwc";
937 reg = <0xfc068610 0x10>;
938 };
939
940 pit: timer@fc068630 {
941 compatible = "atmel,at91sam9260-pit";
942 reg = <0xfc068630 0xf>;
943 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
944 clocks = <&h32ck>;
945 };
946
947 watchdog@fc068640 {
948 compatible = "atmel,at91sam9260-wdt";
949 reg = <0xfc068640 0x10>;
950 status = "disabled";
951 };
952
953 sckc@fc068650 {
954 compatible = "atmel,at91sam9x5-sckc";
955 reg = <0xfc068650 0x4>;
956
957 slow_rc_osc: slow_rc_osc {
958 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
959 #clock-cells = <0>;
960 clock-frequency = <32768>;
961 clock-accuracy = <250000000>;
962 atmel,startup-time-usec = <75>;
963 };
964
965 slow_osc: slow_osc {
966 compatible = "atmel,at91sam9x5-clk-slow-osc";
967 #clock-cells = <0>;
968 clocks = <&slow_xtal>;
969 atmel,startup-time-usec = <1200000>;
970 };
971
972 clk32k: slowck {
973 compatible = "atmel,at91sam9x5-clk-slow";
974 #clock-cells = <0>;
975 clocks = <&slow_rc_osc &slow_osc>;
976 };
977 };
978
979 rtc@fc0686b0 {
980 compatible = "atmel,at91rm9200-rtc";
981 reg = <0xfc0686b0 0x30>;
982 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
983 };
984
985 dbgu: serial@fc069000 {
986 compatible = "atmel,at91sam9260-usart";
987 reg = <0xfc069000 0x200>;
988 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
989 pinctrl-names = "default";
990 pinctrl-0 = <&pinctrl_dbgu>;
991 clocks = <&dbgu_clk>;
992 clock-names = "usart";
993 status = "disabled";
994 };
995
996
997 pinctrl@fc06a000 {
998 #address-cells = <1>;
999 #size-cells = <1>;
1000 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
1001 ranges = <0xfc06a000 0xfc06a000 0x4000>;
1002 /* WARNING: revisit as pin spec has changed */
1003 atmel,mux-mask = <
1004 /* A B C */
1005 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
1006 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
1007 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
1008 0x00000000 0x00000000 0x00000000 /* pioD */
1009 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
1010 >;
1011
1012 pioA: gpio@fc06a000 {
1013 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1014 reg = <0xfc06a000 0x100>;
1015 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
1016 #gpio-cells = <2>;
1017 gpio-controller;
1018 interrupt-controller;
1019 #interrupt-cells = <2>;
1020 clocks = <&pioA_clk>;
1021 };
1022
1023 pioB: gpio@fc06b000 {
1024 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1025 reg = <0xfc06b000 0x100>;
1026 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
1027 #gpio-cells = <2>;
1028 gpio-controller;
1029 interrupt-controller;
1030 #interrupt-cells = <2>;
1031 clocks = <&pioB_clk>;
1032 };
1033
1034 pioC: gpio@fc06c000 {
1035 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1036 reg = <0xfc06c000 0x100>;
1037 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
1038 #gpio-cells = <2>;
1039 gpio-controller;
1040 interrupt-controller;
1041 #interrupt-cells = <2>;
1042 clocks = <&pioC_clk>;
1043 };
1044
1045 pioE: gpio@fc06d000 {
1046 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1047 reg = <0xfc06d000 0x100>;
1048 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
1049 #gpio-cells = <2>;
1050 gpio-controller;
1051 interrupt-controller;
1052 #interrupt-cells = <2>;
1053 clocks = <&pioE_clk>;
1054 };
1055
1056 /* pinctrl pin settings */
1057 adc0 {
1058 pinctrl_adc0_adtrg: adc0_adtrg {
1059 atmel,pins =
1060 <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
1061 };
1062 pinctrl_adc0_ad0: adc0_ad0 {
1063 atmel,pins =
1064 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1065 };
1066 pinctrl_adc0_ad1: adc0_ad1 {
1067 atmel,pins =
1068 <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1069 };
1070 pinctrl_adc0_ad2: adc0_ad2 {
1071 atmel,pins =
1072 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1073 };
1074 pinctrl_adc0_ad3: adc0_ad3 {
1075 atmel,pins =
1076 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1077 };
1078 pinctrl_adc0_ad4: adc0_ad4 {
1079 atmel,pins =
1080 <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1081 };
1082 };
1083
1084 dbgu {
1085 pinctrl_dbgu: dbgu-0 {
1086 atmel,pins =
1087 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */
1088 <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */
1089 };
1090 };
1091
1092 i2c0 {
1093 pinctrl_i2c0: i2c0-0 {
1094 atmel,pins =
1095 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1096 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1097 };
1098 };
1099
1100 i2c2 {
1101 pinctrl_i2c2: i2c2-0 {
1102 atmel,pins =
1103 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
1104 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1105 };
1106 };
1107
1108 macb0 {
1109 pinctrl_macb0_rmii: macb0_rmii-0 {
1110 atmel,pins =
1111 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */
1112 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */
1113 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */
1114 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */
1115 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */
1116 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */
1117 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */
1118 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
1119 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */
1120 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */
1121 >;
1122 };
1123 };
1124
1125 mmc0 {
1126 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1127 atmel,pins =
1128 <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1129 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDB, conflict with NAND_D0 */
1130 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB0, conflict with NAND_D1 */
1131 >;
1132 };
1133 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1134 atmel,pins =
1135 <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB1, conflict with NAND_D2 */
1136 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB2, conflict with NAND_D3 */
1137 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB3, conflict with NAND_D4 */
1138 >;
1139 };
1140 };
1141
1142 mmc1 {
1143 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
1144 atmel,pins =
1145 <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */
1146 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */
1147 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */
1148 >;
1149 };
1150 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
1151 atmel,pins =
1152 <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */
1153 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */
1154 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */
1155 >;
1156 };
1157 };
1158
1159 nand0 {
1160 pinctrl_nand: nand-0 {
1161 atmel,pins =
1162 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */
1163 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */
1164
1165 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */
1166 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */
1167
1168 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */
1169 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */
1170 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
1171 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */
1172 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */
1173 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */
1174 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */
1175 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */
1176 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */
1177 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1178 };
1179 };
1180
1181 spi0 {
1182 pinctrl_spi0: spi0-0 {
1183 atmel,pins =
1184 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
1185 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
1186 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
1187 >;
1188 };
1189 };
1190
1191 usart2 {
1192 pinctrl_usart2: usart2-0 {
1193 atmel,pins =
1194 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1195 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */
1196 >;
1197 };
1198 pinctrl_usart2_rts: usart2_rts-0 {
1199 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */
1200 };
1201 pinctrl_usart2_cts: usart2_cts-0 {
1202 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */
1203 };
1204 };
1205
1206 usart3 {
1207 pinctrl_usart3: usart3-0 {
1208 atmel,pins =
1209 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1210 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1211 >;
1212 };
1213 };
1214
1215 usart4 {
1216 pinctrl_usart4: usart4-0 {
1217 atmel,pins =
1218 <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1219 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1220 >;
1221 };
1222 pinctrl_usart4_rts: usart4_rts-0 {
1223 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */
1224 };
1225 pinctrl_usart4_cts: usart4_cts-0 {
1226 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
1227 };
1228 };
1229 };
1230
1231 aic: interrupt-controller@fc06e000 {
1232 #interrupt-cells = <3>;
1233 compatible = "atmel,sama5d4-aic";
1234 interrupt-controller;
1235 reg = <0xfc06e000 0x200>;
1236 atmel,external-irqs = <56>;
1237 };
1238 };
1239 };
1240};
diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
index 249f65be2a50..f863a10cb1b2 100644
--- a/arch/arm/boot/dts/sh7372.dtsi
+++ b/arch/arm/boot/dts/sh7372.dtsi
@@ -21,6 +21,7 @@
21 compatible = "arm,cortex-a8"; 21 compatible = "arm,cortex-a8";
22 device_type = "cpu"; 22 device_type = "cpu";
23 reg = <0x0>; 23 reg = <0x0>;
24 clock-frequency = <800000000>;
24 }; 25 };
25 }; 26 };
26 27
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 18662aec2ec4..99659db97e89 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -173,6 +173,10 @@
173 }; 173 };
174}; 174};
175 175
176&cmt1 {
177 status = "ok";
178};
179
176&i2c0 { 180&i2c0 {
177 status = "okay"; 181 status = "okay";
178 as3711@40 { 182 as3711@40 {
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 910b79079d5a..d7f52cf31350 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -23,11 +23,13 @@
23 device_type = "cpu"; 23 device_type = "cpu";
24 compatible = "arm,cortex-a9"; 24 compatible = "arm,cortex-a9";
25 reg = <0>; 25 reg = <0>;
26 clock-frequency = <1196000000>;
26 }; 27 };
27 cpu@1 { 28 cpu@1 {
28 device_type = "cpu"; 29 device_type = "cpu";
29 compatible = "arm,cortex-a9"; 30 compatible = "arm,cortex-a9";
30 reg = <1>; 31 reg = <1>;
32 clock-frequency = <1196000000>;
31 }; 33 };
32 }; 34 };
33 35
@@ -45,6 +47,16 @@
45 <0 56 IRQ_TYPE_LEVEL_HIGH>; 47 <0 56 IRQ_TYPE_LEVEL_HIGH>;
46 }; 48 };
47 49
50 cmt1: timer@e6138000 {
51 compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
52 reg = <0xe6138000 0x200>;
53 interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
54
55 renesas,channels-mask = <0x3f>;
56
57 status = "disabled";
58 };
59
48 irqpin0: irqpin@e6900000 { 60 irqpin0: irqpin@e6900000 {
49 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; 61 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
50 #interrupt-cells = <2>; 62 #interrupt-cells = <2>;
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 6cc83d4c6c76..587cadcf7001 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -146,6 +146,11 @@
146 cache-level = <2>; 146 cache-level = <2>;
147 }; 147 };
148 148
149 memory-controller@f8006000 {
150 compatible = "xlnx,zynq-ddrc-a05";
151 reg = <0xf8006000 0x1000>;
152 } ;
153
149 uart0: serial@e0000000 { 154 uart0: serial@e0000000 {
150 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 155 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
151 status = "disabled"; 156 status = "disabled";
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 16:37:34 -0500