aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/hip04.dtsi1
-rw-r--r--arch/arm/boot/dts/omap3-beagle-xm.dts1
-rw-r--r--arch/arm/boot/dts/omap3-beagle.dts1
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts52
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts1
5 files changed, 52 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
index 238814596a87..44044f275115 100644
--- a/arch/arm/boot/dts/hip04.dtsi
+++ b/arch/arm/boot/dts/hip04.dtsi
@@ -275,7 +275,6 @@
275 compatible = "arm,coresight-etb10", "arm,primecell"; 275 compatible = "arm,coresight-etb10", "arm,primecell";
276 reg = <0 0xe3c42000 0 0x1000>; 276 reg = <0 0xe3c42000 0 0x1000>;
277 277
278 coresight-default-sink;
279 clocks = <&clk_375m>; 278 clocks = <&clk_375m>;
280 clock-names = "apb_pclk"; 279 clock-names = "apb_pclk";
281 port { 280 port {
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 25f7b0a22114..8cdca51b6984 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -150,7 +150,6 @@
150 compatible = "arm,coresight-etb10", "arm,primecell"; 150 compatible = "arm,coresight-etb10", "arm,primecell";
151 reg = <0x5401b000 0x1000>; 151 reg = <0x5401b000 0x1000>;
152 152
153 coresight-default-sink;
154 clocks = <&emu_src_ck>; 153 clocks = <&emu_src_ck>;
155 clock-names = "apb_pclk"; 154 clock-names = "apb_pclk";
156 port { 155 port {
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index c792391ef090..6d4c46be8c39 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -145,7 +145,6 @@
145 compatible = "arm,coresight-etb10", "arm,primecell"; 145 compatible = "arm,coresight-etb10", "arm,primecell";
146 reg = <0x5401b000 0x1000>; 146 reg = <0x5401b000 0x1000>;
147 147
148 coresight-default-sink;
149 clocks = <&emu_src_ck>; 148 clocks = <&emu_src_ck>;
150 clock-names = "apb_pclk"; 149 clock-names = "apb_pclk";
151 port { 150 port {
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index db80f9d376fa..2cab149b191c 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -609,6 +609,58 @@
609 pinctrl-0 = <&i2c3_pins>; 609 pinctrl-0 = <&i2c3_pins>;
610 610
611 clock-frequency = <400000>; 611 clock-frequency = <400000>;
612
613 lis302dl: lis3lv02d@1d {
614 compatible = "st,lis3lv02d";
615 reg = <0x1d>;
616
617 Vdd-supply = <&vaux1>;
618 Vdd_IO-supply = <&vio>;
619
620 interrupt-parent = <&gpio6>;
621 interrupts = <21 20>; /* 181 and 180 */
622
623 /* click flags */
624 st,click-single-x;
625 st,click-single-y;
626 st,click-single-z;
627
628 /* Limits are 0.5g * value */
629 st,click-threshold-x = <8>;
630 st,click-threshold-y = <8>;
631 st,click-threshold-z = <10>;
632
633 /* Click must be longer than time limit */
634 st,click-time-limit = <9>;
635
636 /* Kind of debounce filter */
637 st,click-latency = <50>;
638
639 /* Interrupt line 2 for click detection */
640 st,irq2-click;
641
642 st,wakeup-x-hi;
643 st,wakeup-y-hi;
644 st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */
645
646 st,wakeup2-z-hi;
647 st,wakeup2-threshold = <(900/18)>; /* millig-value / 18 to get HW values */
648
649 st,hipass1-disable;
650 st,hipass2-disable;
651
652 st,axis-x = <1>; /* LIS3_DEV_X */
653 st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */
654 st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */
655
656 st,min-limit-x = <(-32)>;
657 st,min-limit-y = <3>;
658 st,min-limit-z = <3>;
659
660 st,max-limit-x = <(-3)>;
661 st,max-limit-y = <32>;
662 st,max-limit-z = <32>;
663 };
612}; 664};
613 665
614&mmc1 { 666&mmc1 {
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 33920df03640..7a2aeacd62c0 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -362,7 +362,6 @@
362 compatible = "arm,coresight-etb10", "arm,primecell"; 362 compatible = "arm,coresight-etb10", "arm,primecell";
363 reg = <0 0x20010000 0 0x1000>; 363 reg = <0 0x20010000 0 0x1000>;
364 364
365 coresight-default-sink;
366 clocks = <&oscclk6a>; 365 clocks = <&oscclk6a>;
367 clock-names = "apb_pclk"; 366 clock-names = "apb_pclk";
368 port { 367 port {