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-rw-r--r--arch/arm/boot/dts/Makefile10
-rw-r--r--arch/arm/boot/dts/emev2.dtsi7
-rw-r--r--arch/arm/boot/dts/imx31.dtsi17
-rw-r--r--arch/arm/boot/dts/marco-evb.dts54
-rw-r--r--arch/arm/boot/dts/marco.dtsi756
-rw-r--r--arch/arm/boot/dts/sh73a0-reference.dtsi24
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi100
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi22
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5.dts34
-rw-r--r--arch/arm/boot/dts/socfpga_vt.dts64
-rw-r--r--arch/arm/boot/dts/tegra114-dalmore.dts21
-rw-r--r--arch/arm/boot/dts/tegra114-pluto.dts21
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi153
-rw-r--r--arch/arm/boot/dts/tegra20-harmony.dts4
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts6
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts4
-rw-r--r--arch/arm/boot/dts/tegra20-trimslice.dts4
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts4
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi96
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi91
-rw-r--r--arch/arm/boot/dts/wm8850-w70v2.dts47
-rw-r--r--arch/arm/boot/dts/wm8850.dtsi224
22 files changed, 1746 insertions, 17 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5ebb44fe826a..042f2111485b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
73 kirkwood-ts219-6281.dtb \ 73 kirkwood-ts219-6281.dtb \
74 kirkwood-ts219-6282.dtb \ 74 kirkwood-ts219-6282.dtb \
75 kirkwood-openblocks_a6.dtb 75 kirkwood-openblocks_a6.dtb
76dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
76dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \ 77dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
77 msm8960-cdp.dtb 78 msm8960-cdp.dtb
78dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ 79dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
@@ -124,6 +125,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
124 r8a7740-armadillo800eva.dtb \ 125 r8a7740-armadillo800eva.dtb \
125 sh73a0-kzm9g.dtb \ 126 sh73a0-kzm9g.dtb \
126 sh7372-mackerel.dtb 127 sh7372-mackerel.dtb
128dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
129 socfpga_vt.dtb
127dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \ 130dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
128 spear1340-evb.dtb 131 spear1340-evb.dtb
129dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \ 132dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
@@ -143,7 +146,9 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
143 tegra20-ventana.dtb \ 146 tegra20-ventana.dtb \
144 tegra20-whistler.dtb \ 147 tegra20-whistler.dtb \
145 tegra30-cardhu-a02.dtb \ 148 tegra30-cardhu-a02.dtb \
146 tegra30-cardhu-a04.dtb 149 tegra30-cardhu-a04.dtb \
150 tegra114-dalmore.dtb \
151 tegra114-pluto.dtb
147dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \ 152dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
148 vexpress-v2p-ca9.dtb \ 153 vexpress-v2p-ca9.dtb \
149 vexpress-v2p-ca15-tc1.dtb \ 154 vexpress-v2p-ca15-tc1.dtb \
@@ -151,7 +156,8 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
151 xenvm-4.2.dtb 156 xenvm-4.2.dtb
152dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \ 157dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
153 wm8505-ref.dtb \ 158 wm8505-ref.dtb \
154 wm8650-mid.dtb 159 wm8650-mid.dtb \
160 wm8850-w70v2.dtb
155dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb 161dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb
156 162
157targets += dtbs 163targets += dtbs
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
index eb504a6c0f4a..c8a8c08b48dd 100644
--- a/arch/arm/boot/dts/emev2.dtsi
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -15,11 +15,18 @@
15 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
16 16
17 cpus { 17 cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
18 cpu@0 { 21 cpu@0 {
22 device_type = "cpu";
19 compatible = "arm,cortex-a9"; 23 compatible = "arm,cortex-a9";
24 reg = <0>;
20 }; 25 };
21 cpu@1 { 26 cpu@1 {
27 device_type = "cpu";
22 compatible = "arm,cortex-a9"; 28 compatible = "arm,cortex-a9";
29 reg = <1>;
23 }; 30 };
24 }; 31 };
25 32
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
index eef7099f3e3c..454c2d175402 100644
--- a/arch/arm/boot/dts/imx31.dtsi
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -45,6 +45,8 @@
45 compatible = "fsl,imx31-uart", "fsl,imx21-uart"; 45 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
46 reg = <0x43f90000 0x4000>; 46 reg = <0x43f90000 0x4000>;
47 interrupts = <45>; 47 interrupts = <45>;
48 clocks = <&clks 10>, <&clks 30>;
49 clock-names = "ipg", "per";
48 status = "disabled"; 50 status = "disabled";
49 }; 51 };
50 52
@@ -52,12 +54,16 @@
52 compatible = "fsl,imx31-uart", "fsl,imx21-uart"; 54 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
53 reg = <0x43f94000 0x4000>; 55 reg = <0x43f94000 0x4000>;
54 interrupts = <32>; 56 interrupts = <32>;
57 clocks = <&clks 10>, <&clks 31>;
58 clock-names = "ipg", "per";
55 status = "disabled"; 59 status = "disabled";
56 }; 60 };
57 61
58 uart4: serial@43fb0000 { 62 uart4: serial@43fb0000 {
59 compatible = "fsl,imx31-uart", "fsl,imx21-uart"; 63 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
60 reg = <0x43fb0000 0x4000>; 64 reg = <0x43fb0000 0x4000>;
65 clocks = <&clks 10>, <&clks 49>;
66 clock-names = "ipg", "per";
61 interrupts = <46>; 67 interrupts = <46>;
62 status = "disabled"; 68 status = "disabled";
63 }; 69 };
@@ -66,6 +72,8 @@
66 compatible = "fsl,imx31-uart", "fsl,imx21-uart"; 72 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
67 reg = <0x43fb4000 0x4000>; 73 reg = <0x43fb4000 0x4000>;
68 interrupts = <47>; 74 interrupts = <47>;
75 clocks = <&clks 10>, <&clks 50>;
76 clock-names = "ipg", "per";
69 status = "disabled"; 77 status = "disabled";
70 }; 78 };
71 }; 79 };
@@ -81,8 +89,17 @@
81 compatible = "fsl,imx31-uart", "fsl,imx21-uart"; 89 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
82 reg = <0x5000c000 0x4000>; 90 reg = <0x5000c000 0x4000>;
83 interrupts = <18>; 91 interrupts = <18>;
92 clocks = <&clks 10>, <&clks 48>;
93 clock-names = "ipg", "per";
84 status = "disabled"; 94 status = "disabled";
85 }; 95 };
96
97 clks: ccm@53f80000{
98 compatible = "fsl,imx31-ccm";
99 reg = <0x53f80000 0x4000>;
100 interrupts = <0 31 0x04 0 53 0x04>;
101 #clock-cells = <1>;
102 };
86 }; 103 };
87 }; 104 };
88}; 105};
diff --git a/arch/arm/boot/dts/marco-evb.dts b/arch/arm/boot/dts/marco-evb.dts
new file mode 100644
index 000000000000..5130aeacfca5
--- /dev/null
+++ b/arch/arm/boot/dts/marco-evb.dts
@@ -0,0 +1,54 @@
1/*
2 * DTS file for CSR SiRFmarco Evaluation Board
3 *
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/dts-v1/;
10
11/include/ "marco.dtsi"
12
13/ {
14 model = "CSR SiRFmarco Evaluation Board";
15 compatible = "sirf,marco-cb", "sirf,marco";
16
17 memory {
18 reg = <0x40000000 0x60000000>;
19 };
20
21 axi {
22 peri-iobg {
23 uart1: uart@cc060000 {
24 status = "okay";
25 };
26 uart2: uart@cc070000 {
27 status = "okay";
28 };
29 i2c0: i2c@cc0e0000 {
30 status = "okay";
31 fpga-cpld@4d {
32 compatible = "sirf,fpga-cpld";
33 reg = <0x4d>;
34 };
35 };
36 spi1: spi@cc170000 {
37 status = "okay";
38 pinctrl-names = "default";
39 pinctrl-0 = <&spi1_pins_a>;
40 spi@0 {
41 compatible = "spidev";
42 reg = <0>;
43 spi-max-frequency = <1000000>;
44 };
45 };
46 pci-iobg {
47 sd0: sdhci@cd000000 {
48 bus-width = <8>;
49 status = "okay";
50 };
51 };
52 };
53 };
54};
diff --git a/arch/arm/boot/dts/marco.dtsi b/arch/arm/boot/dts/marco.dtsi
new file mode 100644
index 000000000000..1579c3491ccd
--- /dev/null
+++ b/arch/arm/boot/dts/marco.dtsi
@@ -0,0 +1,756 @@
1/*
2 * DTS file for CSR SiRFmarco SoC
3 *
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/include/ "skeleton.dtsi"
10/ {
11 compatible = "sirf,marco";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&gic>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 device_type = "cpu";
22 compatible = "arm,cortex-a9";
23 reg = <0>;
24 };
25 cpu@1 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a9";
28 reg = <1>;
29 };
30 };
31
32 axi {
33 compatible = "simple-bus";
34 #address-cells = <1>;
35 #size-cells = <1>;
36 ranges = <0x40000000 0x40000000 0xa0000000>;
37
38 l2-cache-controller@c0030000 {
39 compatible = "sirf,marco-pl310-cache", "arm,pl310-cache";
40 reg = <0xc0030000 0x1000>;
41 interrupts = <0 59 0>;
42 arm,tag-latency = <1 1 1>;
43 arm,data-latency = <1 1 1>;
44 arm,filter-ranges = <0x40000000 0x80000000>;
45 };
46
47 gic: interrupt-controller@c0011000 {
48 compatible = "arm,cortex-a9-gic";
49 interrupt-controller;
50 #interrupt-cells = <3>;
51 reg = <0xc0011000 0x1000>,
52 <0xc0010100 0x0100>;
53 };
54
55 rstc-iobg {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <1>;
59 ranges = <0xc2000000 0xc2000000 0x1000000>;
60
61 reset-controller@c2000000 {
62 compatible = "sirf,marco-rstc";
63 reg = <0xc2000000 0x10000>;
64 };
65 };
66
67 sys-iobg {
68 compatible = "simple-bus";
69 #address-cells = <1>;
70 #size-cells = <1>;
71 ranges = <0xc3000000 0xc3000000 0x1000000>;
72
73 clock-controller@c3000000 {
74 compatible = "sirf,marco-clkc";
75 reg = <0xc3000000 0x1000>;
76 interrupts = <0 3 0>;
77 };
78
79 rsc-controller@c3010000 {
80 compatible = "sirf,marco-rsc";
81 reg = <0xc3010000 0x1000>;
82 };
83 };
84
85 mem-iobg {
86 compatible = "simple-bus";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 ranges = <0xc4000000 0xc4000000 0x1000000>;
90
91 memory-controller@c4000000 {
92 compatible = "sirf,marco-memc";
93 reg = <0xc4000000 0x10000>;
94 interrupts = <0 27 0>;
95 };
96 };
97
98 disp-iobg0 {
99 compatible = "simple-bus";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges = <0xc5000000 0xc5000000 0x1000000>;
103
104 display0@c5000000 {
105 compatible = "sirf,marco-lcd";
106 reg = <0xc5000000 0x10000>;
107 interrupts = <0 30 0>;
108 };
109
110 vpp0@c5010000 {
111 compatible = "sirf,marco-vpp";
112 reg = <0xc5010000 0x10000>;
113 interrupts = <0 31 0>;
114 };
115 };
116
117 disp-iobg1 {
118 compatible = "simple-bus";
119 #address-cells = <1>;
120 #size-cells = <1>;
121 ranges = <0xc6000000 0xc6000000 0x1000000>;
122
123 display1@c6000000 {
124 compatible = "sirf,marco-lcd";
125 reg = <0xc6000000 0x10000>;
126 interrupts = <0 62 0>;
127 };
128
129 vpp1@c6010000 {
130 compatible = "sirf,marco-vpp";
131 reg = <0xc6010000 0x10000>;
132 interrupts = <0 63 0>;
133 };
134 };
135
136 graphics-iobg {
137 compatible = "simple-bus";
138 #address-cells = <1>;
139 #size-cells = <1>;
140 ranges = <0xc8000000 0xc8000000 0x1000000>;
141
142 graphics@c8000000 {
143 compatible = "powervr,sgx540";
144 reg = <0xc8000000 0x1000000>;
145 interrupts = <0 6 0>;
146 };
147 };
148
149 multimedia-iobg {
150 compatible = "simple-bus";
151 #address-cells = <1>;
152 #size-cells = <1>;
153 ranges = <0xc9000000 0xc9000000 0x1000000>;
154
155 multimedia@a0000000 {
156 compatible = "sirf,marco-video-codec";
157 reg = <0xc9000000 0x1000000>;
158 interrupts = <0 5 0>;
159 };
160 };
161
162 dsp-iobg {
163 compatible = "simple-bus";
164 #address-cells = <1>;
165 #size-cells = <1>;
166 ranges = <0xca000000 0xca000000 0x2000000>;
167
168 dspif@ca000000 {
169 compatible = "sirf,marco-dspif";
170 reg = <0xca000000 0x10000>;
171 interrupts = <0 9 0>;
172 };
173
174 gps@ca010000 {
175 compatible = "sirf,marco-gps";
176 reg = <0xca010000 0x10000>;
177 interrupts = <0 7 0>;
178 };
179
180 dsp@cb000000 {
181 compatible = "sirf,marco-dsp";
182 reg = <0xcb000000 0x1000000>;
183 interrupts = <0 8 0>;
184 };
185 };
186
187 peri-iobg {
188 compatible = "simple-bus";
189 #address-cells = <1>;
190 #size-cells = <1>;
191 ranges = <0xcc000000 0xcc000000 0x2000000>;
192
193 timer@cc020000 {
194 compatible = "sirf,marco-tick";
195 reg = <0xcc020000 0x1000>;
196 interrupts = <0 0 0>,
197 <0 1 0>,
198 <0 2 0>,
199 <0 49 0>,
200 <0 50 0>,
201 <0 51 0>;
202 };
203
204 nand@cc030000 {
205 compatible = "sirf,marco-nand";
206 reg = <0xcc030000 0x10000>;
207 interrupts = <0 41 0>;
208 };
209
210 audio@cc040000 {
211 compatible = "sirf,marco-audio";
212 reg = <0xcc040000 0x10000>;
213 interrupts = <0 35 0>;
214 };
215
216 uart0: uart@cc050000 {
217 cell-index = <0>;
218 compatible = "sirf,marco-uart";
219 reg = <0xcc050000 0x1000>;
220 interrupts = <0 17 0>;
221 fifosize = <128>;
222 status = "disabled";
223 };
224
225 uart1: uart@cc060000 {
226 cell-index = <1>;
227 compatible = "sirf,marco-uart";
228 reg = <0xcc060000 0x1000>;
229 interrupts = <0 18 0>;
230 fifosize = <32>;
231 status = "disabled";
232 };
233
234 uart2: uart@cc070000 {
235 cell-index = <2>;
236 compatible = "sirf,marco-uart";
237 reg = <0xcc070000 0x1000>;
238 interrupts = <0 19 0>;
239 fifosize = <128>;
240 status = "disabled";
241 };
242
243 uart3: uart@cc190000 {
244 cell-index = <3>;
245 compatible = "sirf,marco-uart";
246 reg = <0xcc190000 0x1000>;
247 interrupts = <0 66 0>;
248 fifosize = <128>;
249 status = "disabled";
250 };
251
252 uart4: uart@cc1a0000 {
253 cell-index = <4>;
254 compatible = "sirf,marco-uart";
255 reg = <0xcc1a0000 0x1000>;
256 interrupts = <0 69 0>;
257 fifosize = <128>;
258 status = "disabled";
259 };
260
261 usp0: usp@cc080000 {
262 cell-index = <0>;
263 compatible = "sirf,marco-usp";
264 reg = <0xcc080000 0x10000>;
265 interrupts = <0 20 0>;
266 status = "disabled";
267 };
268
269 usp1: usp@cc090000 {
270 cell-index = <1>;
271 compatible = "sirf,marco-usp";
272 reg = <0xcc090000 0x10000>;
273 interrupts = <0 21 0>;
274 status = "disabled";
275 };
276
277 usp2: usp@cc0a0000 {
278 cell-index = <2>;
279 compatible = "sirf,marco-usp";
280 reg = <0xcc0a0000 0x10000>;
281 interrupts = <0 22 0>;
282 status = "disabled";
283 };
284
285 dmac0: dma-controller@cc0b0000 {
286 cell-index = <0>;
287 compatible = "sirf,marco-dmac";
288 reg = <0xcc0b0000 0x10000>;
289 interrupts = <0 12 0>;
290 };
291
292 dmac1: dma-controller@cc160000 {
293 cell-index = <1>;
294 compatible = "sirf,marco-dmac";
295 reg = <0xcc160000 0x10000>;
296 interrupts = <0 13 0>;
297 };
298
299 vip@cc0c0000 {
300 compatible = "sirf,marco-vip";
301 reg = <0xcc0c0000 0x10000>;
302 };
303
304 spi0: spi@cc0d0000 {
305 cell-index = <0>;
306 compatible = "sirf,marco-spi";
307 reg = <0xcc0d0000 0x10000>;
308 interrupts = <0 15 0>;
309 sirf,spi-num-chipselects = <1>;
310 cs-gpios = <&gpio 0 0>;
311 sirf,spi-dma-rx-channel = <25>;
312 sirf,spi-dma-tx-channel = <20>;
313 #address-cells = <1>;
314 #size-cells = <0>;
315 status = "disabled";
316 };
317
318 spi1: spi@cc170000 {
319 cell-index = <1>;
320 compatible = "sirf,marco-spi";
321 reg = <0xcc170000 0x10000>;
322 interrupts = <0 16 0>;
323 sirf,spi-num-chipselects = <1>;
324 cs-gpios = <&gpio 0 0>;
325 sirf,spi-dma-rx-channel = <12>;
326 sirf,spi-dma-tx-channel = <13>;
327 #address-cells = <1>;
328 #size-cells = <0>;
329 status = "disabled";
330 };
331
332 i2c0: i2c@cc0e0000 {
333 cell-index = <0>;
334 compatible = "sirf,marco-i2c";
335 reg = <0xcc0e0000 0x10000>;
336 interrupts = <0 24 0>;
337 #address-cells = <1>;
338 #size-cells = <0>;
339 status = "disabled";
340 };
341
342 i2c1: i2c@cc0f0000 {
343 cell-index = <1>;
344 compatible = "sirf,marco-i2c";
345 reg = <0xcc0f0000 0x10000>;
346 interrupts = <0 25 0>;
347 #address-cells = <1>;
348 #size-cells = <0>;
349 status = "disabled";
350 };
351
352 tsc@cc110000 {
353 compatible = "sirf,marco-tsc";
354 reg = <0xcc110000 0x10000>;
355 interrupts = <0 33 0>;
356 };
357
358 gpio: pinctrl@cc120000 {
359 #gpio-cells = <2>;
360 #interrupt-cells = <2>;
361 compatible = "sirf,marco-pinctrl";
362 reg = <0xcc120000 0x10000>;
363 interrupts = <0 43 0>,
364 <0 44 0>,
365 <0 45 0>,
366 <0 46 0>,
367 <0 47 0>;
368 gpio-controller;
369 interrupt-controller;
370
371 lcd_16pins_a: lcd0_0 {
372 lcd {
373 sirf,pins = "lcd_16bitsgrp";
374 sirf,function = "lcd_16bits";
375 };
376 };
377 lcd_18pins_a: lcd0_1 {
378 lcd {
379 sirf,pins = "lcd_18bitsgrp";
380 sirf,function = "lcd_18bits";
381 };
382 };
383 lcd_24pins_a: lcd0_2 {
384 lcd {
385 sirf,pins = "lcd_24bitsgrp";
386 sirf,function = "lcd_24bits";
387 };
388 };
389 lcdrom_pins_a: lcdrom0_0 {
390 lcd {
391 sirf,pins = "lcdromgrp";
392 sirf,function = "lcdrom";
393 };
394 };
395 uart0_pins_a: uart0_0 {
396 uart {
397 sirf,pins = "uart0grp";
398 sirf,function = "uart0";
399 };
400 };
401 uart1_pins_a: uart1_0 {
402 uart {
403 sirf,pins = "uart1grp";
404 sirf,function = "uart1";
405 };
406 };
407 uart2_pins_a: uart2_0 {
408 uart {
409 sirf,pins = "uart2grp";
410 sirf,function = "uart2";
411 };
412 };
413 uart2_noflow_pins_a: uart2_1 {
414 uart {
415 sirf,pins = "uart2_nostreamctrlgrp";
416 sirf,function = "uart2_nostreamctrl";
417 };
418 };
419 spi0_pins_a: spi0_0 {
420 spi {
421 sirf,pins = "spi0grp";
422 sirf,function = "spi0";
423 };
424 };
425 spi1_pins_a: spi1_0 {
426 spi {
427 sirf,pins = "spi1grp";
428 sirf,function = "spi1";
429 };
430 };
431 i2c0_pins_a: i2c0_0 {
432 i2c {
433 sirf,pins = "i2c0grp";
434 sirf,function = "i2c0";
435 };
436 };
437 i2c1_pins_a: i2c1_0 {
438 i2c {
439 sirf,pins = "i2c1grp";
440 sirf,function = "i2c1";
441 };
442 };
443 pwm0_pins_a: pwm0_0 {
444 pwm {
445 sirf,pins = "pwm0grp";
446 sirf,function = "pwm0";
447 };
448 };
449 pwm1_pins_a: pwm1_0 {
450 pwm {
451 sirf,pins = "pwm1grp";
452 sirf,function = "pwm1";
453 };
454 };
455 pwm2_pins_a: pwm2_0 {
456 pwm {
457 sirf,pins = "pwm2grp";
458 sirf,function = "pwm2";
459 };
460 };
461 pwm3_pins_a: pwm3_0 {
462 pwm {
463 sirf,pins = "pwm3grp";
464 sirf,function = "pwm3";
465 };
466 };
467 gps_pins_a: gps_0 {
468 gps {
469 sirf,pins = "gpsgrp";
470 sirf,function = "gps";
471 };
472 };
473 vip_pins_a: vip_0 {
474 vip {
475 sirf,pins = "vipgrp";
476 sirf,function = "vip";
477 };
478 };
479 sdmmc0_pins_a: sdmmc0_0 {
480 sdmmc0 {
481 sirf,pins = "sdmmc0grp";
482 sirf,function = "sdmmc0";
483 };
484 };
485 sdmmc1_pins_a: sdmmc1_0 {
486 sdmmc1 {
487 sirf,pins = "sdmmc1grp";
488 sirf,function = "sdmmc1";
489 };
490 };
491 sdmmc2_pins_a: sdmmc2_0 {
492 sdmmc2 {
493 sirf,pins = "sdmmc2grp";
494 sirf,function = "sdmmc2";
495 };
496 };
497 sdmmc3_pins_a: sdmmc3_0 {
498 sdmmc3 {
499 sirf,pins = "sdmmc3grp";
500 sirf,function = "sdmmc3";
501 };
502 };
503 sdmmc4_pins_a: sdmmc4_0 {
504 sdmmc4 {
505 sirf,pins = "sdmmc4grp";
506 sirf,function = "sdmmc4";
507 };
508 };
509 sdmmc5_pins_a: sdmmc5_0 {
510 sdmmc5 {
511 sirf,pins = "sdmmc5grp";
512 sirf,function = "sdmmc5";
513 };
514 };
515 i2s_pins_a: i2s_0 {
516 i2s {
517 sirf,pins = "i2sgrp";
518 sirf,function = "i2s";
519 };
520 };
521 ac97_pins_a: ac97_0 {
522 ac97 {
523 sirf,pins = "ac97grp";
524 sirf,function = "ac97";
525 };
526 };
527 nand_pins_a: nand_0 {
528 nand {
529 sirf,pins = "nandgrp";
530 sirf,function = "nand";
531 };
532 };
533 usp0_pins_a: usp0_0 {
534 usp0 {
535 sirf,pins = "usp0grp";
536 sirf,function = "usp0";
537 };
538 };
539 usp1_pins_a: usp1_0 {
540 usp1 {
541 sirf,pins = "usp1grp";
542 sirf,function = "usp1";
543 };
544 };
545 usp2_pins_a: usp2_0 {
546 usp2 {
547 sirf,pins = "usp2grp";
548 sirf,function = "usp2";
549 };
550 };
551 usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus_0 {
552 usb0_utmi_drvbus {
553 sirf,pins = "usb0_utmi_drvbusgrp";
554 sirf,function = "usb0_utmi_drvbus";
555 };
556 };
557 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus_0 {
558 usb1_utmi_drvbus {
559 sirf,pins = "usb1_utmi_drvbusgrp";
560 sirf,function = "usb1_utmi_drvbus";
561 };
562 };
563 warm_rst_pins_a: warm_rst_0 {
564 warm_rst {
565 sirf,pins = "warm_rstgrp";
566 sirf,function = "warm_rst";
567 };
568 };
569 pulse_count_pins_a: pulse_count_0 {
570 pulse_count {
571 sirf,pins = "pulse_countgrp";
572 sirf,function = "pulse_count";
573 };
574 };
575 cko0_rst_pins_a: cko0_rst_0 {
576 cko0_rst {
577 sirf,pins = "cko0_rstgrp";
578 sirf,function = "cko0_rst";
579 };
580 };
581 cko1_rst_pins_a: cko1_rst_0 {
582 cko1_rst {
583 sirf,pins = "cko1_rstgrp";
584 sirf,function = "cko1_rst";
585 };
586 };
587 };
588
589 pwm@cc130000 {
590 compatible = "sirf,marco-pwm";
591 reg = <0xcc130000 0x10000>;
592 };
593
594 efusesys@cc140000 {
595 compatible = "sirf,marco-efuse";
596 reg = <0xcc140000 0x10000>;
597 };
598
599 pulsec@cc150000 {
600 compatible = "sirf,marco-pulsec";
601 reg = <0xcc150000 0x10000>;
602 interrupts = <0 48 0>;
603 };
604
605 pci-iobg {
606 compatible = "sirf,marco-pciiobg", "simple-bus";
607 #address-cells = <1>;
608 #size-cells = <1>;
609 ranges = <0xcd000000 0xcd000000 0x1000000>;
610
611 sd0: sdhci@cd000000 {
612 cell-index = <0>;
613 compatible = "sirf,marco-sdhc";
614 reg = <0xcd000000 0x100000>;
615 interrupts = <0 38 0>;
616 status = "disabled";
617 };
618
619 sd1: sdhci@cd100000 {
620 cell-index = <1>;
621 compatible = "sirf,marco-sdhc";
622 reg = <0xcd100000 0x100000>;
623 interrupts = <0 38 0>;
624 status = "disabled";
625 };
626
627 sd2: sdhci@cd200000 {
628 cell-index = <2>;
629 compatible = "sirf,marco-sdhc";
630 reg = <0xcd200000 0x100000>;
631 interrupts = <0 23 0>;
632 status = "disabled";
633 };
634
635 sd3: sdhci@cd300000 {
636 cell-index = <3>;
637 compatible = "sirf,marco-sdhc";
638 reg = <0xcd300000 0x100000>;
639 interrupts = <0 23 0>;
640 status = "disabled";
641 };
642
643 sd4: sdhci@cd400000 {
644 cell-index = <4>;
645 compatible = "sirf,marco-sdhc";
646 reg = <0xcd400000 0x100000>;
647 interrupts = <0 39 0>;
648 status = "disabled";
649 };
650
651 sd5: sdhci@cd500000 {
652 cell-index = <5>;
653 compatible = "sirf,marco-sdhc";
654 reg = <0xcd500000 0x100000>;
655 interrupts = <0 39 0>;
656 status = "disabled";
657 };
658
659 pci-copy@cd900000 {
660 compatible = "sirf,marco-pcicp";
661 reg = <0xcd900000 0x100000>;
662 interrupts = <0 40 0>;
663 };
664
665 rom-interface@cda00000 {
666 compatible = "sirf,marco-romif";
667 reg = <0xcda00000 0x100000>;
668 };
669 };
670 };
671
672 rtc-iobg {
673 compatible = "sirf,marco-rtciobg", "sirf-marco-rtciobg-bus";
674 #address-cells = <1>;
675 #size-cells = <1>;
676 reg = <0xc1000000 0x10000>;
677
678 gpsrtc@1000 {
679 compatible = "sirf,marco-gpsrtc";
680 reg = <0x1000 0x1000>;
681 interrupts = <0 55 0>,
682 <0 56 0>,
683 <0 57 0>;
684 };
685
686 sysrtc@2000 {
687 compatible = "sirf,marco-sysrtc";
688 reg = <0x2000 0x1000>;
689 interrupts = <0 52 0>,
690 <0 53 0>,
691 <0 54 0>;
692 };
693
694 pwrc@3000 {
695 compatible = "sirf,marco-pwrc";
696 reg = <0x3000 0x1000>;
697 interrupts = <0 32 0>;
698 };
699 };
700
701 uus-iobg {
702 compatible = "simple-bus";
703 #address-cells = <1>;
704 #size-cells = <1>;
705 ranges = <0xce000000 0xce000000 0x1000000>;
706
707 usb0: usb@ce000000 {
708 compatible = "chipidea,ci13611a-marco";
709 reg = <0xce000000 0x10000>;
710 interrupts = <0 10 0>;
711 };
712
713 usb1: usb@ce010000 {
714 compatible = "chipidea,ci13611a-marco";
715 reg = <0xce010000 0x10000>;
716 interrupts = <0 11 0>;
717 };
718
719 security@ce020000 {
720 compatible = "sirf,marco-security";
721 reg = <0xce020000 0x10000>;
722 interrupts = <0 42 0>;
723 };
724 };
725
726 can-iobg {
727 compatible = "simple-bus";
728 #address-cells = <1>;
729 #size-cells = <1>;
730 ranges = <0xd0000000 0xd0000000 0x1000000>;
731
732 can0: can@d0000000 {
733 compatible = "sirf,marco-can";
734 reg = <0xd0000000 0x10000>;
735 };
736
737 can1: can@d0010000 {
738 compatible = "sirf,marco-can";
739 reg = <0xd0010000 0x10000>;
740 };
741 };
742
743 lvds-iobg {
744 compatible = "simple-bus";
745 #address-cells = <1>;
746 #size-cells = <1>;
747 ranges = <0xd1000000 0xd1000000 0x1000000>;
748
749 lvds@d1000000 {
750 compatible = "sirf,marco-lvds";
751 reg = <0xd1000000 0x10000>;
752 interrupts = <0 64 0>;
753 };
754 };
755 };
756};
diff --git a/arch/arm/boot/dts/sh73a0-reference.dtsi b/arch/arm/boot/dts/sh73a0-reference.dtsi
new file mode 100644
index 000000000000..d4bb0125b2b2
--- /dev/null
+++ b/arch/arm/boot/dts/sh73a0-reference.dtsi
@@ -0,0 +1,24 @@
1/*
2 * Device Tree Source for the SH73A0 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "sh73a0.dtsi"
12
13/ {
14 compatible = "renesas,sh73a0";
15
16 mmcif: mmcif@0x10010000 {
17 compatible = "renesas,sh-mmcif";
18 reg = <0xe6bd0000 0x100>;
19 interrupt-parent = <&gic>;
20 interrupts = <0 140 0x4
21 0 141 0x4>;
22 reg-io-width = <4>;
23 };
24};
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
new file mode 100644
index 000000000000..8a59465d0231
--- /dev/null
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -0,0 +1,100 @@
1/*
2 * Device Tree Source for the SH73A0 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "renesas,sh73a0";
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 device_type = "cpu";
22 compatible = "arm,cortex-a9";
23 reg = <0>;
24 };
25 cpu@1 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a9";
28 reg = <1>;
29 };
30 };
31
32 gic: interrupt-controller@f0001000 {
33 compatible = "arm,cortex-a9-gic";
34 #interrupt-cells = <3>;
35 #address-cells = <1>;
36 interrupt-controller;
37 reg = <0xf0001000 0x1000>,
38 <0xf0000100 0x100>;
39 };
40
41 i2c0: i2c@0xe6820000 {
42 #address-cells = <1>;
43 #size-cells = <0>;
44 compatible = "renesas,rmobile-iic";
45 reg = <0xe6820000 0x425>;
46 interrupt-parent = <&gic>;
47 interrupts = <0 167 0x4
48 0 168 0x4
49 0 169 0x4
50 0 170 0x4>;
51 };
52
53 i2c1: i2c@0xe6822000 {
54 #address-cells = <1>;
55 #size-cells = <0>;
56 compatible = "renesas,rmobile-iic";
57 reg = <0xe6822000 0x425>;
58 interrupt-parent = <&gic>;
59 interrupts = <0 51 0x4
60 0 52 0x4
61 0 53 0x4
62 0 54 0x4>;
63 };
64
65 i2c2: i2c@0xe6824000 {
66 #address-cells = <1>;
67 #size-cells = <0>;
68 compatible = "renesas,rmobile-iic";
69 reg = <0xe6824000 0x425>;
70 interrupt-parent = <&gic>;
71 interrupts = <0 171 0x4
72 0 172 0x4
73 0 173 0x4
74 0 174 0x4>;
75 };
76
77 i2c3: i2c@0xe6826000 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 compatible = "renesas,rmobile-iic";
81 reg = <0xe6826000 0x425>;
82 interrupt-parent = <&gic>;
83 interrupts = <0 183 0x4
84 0 184 0x4
85 0 185 0x4
86 0 186 0x4>;
87 };
88
89 i2c4: i2c@0xe6828000 {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 compatible = "renesas,rmobile-iic";
93 reg = <0xe6828000 0x425>;
94 interrupt-parent = <&gic>;
95 interrupts = <0 187 0x4
96 0 188 0x4
97 0 189 0x4
98 0 190 0x4>;
99 };
100};
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 19aec421bb26..936d2306e7e1 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -25,6 +25,10 @@
25 ethernet0 = &gmac0; 25 ethernet0 = &gmac0;
26 serial0 = &uart0; 26 serial0 = &uart0;
27 serial1 = &uart1; 27 serial1 = &uart1;
28 timer0 = &timer0;
29 timer1 = &timer1;
30 timer2 = &timer2;
31 timer3 = &timer3;
28 }; 32 };
29 33
30 cpus { 34 cpus {
@@ -98,47 +102,41 @@
98 interrupts = <1 13 0xf04>; 102 interrupts = <1 13 0xf04>;
99 }; 103 };
100 104
101 timer0: timer@ffc08000 { 105 timer0: timer0@ffc08000 {
102 compatible = "snps,dw-apb-timer-sp"; 106 compatible = "snps,dw-apb-timer-sp";
103 interrupts = <0 167 4>; 107 interrupts = <0 167 4>;
104 clock-frequency = <200000000>;
105 reg = <0xffc08000 0x1000>; 108 reg = <0xffc08000 0x1000>;
106 }; 109 };
107 110
108 timer1: timer@ffc09000 { 111 timer1: timer1@ffc09000 {
109 compatible = "snps,dw-apb-timer-sp"; 112 compatible = "snps,dw-apb-timer-sp";
110 interrupts = <0 168 4>; 113 interrupts = <0 168 4>;
111 clock-frequency = <200000000>;
112 reg = <0xffc09000 0x1000>; 114 reg = <0xffc09000 0x1000>;
113 }; 115 };
114 116
115 timer2: timer@ffd00000 { 117 timer2: timer2@ffd00000 {
116 compatible = "snps,dw-apb-timer-osc"; 118 compatible = "snps,dw-apb-timer-osc";
117 interrupts = <0 169 4>; 119 interrupts = <0 169 4>;
118 clock-frequency = <200000000>;
119 reg = <0xffd00000 0x1000>; 120 reg = <0xffd00000 0x1000>;
120 }; 121 };
121 122
122 timer3: timer@ffd01000 { 123 timer3: timer3@ffd01000 {
123 compatible = "snps,dw-apb-timer-osc"; 124 compatible = "snps,dw-apb-timer-osc";
124 interrupts = <0 170 4>; 125 interrupts = <0 170 4>;
125 clock-frequency = <200000000>;
126 reg = <0xffd01000 0x1000>; 126 reg = <0xffd01000 0x1000>;
127 }; 127 };
128 128
129 uart0: uart@ffc02000 { 129 uart0: serial0@ffc02000 {
130 compatible = "snps,dw-apb-uart"; 130 compatible = "snps,dw-apb-uart";
131 reg = <0xffc02000 0x1000>; 131 reg = <0xffc02000 0x1000>;
132 clock-frequency = <7372800>;
133 interrupts = <0 162 4>; 132 interrupts = <0 162 4>;
134 reg-shift = <2>; 133 reg-shift = <2>;
135 reg-io-width = <4>; 134 reg-io-width = <4>;
136 }; 135 };
137 136
138 uart1: uart@ffc03000 { 137 uart1: serial1@ffc03000 {
139 compatible = "snps,dw-apb-uart"; 138 compatible = "snps,dw-apb-uart";
140 reg = <0xffc03000 0x1000>; 139 reg = <0xffc03000 0x1000>;
141 clock-frequency = <7372800>;
142 interrupts = <0 163 4>; 140 interrupts = <0 163 4>;
143 reg-shift = <2>; 141 reg-shift = <2>;
144 reg-io-width = <4>; 142 reg-io-width = <4>;
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index ab7e4a94299f..3ae8a83a0875 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -20,7 +20,7 @@
20 20
21/ { 21/ {
22 model = "Altera SOCFPGA Cyclone V"; 22 model = "Altera SOCFPGA Cyclone V";
23 compatible = "altr,socfpga-cyclone5"; 23 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
24 24
25 chosen { 25 chosen {
26 bootargs = "console=ttyS0,57600"; 26 bootargs = "console=ttyS0,57600";
@@ -29,6 +29,36 @@
29 memory { 29 memory {
30 name = "memory"; 30 name = "memory";
31 device_type = "memory"; 31 device_type = "memory";
32 reg = <0x0 0x10000000>; /* 256MB */ 32 reg = <0x0 0x40000000>; /* 1GB */
33 };
34
35 soc {
36 timer0@ffc08000 {
37 clock-frequency = <100000000>;
38 };
39
40 timer1@ffc09000 {
41 clock-frequency = <100000000>;
42 };
43
44 timer2@ffd00000 {
45 clock-frequency = <25000000>;
46 };
47
48 timer3@ffd01000 {
49 clock-frequency = <25000000>;
50 };
51
52 serial0@ffc02000 {
53 clock-frequency = <100000000>;
54 };
55
56 serial1@ffc03000 {
57 clock-frequency = <100000000>;
58 };
59
60 sysmgr@ffd08000 {
61 cpu1-start-addr = <0xffd080c4>;
62 };
33 }; 63 };
34}; 64};
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
new file mode 100644
index 000000000000..1036eba40bbf
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -0,0 +1,64 @@
1/*
2 * Copyright (C) 2013 Altera Corporation <www.altera.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18/dts-v1/;
19/include/ "socfpga.dtsi"
20
21/ {
22 model = "Altera SOCFPGA VT";
23 compatible = "altr,socfpga-vt", "altr,socfpga";
24
25 chosen {
26 bootargs = "console=ttyS0,57600";
27 };
28
29 memory {
30 name = "memory";
31 device_type = "memory";
32 reg = <0x0 0x40000000>; /* 1 GB */
33 };
34
35 soc {
36 timer0@ffc08000 {
37 clock-frequency = <7000000>;
38 };
39
40 timer1@ffc09000 {
41 clock-frequency = <7000000>;
42 };
43
44 timer2@ffd00000 {
45 clock-frequency = <7000000>;
46 };
47
48 timer3@ffd01000 {
49 clock-frequency = <7000000>;
50 };
51
52 serial0@ffc02000 {
53 clock-frequency = <7372800>;
54 };
55
56 serial1@ffc03000 {
57 clock-frequency = <7372800>;
58 };
59
60 sysmgr@ffd08000 {
61 cpu1-start-addr = <0xffd08010>;
62 };
63 };
64};
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
new file mode 100644
index 000000000000..a30aca62658a
--- /dev/null
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -0,0 +1,21 @@
1/dts-v1/;
2
3/include/ "tegra114.dtsi"
4
5/ {
6 model = "NVIDIA Tegra114 Dalmore evaluation board";
7 compatible = "nvidia,dalmore", "nvidia,tegra114";
8
9 memory {
10 reg = <0x80000000 0x40000000>;
11 };
12
13 serial@70006300 {
14 status = "okay";
15 clock-frequency = <408000000>;
16 };
17
18 pmc {
19 nvidia,invert-interrupt;
20 };
21};
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts
new file mode 100644
index 000000000000..9bea8f57aa47
--- /dev/null
+++ b/arch/arm/boot/dts/tegra114-pluto.dts
@@ -0,0 +1,21 @@
1/dts-v1/;
2
3/include/ "tegra114.dtsi"
4
5/ {
6 model = "NVIDIA Tegra114 Pluto evaluation board";
7 compatible = "nvidia,pluto", "nvidia,tegra114";
8
9 memory {
10 reg = <0x80000000 0x40000000>;
11 };
12
13 serial@70006300 {
14 status = "okay";
15 clock-frequency = <408000000>;
16 };
17
18 pmc {
19 nvidia,invert-interrupt;
20 };
21};
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
new file mode 100644
index 000000000000..1dfaf2874c57
--- /dev/null
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -0,0 +1,153 @@
1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra114";
5 interrupt-parent = <&gic>;
6
7 gic: interrupt-controller {
8 compatible = "arm,cortex-a15-gic";
9 #interrupt-cells = <3>;
10 interrupt-controller;
11 reg = <0x50041000 0x1000>,
12 <0x50042000 0x1000>,
13 <0x50044000 0x2000>,
14 <0x50046000 0x2000>;
15 interrupts = <1 9 0xf04>;
16 };
17
18 timer@60005000 {
19 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
20 reg = <0x60005000 0x400>;
21 interrupts = <0 0 0x04
22 0 1 0x04
23 0 41 0x04
24 0 42 0x04
25 0 121 0x04
26 0 122 0x04>;
27 };
28
29 tegra_car: clock {
30 compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
31 reg = <0x60006000 0x1000>;
32 #clock-cells = <1>;
33 };
34
35 ahb: ahb {
36 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
37 reg = <0x6000c004 0x14c>;
38 };
39
40 gpio: gpio {
41 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
42 reg = <0x6000d000 0x1000>;
43 interrupts = <0 32 0x04
44 0 33 0x04
45 0 34 0x04
46 0 35 0x04
47 0 55 0x04
48 0 87 0x04
49 0 89 0x04
50 0 125 0x04>;
51 #gpio-cells = <2>;
52 gpio-controller;
53 #interrupt-cells = <2>;
54 interrupt-controller;
55 };
56
57 pinmux: pinmux {
58 compatible = "nvidia,tegra114-pinmux";
59 reg = <0x70000868 0x148 /* Pad control registers */
60 0x70003000 0x40c>; /* Mux registers */
61 };
62
63 serial@70006000 {
64 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
65 reg = <0x70006000 0x40>;
66 reg-shift = <2>;
67 interrupts = <0 36 0x04>;
68 status = "disabled";
69 };
70
71 serial@70006040 {
72 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
73 reg = <0x70006040 0x40>;
74 reg-shift = <2>;
75 interrupts = <0 37 0x04>;
76 status = "disabled";
77 };
78
79 serial@70006200 {
80 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
81 reg = <0x70006200 0x100>;
82 reg-shift = <2>;
83 interrupts = <0 46 0x04>;
84 status = "disabled";
85 };
86
87 serial@70006300 {
88 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
89 reg = <0x70006300 0x100>;
90 reg-shift = <2>;
91 interrupts = <0 90 0x04>;
92 status = "disabled";
93 };
94
95 rtc {
96 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
97 reg = <0x7000e000 0x100>;
98 interrupts = <0 2 0x04>;
99 };
100
101 pmc {
102 compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc";
103 reg = <0x7000e400 0x400>;
104 };
105
106 iommu {
107 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
108 reg = <0x7000f010 0x02c
109 0x7000f1f0 0x010
110 0x7000f228 0x074>;
111 nvidia,#asids = <4>;
112 dma-window = <0 0x40000000>;
113 nvidia,swgroups = <0x18659fe>;
114 nvidia,ahb = <&ahb>;
115 };
116
117 cpus {
118 #address-cells = <1>;
119 #size-cells = <0>;
120
121 cpu@0 {
122 device_type = "cpu";
123 compatible = "arm,cortex-a15";
124 reg = <0>;
125 };
126
127 cpu@1 {
128 device_type = "cpu";
129 compatible = "arm,cortex-a15";
130 reg = <1>;
131 };
132
133 cpu@2 {
134 device_type = "cpu";
135 compatible = "arm,cortex-a15";
136 reg = <2>;
137 };
138
139 cpu@3 {
140 device_type = "cpu";
141 compatible = "arm,cortex-a15";
142 reg = <3>;
143 };
144 };
145
146 timer {
147 compatible = "arm,armv7-timer";
148 interrupts = <1 13 0xf08>,
149 <1 14 0xf08>,
150 <1 11 0xf08>,
151 <1 10 0xf08>;
152 };
153};
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 43eb72af8948..2b4169702c8d 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -432,6 +432,10 @@
432 status = "okay"; 432 status = "okay";
433 }; 433 };
434 434
435 usb-phy@c5004400 {
436 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
437 };
438
435 sdhci@c8000200 { 439 sdhci@c8000200 {
436 status = "okay"; 440 status = "okay";
437 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 441 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 6a93d1404c76..11b30db63ff2 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -266,6 +266,8 @@
266 clock-frequency = <80000>; 266 clock-frequency = <80000>;
267 request-gpios = <&gpio 170 0>; /* gpio PV2 */ 267 request-gpios = <&gpio 170 0>; /* gpio PV2 */
268 slave-addr = <138>; 268 slave-addr = <138>;
269 clocks = <&tegra_car 67>, <&tegra_car 124>;
270 clock-names = "div-clk", "fast-clk";
269 }; 271 };
270 272
271 i2c@7000d000 { 273 i2c@7000d000 {
@@ -418,6 +420,10 @@
418 status = "okay"; 420 status = "okay";
419 }; 421 };
420 422
423 usb-phy@c5004400 {
424 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
425 };
426
421 sdhci@c8000000 { 427 sdhci@c8000000 {
422 status = "okay"; 428 status = "okay";
423 cd-gpios = <&gpio 173 0>; /* gpio PV5 */ 429 cd-gpios = <&gpio 173 0>; /* gpio PV5 */
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 420459825b46..607bf0c6bf9c 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -561,6 +561,10 @@
561 status = "okay"; 561 status = "okay";
562 }; 562 };
563 563
564 usb-phy@c5004400 {
565 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
566 };
567
564 sdhci@c8000000 { 568 sdhci@c8000000 {
565 status = "okay"; 569 status = "okay";
566 power-gpios = <&gpio 86 0>; /* gpio PK6 */ 570 power-gpios = <&gpio 86 0>; /* gpio PK6 */
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index b70b4cb754c8..e47cf6a58b6f 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -310,6 +310,10 @@
310 status = "okay"; 310 status = "okay";
311 }; 311 };
312 312
313 usb-phy@c5004400 {
314 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
315 };
316
313 sdhci@c8000000 { 317 sdhci@c8000000 {
314 status = "okay"; 318 status = "okay";
315 bus-width = <4>; 319 bus-width = <4>;
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index adc47547eaae..f6c61d10fd27 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -497,6 +497,10 @@
497 status = "okay"; 497 status = "okay";
498 }; 498 };
499 499
500 usb-phy@c5004400 {
501 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
502 };
503
500 sdhci@c8000000 { 504 sdhci@c8000000 {
501 status = "okay"; 505 status = "okay";
502 power-gpios = <&gpio 86 0>; /* gpio PK6 */ 506 power-gpios = <&gpio 86 0>; /* gpio PK6 */
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index b8effa1cbda7..2e7c83c7253b 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -9,6 +9,7 @@
9 reg = <0x50000000 0x00024000>; 9 reg = <0x50000000 0x00024000>;
10 interrupts = <0 65 0x04 /* mpcore syncpt */ 10 interrupts = <0 65 0x04 /* mpcore syncpt */
11 0 67 0x04>; /* mpcore general */ 11 0 67 0x04>; /* mpcore general */
12 clocks = <&tegra_car 28>;
12 13
13 #address-cells = <1>; 14 #address-cells = <1>;
14 #size-cells = <1>; 15 #size-cells = <1>;
@@ -19,41 +20,49 @@
19 compatible = "nvidia,tegra20-mpe"; 20 compatible = "nvidia,tegra20-mpe";
20 reg = <0x54040000 0x00040000>; 21 reg = <0x54040000 0x00040000>;
21 interrupts = <0 68 0x04>; 22 interrupts = <0 68 0x04>;
23 clocks = <&tegra_car 60>;
22 }; 24 };
23 25
24 vi { 26 vi {
25 compatible = "nvidia,tegra20-vi"; 27 compatible = "nvidia,tegra20-vi";
26 reg = <0x54080000 0x00040000>; 28 reg = <0x54080000 0x00040000>;
27 interrupts = <0 69 0x04>; 29 interrupts = <0 69 0x04>;
30 clocks = <&tegra_car 100>;
28 }; 31 };
29 32
30 epp { 33 epp {
31 compatible = "nvidia,tegra20-epp"; 34 compatible = "nvidia,tegra20-epp";
32 reg = <0x540c0000 0x00040000>; 35 reg = <0x540c0000 0x00040000>;
33 interrupts = <0 70 0x04>; 36 interrupts = <0 70 0x04>;
37 clocks = <&tegra_car 19>;
34 }; 38 };
35 39
36 isp { 40 isp {
37 compatible = "nvidia,tegra20-isp"; 41 compatible = "nvidia,tegra20-isp";
38 reg = <0x54100000 0x00040000>; 42 reg = <0x54100000 0x00040000>;
39 interrupts = <0 71 0x04>; 43 interrupts = <0 71 0x04>;
44 clocks = <&tegra_car 23>;
40 }; 45 };
41 46
42 gr2d { 47 gr2d {
43 compatible = "nvidia,tegra20-gr2d"; 48 compatible = "nvidia,tegra20-gr2d";
44 reg = <0x54140000 0x00040000>; 49 reg = <0x54140000 0x00040000>;
45 interrupts = <0 72 0x04>; 50 interrupts = <0 72 0x04>;
51 clocks = <&tegra_car 21>;
46 }; 52 };
47 53
48 gr3d { 54 gr3d {
49 compatible = "nvidia,tegra20-gr3d"; 55 compatible = "nvidia,tegra20-gr3d";
50 reg = <0x54180000 0x00040000>; 56 reg = <0x54180000 0x00040000>;
57 clocks = <&tegra_car 24>;
51 }; 58 };
52 59
53 dc@54200000 { 60 dc@54200000 {
54 compatible = "nvidia,tegra20-dc"; 61 compatible = "nvidia,tegra20-dc";
55 reg = <0x54200000 0x00040000>; 62 reg = <0x54200000 0x00040000>;
56 interrupts = <0 73 0x04>; 63 interrupts = <0 73 0x04>;
64 clocks = <&tegra_car 27>, <&tegra_car 121>;
65 clock-names = "disp1", "parent";
57 66
58 rgb { 67 rgb {
59 status = "disabled"; 68 status = "disabled";
@@ -64,6 +73,8 @@
64 compatible = "nvidia,tegra20-dc"; 73 compatible = "nvidia,tegra20-dc";
65 reg = <0x54240000 0x00040000>; 74 reg = <0x54240000 0x00040000>;
66 interrupts = <0 74 0x04>; 75 interrupts = <0 74 0x04>;
76 clocks = <&tegra_car 26>, <&tegra_car 121>;
77 clock-names = "disp2", "parent";
67 78
68 rgb { 79 rgb {
69 status = "disabled"; 80 status = "disabled";
@@ -74,6 +85,8 @@
74 compatible = "nvidia,tegra20-hdmi"; 85 compatible = "nvidia,tegra20-hdmi";
75 reg = <0x54280000 0x00040000>; 86 reg = <0x54280000 0x00040000>;
76 interrupts = <0 75 0x04>; 87 interrupts = <0 75 0x04>;
88 clocks = <&tegra_car 51>, <&tegra_car 117>;
89 clock-names = "hdmi", "parent";
77 status = "disabled"; 90 status = "disabled";
78 }; 91 };
79 92
@@ -81,12 +94,14 @@
81 compatible = "nvidia,tegra20-tvo"; 94 compatible = "nvidia,tegra20-tvo";
82 reg = <0x542c0000 0x00040000>; 95 reg = <0x542c0000 0x00040000>;
83 interrupts = <0 76 0x04>; 96 interrupts = <0 76 0x04>;
97 clocks = <&tegra_car 102>;
84 status = "disabled"; 98 status = "disabled";
85 }; 99 };
86 100
87 dsi { 101 dsi {
88 compatible = "nvidia,tegra20-dsi"; 102 compatible = "nvidia,tegra20-dsi";
89 reg = <0x54300000 0x00040000>; 103 reg = <0x54300000 0x00040000>;
104 clocks = <&tegra_car 48>;
90 status = "disabled"; 105 status = "disabled";
91 }; 106 };
92 }; 107 };
@@ -123,6 +138,12 @@
123 0 42 0x04>; 138 0 42 0x04>;
124 }; 139 };
125 140
141 tegra_car: clock {
142 compatible = "nvidia,tegra20-car";
143 reg = <0x60006000 0x1000>;
144 #clock-cells = <1>;
145 };
146
126 apbdma: dma { 147 apbdma: dma {
127 compatible = "nvidia,tegra20-apbdma"; 148 compatible = "nvidia,tegra20-apbdma";
128 reg = <0x6000a000 0x1200>; 149 reg = <0x6000a000 0x1200>;
@@ -142,6 +163,7 @@
142 0 117 0x04 163 0 117 0x04
143 0 118 0x04 164 0 118 0x04
144 0 119 0x04>; 165 0 119 0x04>;
166 clocks = <&tegra_car 34>;
145 }; 167 };
146 168
147 ahb { 169 ahb {
@@ -183,6 +205,7 @@
183 reg = <0x70002800 0x200>; 205 reg = <0x70002800 0x200>;
184 interrupts = <0 13 0x04>; 206 interrupts = <0 13 0x04>;
185 nvidia,dma-request-selector = <&apbdma 2>; 207 nvidia,dma-request-selector = <&apbdma 2>;
208 clocks = <&tegra_car 11>;
186 status = "disabled"; 209 status = "disabled";
187 }; 210 };
188 211
@@ -191,6 +214,7 @@
191 reg = <0x70002a00 0x200>; 214 reg = <0x70002a00 0x200>;
192 interrupts = <0 3 0x04>; 215 interrupts = <0 3 0x04>;
193 nvidia,dma-request-selector = <&apbdma 1>; 216 nvidia,dma-request-selector = <&apbdma 1>;
217 clocks = <&tegra_car 18>;
194 status = "disabled"; 218 status = "disabled";
195 }; 219 };
196 220
@@ -199,6 +223,7 @@
199 reg = <0x70006000 0x40>; 223 reg = <0x70006000 0x40>;
200 reg-shift = <2>; 224 reg-shift = <2>;
201 interrupts = <0 36 0x04>; 225 interrupts = <0 36 0x04>;
226 clocks = <&tegra_car 6>;
202 status = "disabled"; 227 status = "disabled";
203 }; 228 };
204 229
@@ -207,6 +232,7 @@
207 reg = <0x70006040 0x40>; 232 reg = <0x70006040 0x40>;
208 reg-shift = <2>; 233 reg-shift = <2>;
209 interrupts = <0 37 0x04>; 234 interrupts = <0 37 0x04>;
235 clocks = <&tegra_car 96>;
210 status = "disabled"; 236 status = "disabled";
211 }; 237 };
212 238
@@ -215,6 +241,7 @@
215 reg = <0x70006200 0x100>; 241 reg = <0x70006200 0x100>;
216 reg-shift = <2>; 242 reg-shift = <2>;
217 interrupts = <0 46 0x04>; 243 interrupts = <0 46 0x04>;
244 clocks = <&tegra_car 55>;
218 status = "disabled"; 245 status = "disabled";
219 }; 246 };
220 247
@@ -223,6 +250,7 @@
223 reg = <0x70006300 0x100>; 250 reg = <0x70006300 0x100>;
224 reg-shift = <2>; 251 reg-shift = <2>;
225 interrupts = <0 90 0x04>; 252 interrupts = <0 90 0x04>;
253 clocks = <&tegra_car 65>;
226 status = "disabled"; 254 status = "disabled";
227 }; 255 };
228 256
@@ -231,6 +259,7 @@
231 reg = <0x70006400 0x100>; 259 reg = <0x70006400 0x100>;
232 reg-shift = <2>; 260 reg-shift = <2>;
233 interrupts = <0 91 0x04>; 261 interrupts = <0 91 0x04>;
262 clocks = <&tegra_car 66>;
234 status = "disabled"; 263 status = "disabled";
235 }; 264 };
236 265
@@ -238,6 +267,7 @@
238 compatible = "nvidia,tegra20-pwm"; 267 compatible = "nvidia,tegra20-pwm";
239 reg = <0x7000a000 0x100>; 268 reg = <0x7000a000 0x100>;
240 #pwm-cells = <2>; 269 #pwm-cells = <2>;
270 clocks = <&tegra_car 17>;
241 }; 271 };
242 272
243 rtc { 273 rtc {
@@ -252,6 +282,8 @@
252 interrupts = <0 38 0x04>; 282 interrupts = <0 38 0x04>;
253 #address-cells = <1>; 283 #address-cells = <1>;
254 #size-cells = <0>; 284 #size-cells = <0>;
285 clocks = <&tegra_car 12>, <&tegra_car 124>;
286 clock-names = "div-clk", "fast-clk";
255 status = "disabled"; 287 status = "disabled";
256 }; 288 };
257 289
@@ -262,6 +294,7 @@
262 nvidia,dma-request-selector = <&apbdma 11>; 294 nvidia,dma-request-selector = <&apbdma 11>;
263 #address-cells = <1>; 295 #address-cells = <1>;
264 #size-cells = <0>; 296 #size-cells = <0>;
297 clocks = <&tegra_car 43>;
265 status = "disabled"; 298 status = "disabled";
266 }; 299 };
267 300
@@ -271,6 +304,8 @@
271 interrupts = <0 84 0x04>; 304 interrupts = <0 84 0x04>;
272 #address-cells = <1>; 305 #address-cells = <1>;
273 #size-cells = <0>; 306 #size-cells = <0>;
307 clocks = <&tegra_car 54>, <&tegra_car 124>;
308 clock-names = "div-clk", "fast-clk";
274 status = "disabled"; 309 status = "disabled";
275 }; 310 };
276 311
@@ -280,6 +315,8 @@
280 interrupts = <0 92 0x04>; 315 interrupts = <0 92 0x04>;
281 #address-cells = <1>; 316 #address-cells = <1>;
282 #size-cells = <0>; 317 #size-cells = <0>;
318 clocks = <&tegra_car 67>, <&tegra_car 124>;
319 clock-names = "div-clk", "fast-clk";
283 status = "disabled"; 320 status = "disabled";
284 }; 321 };
285 322
@@ -289,6 +326,8 @@
289 interrupts = <0 53 0x04>; 326 interrupts = <0 53 0x04>;
290 #address-cells = <1>; 327 #address-cells = <1>;
291 #size-cells = <0>; 328 #size-cells = <0>;
329 clocks = <&tegra_car 47>, <&tegra_car 124>;
330 clock-names = "div-clk", "fast-clk";
292 status = "disabled"; 331 status = "disabled";
293 }; 332 };
294 333
@@ -299,6 +338,7 @@
299 nvidia,dma-request-selector = <&apbdma 15>; 338 nvidia,dma-request-selector = <&apbdma 15>;
300 #address-cells = <1>; 339 #address-cells = <1>;
301 #size-cells = <0>; 340 #size-cells = <0>;
341 clocks = <&tegra_car 41>;
302 status = "disabled"; 342 status = "disabled";
303 }; 343 };
304 344
@@ -309,6 +349,7 @@
309 nvidia,dma-request-selector = <&apbdma 16>; 349 nvidia,dma-request-selector = <&apbdma 16>;
310 #address-cells = <1>; 350 #address-cells = <1>;
311 #size-cells = <0>; 351 #size-cells = <0>;
352 clocks = <&tegra_car 44>;
312 status = "disabled"; 353 status = "disabled";
313 }; 354 };
314 355
@@ -319,6 +360,7 @@
319 nvidia,dma-request-selector = <&apbdma 17>; 360 nvidia,dma-request-selector = <&apbdma 17>;
320 #address-cells = <1>; 361 #address-cells = <1>;
321 #size-cells = <0>; 362 #size-cells = <0>;
363 clocks = <&tegra_car 46>;
322 status = "disabled"; 364 status = "disabled";
323 }; 365 };
324 366
@@ -329,6 +371,7 @@
329 nvidia,dma-request-selector = <&apbdma 18>; 371 nvidia,dma-request-selector = <&apbdma 18>;
330 #address-cells = <1>; 372 #address-cells = <1>;
331 #size-cells = <0>; 373 #size-cells = <0>;
374 clocks = <&tegra_car 68>;
332 status = "disabled"; 375 status = "disabled";
333 }; 376 };
334 377
@@ -357,12 +400,40 @@
357 #size-cells = <0>; 400 #size-cells = <0>;
358 }; 401 };
359 402
403 phy1: usb-phy@c5000400 {
404 compatible = "nvidia,tegra20-usb-phy";
405 reg = <0xc5000400 0x3c00>;
406 phy_type = "utmi";
407 nvidia,has-legacy-mode;
408 clocks = <&tegra_car 22>, <&tegra_car 127>;
409 clock-names = "phy", "pll_u";
410 };
411
412 phy2: usb-phy@c5004400 {
413 compatible = "nvidia,tegra20-usb-phy";
414 reg = <0xc5004400 0x3c00>;
415 phy_type = "ulpi";
416 clocks = <&tegra_car 94>, <&tegra_car 127>;
417 clock-names = "phy", "pll_u";
418 };
419
420 phy3: usb-phy@c5008400 {
421 compatible = "nvidia,tegra20-usb-phy";
422 reg = <0xc5008400 0x3C00>;
423 phy_type = "utmi";
424 clocks = <&tegra_car 22>, <&tegra_car 127>;
425 clock-names = "phy", "pll_u";
426 };
427
360 usb@c5000000 { 428 usb@c5000000 {
361 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 429 compatible = "nvidia,tegra20-ehci", "usb-ehci";
362 reg = <0xc5000000 0x4000>; 430 reg = <0xc5000000 0x4000>;
363 interrupts = <0 20 0x04>; 431 interrupts = <0 20 0x04>;
364 phy_type = "utmi"; 432 phy_type = "utmi";
365 nvidia,has-legacy-mode; 433 nvidia,has-legacy-mode;
434 clocks = <&tegra_car 22>;
435 nvidia,needs-double-reset;
436 nvidia,phy = <&phy1>;
366 status = "disabled"; 437 status = "disabled";
367 }; 438 };
368 439
@@ -371,6 +442,8 @@
371 reg = <0xc5004000 0x4000>; 442 reg = <0xc5004000 0x4000>;
372 interrupts = <0 21 0x04>; 443 interrupts = <0 21 0x04>;
373 phy_type = "ulpi"; 444 phy_type = "ulpi";
445 clocks = <&tegra_car 58>;
446 nvidia,phy = <&phy2>;
374 status = "disabled"; 447 status = "disabled";
375 }; 448 };
376 449
@@ -379,6 +452,8 @@
379 reg = <0xc5008000 0x4000>; 452 reg = <0xc5008000 0x4000>;
380 interrupts = <0 97 0x04>; 453 interrupts = <0 97 0x04>;
381 phy_type = "utmi"; 454 phy_type = "utmi";
455 clocks = <&tegra_car 59>;
456 nvidia,phy = <&phy3>;
382 status = "disabled"; 457 status = "disabled";
383 }; 458 };
384 459
@@ -386,6 +461,7 @@
386 compatible = "nvidia,tegra20-sdhci"; 461 compatible = "nvidia,tegra20-sdhci";
387 reg = <0xc8000000 0x200>; 462 reg = <0xc8000000 0x200>;
388 interrupts = <0 14 0x04>; 463 interrupts = <0 14 0x04>;
464 clocks = <&tegra_car 14>;
389 status = "disabled"; 465 status = "disabled";
390 }; 466 };
391 467
@@ -393,6 +469,7 @@
393 compatible = "nvidia,tegra20-sdhci"; 469 compatible = "nvidia,tegra20-sdhci";
394 reg = <0xc8000200 0x200>; 470 reg = <0xc8000200 0x200>;
395 interrupts = <0 15 0x04>; 471 interrupts = <0 15 0x04>;
472 clocks = <&tegra_car 9>;
396 status = "disabled"; 473 status = "disabled";
397 }; 474 };
398 475
@@ -400,6 +477,7 @@
400 compatible = "nvidia,tegra20-sdhci"; 477 compatible = "nvidia,tegra20-sdhci";
401 reg = <0xc8000400 0x200>; 478 reg = <0xc8000400 0x200>;
402 interrupts = <0 19 0x04>; 479 interrupts = <0 19 0x04>;
480 clocks = <&tegra_car 69>;
403 status = "disabled"; 481 status = "disabled";
404 }; 482 };
405 483
@@ -407,9 +485,27 @@
407 compatible = "nvidia,tegra20-sdhci"; 485 compatible = "nvidia,tegra20-sdhci";
408 reg = <0xc8000600 0x200>; 486 reg = <0xc8000600 0x200>;
409 interrupts = <0 31 0x04>; 487 interrupts = <0 31 0x04>;
488 clocks = <&tegra_car 15>;
410 status = "disabled"; 489 status = "disabled";
411 }; 490 };
412 491
492 cpus {
493 #address-cells = <1>;
494 #size-cells = <0>;
495
496 cpu@0 {
497 device_type = "cpu";
498 compatible = "arm,cortex-a9";
499 reg = <0>;
500 };
501
502 cpu@1 {
503 device_type = "cpu";
504 compatible = "arm,cortex-a9";
505 reg = <1>;
506 };
507 };
508
413 pmu { 509 pmu {
414 compatible = "arm,cortex-a9-pmu"; 510 compatible = "arm,cortex-a9-pmu";
415 interrupts = <0 56 0x04 511 interrupts = <0 56 0x04
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 529fdb82dfdb..2de8b919d78c 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -9,6 +9,7 @@
9 reg = <0x50000000 0x00024000>; 9 reg = <0x50000000 0x00024000>;
10 interrupts = <0 65 0x04 /* mpcore syncpt */ 10 interrupts = <0 65 0x04 /* mpcore syncpt */
11 0 67 0x04>; /* mpcore general */ 11 0 67 0x04>; /* mpcore general */
12 clocks = <&tegra_car 28>;
12 13
13 #address-cells = <1>; 14 #address-cells = <1>;
14 #size-cells = <1>; 15 #size-cells = <1>;
@@ -19,41 +20,50 @@
19 compatible = "nvidia,tegra30-mpe"; 20 compatible = "nvidia,tegra30-mpe";
20 reg = <0x54040000 0x00040000>; 21 reg = <0x54040000 0x00040000>;
21 interrupts = <0 68 0x04>; 22 interrupts = <0 68 0x04>;
23 clocks = <&tegra_car 60>;
22 }; 24 };
23 25
24 vi { 26 vi {
25 compatible = "nvidia,tegra30-vi"; 27 compatible = "nvidia,tegra30-vi";
26 reg = <0x54080000 0x00040000>; 28 reg = <0x54080000 0x00040000>;
27 interrupts = <0 69 0x04>; 29 interrupts = <0 69 0x04>;
30 clocks = <&tegra_car 164>;
28 }; 31 };
29 32
30 epp { 33 epp {
31 compatible = "nvidia,tegra30-epp"; 34 compatible = "nvidia,tegra30-epp";
32 reg = <0x540c0000 0x00040000>; 35 reg = <0x540c0000 0x00040000>;
33 interrupts = <0 70 0x04>; 36 interrupts = <0 70 0x04>;
37 clocks = <&tegra_car 19>;
34 }; 38 };
35 39
36 isp { 40 isp {
37 compatible = "nvidia,tegra30-isp"; 41 compatible = "nvidia,tegra30-isp";
38 reg = <0x54100000 0x00040000>; 42 reg = <0x54100000 0x00040000>;
39 interrupts = <0 71 0x04>; 43 interrupts = <0 71 0x04>;
44 clocks = <&tegra_car 23>;
40 }; 45 };
41 46
42 gr2d { 47 gr2d {
43 compatible = "nvidia,tegra30-gr2d"; 48 compatible = "nvidia,tegra30-gr2d";
44 reg = <0x54140000 0x00040000>; 49 reg = <0x54140000 0x00040000>;
45 interrupts = <0 72 0x04>; 50 interrupts = <0 72 0x04>;
51 clocks = <&tegra_car 21>;
46 }; 52 };
47 53
48 gr3d { 54 gr3d {
49 compatible = "nvidia,tegra30-gr3d"; 55 compatible = "nvidia,tegra30-gr3d";
50 reg = <0x54180000 0x00040000>; 56 reg = <0x54180000 0x00040000>;
57 clocks = <&tegra_car 24 &tegra_car 98>;
58 clock-names = "3d", "3d2";
51 }; 59 };
52 60
53 dc@54200000 { 61 dc@54200000 {
54 compatible = "nvidia,tegra30-dc"; 62 compatible = "nvidia,tegra30-dc";
55 reg = <0x54200000 0x00040000>; 63 reg = <0x54200000 0x00040000>;
56 interrupts = <0 73 0x04>; 64 interrupts = <0 73 0x04>;
65 clocks = <&tegra_car 27>, <&tegra_car 179>;
66 clock-names = "disp1", "parent";
57 67
58 rgb { 68 rgb {
59 status = "disabled"; 69 status = "disabled";
@@ -64,6 +74,8 @@
64 compatible = "nvidia,tegra30-dc"; 74 compatible = "nvidia,tegra30-dc";
65 reg = <0x54240000 0x00040000>; 75 reg = <0x54240000 0x00040000>;
66 interrupts = <0 74 0x04>; 76 interrupts = <0 74 0x04>;
77 clocks = <&tegra_car 26>, <&tegra_car 179>;
78 clock-names = "disp2", "parent";
67 79
68 rgb { 80 rgb {
69 status = "disabled"; 81 status = "disabled";
@@ -74,6 +86,8 @@
74 compatible = "nvidia,tegra30-hdmi"; 86 compatible = "nvidia,tegra30-hdmi";
75 reg = <0x54280000 0x00040000>; 87 reg = <0x54280000 0x00040000>;
76 interrupts = <0 75 0x04>; 88 interrupts = <0 75 0x04>;
89 clocks = <&tegra_car 51>, <&tegra_car 189>;
90 clock-names = "hdmi", "parent";
77 status = "disabled"; 91 status = "disabled";
78 }; 92 };
79 93
@@ -81,12 +95,14 @@
81 compatible = "nvidia,tegra30-tvo"; 95 compatible = "nvidia,tegra30-tvo";
82 reg = <0x542c0000 0x00040000>; 96 reg = <0x542c0000 0x00040000>;
83 interrupts = <0 76 0x04>; 97 interrupts = <0 76 0x04>;
98 clocks = <&tegra_car 169>;
84 status = "disabled"; 99 status = "disabled";
85 }; 100 };
86 101
87 dsi { 102 dsi {
88 compatible = "nvidia,tegra30-dsi"; 103 compatible = "nvidia,tegra30-dsi";
89 reg = <0x54300000 0x00040000>; 104 reg = <0x54300000 0x00040000>;
105 clocks = <&tegra_car 48>;
90 status = "disabled"; 106 status = "disabled";
91 }; 107 };
92 }; 108 };
@@ -125,6 +141,12 @@
125 0 122 0x04>; 141 0 122 0x04>;
126 }; 142 };
127 143
144 tegra_car: clock {
145 compatible = "nvidia,tegra30-car";
146 reg = <0x60006000 0x1000>;
147 #clock-cells = <1>;
148 };
149
128 apbdma: dma { 150 apbdma: dma {
129 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 151 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
130 reg = <0x6000a000 0x1400>; 152 reg = <0x6000a000 0x1400>;
@@ -160,6 +182,7 @@
160 0 141 0x04 182 0 141 0x04
161 0 142 0x04 183 0 142 0x04
162 0 143 0x04>; 184 0 143 0x04>;
185 clocks = <&tegra_car 34>;
163 }; 186 };
164 187
165 ahb: ahb { 188 ahb: ahb {
@@ -195,6 +218,7 @@
195 reg = <0x70006000 0x40>; 218 reg = <0x70006000 0x40>;
196 reg-shift = <2>; 219 reg-shift = <2>;
197 interrupts = <0 36 0x04>; 220 interrupts = <0 36 0x04>;
221 clocks = <&tegra_car 6>;
198 status = "disabled"; 222 status = "disabled";
199 }; 223 };
200 224
@@ -203,6 +227,7 @@
203 reg = <0x70006040 0x40>; 227 reg = <0x70006040 0x40>;
204 reg-shift = <2>; 228 reg-shift = <2>;
205 interrupts = <0 37 0x04>; 229 interrupts = <0 37 0x04>;
230 clocks = <&tegra_car 160>;
206 status = "disabled"; 231 status = "disabled";
207 }; 232 };
208 233
@@ -211,6 +236,7 @@
211 reg = <0x70006200 0x100>; 236 reg = <0x70006200 0x100>;
212 reg-shift = <2>; 237 reg-shift = <2>;
213 interrupts = <0 46 0x04>; 238 interrupts = <0 46 0x04>;
239 clocks = <&tegra_car 55>;
214 status = "disabled"; 240 status = "disabled";
215 }; 241 };
216 242
@@ -219,6 +245,7 @@
219 reg = <0x70006300 0x100>; 245 reg = <0x70006300 0x100>;
220 reg-shift = <2>; 246 reg-shift = <2>;
221 interrupts = <0 90 0x04>; 247 interrupts = <0 90 0x04>;
248 clocks = <&tegra_car 65>;
222 status = "disabled"; 249 status = "disabled";
223 }; 250 };
224 251
@@ -227,6 +254,7 @@
227 reg = <0x70006400 0x100>; 254 reg = <0x70006400 0x100>;
228 reg-shift = <2>; 255 reg-shift = <2>;
229 interrupts = <0 91 0x04>; 256 interrupts = <0 91 0x04>;
257 clocks = <&tegra_car 66>;
230 status = "disabled"; 258 status = "disabled";
231 }; 259 };
232 260
@@ -234,6 +262,7 @@
234 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; 262 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
235 reg = <0x7000a000 0x100>; 263 reg = <0x7000a000 0x100>;
236 #pwm-cells = <2>; 264 #pwm-cells = <2>;
265 clocks = <&tegra_car 17>;
237 }; 266 };
238 267
239 rtc { 268 rtc {
@@ -248,6 +277,8 @@
248 interrupts = <0 38 0x04>; 277 interrupts = <0 38 0x04>;
249 #address-cells = <1>; 278 #address-cells = <1>;
250 #size-cells = <0>; 279 #size-cells = <0>;
280 clocks = <&tegra_car 12>, <&tegra_car 182>;
281 clock-names = "div-clk", "fast-clk";
251 status = "disabled"; 282 status = "disabled";
252 }; 283 };
253 284
@@ -257,6 +288,8 @@
257 interrupts = <0 84 0x04>; 288 interrupts = <0 84 0x04>;
258 #address-cells = <1>; 289 #address-cells = <1>;
259 #size-cells = <0>; 290 #size-cells = <0>;
291 clocks = <&tegra_car 54>, <&tegra_car 182>;
292 clock-names = "div-clk", "fast-clk";
260 status = "disabled"; 293 status = "disabled";
261 }; 294 };
262 295
@@ -266,6 +299,8 @@
266 interrupts = <0 92 0x04>; 299 interrupts = <0 92 0x04>;
267 #address-cells = <1>; 300 #address-cells = <1>;
268 #size-cells = <0>; 301 #size-cells = <0>;
302 clocks = <&tegra_car 67>, <&tegra_car 182>;
303 clock-names = "div-clk", "fast-clk";
269 status = "disabled"; 304 status = "disabled";
270 }; 305 };
271 306
@@ -275,6 +310,8 @@
275 interrupts = <0 120 0x04>; 310 interrupts = <0 120 0x04>;
276 #address-cells = <1>; 311 #address-cells = <1>;
277 #size-cells = <0>; 312 #size-cells = <0>;
313 clocks = <&tegra_car 103>, <&tegra_car 182>;
314 clock-names = "div-clk", "fast-clk";
278 status = "disabled"; 315 status = "disabled";
279 }; 316 };
280 317
@@ -284,6 +321,8 @@
284 interrupts = <0 53 0x04>; 321 interrupts = <0 53 0x04>;
285 #address-cells = <1>; 322 #address-cells = <1>;
286 #size-cells = <0>; 323 #size-cells = <0>;
324 clocks = <&tegra_car 47>, <&tegra_car 182>;
325 clock-names = "div-clk", "fast-clk";
287 status = "disabled"; 326 status = "disabled";
288 }; 327 };
289 328
@@ -294,6 +333,7 @@
294 nvidia,dma-request-selector = <&apbdma 15>; 333 nvidia,dma-request-selector = <&apbdma 15>;
295 #address-cells = <1>; 334 #address-cells = <1>;
296 #size-cells = <0>; 335 #size-cells = <0>;
336 clocks = <&tegra_car 41>;
297 status = "disabled"; 337 status = "disabled";
298 }; 338 };
299 339
@@ -304,6 +344,7 @@
304 nvidia,dma-request-selector = <&apbdma 16>; 344 nvidia,dma-request-selector = <&apbdma 16>;
305 #address-cells = <1>; 345 #address-cells = <1>;
306 #size-cells = <0>; 346 #size-cells = <0>;
347 clocks = <&tegra_car 44>;
307 status = "disabled"; 348 status = "disabled";
308 }; 349 };
309 350
@@ -314,6 +355,7 @@
314 nvidia,dma-request-selector = <&apbdma 17>; 355 nvidia,dma-request-selector = <&apbdma 17>;
315 #address-cells = <1>; 356 #address-cells = <1>;
316 #size-cells = <0>; 357 #size-cells = <0>;
358 clocks = <&tegra_car 46>;
317 status = "disabled"; 359 status = "disabled";
318 }; 360 };
319 361
@@ -324,6 +366,7 @@
324 nvidia,dma-request-selector = <&apbdma 18>; 366 nvidia,dma-request-selector = <&apbdma 18>;
325 #address-cells = <1>; 367 #address-cells = <1>;
326 #size-cells = <0>; 368 #size-cells = <0>;
369 clocks = <&tegra_car 68>;
327 status = "disabled"; 370 status = "disabled";
328 }; 371 };
329 372
@@ -334,6 +377,7 @@
334 nvidia,dma-request-selector = <&apbdma 27>; 377 nvidia,dma-request-selector = <&apbdma 27>;
335 #address-cells = <1>; 378 #address-cells = <1>;
336 #size-cells = <0>; 379 #size-cells = <0>;
380 clocks = <&tegra_car 104>;
337 status = "disabled"; 381 status = "disabled";
338 }; 382 };
339 383
@@ -344,6 +388,7 @@
344 nvidia,dma-request-selector = <&apbdma 28>; 388 nvidia,dma-request-selector = <&apbdma 28>;
345 #address-cells = <1>; 389 #address-cells = <1>;
346 #size-cells = <0>; 390 #size-cells = <0>;
391 clocks = <&tegra_car 105>;
347 status = "disabled"; 392 status = "disabled";
348 }; 393 };
349 394
@@ -377,7 +422,13 @@
377 0x70080200 0x100>; 422 0x70080200 0x100>;
378 interrupts = <0 103 0x04>; 423 interrupts = <0 103 0x04>;
379 nvidia,dma-request-selector = <&apbdma 1>; 424 nvidia,dma-request-selector = <&apbdma 1>;
380 425 clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
426 <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
427 <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
428 <&tegra_car 110>, <&tegra_car 162>;
429 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
430 "i2s3", "i2s4", "dam0", "dam1", "dam2",
431 "spdif_in";
381 ranges; 432 ranges;
382 #address-cells = <1>; 433 #address-cells = <1>;
383 #size-cells = <1>; 434 #size-cells = <1>;
@@ -386,6 +437,7 @@
386 compatible = "nvidia,tegra30-i2s"; 437 compatible = "nvidia,tegra30-i2s";
387 reg = <0x70080300 0x100>; 438 reg = <0x70080300 0x100>;
388 nvidia,ahub-cif-ids = <4 4>; 439 nvidia,ahub-cif-ids = <4 4>;
440 clocks = <&tegra_car 30>;
389 status = "disabled"; 441 status = "disabled";
390 }; 442 };
391 443
@@ -393,6 +445,7 @@
393 compatible = "nvidia,tegra30-i2s"; 445 compatible = "nvidia,tegra30-i2s";
394 reg = <0x70080400 0x100>; 446 reg = <0x70080400 0x100>;
395 nvidia,ahub-cif-ids = <5 5>; 447 nvidia,ahub-cif-ids = <5 5>;
448 clocks = <&tegra_car 11>;
396 status = "disabled"; 449 status = "disabled";
397 }; 450 };
398 451
@@ -400,6 +453,7 @@
400 compatible = "nvidia,tegra30-i2s"; 453 compatible = "nvidia,tegra30-i2s";
401 reg = <0x70080500 0x100>; 454 reg = <0x70080500 0x100>;
402 nvidia,ahub-cif-ids = <6 6>; 455 nvidia,ahub-cif-ids = <6 6>;
456 clocks = <&tegra_car 18>;
403 status = "disabled"; 457 status = "disabled";
404 }; 458 };
405 459
@@ -407,6 +461,7 @@
407 compatible = "nvidia,tegra30-i2s"; 461 compatible = "nvidia,tegra30-i2s";
408 reg = <0x70080600 0x100>; 462 reg = <0x70080600 0x100>;
409 nvidia,ahub-cif-ids = <7 7>; 463 nvidia,ahub-cif-ids = <7 7>;
464 clocks = <&tegra_car 101>;
410 status = "disabled"; 465 status = "disabled";
411 }; 466 };
412 467
@@ -414,6 +469,7 @@
414 compatible = "nvidia,tegra30-i2s"; 469 compatible = "nvidia,tegra30-i2s";
415 reg = <0x70080700 0x100>; 470 reg = <0x70080700 0x100>;
416 nvidia,ahub-cif-ids = <8 8>; 471 nvidia,ahub-cif-ids = <8 8>;
472 clocks = <&tegra_car 102>;
417 status = "disabled"; 473 status = "disabled";
418 }; 474 };
419 }; 475 };
@@ -422,6 +478,7 @@
422 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 478 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
423 reg = <0x78000000 0x200>; 479 reg = <0x78000000 0x200>;
424 interrupts = <0 14 0x04>; 480 interrupts = <0 14 0x04>;
481 clocks = <&tegra_car 14>;
425 status = "disabled"; 482 status = "disabled";
426 }; 483 };
427 484
@@ -429,6 +486,7 @@
429 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 486 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
430 reg = <0x78000200 0x200>; 487 reg = <0x78000200 0x200>;
431 interrupts = <0 15 0x04>; 488 interrupts = <0 15 0x04>;
489 clocks = <&tegra_car 9>;
432 status = "disabled"; 490 status = "disabled";
433 }; 491 };
434 492
@@ -436,6 +494,7 @@
436 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 494 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
437 reg = <0x78000400 0x200>; 495 reg = <0x78000400 0x200>;
438 interrupts = <0 19 0x04>; 496 interrupts = <0 19 0x04>;
497 clocks = <&tegra_car 69>;
439 status = "disabled"; 498 status = "disabled";
440 }; 499 };
441 500
@@ -443,9 +502,39 @@
443 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 502 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
444 reg = <0x78000600 0x200>; 503 reg = <0x78000600 0x200>;
445 interrupts = <0 31 0x04>; 504 interrupts = <0 31 0x04>;
505 clocks = <&tegra_car 15>;
446 status = "disabled"; 506 status = "disabled";
447 }; 507 };
448 508
509 cpus {
510 #address-cells = <1>;
511 #size-cells = <0>;
512
513 cpu@0 {
514 device_type = "cpu";
515 compatible = "arm,cortex-a9";
516 reg = <0>;
517 };
518
519 cpu@1 {
520 device_type = "cpu";
521 compatible = "arm,cortex-a9";
522 reg = <1>;
523 };
524
525 cpu@2 {
526 device_type = "cpu";
527 compatible = "arm,cortex-a9";
528 reg = <2>;
529 };
530
531 cpu@3 {
532 device_type = "cpu";
533 compatible = "arm,cortex-a9";
534 reg = <3>;
535 };
536 };
537
449 pmu { 538 pmu {
450 compatible = "arm,cortex-a9-pmu"; 539 compatible = "arm,cortex-a9-pmu";
451 interrupts = <0 144 0x04 540 interrupts = <0 144 0x04
diff --git a/arch/arm/boot/dts/wm8850-w70v2.dts b/arch/arm/boot/dts/wm8850-w70v2.dts
new file mode 100644
index 000000000000..fcc660c89540
--- /dev/null
+++ b/arch/arm/boot/dts/wm8850-w70v2.dts
@@ -0,0 +1,47 @@
1/*
2 * wm8850-w70v2.dts
3 * - Device tree file for Wondermedia WM8850 Tablet
4 * - 'W70-V2' mainboard
5 * - HongLianYing 'HLY070ML268-21A' 7" LCD panel
6 *
7 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
8 *
9 * Licensed under GPLv2 or later
10 */
11
12/dts-v1/;
13/include/ "wm8850.dtsi"
14
15/ {
16 model = "Wondermedia WM8850-W70v2 Tablet";
17
18 /*
19 * Display node is based on Sascha Hauer's patch on dri-devel.
20 * Added a bpp property to calculate the size of the framebuffer
21 * until the binding is formalized.
22 */
23 display: display@0 {
24 modes {
25 mode0: mode@0 {
26 hactive = <800>;
27 vactive = <480>;
28 hback-porch = <88>;
29 hfront-porch = <40>;
30 hsync-len = <0>;
31 vback-porch = <32>;
32 vfront-porch = <11>;
33 vsync-len = <1>;
34 clock = <0>; /* unused but required */
35 bpp = <16>; /* non-standard but required */
36 };
37 };
38 };
39
40 backlight {
41 compatible = "pwm-backlight";
42 pwms = <&pwm 0 50000 1>; /* duty inverted */
43
44 brightness-levels = <0 40 60 80 100 130 190 255>;
45 default-brightness-level = <5>;
46 };
47};
diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi
new file mode 100644
index 000000000000..e8cbfdc87bba
--- /dev/null
+++ b/arch/arm/boot/dts/wm8850.dtsi
@@ -0,0 +1,224 @@
1/*
2 * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 compatible = "wm,wm8850";
13
14 aliases {
15 serial0 = &uart0;
16 serial1 = &uart1;
17 serial2 = &uart2;
18 serial3 = &uart3;
19 };
20
21 soc {
22 #address-cells = <1>;
23 #size-cells = <1>;
24 compatible = "simple-bus";
25 ranges;
26 interrupt-parent = <&intc0>;
27
28 intc0: interrupt-controller@d8140000 {
29 compatible = "via,vt8500-intc";
30 interrupt-controller;
31 reg = <0xd8140000 0x10000>;
32 #interrupt-cells = <1>;
33 };
34
35 /* Secondary IC cascaded to intc0 */
36 intc1: interrupt-controller@d8150000 {
37 compatible = "via,vt8500-intc";
38 interrupt-controller;
39 #interrupt-cells = <1>;
40 reg = <0xD8150000 0x10000>;
41 interrupts = <56 57 58 59 60 61 62 63>;
42 };
43
44 gpio: gpio-controller@d8110000 {
45 compatible = "wm,wm8650-gpio";
46 gpio-controller;
47 reg = <0xd8110000 0x10000>;
48 #gpio-cells = <3>;
49 };
50
51 pmc@d8130000 {
52 compatible = "via,vt8500-pmc";
53 reg = <0xd8130000 0x1000>;
54
55 clocks {
56 #address-cells = <1>;
57 #size-cells = <0>;
58
59 ref25: ref25M {
60 #clock-cells = <0>;
61 compatible = "fixed-clock";
62 clock-frequency = <25000000>;
63 };
64
65 ref24: ref24M {
66 #clock-cells = <0>;
67 compatible = "fixed-clock";
68 clock-frequency = <24000000>;
69 };
70
71 plla: plla {
72 #clock-cells = <0>;
73 compatible = "wm,wm8750-pll-clock";
74 clocks = <&ref25>;
75 reg = <0x200>;
76 };
77
78 pllb: pllb {
79 #clock-cells = <0>;
80 compatible = "wm,wm8750-pll-clock";
81 clocks = <&ref25>;
82 reg = <0x204>;
83 };
84
85 clkuart0: uart0 {
86 #clock-cells = <0>;
87 compatible = "via,vt8500-device-clock";
88 clocks = <&ref24>;
89 enable-reg = <0x254>;
90 enable-bit = <24>;
91 };
92
93 clkuart1: uart1 {
94 #clock-cells = <0>;
95 compatible = "via,vt8500-device-clock";
96 clocks = <&ref24>;
97 enable-reg = <0x254>;
98 enable-bit = <25>;
99 };
100
101 clkuart2: uart2 {
102 #clock-cells = <0>;
103 compatible = "via,vt8500-device-clock";
104 clocks = <&ref24>;
105 enable-reg = <0x254>;
106 enable-bit = <26>;
107 };
108
109 clkuart3: uart3 {
110 #clock-cells = <0>;
111 compatible = "via,vt8500-device-clock";
112 clocks = <&ref24>;
113 enable-reg = <0x254>;
114 enable-bit = <27>;
115 };
116
117 clkpwm: pwm {
118 #clock-cells = <0>;
119 compatible = "via,vt8500-device-clock";
120 clocks = <&pllb>;
121 divisor-reg = <0x350>;
122 enable-reg = <0x250>;
123 enable-bit = <17>;
124 };
125
126 clksdhc: sdhc {
127 #clock-cells = <0>;
128 compatible = "via,vt8500-device-clock";
129 clocks = <&pllb>;
130 divisor-reg = <0x330>;
131 divisor-mask = <0x3f>;
132 enable-reg = <0x250>;
133 enable-bit = <0>;
134 };
135 };
136 };
137
138 fb@d8051700 {
139 compatible = "wm,wm8505-fb";
140 reg = <0xd8051700 0x200>;
141 display = <&display>;
142 default-mode = <&mode0>;
143 };
144
145 ge_rops@d8050400 {
146 compatible = "wm,prizm-ge-rops";
147 reg = <0xd8050400 0x100>;
148 };
149
150 pwm: pwm@d8220000 {
151 #pwm-cells = <3>;
152 compatible = "via,vt8500-pwm";
153 reg = <0xd8220000 0x100>;
154 clocks = <&clkpwm>;
155 };
156
157 timer@d8130100 {
158 compatible = "via,vt8500-timer";
159 reg = <0xd8130100 0x28>;
160 interrupts = <36>;
161 };
162
163 ehci@d8007900 {
164 compatible = "via,vt8500-ehci";
165 reg = <0xd8007900 0x200>;
166 interrupts = <26>;
167 };
168
169 uhci@d8007b00 {
170 compatible = "platform-uhci";
171 reg = <0xd8007b00 0x200>;
172 interrupts = <26>;
173 };
174
175 uhci@d8008d00 {
176 compatible = "platform-uhci";
177 reg = <0xd8008d00 0x200>;
178 interrupts = <26>;
179 };
180
181 uart0: uart@d8200000 {
182 compatible = "via,vt8500-uart";
183 reg = <0xd8200000 0x1040>;
184 interrupts = <32>;
185 clocks = <&clkuart0>;
186 };
187
188 uart1: uart@d82b0000 {
189 compatible = "via,vt8500-uart";
190 reg = <0xd82b0000 0x1040>;
191 interrupts = <33>;
192 clocks = <&clkuart1>;
193 };
194
195 uart2: uart@d8210000 {
196 compatible = "via,vt8500-uart";
197 reg = <0xd8210000 0x1040>;
198 interrupts = <47>;
199 clocks = <&clkuart2>;
200 };
201
202 uart3: uart@d82c0000 {
203 compatible = "via,vt8500-uart";
204 reg = <0xd82c0000 0x1040>;
205 interrupts = <50>;
206 clocks = <&clkuart3>;
207 };
208
209 rtc@d8100000 {
210 compatible = "via,vt8500-rtc";
211 reg = <0xd8100000 0x10000>;
212 interrupts = <48>;
213 };
214
215 sdhc@d800a000 {
216 compatible = "wm,wm8505-sdhc";
217 reg = <0xd800a000 0x1000>;
218 interrupts = <20 21>;
219 clocks = <&clksdhc>;
220 bus-width = <4>;
221 sdon-inverted;
222 };
223 };
224};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 01:03:35 -0500