aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/Makefile6
-rw-r--r--arch/arm/boot/dts/armada-370-db.dts5
-rw-r--r--arch/arm/boot/dts/armada-370-mirabox.dts37
-rw-r--r--arch/arm/boot/dts/armada-370-netgear-rn102.dts179
-rw-r--r--arch/arm/boot/dts/armada-370-rd.dts37
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi113
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi123
-rw-r--r--arch/arm/boot/dts/armada-xp-axpwifiap.dts164
-rw-r--r--arch/arm/boot/dts/armada-xp-db.dts131
-rw-r--r--arch/arm/boot/dts/armada-xp-gp.dts107
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78230.dtsi228
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78260.dtsi269
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78460.dtsi417
-rw-r--r--arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts88
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi11
-rw-r--r--arch/arm/boot/dts/da850-evm.dts11
-rw-r--r--arch/arm/boot/dts/da850.dtsi46
-rw-r--r--arch/arm/boot/dts/imx25.dtsi35
-rw-r--r--arch/arm/boot/dts/imx27-apf27dev.dts5
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts93
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts44
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts13
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore-som.dts125
-rw-r--r--arch/arm/boot/dts/imx27.dtsi120
-rw-r--r--arch/arm/boot/dts/imx31.dtsi17
-rw-r--r--arch/arm/boot/dts/imx51-apf51.dts4
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts5
-rw-r--r--arch/arm/boot/dts/imx51.dtsi632
-rw-r--r--arch/arm/boot/dts/imx53-qsb.dts18
-rw-r--r--arch/arm/boot/dts/imx53.dtsi56
-rw-r--r--arch/arm/boot/dts/imx6dl-pinfunc.h2138
-rw-r--r--arch/arm/boot/dts/imx6dl-sabreauto.dts22
-rw-r--r--arch/arm/boot/dts/imx6dl-sabresd.dts19
-rw-r--r--arch/arm/boot/dts/imx6dl-wandboard.dts24
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi254
-rw-r--r--arch/arm/boot/dts/imx6q-arm2.dts14
-rw-r--r--arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi112
-rw-r--r--arch/arm/boot/dts/imx6q-pinfunc.h2050
-rw-r--r--arch/arm/boot/dts/imx6q-sabreauto.dts22
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts22
-rw-r--r--arch/arm/boot/dts/imx6q-sabresd.dts19
-rw-r--r--arch/arm/boot/dts/imx6q-wandboard.dts26
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi393
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabreauto.dtsi22
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabresd.dtsi92
-rw-r--r--arch/arm/boot/dts/imx6qdl-wandboard.dtsi137
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi770
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi35
-rw-r--r--arch/arm/boot/dts/kirkwood-6281.dtsi66
-rw-r--r--arch/arm/boot/dts/kirkwood-6282.dtsi102
-rw-r--r--arch/arm/boot/dts/kirkwood-cloudbox.dts4
-rw-r--r--arch/arm/boot/dts/kirkwood-db-88f6281.dts7
-rw-r--r--arch/arm/boot/dts/kirkwood-db-88f6282.dts7
-rw-r--r--arch/arm/boot/dts/kirkwood-db.dtsi10
-rw-r--r--arch/arm/boot/dts/kirkwood-dns320.dts2
-rw-r--r--arch/arm/boot/dts/kirkwood-dns325.dts2
-rw-r--r--arch/arm/boot/dts/kirkwood-dnskw.dtsi4
-rw-r--r--arch/arm/boot/dts/kirkwood-dockstar.dts4
-rw-r--r--arch/arm/boot/dts/kirkwood-dreamplug.dts4
-rw-r--r--arch/arm/boot/dts/kirkwood-goflexnet.dts4
-rw-r--r--arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts4
-rw-r--r--arch/arm/boot/dts/kirkwood-ib62x0.dts4
-rw-r--r--arch/arm/boot/dts/kirkwood-iconnect.dts23
-rw-r--r--arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts4
-rw-r--r--arch/arm/boot/dts/kirkwood-is2.dts2
-rw-r--r--arch/arm/boot/dts/kirkwood-km_kirkwood.dts4
-rw-r--r--arch/arm/boot/dts/kirkwood-lschlv2.dts2
-rw-r--r--arch/arm/boot/dts/kirkwood-lsxhl.dts2
-rw-r--r--arch/arm/boot/dts/kirkwood-lsxl.dtsi4
-rw-r--r--arch/arm/boot/dts/kirkwood-mplcec4.dts23
-rw-r--r--arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts43
-rw-r--r--arch/arm/boot/dts/kirkwood-ns2-common.dtsi4
-rw-r--r--arch/arm/boot/dts/kirkwood-ns2.dts2
-rw-r--r--arch/arm/boot/dts/kirkwood-ns2lite.dts2
-rw-r--r--arch/arm/boot/dts/kirkwood-ns2max.dts2
-rw-r--r--arch/arm/boot/dts/kirkwood-ns2mini.dts2
-rw-r--r--arch/arm/boot/dts/kirkwood-nsa310-common.dtsi107
-rw-r--r--arch/arm/boot/dts/kirkwood-nsa310.dts111
-rw-r--r--arch/arm/boot/dts/kirkwood-nsa310a.dts165
-rw-r--r--arch/arm/boot/dts/kirkwood-openblocks_a6.dts4
-rw-r--r--arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi4
-rw-r--r--arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts2
-rw-r--r--arch/arm/boot/dts/kirkwood-sheevaplug.dts2
-rw-r--r--arch/arm/boot/dts/kirkwood-topkick.dts4
-rw-r--r--arch/arm/boot/dts/kirkwood-ts219-6281.dts6
-rw-r--r--arch/arm/boot/dts/kirkwood-ts219-6282.dts25
-rw-r--r--arch/arm/boot/dts/kirkwood-ts219.dtsi17
-rw-r--r--arch/arm/boot/dts/kirkwood.dtsi17
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts6
-rw-r--r--arch/arm/boot/dts/vf610-twr.dts7
90 files changed, 5949 insertions, 4181 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 454288db3180..f9f4c4d9c704 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -91,6 +91,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
91 kirkwood-ns2max.dtb \ 91 kirkwood-ns2max.dtb \
92 kirkwood-ns2mini.dtb \ 92 kirkwood-ns2mini.dtb \
93 kirkwood-nsa310.dtb \ 93 kirkwood-nsa310.dtb \
94 kirkwood-nsa310a.dtb \
94 kirkwood-sheevaplug.dtb \ 95 kirkwood-sheevaplug.dtb \
95 kirkwood-sheevaplug-esata.dtb \ 96 kirkwood-sheevaplug-esata.dtb \
96 kirkwood-topkick.dtb \ 97 kirkwood-topkick.dtb \
@@ -102,7 +103,9 @@ dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
102 msm8960-cdp.dtb 103 msm8960-cdp.dtb
103dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ 104dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
104 armada-370-mirabox.dtb \ 105 armada-370-mirabox.dtb \
106 armada-370-netgear-rn102.dtb \
105 armada-370-rd.dtb \ 107 armada-370-rd.dtb \
108 armada-xp-axpwifiap.dtb \
106 armada-xp-db.dtb \ 109 armada-xp-db.dtb \
107 armada-xp-gp.dtb \ 110 armada-xp-gp.dtb \
108 armada-xp-openblocks-ax3-4.dtb 111 armada-xp-openblocks-ax3-4.dtb
@@ -114,6 +117,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
114 imx27-pdk.dtb \ 117 imx27-pdk.dtb \
115 imx27-phytec-phycore-som.dtb \ 118 imx27-phytec-phycore-som.dtb \
116 imx27-phytec-phycore-rdk.dtb \ 119 imx27-phytec-phycore-rdk.dtb \
120 imx27-phytec-phycard-s-som.dtb \
121 imx27-phytec-phycard-s-rdk.dtb \
117 imx31-bug.dtb \ 122 imx31-bug.dtb \
118 imx51-apf51.dtb \ 123 imx51-apf51.dtb \
119 imx51-apf51dev.dtb \ 124 imx51-apf51dev.dtb \
@@ -133,6 +138,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
133 imx6q-sabrelite.dtb \ 138 imx6q-sabrelite.dtb \
134 imx6q-sabresd.dtb \ 139 imx6q-sabresd.dtb \
135 imx6q-sbc6x.dtb \ 140 imx6q-sbc6x.dtb \
141 imx6q-wandboard.dtb \
136 imx6sl-evk.dtb \ 142 imx6sl-evk.dtb \
137 vf610-twr.dtb 143 vf610-twr.dtb
138dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ 144dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index beee1699d49e..90ce29dbe119 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -14,7 +14,7 @@
14 */ 14 */
15 15
16/dts-v1/; 16/dts-v1/;
17/include/ "armada-370.dtsi" 17#include "armada-370.dtsi"
18 18
19/ { 19/ {
20 model = "Marvell Armada 370 Evaluation Board"; 20 model = "Marvell Armada 370 Evaluation Board";
@@ -30,6 +30,9 @@
30 }; 30 };
31 31
32 soc { 32 soc {
33 ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
34 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
35
33 internal-regs { 36 internal-regs {
34 serial@12000 { 37 serial@12000 {
35 clock-frequency = <200000000>; 38 clock-frequency = <200000000>;
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 45b107763e3b..2471d9da767b 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -9,7 +9,7 @@
9 */ 9 */
10 10
11/dts-v1/; 11/dts-v1/;
12/include/ "armada-370.dtsi" 12#include "armada-370.dtsi"
13 13
14/ { 14/ {
15 model = "Globalscale Mirabox"; 15 model = "Globalscale Mirabox";
@@ -25,6 +25,25 @@
25 }; 25 };
26 26
27 soc { 27 soc {
28 ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
29 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
30
31 pcie-controller {
32 status = "okay";
33
34 /* Internal mini-PCIe connector */
35 pcie@1,0 {
36 /* Port 0, Lane 0 */
37 status = "okay";
38 };
39
40 /* Connected on the PCB to a USB 3.0 XHCI controller */
41 pcie@2,0 {
42 /* Port 1, Lane 0 */
43 status = "okay";
44 };
45 };
46
28 internal-regs { 47 internal-regs {
29 serial@12000 { 48 serial@12000 {
30 clock-frequency = <200000000>; 49 clock-frequency = <200000000>;
@@ -120,22 +139,6 @@
120 reg = <0x25>; 139 reg = <0x25>;
121 }; 140 };
122 }; 141 };
123
124 pcie-controller {
125 status = "okay";
126
127 /* Internal mini-PCIe connector */
128 pcie@1,0 {
129 /* Port 0, Lane 0 */
130 status = "okay";
131 };
132
133 /* Connected on the PCB to a USB 3.0 XHCI controller */
134 pcie@2,0 {
135 /* Port 1, Lane 0 */
136 status = "okay";
137 };
138 };
139 }; 142 };
140 }; 143 };
141}; 144};
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
new file mode 100644
index 000000000000..05e4485a8225
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -0,0 +1,179 @@
1/*
2 * Device Tree file for NETGEAR ReadyNAS 102
3 *
4 * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12/dts-v1/;
13
14#include "armada-370.dtsi"
15
16/ {
17 model = "NETGEAR ReadyNAS 102";
18 compatible = "netgear,readynas-102", "marvell,armada370", "marvell,armada-370-xp";
19
20 chosen {
21 bootargs = "console=ttyS0,115200 earlyprintk";
22 };
23
24 memory {
25 device_type = "memory";
26 reg = <0x00000000 0x20000000>; /* 512 MB */
27 };
28
29 soc {
30 internal-regs {
31 serial@12000 {
32 clock-frequency = <200000000>;
33 status = "okay";
34 };
35
36 sata@a0000 {
37 nr-ports = <2>;
38 status = "okay";
39 };
40
41 pinctrl {
42 power_led_pin: power-led-pin {
43 marvell,pins = "mpp57";
44 marvell,function = "gpio";
45 };
46 sata1_led_pin: sata1-led-pin {
47 marvell,pins = "mpp15";
48 marvell,function = "gpio";
49 };
50
51 sata2_led_pin: sata2-led-pin {
52 marvell,pins = "mpp14";
53 marvell,function = "gpio";
54 };
55
56 backup_led_pin: backup-led-pin {
57 marvell,pins = "mpp56";
58 marvell,function = "gpio";
59 };
60 };
61
62 mdio {
63 phy0: ethernet-phy@0 {
64 reg = <0>;
65 };
66 };
67
68 ethernet@74000 {
69 status = "okay";
70 phy = <&phy0>;
71 phy-mode = "rgmii-id";
72 };
73
74 usb@50000 {
75 status = "okay";
76 };
77
78 i2c@11000 {
79 compatible = "marvell,mv64xxx-i2c";
80 clock-frequency = <100000>;
81 status = "okay";
82
83 g762: g762@3e {
84 compatible = "gmt,g762";
85 reg = <0x3e>;
86 clocks = <&g762_clk>; /* input clock */
87 fan_gear_mode = <0>;
88 fan_startv = <1>;
89 pwm_polarity = <0>;
90 };
91 };
92
93 pcie-controller {
94 status = "okay";
95
96 /* Connected to Marvell SATA controller */
97 pcie@1,0 {
98 /* Port 0, Lane 0 */
99 status = "okay";
100 };
101
102 /* Connected to FL1009 USB 3.0 controller */
103 pcie@2,0 {
104 /* Port 1, Lane 0 */
105 status = "okay";
106 };
107 };
108 };
109 };
110
111 clocks {
112 #address-cells = <1>;
113 #size-cells = <0>;
114
115 g762_clk: fixedclk {
116 compatible = "fixed-clock";
117 #clock-cells = <0>;
118 clock-frequency = <8192>;
119 };
120 };
121
122 gpio_leds {
123 compatible = "gpio-leds";
124 pinctrl-0 = < &power_led_pin
125 &sata1_led_pin
126 &sata2_led_pin
127 &backup_led_pin >;
128 pinctrl-names = "default";
129
130 blue_power_led {
131 label = "rn102:blue:pwr";
132 gpios = <&gpio1 25 1>; /* GPIO 57 Active Low */
133 linux,default-trigger = "heartbeat";
134 };
135
136 green_sata1_led {
137 label = "rn102:green:sata1";
138 gpios = <&gpio0 15 1>; /* GPIO 15 Active Low */
139 default-state = "on";
140 };
141
142 green_sata2_led {
143 label = "rn102:green:sata2";
144 gpios = <&gpio0 14 1>; /* GPIO 14 Active Low */
145 default-state = "on";
146 };
147
148 green_backup_led {
149 label = "rn102:green:backup";
150 gpios = <&gpio1 24 1>; /* GPIO 56 Active Low */
151 default-state = "on";
152 };
153 };
154
155 gpio_keys {
156 compatible = "gpio-keys";
157 #address-cells = <1>;
158 #size-cells = <0>;
159
160 button@1 {
161 label = "Power Button";
162 linux,code = <116>; /* KEY_POWER */
163 gpios = <&gpio1 30 1>;
164 };
165
166 button@2 {
167 label = "Reset Button";
168 linux,code = <0x198>; /* KEY_RESTART */
169 gpios = <&gpio0 6 1>;
170 };
171
172 button@3 {
173 label = "Backup Button";
174 linux,code = <133>; /* KEY_COPY */
175 gpios = <&gpio1 26 1>;
176 };
177 };
178
179};
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index a3a2fedb8726..f81810a59629 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -12,7 +12,7 @@
12 */ 12 */
13 13
14/dts-v1/; 14/dts-v1/;
15/include/ "armada-370.dtsi" 15#include "armada-370.dtsi"
16 16
17/ { 17/ {
18 model = "Marvell Armada 370 Reference Design"; 18 model = "Marvell Armada 370 Reference Design";
@@ -28,6 +28,25 @@
28 }; 28 };
29 29
30 soc { 30 soc {
31 ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
32 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
33
34 pcie-controller {
35 status = "okay";
36
37 /* Internal mini-PCIe connector */
38 pcie@1,0 {
39 /* Port 0, Lane 0 */
40 status = "okay";
41 };
42
43 /* Internal mini-PCIe connector */
44 pcie@2,0 {
45 /* Port 1, Lane 0 */
46 status = "okay";
47 };
48 };
49
31 internal-regs { 50 internal-regs {
32 serial@12000 { 51 serial@12000 {
33 clock-frequency = <200000000>; 52 clock-frequency = <200000000>;
@@ -85,22 +104,6 @@
85 gpios = <&gpio0 6 1>; 104 gpios = <&gpio0 6 1>;
86 }; 105 };
87 }; 106 };
88
89 pcie-controller {
90 status = "okay";
91
92 /* Internal mini-PCIe connector */
93 pcie@1,0 {
94 /* Port 0, Lane 0 */
95 status = "okay";
96 };
97
98 /* Internal mini-PCIe connector */
99 pcie@2,0 {
100 /* Port 1, Lane 0 */
101 status = "okay";
102 };
103 };
104 }; 107 };
105 }; 108 };
106 }; 109 };
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 90b117624abb..1de2dae0fdae 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -18,6 +18,8 @@
18 18
19/include/ "skeleton64.dtsi" 19/include/ "skeleton64.dtsi"
20 20
21#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
22
21/ { 23/ {
22 model = "Marvell Armada 370 and XP SoC"; 24 model = "Marvell Armada 370 and XP SoC";
23 compatible = "marvell,armada-370-xp"; 25 compatible = "marvell,armada-370-xp";
@@ -38,18 +40,73 @@
38 }; 40 };
39 41
40 soc { 42 soc {
41 #address-cells = <1>; 43 #address-cells = <2>;
42 #size-cells = <1>; 44 #size-cells = <1>;
43 compatible = "simple-bus"; 45 controller = <&mbusc>;
44 interrupt-parent = <&mpic>; 46 interrupt-parent = <&mpic>;
45 ranges = <0 0 0xd0000000 0x0100000 /* internal registers */ 47 pcie-mem-aperture = <0xe0000000 0x8000000>;
46 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>; 48 pcie-io-aperture = <0xe8000000 0x100000>;
49
50 devbus-bootcs {
51 compatible = "marvell,mvebu-devbus";
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
54 #address-cells = <1>;
55 #size-cells = <1>;
56 clocks = <&coreclk 0>;
57 status = "disabled";
58 };
59
60 devbus-cs0 {
61 compatible = "marvell,mvebu-devbus";
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
64 #address-cells = <1>;
65 #size-cells = <1>;
66 clocks = <&coreclk 0>;
67 status = "disabled";
68 };
69
70 devbus-cs1 {
71 compatible = "marvell,mvebu-devbus";
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
73 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
74 #address-cells = <1>;
75 #size-cells = <1>;
76 clocks = <&coreclk 0>;
77 status = "disabled";
78 };
79
80 devbus-cs2 {
81 compatible = "marvell,mvebu-devbus";
82 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
83 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
84 #address-cells = <1>;
85 #size-cells = <1>;
86 clocks = <&coreclk 0>;
87 status = "disabled";
88 };
89
90 devbus-cs3 {
91 compatible = "marvell,mvebu-devbus";
92 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
93 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
94 #address-cells = <1>;
95 #size-cells = <1>;
96 clocks = <&coreclk 0>;
97 status = "disabled";
98 };
47 99
48 internal-regs { 100 internal-regs {
49 compatible = "simple-bus"; 101 compatible = "simple-bus";
50 #address-cells = <1>; 102 #address-cells = <1>;
51 #size-cells = <1>; 103 #size-cells = <1>;
52 ranges; 104 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
105
106 mbusc: mbus-controller@20000 {
107 compatible = "marvell,mbus-controller";
108 reg = <0x20000 0x100>, <0x20180 0x20>;
109 };
53 110
54 mpic: interrupt-controller@20000 { 111 mpic: interrupt-controller@20000 {
55 compatible = "marvell,mpic"; 112 compatible = "marvell,mpic";
@@ -81,10 +138,8 @@
81 }; 138 };
82 139
83 timer@20300 { 140 timer@20300 {
84 compatible = "marvell,armada-370-xp-timer";
85 reg = <0x20300 0x30>, <0x21040 0x30>; 141 reg = <0x20300 0x30>, <0x21040 0x30>;
86 interrupts = <37>, <38>, <39>, <40>, <5>, <6>; 142 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
87 clocks = <&coreclk 2>;
88 }; 143 };
89 144
90 sata@a0000 { 145 sata@a0000 {
@@ -195,50 +250,6 @@
195 status = "disabled"; 250 status = "disabled";
196 }; 251 };
197 252
198 devbus-bootcs@10400 {
199 compatible = "marvell,mvebu-devbus";
200 reg = <0x10400 0x8>;
201 #address-cells = <1>;
202 #size-cells = <1>;
203 clocks = <&coreclk 0>;
204 status = "disabled";
205 };
206
207 devbus-cs0@10408 {
208 compatible = "marvell,mvebu-devbus";
209 reg = <0x10408 0x8>;
210 #address-cells = <1>;
211 #size-cells = <1>;
212 clocks = <&coreclk 0>;
213 status = "disabled";
214 };
215
216 devbus-cs1@10410 {
217 compatible = "marvell,mvebu-devbus";
218 reg = <0x10410 0x8>;
219 #address-cells = <1>;
220 #size-cells = <1>;
221 clocks = <&coreclk 0>;
222 status = "disabled";
223 };
224
225 devbus-cs2@10418 {
226 compatible = "marvell,mvebu-devbus";
227 reg = <0x10418 0x8>;
228 #address-cells = <1>;
229 #size-cells = <1>;
230 clocks = <&coreclk 0>;
231 status = "disabled";
232 };
233
234 devbus-cs3@10420 {
235 compatible = "marvell,mvebu-devbus";
236 reg = <0x10420 0x8>;
237 #address-cells = <1>;
238 #size-cells = <1>;
239 clocks = <&coreclk 0>;
240 status = "disabled";
241 };
242 }; 253 };
243 }; 254 };
244 }; 255 };
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index fa3dfc6b4c6a..e134d7a90c9a 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -15,7 +15,7 @@
15 * common to all Armada SoCs. 15 * common to all Armada SoCs.
16 */ 16 */
17 17
18/include/ "armada-370-xp.dtsi" 18#include "armada-370-xp.dtsi"
19/include/ "skeleton.dtsi" 19/include/ "skeleton.dtsi"
20 20
21/ { 21/ {
@@ -29,8 +29,66 @@
29 }; 29 };
30 30
31 soc { 31 soc {
32 ranges = <0 0xd0000000 0x0100000 /* internal registers */ 32 compatible = "marvell,armada370-mbus", "simple-bus";
33 0xe0000000 0xe0000000 0x8100000 /* PCIe */>; 33
34 bootrom {
35 compatible = "marvell,bootrom";
36 reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
37 };
38
39 pcie-controller {
40 compatible = "marvell,armada-370-pcie";
41 status = "disabled";
42 device_type = "pci";
43
44 #address-cells = <3>;
45 #size-cells = <2>;
46
47 bus-range = <0x00 0xff>;
48
49 ranges =
50 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
51 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
52 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
53 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
54 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
55 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
56
57 pcie@1,0 {
58 device_type = "pci";
59 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
60 reg = <0x0800 0 0 0 0>;
61 #address-cells = <3>;
62 #size-cells = <2>;
63 #interrupt-cells = <1>;
64 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
65 0x81000000 0 0 0x81000000 0x1 0 1 0>;
66 interrupt-map-mask = <0 0 0 0>;
67 interrupt-map = <0 0 0 0 &mpic 58>;
68 marvell,pcie-port = <0>;
69 marvell,pcie-lane = <0>;
70 clocks = <&gateclk 5>;
71 status = "disabled";
72 };
73
74 pcie@2,0 {
75 device_type = "pci";
76 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
77 reg = <0x1000 0 0 0 0>;
78 #address-cells = <3>;
79 #size-cells = <2>;
80 #interrupt-cells = <1>;
81 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
82 0x81000000 0 0 0x81000000 0x2 0 1 0>;
83 interrupt-map-mask = <0 0 0 0>;
84 interrupt-map = <0 0 0 0 &mpic 62>;
85 marvell,pcie-port = <1>;
86 marvell,pcie-lane = <0>;
87 clocks = <&gateclk 9>;
88 status = "disabled";
89 };
90 };
91
34 internal-regs { 92 internal-regs {
35 system-controller@18200 { 93 system-controller@18200 {
36 compatible = "marvell,armada-370-xp-system-controller"; 94 compatible = "marvell,armada-370-xp-system-controller";
@@ -78,7 +136,7 @@
78 gpio-controller; 136 gpio-controller;
79 #gpio-cells = <2>; 137 #gpio-cells = <2>;
80 interrupt-controller; 138 interrupt-controller;
81 #interrupts-cells = <2>; 139 #interrupt-cells = <2>;
82 interrupts = <82>, <83>, <84>, <85>; 140 interrupts = <82>, <83>, <84>, <85>;
83 }; 141 };
84 142
@@ -89,7 +147,7 @@
89 gpio-controller; 147 gpio-controller;
90 #gpio-cells = <2>; 148 #gpio-cells = <2>;
91 interrupt-controller; 149 interrupt-controller;
92 #interrupts-cells = <2>; 150 #interrupt-cells = <2>;
93 interrupts = <87>, <88>, <89>, <90>; 151 interrupts = <87>, <88>, <89>, <90>;
94 }; 152 };
95 153
@@ -100,10 +158,15 @@
100 gpio-controller; 158 gpio-controller;
101 #gpio-cells = <2>; 159 #gpio-cells = <2>;
102 interrupt-controller; 160 interrupt-controller;
103 #interrupts-cells = <2>; 161 #interrupt-cells = <2>;
104 interrupts = <91>; 162 interrupts = <91>;
105 }; 163 };
106 164
165 timer@20300 {
166 compatible = "marvell,armada-370-timer";
167 clocks = <&coreclk 2>;
168 };
169
107 coreclk: mvebu-sar@18230 { 170 coreclk: mvebu-sar@18230 {
108 compatible = "marvell,armada-370-core-clock"; 171 compatible = "marvell,armada-370-core-clock";
109 reg = <0x18230 0x08>; 172 reg = <0x18230 0x08>;
@@ -169,54 +232,6 @@
169 0x18304 0x4>; 232 0x18304 0x4>;
170 status = "okay"; 233 status = "okay";
171 }; 234 };
172
173 pcie-controller {
174 compatible = "marvell,armada-370-pcie";
175 status = "disabled";
176 device_type = "pci";
177
178 #address-cells = <3>;
179 #size-cells = <2>;
180
181 bus-range = <0x00 0xff>;
182
183 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
184 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
185 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
186 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
187
188 pcie@1,0 {
189 device_type = "pci";
190 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
191 reg = <0x0800 0 0 0 0>;
192 #address-cells = <3>;
193 #size-cells = <2>;
194 #interrupt-cells = <1>;
195 ranges;
196 interrupt-map-mask = <0 0 0 0>;
197 interrupt-map = <0 0 0 0 &mpic 58>;
198 marvell,pcie-port = <0>;
199 marvell,pcie-lane = <0>;
200 clocks = <&gateclk 5>;
201 status = "disabled";
202 };
203
204 pcie@2,0 {
205 device_type = "pci";
206 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
207 reg = <0x1000 0 0 0 0>;
208 #address-cells = <3>;
209 #size-cells = <2>;
210 #interrupt-cells = <1>;
211 ranges;
212 interrupt-map-mask = <0 0 0 0>;
213 interrupt-map = <0 0 0 0 &mpic 62>;
214 marvell,pcie-port = <1>;
215 marvell,pcie-lane = <0>;
216 clocks = <&gateclk 9>;
217 status = "disabled";
218 };
219 };
220 }; 235 };
221 }; 236 };
222}; 237};
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
new file mode 100644
index 000000000000..c5fe57269f5a
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -0,0 +1,164 @@
1/*
2 * Device Tree file for Marvell RD-AXPWiFiAP.
3 *
4 * Note: this board is shipped with a new generation boot loader that
5 * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
6 * is used, the CONFIG_DEBUG_MVEBU_UART_ALTERNATE option should be
7 * used.
8 *
9 * Copyright (C) 2013 Marvell
10 *
11 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 *
13 * This file is licensed under the terms of the GNU General Public
14 * License version 2. This program is licensed "as is" without any
15 * warranty of any kind, whether express or implied.
16 */
17
18/dts-v1/;
19#include "armada-xp-mv78230.dtsi"
20
21/ {
22 model = "Marvell RD-AXPWiFiAP";
23 compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
24
25 chosen {
26 bootargs = "console=ttyS0,115200 earlyprintk";
27 };
28
29 memory {
30 device_type = "memory";
31 reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
32 };
33
34 soc {
35 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
36 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
37
38 pcie-controller {
39 status = "okay";
40
41 /* First mini-PCIe port */
42 pcie@1,0 {
43 /* Port 0, Lane 0 */
44 status = "okay";
45 };
46
47 /* Second mini-PCIe port */
48 pcie@2,0 {
49 /* Port 0, Lane 1 */
50 status = "okay";
51 };
52
53 /* Renesas uPD720202 USB 3.0 controller */
54 pcie@3,0 {
55 /* Port 0, Lane 3 */
56 status = "okay";
57 };
58 };
59
60 internal-regs {
61 pinctrl {
62 pinctrl-0 = <&pmx_phy_int>;
63 pinctrl-names = "default";
64
65 pmx_ge0: pmx-ge0 {
66 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
67 "mpp4", "mpp5", "mpp6", "mpp7",
68 "mpp8", "mpp9", "mpp10", "mpp11";
69 marvell,function = "ge0";
70 };
71
72 pmx_ge1: pmx-ge1 {
73 marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15",
74 "mpp16", "mpp17", "mpp18", "mpp19",
75 "mpp20", "mpp21", "mpp22", "mpp23";
76 marvell,function = "ge1";
77 };
78
79 pmx_keys: pmx-keys {
80 marvell,pins = "mpp33";
81 marvell,function = "gpio";
82 };
83
84 pmx_spi: pmx-spi {
85 marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39";
86 marvell,function = "spi";
87 };
88
89 pmx_phy_int: pmx-phy-int {
90 marvell,pins = "mpp32";
91 marvell,function = "gpio";
92 };
93 };
94
95 serial@12000 {
96 clock-frequency = <250000000>;
97 status = "okay";
98 };
99
100 serial@12100 {
101 clock-frequency = <250000000>;
102 status = "okay";
103 };
104
105 sata@a0000 {
106 nr-ports = <1>;
107 status = "okay";
108 };
109
110 mdio {
111 phy0: ethernet-phy@0 {
112 reg = <0>;
113 };
114
115 phy1: ethernet-phy@1 {
116 reg = <1>;
117 };
118 };
119
120 ethernet@70000 {
121 pinctrl-0 = <&pmx_ge0>;
122 pinctrl-names = "default";
123 status = "okay";
124 phy = <&phy0>;
125 phy-mode = "rgmii-id";
126 };
127 ethernet@74000 {
128 pinctrl-0 = <&pmx_ge1>;
129 pinctrl-names = "default";
130 status = "okay";
131 phy = <&phy1>;
132 phy-mode = "rgmii-id";
133 };
134
135 spi0: spi@10600 {
136 status = "okay";
137 pinctrl-0 = <&pmx_spi>;
138 pinctrl-names = "default";
139
140 spi-flash@0 {
141 #address-cells = <1>;
142 #size-cells = <1>;
143 compatible = "n25q128a13";
144 reg = <0>; /* Chip select 0 */
145 spi-max-frequency = <108000000>;
146 };
147 };
148 };
149 };
150
151 gpio_keys {
152 compatible = "gpio-keys";
153 #address-cells = <1>;
154 #size-cells = <0>;
155 pinctrl-0 = <&pmx_keys>;
156 pinctrl-names = "default";
157
158 button@1 {
159 label = "Factory Reset Button";
160 linux,code = <141>; /* KEY_SETUP */
161 gpios = <&gpio1 1 1>;
162 };
163 };
164};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index e28e68ff864d..bcf6d79a57ec 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -14,7 +14,7 @@
14 */ 14 */
15 15
16/dts-v1/; 16/dts-v1/;
17/include/ "armada-xp-mv78460.dtsi" 17#include "armada-xp-mv78460.dtsi"
18 18
19/ { 19/ {
20 model = "Marvell Armada XP Evaluation Board"; 20 model = "Marvell Armada XP Evaluation Board";
@@ -30,9 +30,70 @@
30 }; 30 };
31 31
32 soc { 32 soc {
33 ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ 33 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
34 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ 34 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
35 0xf0000000 0 0xf0000000 0x1000000>; /* Device Bus, NOR 16MiB */ 35 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
36
37 devbus-bootcs {
38 status = "okay";
39
40 /* Device Bus parameters are required */
41
42 /* Read parameters */
43 devbus,bus-width = <8>;
44 devbus,turn-off-ps = <60000>;
45 devbus,badr-skew-ps = <0>;
46 devbus,acc-first-ps = <124000>;
47 devbus,acc-next-ps = <248000>;
48 devbus,rd-setup-ps = <0>;
49 devbus,rd-hold-ps = <0>;
50
51 /* Write parameters */
52 devbus,sync-enable = <0>;
53 devbus,wr-high-ps = <60000>;
54 devbus,wr-low-ps = <60000>;
55 devbus,ale-wr-ps = <60000>;
56
57 /* NOR 16 MiB */
58 nor@0 {
59 compatible = "cfi-flash";
60 reg = <0 0x1000000>;
61 bank-width = <2>;
62 };
63 };
64
65 pcie-controller {
66 status = "okay";
67
68 /*
69 * All 6 slots are physically present as
70 * standard PCIe slots on the board.
71 */
72 pcie@1,0 {
73 /* Port 0, Lane 0 */
74 status = "okay";
75 };
76 pcie@2,0 {
77 /* Port 0, Lane 1 */
78 status = "okay";
79 };
80 pcie@3,0 {
81 /* Port 0, Lane 2 */
82 status = "okay";
83 };
84 pcie@4,0 {
85 /* Port 0, Lane 3 */
86 status = "okay";
87 };
88 pcie@9,0 {
89 /* Port 2, Lane 0 */
90 status = "okay";
91 };
92 pcie@10,0 {
93 /* Port 3, Lane 0 */
94 status = "okay";
95 };
96 };
36 97
37 internal-regs { 98 internal-regs {
38 serial@12000 { 99 serial@12000 {
@@ -127,68 +188,6 @@
127 spi-max-frequency = <20000000>; 188 spi-max-frequency = <20000000>;
128 }; 189 };
129 }; 190 };
130
131 pcie-controller {
132 status = "okay";
133
134 /*
135 * All 6 slots are physically present as
136 * standard PCIe slots on the board.
137 */
138 pcie@1,0 {
139 /* Port 0, Lane 0 */
140 status = "okay";
141 };
142 pcie@2,0 {
143 /* Port 0, Lane 1 */
144 status = "okay";
145 };
146 pcie@3,0 {
147 /* Port 0, Lane 2 */
148 status = "okay";
149 };
150 pcie@4,0 {
151 /* Port 0, Lane 3 */
152 status = "okay";
153 };
154 pcie@9,0 {
155 /* Port 2, Lane 0 */
156 status = "okay";
157 };
158 pcie@10,0 {
159 /* Port 3, Lane 0 */
160 status = "okay";
161 };
162 };
163
164 devbus-bootcs@10400 {
165 status = "okay";
166 ranges = <0 0xf0000000 0x1000000>;
167
168 /* Device Bus parameters are required */
169
170 /* Read parameters */
171 devbus,bus-width = <8>;
172 devbus,turn-off-ps = <60000>;
173 devbus,badr-skew-ps = <0>;
174 devbus,acc-first-ps = <124000>;
175 devbus,acc-next-ps = <248000>;
176 devbus,rd-setup-ps = <0>;
177 devbus,rd-hold-ps = <0>;
178
179 /* Write parameters */
180 devbus,sync-enable = <0>;
181 devbus,wr-high-ps = <60000>;
182 devbus,wr-low-ps = <60000>;
183 devbus,ale-wr-ps = <60000>;
184
185 /* NOR 16 MiB */
186 nor@0 {
187 compatible = "cfi-flash";
188 reg = <0 0x1000000>;
189 bank-width = <2>;
190 };
191 };
192 }; 191 };
193 }; 192 };
194}; 193};
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index c87b2de29c30..2298e4a910e2 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -14,7 +14,7 @@
14 */ 14 */
15 15
16/dts-v1/; 16/dts-v1/;
17/include/ "armada-xp-mv78460.dtsi" 17#include "armada-xp-mv78460.dtsi"
18 18
19/ { 19/ {
20 model = "Marvell Armada XP Development Board DB-MV784MP-GP"; 20 model = "Marvell Armada XP Development Board DB-MV784MP-GP";
@@ -39,9 +39,58 @@
39 }; 39 };
40 40
41 soc { 41 soc {
42 ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ 42 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
43 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ 43 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
44 0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB */>; 44 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
45
46 devbus-bootcs {
47 status = "okay";
48
49 /* Device Bus parameters are required */
50
51 /* Read parameters */
52 devbus,bus-width = <8>;
53 devbus,turn-off-ps = <60000>;
54 devbus,badr-skew-ps = <0>;
55 devbus,acc-first-ps = <124000>;
56 devbus,acc-next-ps = <248000>;
57 devbus,rd-setup-ps = <0>;
58 devbus,rd-hold-ps = <0>;
59
60 /* Write parameters */
61 devbus,sync-enable = <0>;
62 devbus,wr-high-ps = <60000>;
63 devbus,wr-low-ps = <60000>;
64 devbus,ale-wr-ps = <60000>;
65
66 /* NOR 16 MiB */
67 nor@0 {
68 compatible = "cfi-flash";
69 reg = <0 0x1000000>;
70 bank-width = <2>;
71 };
72 };
73
74 pcie-controller {
75 status = "okay";
76
77 /*
78 * The 3 slots are physically present as
79 * standard PCIe slots on the board.
80 */
81 pcie@1,0 {
82 /* Port 0, Lane 0 */
83 status = "okay";
84 };
85 pcie@9,0 {
86 /* Port 2, Lane 0 */
87 status = "okay";
88 };
89 pcie@10,0 {
90 /* Port 3, Lane 0 */
91 status = "okay";
92 };
93 };
45 94
46 internal-regs { 95 internal-regs {
47 serial@12000 { 96 serial@12000 {
@@ -126,56 +175,6 @@
126 spi-max-frequency = <108000000>; 175 spi-max-frequency = <108000000>;
127 }; 176 };
128 }; 177 };
129
130 devbus-bootcs@10400 {
131 status = "okay";
132 ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
133
134 /* Device Bus parameters are required */
135
136 /* Read parameters */
137 devbus,bus-width = <8>;
138 devbus,turn-off-ps = <60000>;
139 devbus,badr-skew-ps = <0>;
140 devbus,acc-first-ps = <124000>;
141 devbus,acc-next-ps = <248000>;
142 devbus,rd-setup-ps = <0>;
143 devbus,rd-hold-ps = <0>;
144
145 /* Write parameters */
146 devbus,sync-enable = <0>;
147 devbus,wr-high-ps = <60000>;
148 devbus,wr-low-ps = <60000>;
149 devbus,ale-wr-ps = <60000>;
150
151 /* NOR 16 MiB */
152 nor@0 {
153 compatible = "cfi-flash";
154 reg = <0 0x1000000>;
155 bank-width = <2>;
156 };
157 };
158
159 pcie-controller {
160 status = "okay";
161
162 /*
163 * The 3 slots are physically present as
164 * standard PCIe slots on the board.
165 */
166 pcie@1,0 {
167 /* Port 0, Lane 0 */
168 status = "okay";
169 };
170 pcie@9,0 {
171 /* Port 2, Lane 0 */
172 status = "okay";
173 };
174 pcie@10,0 {
175 /* Port 3, Lane 0 */
176 status = "okay";
177 };
178 };
179 }; 178 };
180 }; 179 };
181}; 180};
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index f8eaa383e07f..0358a33cba48 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -13,7 +13,7 @@
13 * common to all Armada XP SoCs. 13 * common to all Armada XP SoCs.
14 */ 14 */
15 15
16/include/ "armada-xp.dtsi" 16#include "armada-xp.dtsi"
17 17
18/ { 18/ {
19 model = "Marvell Armada XP MV78230 SoC"; 19 model = "Marvell Armada XP MV78230 SoC";
@@ -44,6 +44,124 @@
44 }; 44 };
45 45
46 soc { 46 soc {
47 /*
48 * MV78230 has 2 PCIe units Gen2.0: One unit can be
49 * configured as x4 or quad x1 lanes. One unit is
50 * x4/x1.
51 */
52 pcie-controller {
53 compatible = "marvell,armada-xp-pcie";
54 status = "disabled";
55 device_type = "pci";
56
57 #address-cells = <3>;
58 #size-cells = <2>;
59
60 bus-range = <0x00 0xff>;
61
62 ranges =
63 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
64 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
65 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
66 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
67 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
68 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
69 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
70 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
71 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
72 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
73 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
74 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
75 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
76 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
77 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
78
79 pcie@1,0 {
80 device_type = "pci";
81 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
82 reg = <0x0800 0 0 0 0>;
83 #address-cells = <3>;
84 #size-cells = <2>;
85 #interrupt-cells = <1>;
86 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
87 0x81000000 0 0 0x81000000 0x1 0 1 0>;
88 interrupt-map-mask = <0 0 0 0>;
89 interrupt-map = <0 0 0 0 &mpic 58>;
90 marvell,pcie-port = <0>;
91 marvell,pcie-lane = <0>;
92 clocks = <&gateclk 5>;
93 status = "disabled";
94 };
95
96 pcie@2,0 {
97 device_type = "pci";
98 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
99 reg = <0x1000 0 0 0 0>;
100 #address-cells = <3>;
101 #size-cells = <2>;
102 #interrupt-cells = <1>;
103 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
104 0x81000000 0 0 0x81000000 0x2 0 1 0>;
105 interrupt-map-mask = <0 0 0 0>;
106 interrupt-map = <0 0 0 0 &mpic 59>;
107 marvell,pcie-port = <0>;
108 marvell,pcie-lane = <1>;
109 clocks = <&gateclk 6>;
110 status = "disabled";
111 };
112
113 pcie@3,0 {
114 device_type = "pci";
115 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
116 reg = <0x1800 0 0 0 0>;
117 #address-cells = <3>;
118 #size-cells = <2>;
119 #interrupt-cells = <1>;
120 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
121 0x81000000 0 0 0x81000000 0x3 0 1 0>;
122 interrupt-map-mask = <0 0 0 0>;
123 interrupt-map = <0 0 0 0 &mpic 60>;
124 marvell,pcie-port = <0>;
125 marvell,pcie-lane = <2>;
126 clocks = <&gateclk 7>;
127 status = "disabled";
128 };
129
130 pcie@4,0 {
131 device_type = "pci";
132 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
133 reg = <0x2000 0 0 0 0>;
134 #address-cells = <3>;
135 #size-cells = <2>;
136 #interrupt-cells = <1>;
137 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
138 0x81000000 0 0 0x81000000 0x4 0 1 0>;
139 interrupt-map-mask = <0 0 0 0>;
140 interrupt-map = <0 0 0 0 &mpic 61>;
141 marvell,pcie-port = <0>;
142 marvell,pcie-lane = <3>;
143 clocks = <&gateclk 8>;
144 status = "disabled";
145 };
146
147 pcie@9,0 {
148 device_type = "pci";
149 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
150 reg = <0x4800 0 0 0 0>;
151 #address-cells = <3>;
152 #size-cells = <2>;
153 #interrupt-cells = <1>;
154 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
155 0x81000000 0 0 0x81000000 0x9 0 1 0>;
156 interrupt-map-mask = <0 0 0 0>;
157 interrupt-map = <0 0 0 0 &mpic 99>;
158 marvell,pcie-port = <2>;
159 marvell,pcie-lane = <0>;
160 clocks = <&gateclk 26>;
161 status = "disabled";
162 };
163 };
164
47 internal-regs { 165 internal-regs {
48 pinctrl { 166 pinctrl {
49 compatible = "marvell,mv78230-pinctrl"; 167 compatible = "marvell,mv78230-pinctrl";
@@ -63,7 +181,7 @@
63 gpio-controller; 181 gpio-controller;
64 #gpio-cells = <2>; 182 #gpio-cells = <2>;
65 interrupt-controller; 183 interrupt-controller;
66 #interrupts-cells = <2>; 184 #interrupt-cells = <2>;
67 interrupts = <82>, <83>, <84>, <85>; 185 interrupts = <82>, <83>, <84>, <85>;
68 }; 186 };
69 187
@@ -74,113 +192,9 @@
74 gpio-controller; 192 gpio-controller;
75 #gpio-cells = <2>; 193 #gpio-cells = <2>;
76 interrupt-controller; 194 interrupt-controller;
77 #interrupts-cells = <2>; 195 #interrupt-cells = <2>;
78 interrupts = <87>, <88>, <89>; 196 interrupts = <87>, <88>, <89>;
79 }; 197 };
80
81 /*
82 * MV78230 has 2 PCIe units Gen2.0: One unit can be
83 * configured as x4 or quad x1 lanes. One unit is
84 * x4/x1.
85 */
86 pcie-controller {
87 compatible = "marvell,armada-xp-pcie";
88 status = "disabled";
89 device_type = "pci";
90
91#address-cells = <3>;
92#size-cells = <2>;
93
94 bus-range = <0x00 0xff>;
95
96 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
97 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
98 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
99 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
100 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
101 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
102 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
103
104 pcie@1,0 {
105 device_type = "pci";
106 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
107 reg = <0x0800 0 0 0 0>;
108 #address-cells = <3>;
109 #size-cells = <2>;
110 #interrupt-cells = <1>;
111 ranges;
112 interrupt-map-mask = <0 0 0 0>;
113 interrupt-map = <0 0 0 0 &mpic 58>;
114 marvell,pcie-port = <0>;
115 marvell,pcie-lane = <0>;
116 clocks = <&gateclk 5>;
117 status = "disabled";
118 };
119
120 pcie@2,0 {
121 device_type = "pci";
122 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
123 reg = <0x1000 0 0 0 0>;
124 #address-cells = <3>;
125 #size-cells = <2>;
126 #interrupt-cells = <1>;
127 ranges;
128 interrupt-map-mask = <0 0 0 0>;
129 interrupt-map = <0 0 0 0 &mpic 59>;
130 marvell,pcie-port = <0>;
131 marvell,pcie-lane = <1>;
132 clocks = <&gateclk 6>;
133 status = "disabled";
134 };
135
136 pcie@3,0 {
137 device_type = "pci";
138 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
139 reg = <0x1800 0 0 0 0>;
140 #address-cells = <3>;
141 #size-cells = <2>;
142 #interrupt-cells = <1>;
143 ranges;
144 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 0 &mpic 60>;
146 marvell,pcie-port = <0>;
147 marvell,pcie-lane = <2>;
148 clocks = <&gateclk 7>;
149 status = "disabled";
150 };
151
152 pcie@4,0 {
153 device_type = "pci";
154 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
155 reg = <0x2000 0 0 0 0>;
156 #address-cells = <3>;
157 #size-cells = <2>;
158 #interrupt-cells = <1>;
159 ranges;
160 interrupt-map-mask = <0 0 0 0>;
161 interrupt-map = <0 0 0 0 &mpic 61>;
162 marvell,pcie-port = <0>;
163 marvell,pcie-lane = <3>;
164 clocks = <&gateclk 8>;
165 status = "disabled";
166 };
167
168 pcie@9,0 {
169 device_type = "pci";
170 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
171 reg = <0x4800 0 0 0 0>;
172 #address-cells = <3>;
173 #size-cells = <2>;
174 #interrupt-cells = <1>;
175 ranges;
176 interrupt-map-mask = <0 0 0 0>;
177 interrupt-map = <0 0 0 0 &mpic 99>;
178 marvell,pcie-port = <2>;
179 marvell,pcie-lane = <0>;
180 clocks = <&gateclk 26>;
181 status = "disabled";
182 };
183 };
184 }; 198 };
185 }; 199 };
186}; 200};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 2d9335da210c..0e82c5062243 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -13,7 +13,7 @@
13 * common to all Armada XP SoCs. 13 * common to all Armada XP SoCs.
14 */ 14 */
15 15
16/include/ "armada-xp.dtsi" 16#include "armada-xp.dtsi"
17 17
18/ { 18/ {
19 model = "Marvell Armada XP MV78260 SoC"; 19 model = "Marvell Armada XP MV78260 SoC";
@@ -45,6 +45,145 @@
45 }; 45 };
46 46
47 soc { 47 soc {
48 /*
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
50 * configured as x4 or quad x1 lanes. One unit is
51 * x4/x1.
52 */
53 pcie-controller {
54 compatible = "marvell,armada-xp-pcie";
55 status = "disabled";
56 device_type = "pci";
57
58 #address-cells = <3>;
59 #size-cells = <2>;
60
61 bus-range = <0x00 0xff>;
62
63 ranges =
64 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
65 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
66 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
67 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
68 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
69 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
70 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
71 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
72 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
73 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
74 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
75 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
76 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
77 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
78 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
79 0x82000000 0x9 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
80 0x81000000 0x9 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
81 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
82 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
83
84 pcie@1,0 {
85 device_type = "pci";
86 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
87 reg = <0x0800 0 0 0 0>;
88 #address-cells = <3>;
89 #size-cells = <2>;
90 #interrupt-cells = <1>;
91 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
92 0x81000000 0 0 0x81000000 0x1 0 1 0>;
93 interrupt-map-mask = <0 0 0 0>;
94 interrupt-map = <0 0 0 0 &mpic 58>;
95 marvell,pcie-port = <0>;
96 marvell,pcie-lane = <0>;
97 clocks = <&gateclk 5>;
98 status = "disabled";
99 };
100
101 pcie@2,0 {
102 device_type = "pci";
103 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
104 reg = <0x1000 0 0 0 0>;
105 #address-cells = <3>;
106 #size-cells = <2>;
107 #interrupt-cells = <1>;
108 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
109 0x81000000 0 0 0x81000000 0x2 0 1 0>;
110 interrupt-map-mask = <0 0 0 0>;
111 interrupt-map = <0 0 0 0 &mpic 59>;
112 marvell,pcie-port = <0>;
113 marvell,pcie-lane = <1>;
114 clocks = <&gateclk 6>;
115 status = "disabled";
116 };
117
118 pcie@3,0 {
119 device_type = "pci";
120 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
121 reg = <0x1800 0 0 0 0>;
122 #address-cells = <3>;
123 #size-cells = <2>;
124 #interrupt-cells = <1>;
125 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
126 0x81000000 0 0 0x81000000 0x3 0 1 0>;
127 interrupt-map-mask = <0 0 0 0>;
128 interrupt-map = <0 0 0 0 &mpic 60>;
129 marvell,pcie-port = <0>;
130 marvell,pcie-lane = <2>;
131 clocks = <&gateclk 7>;
132 status = "disabled";
133 };
134
135 pcie@4,0 {
136 device_type = "pci";
137 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
138 reg = <0x2000 0 0 0 0>;
139 #address-cells = <3>;
140 #size-cells = <2>;
141 #interrupt-cells = <1>;
142 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
143 0x81000000 0 0 0x81000000 0x4 0 1 0>;
144 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 0 &mpic 61>;
146 marvell,pcie-port = <0>;
147 marvell,pcie-lane = <3>;
148 clocks = <&gateclk 8>;
149 status = "disabled";
150 };
151
152 pcie@9,0 {
153 device_type = "pci";
154 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
155 reg = <0x4800 0 0 0 0>;
156 #address-cells = <3>;
157 #size-cells = <2>;
158 #interrupt-cells = <1>;
159 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
160 0x81000000 0 0 0x81000000 0x9 0 1 0>;
161 interrupt-map-mask = <0 0 0 0>;
162 interrupt-map = <0 0 0 0 &mpic 99>;
163 marvell,pcie-port = <2>;
164 marvell,pcie-lane = <0>;
165 clocks = <&gateclk 26>;
166 status = "disabled";
167 };
168
169 pcie@10,0 {
170 device_type = "pci";
171 assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
172 reg = <0x5000 0 0 0 0>;
173 #address-cells = <3>;
174 #size-cells = <2>;
175 #interrupt-cells = <1>;
176 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
177 0x81000000 0 0 0x81000000 0xa 0 1 0>;
178 interrupt-map-mask = <0 0 0 0>;
179 interrupt-map = <0 0 0 0 &mpic 103>;
180 marvell,pcie-port = <3>;
181 marvell,pcie-lane = <0>;
182 clocks = <&gateclk 27>;
183 status = "disabled";
184 };
185 };
186
48 internal-regs { 187 internal-regs {
49 pinctrl { 188 pinctrl {
50 compatible = "marvell,mv78260-pinctrl"; 189 compatible = "marvell,mv78260-pinctrl";
@@ -64,7 +203,7 @@
64 gpio-controller; 203 gpio-controller;
65 #gpio-cells = <2>; 204 #gpio-cells = <2>;
66 interrupt-controller; 205 interrupt-controller;
67 #interrupts-cells = <2>; 206 #interrupt-cells = <2>;
68 interrupts = <82>, <83>, <84>, <85>; 207 interrupts = <82>, <83>, <84>, <85>;
69 }; 208 };
70 209
@@ -75,7 +214,7 @@
75 gpio-controller; 214 gpio-controller;
76 #gpio-cells = <2>; 215 #gpio-cells = <2>;
77 interrupt-controller; 216 interrupt-controller;
78 #interrupts-cells = <2>; 217 #interrupt-cells = <2>;
79 interrupts = <87>, <88>, <89>, <90>; 218 interrupts = <87>, <88>, <89>, <90>;
80 }; 219 };
81 220
@@ -86,7 +225,7 @@
86 gpio-controller; 225 gpio-controller;
87 #gpio-cells = <2>; 226 #gpio-cells = <2>;
88 interrupt-controller; 227 interrupt-controller;
89 #interrupts-cells = <2>; 228 #interrupt-cells = <2>;
90 interrupts = <91>; 229 interrupts = <91>;
91 }; 230 };
92 231
@@ -97,128 +236,6 @@
97 clocks = <&gateclk 1>; 236 clocks = <&gateclk 1>;
98 status = "disabled"; 237 status = "disabled";
99 }; 238 };
100
101 /*
102 * MV78260 has 3 PCIe units Gen2.0: Two units can be
103 * configured as x4 or quad x1 lanes. One unit is
104 * x4/x1.
105 */
106 pcie-controller {
107 compatible = "marvell,armada-xp-pcie";
108 status = "disabled";
109 device_type = "pci";
110
111 #address-cells = <3>;
112 #size-cells = <2>;
113
114 bus-range = <0x00 0xff>;
115
116 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
117 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
118 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
119 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
120 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
121 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
122 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
123 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
124 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
125
126 pcie@1,0 {
127 device_type = "pci";
128 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
129 reg = <0x0800 0 0 0 0>;
130 #address-cells = <3>;
131 #size-cells = <2>;
132 #interrupt-cells = <1>;
133 ranges;
134 interrupt-map-mask = <0 0 0 0>;
135 interrupt-map = <0 0 0 0 &mpic 58>;
136 marvell,pcie-port = <0>;
137 marvell,pcie-lane = <0>;
138 clocks = <&gateclk 5>;
139 status = "disabled";
140 };
141
142 pcie@2,0 {
143 device_type = "pci";
144 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
145 reg = <0x1000 0 0 0 0>;
146 #address-cells = <3>;
147 #size-cells = <2>;
148 #interrupt-cells = <1>;
149 ranges;
150 interrupt-map-mask = <0 0 0 0>;
151 interrupt-map = <0 0 0 0 &mpic 59>;
152 marvell,pcie-port = <0>;
153 marvell,pcie-lane = <1>;
154 clocks = <&gateclk 6>;
155 status = "disabled";
156 };
157
158 pcie@3,0 {
159 device_type = "pci";
160 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
161 reg = <0x1800 0 0 0 0>;
162 #address-cells = <3>;
163 #size-cells = <2>;
164 #interrupt-cells = <1>;
165 ranges;
166 interrupt-map-mask = <0 0 0 0>;
167 interrupt-map = <0 0 0 0 &mpic 60>;
168 marvell,pcie-port = <0>;
169 marvell,pcie-lane = <2>;
170 clocks = <&gateclk 7>;
171 status = "disabled";
172 };
173
174 pcie@4,0 {
175 device_type = "pci";
176 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
177 reg = <0x2000 0 0 0 0>;
178 #address-cells = <3>;
179 #size-cells = <2>;
180 #interrupt-cells = <1>;
181 ranges;
182 interrupt-map-mask = <0 0 0 0>;
183 interrupt-map = <0 0 0 0 &mpic 61>;
184 marvell,pcie-port = <0>;
185 marvell,pcie-lane = <3>;
186 clocks = <&gateclk 8>;
187 status = "disabled";
188 };
189
190 pcie@9,0 {
191 device_type = "pci";
192 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
193 reg = <0x4800 0 0 0 0>;
194 #address-cells = <3>;
195 #size-cells = <2>;
196 #interrupt-cells = <1>;
197 ranges;
198 interrupt-map-mask = <0 0 0 0>;
199 interrupt-map = <0 0 0 0 &mpic 99>;
200 marvell,pcie-port = <2>;
201 marvell,pcie-lane = <0>;
202 clocks = <&gateclk 26>;
203 status = "disabled";
204 };
205
206 pcie@10,0 {
207 device_type = "pci";
208 assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
209 reg = <0x5000 0 0 0 0>;
210 #address-cells = <3>;
211 #size-cells = <2>;
212 #interrupt-cells = <1>;
213 ranges;
214 interrupt-map-mask = <0 0 0 0>;
215 interrupt-map = <0 0 0 0 &mpic 103>;
216 marvell,pcie-port = <3>;
217 marvell,pcie-lane = <0>;
218 clocks = <&gateclk 27>;
219 status = "disabled";
220 };
221 };
222 }; 239 };
223 }; 240 };
224}; 241};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index c7b1f4d5c1c7..e82c1b80af17 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -13,7 +13,7 @@
13 * common to all Armada XP SoCs. 13 * common to all Armada XP SoCs.
14 */ 14 */
15 15
16/include/ "armada-xp.dtsi" 16#include "armada-xp.dtsi"
17 17
18/ { 18/ {
19 model = "Marvell Armada XP MV78460 SoC"; 19 model = "Marvell Armada XP MV78460 SoC";
@@ -61,6 +61,227 @@
61 }; 61 };
62 62
63 soc { 63 soc {
64 /*
65 * MV78460 has 4 PCIe units Gen2.0: Two units can be
66 * configured as x4 or quad x1 lanes. Two units are
67 * x4/x1.
68 */
69 pcie-controller {
70 compatible = "marvell,armada-xp-pcie";
71 status = "disabled";
72 device_type = "pci";
73
74 #address-cells = <3>;
75 #size-cells = <2>;
76
77 bus-range = <0x00 0xff>;
78
79 ranges =
80 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
81 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
82 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
83 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
84 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
85 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
86 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
87 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
88 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
89 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
90 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
91 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
92 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
93 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
94 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
95 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
96 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
97 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
98
99 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
100 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
101 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
102 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
103 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
104 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
105 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
106 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
107
108 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
109 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
110
111 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
112 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
113
114 pcie@1,0 {
115 device_type = "pci";
116 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
117 reg = <0x0800 0 0 0 0>;
118 #address-cells = <3>;
119 #size-cells = <2>;
120 #interrupt-cells = <1>;
121 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
122 0x81000000 0 0 0x81000000 0x1 0 1 0>;
123 interrupt-map-mask = <0 0 0 0>;
124 interrupt-map = <0 0 0 0 &mpic 58>;
125 marvell,pcie-port = <0>;
126 marvell,pcie-lane = <0>;
127 clocks = <&gateclk 5>;
128 status = "disabled";
129 };
130
131 pcie@2,0 {
132 device_type = "pci";
133 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
134 reg = <0x1000 0 0 0 0>;
135 #address-cells = <3>;
136 #size-cells = <2>;
137 #interrupt-cells = <1>;
138 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
139 0x81000000 0 0 0x81000000 0x2 0 1 0>;
140 interrupt-map-mask = <0 0 0 0>;
141 interrupt-map = <0 0 0 0 &mpic 59>;
142 marvell,pcie-port = <0>;
143 marvell,pcie-lane = <1>;
144 clocks = <&gateclk 6>;
145 status = "disabled";
146 };
147
148 pcie@3,0 {
149 device_type = "pci";
150 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
151 reg = <0x1800 0 0 0 0>;
152 #address-cells = <3>;
153 #size-cells = <2>;
154 #interrupt-cells = <1>;
155 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
156 0x81000000 0 0 0x81000000 0x3 0 1 0>;
157 interrupt-map-mask = <0 0 0 0>;
158 interrupt-map = <0 0 0 0 &mpic 60>;
159 marvell,pcie-port = <0>;
160 marvell,pcie-lane = <2>;
161 clocks = <&gateclk 7>;
162 status = "disabled";
163 };
164
165 pcie@4,0 {
166 device_type = "pci";
167 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
168 reg = <0x2000 0 0 0 0>;
169 #address-cells = <3>;
170 #size-cells = <2>;
171 #interrupt-cells = <1>;
172 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
173 0x81000000 0 0 0x81000000 0x4 0 1 0>;
174 interrupt-map-mask = <0 0 0 0>;
175 interrupt-map = <0 0 0 0 &mpic 61>;
176 marvell,pcie-port = <0>;
177 marvell,pcie-lane = <3>;
178 clocks = <&gateclk 8>;
179 status = "disabled";
180 };
181
182 pcie@5,0 {
183 device_type = "pci";
184 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
185 reg = <0x2800 0 0 0 0>;
186 #address-cells = <3>;
187 #size-cells = <2>;
188 #interrupt-cells = <1>;
189 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
190 0x81000000 0 0 0x81000000 0x5 0 1 0>;
191 interrupt-map-mask = <0 0 0 0>;
192 interrupt-map = <0 0 0 0 &mpic 62>;
193 marvell,pcie-port = <1>;
194 marvell,pcie-lane = <0>;
195 clocks = <&gateclk 9>;
196 status = "disabled";
197 };
198
199 pcie@6,0 {
200 device_type = "pci";
201 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
202 reg = <0x3000 0 0 0 0>;
203 #address-cells = <3>;
204 #size-cells = <2>;
205 #interrupt-cells = <1>;
206 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
207 0x81000000 0 0 0x81000000 0x6 0 1 0>;
208 interrupt-map-mask = <0 0 0 0>;
209 interrupt-map = <0 0 0 0 &mpic 63>;
210 marvell,pcie-port = <1>;
211 marvell,pcie-lane = <1>;
212 clocks = <&gateclk 10>;
213 status = "disabled";
214 };
215
216 pcie@7,0 {
217 device_type = "pci";
218 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
219 reg = <0x3800 0 0 0 0>;
220 #address-cells = <3>;
221 #size-cells = <2>;
222 #interrupt-cells = <1>;
223 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
224 0x81000000 0 0 0x81000000 0x7 0 1 0>;
225 interrupt-map-mask = <0 0 0 0>;
226 interrupt-map = <0 0 0 0 &mpic 64>;
227 marvell,pcie-port = <1>;
228 marvell,pcie-lane = <2>;
229 clocks = <&gateclk 11>;
230 status = "disabled";
231 };
232
233 pcie@8,0 {
234 device_type = "pci";
235 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
236 reg = <0x4000 0 0 0 0>;
237 #address-cells = <3>;
238 #size-cells = <2>;
239 #interrupt-cells = <1>;
240 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
241 0x81000000 0 0 0x81000000 0x8 0 1 0>;
242 interrupt-map-mask = <0 0 0 0>;
243 interrupt-map = <0 0 0 0 &mpic 65>;
244 marvell,pcie-port = <1>;
245 marvell,pcie-lane = <3>;
246 clocks = <&gateclk 12>;
247 status = "disabled";
248 };
249
250 pcie@9,0 {
251 device_type = "pci";
252 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
253 reg = <0x4800 0 0 0 0>;
254 #address-cells = <3>;
255 #size-cells = <2>;
256 #interrupt-cells = <1>;
257 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
258 0x81000000 0 0 0x81000000 0x9 0 1 0>;
259 interrupt-map-mask = <0 0 0 0>;
260 interrupt-map = <0 0 0 0 &mpic 99>;
261 marvell,pcie-port = <2>;
262 marvell,pcie-lane = <0>;
263 clocks = <&gateclk 26>;
264 status = "disabled";
265 };
266
267 pcie@10,0 {
268 device_type = "pci";
269 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
270 reg = <0x5000 0 0 0 0>;
271 #address-cells = <3>;
272 #size-cells = <2>;
273 #interrupt-cells = <1>;
274 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
275 0x81000000 0 0 0x81000000 0xa 0 1 0>;
276 interrupt-map-mask = <0 0 0 0>;
277 interrupt-map = <0 0 0 0 &mpic 103>;
278 marvell,pcie-port = <3>;
279 marvell,pcie-lane = <0>;
280 clocks = <&gateclk 27>;
281 status = "disabled";
282 };
283 };
284
64 internal-regs { 285 internal-regs {
65 pinctrl { 286 pinctrl {
66 compatible = "marvell,mv78460-pinctrl"; 287 compatible = "marvell,mv78460-pinctrl";
@@ -80,7 +301,7 @@
80 gpio-controller; 301 gpio-controller;
81 #gpio-cells = <2>; 302 #gpio-cells = <2>;
82 interrupt-controller; 303 interrupt-controller;
83 #interrupts-cells = <2>; 304 #interrupt-cells = <2>;
84 interrupts = <82>, <83>, <84>, <85>; 305 interrupts = <82>, <83>, <84>, <85>;
85 }; 306 };
86 307
@@ -91,7 +312,7 @@
91 gpio-controller; 312 gpio-controller;
92 #gpio-cells = <2>; 313 #gpio-cells = <2>;
93 interrupt-controller; 314 interrupt-controller;
94 #interrupts-cells = <2>; 315 #interrupt-cells = <2>;
95 interrupts = <87>, <88>, <89>, <90>; 316 interrupts = <87>, <88>, <89>, <90>;
96 }; 317 };
97 318
@@ -102,7 +323,7 @@
102 gpio-controller; 323 gpio-controller;
103 #gpio-cells = <2>; 324 #gpio-cells = <2>;
104 interrupt-controller; 325 interrupt-controller;
105 #interrupts-cells = <2>; 326 #interrupt-cells = <2>;
106 interrupts = <91>; 327 interrupts = <91>;
107 }; 328 };
108 329
@@ -113,194 +334,6 @@
113 clocks = <&gateclk 1>; 334 clocks = <&gateclk 1>;
114 status = "disabled"; 335 status = "disabled";
115 }; 336 };
116
117 /*
118 * MV78460 has 4 PCIe units Gen2.0: Two units can be
119 * configured as x4 or quad x1 lanes. Two units are
120 * x4/x1.
121 */
122 pcie-controller {
123 compatible = "marvell,armada-xp-pcie";
124 status = "disabled";
125 device_type = "pci";
126
127 #address-cells = <3>;
128 #size-cells = <2>;
129
130 bus-range = <0x00 0xff>;
131
132 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
133 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
134 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
135 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
136 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
137 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
138 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
139 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */
140 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */
141 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */
142 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
143 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
144
145 pcie@1,0 {
146 device_type = "pci";
147 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
148 reg = <0x0800 0 0 0 0>;
149 #address-cells = <3>;
150 #size-cells = <2>;
151 #interrupt-cells = <1>;
152 ranges;
153 interrupt-map-mask = <0 0 0 0>;
154 interrupt-map = <0 0 0 0 &mpic 58>;
155 marvell,pcie-port = <0>;
156 marvell,pcie-lane = <0>;
157 clocks = <&gateclk 5>;
158 status = "disabled";
159 };
160
161 pcie@2,0 {
162 device_type = "pci";
163 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
164 reg = <0x1000 0 0 0 0>;
165 #address-cells = <3>;
166 #size-cells = <2>;
167 #interrupt-cells = <1>;
168 ranges;
169 interrupt-map-mask = <0 0 0 0>;
170 interrupt-map = <0 0 0 0 &mpic 59>;
171 marvell,pcie-port = <0>;
172 marvell,pcie-lane = <1>;
173 clocks = <&gateclk 6>;
174 status = "disabled";
175 };
176
177 pcie@3,0 {
178 device_type = "pci";
179 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
180 reg = <0x1800 0 0 0 0>;
181 #address-cells = <3>;
182 #size-cells = <2>;
183 #interrupt-cells = <1>;
184 ranges;
185 interrupt-map-mask = <0 0 0 0>;
186 interrupt-map = <0 0 0 0 &mpic 60>;
187 marvell,pcie-port = <0>;
188 marvell,pcie-lane = <2>;
189 clocks = <&gateclk 7>;
190 status = "disabled";
191 };
192
193 pcie@4,0 {
194 device_type = "pci";
195 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
196 reg = <0x2000 0 0 0 0>;
197 #address-cells = <3>;
198 #size-cells = <2>;
199 #interrupt-cells = <1>;
200 ranges;
201 interrupt-map-mask = <0 0 0 0>;
202 interrupt-map = <0 0 0 0 &mpic 61>;
203 marvell,pcie-port = <0>;
204 marvell,pcie-lane = <3>;
205 clocks = <&gateclk 8>;
206 status = "disabled";
207 };
208
209 pcie@5,0 {
210 device_type = "pci";
211 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
212 reg = <0x2800 0 0 0 0>;
213 #address-cells = <3>;
214 #size-cells = <2>;
215 #interrupt-cells = <1>;
216 ranges;
217 interrupt-map-mask = <0 0 0 0>;
218 interrupt-map = <0 0 0 0 &mpic 62>;
219 marvell,pcie-port = <1>;
220 marvell,pcie-lane = <0>;
221 clocks = <&gateclk 9>;
222 status = "disabled";
223 };
224
225 pcie@6,0 {
226 device_type = "pci";
227 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
228 reg = <0x3000 0 0 0 0>;
229 #address-cells = <3>;
230 #size-cells = <2>;
231 #interrupt-cells = <1>;
232 ranges;
233 interrupt-map-mask = <0 0 0 0>;
234 interrupt-map = <0 0 0 0 &mpic 63>;
235 marvell,pcie-port = <1>;
236 marvell,pcie-lane = <1>;
237 clocks = <&gateclk 10>;
238 status = "disabled";
239 };
240
241 pcie@7,0 {
242 device_type = "pci";
243 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
244 reg = <0x3800 0 0 0 0>;
245 #address-cells = <3>;
246 #size-cells = <2>;
247 #interrupt-cells = <1>;
248 ranges;
249 interrupt-map-mask = <0 0 0 0>;
250 interrupt-map = <0 0 0 0 &mpic 64>;
251 marvell,pcie-port = <1>;
252 marvell,pcie-lane = <2>;
253 clocks = <&gateclk 11>;
254 status = "disabled";
255 };
256
257 pcie@8,0 {
258 device_type = "pci";
259 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
260 reg = <0x4000 0 0 0 0>;
261 #address-cells = <3>;
262 #size-cells = <2>;
263 #interrupt-cells = <1>;
264 ranges;
265 interrupt-map-mask = <0 0 0 0>;
266 interrupt-map = <0 0 0 0 &mpic 65>;
267 marvell,pcie-port = <1>;
268 marvell,pcie-lane = <3>;
269 clocks = <&gateclk 12>;
270 status = "disabled";
271 };
272 pcie@9,0 {
273 device_type = "pci";
274 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
275 reg = <0x4800 0 0 0 0>;
276 #address-cells = <3>;
277 #size-cells = <2>;
278 #interrupt-cells = <1>;
279 ranges;
280 interrupt-map-mask = <0 0 0 0>;
281 interrupt-map = <0 0 0 0 &mpic 99>;
282 marvell,pcie-port = <2>;
283 marvell,pcie-lane = <0>;
284 clocks = <&gateclk 26>;
285 status = "disabled";
286 };
287
288 pcie@10,0 {
289 device_type = "pci";
290 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
291 reg = <0x5000 0 0 0 0>;
292 #address-cells = <3>;
293 #size-cells = <2>;
294 #interrupt-cells = <1>;
295 ranges;
296 interrupt-map-mask = <0 0 0 0>;
297 interrupt-map = <0 0 0 0 &mpic 103>;
298 marvell,pcie-port = <3>;
299 marvell,pcie-lane = <0>;
300 clocks = <&gateclk 27>;
301 status = "disabled";
302 };
303 };
304 }; 337 };
305 }; 338 };
306}; 339};
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 8f510458ea86..5695afcc04bf 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -11,7 +11,7 @@
11 */ 11 */
12 12
13/dts-v1/; 13/dts-v1/;
14/include/ "armada-xp-mv78260.dtsi" 14#include "armada-xp-mv78260.dtsi"
15 15
16/ { 16/ {
17 model = "PlatHome OpenBlocks AX3-4 board"; 17 model = "PlatHome OpenBlocks AX3-4 board";
@@ -27,9 +27,46 @@
27 }; 27 };
28 28
29 soc { 29 soc {
30 ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ 30 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
31 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ 31 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
32 0xf0000000 0 0xf0000000 0x8000000 /* Device Bus, NOR 128MiB */>; 32 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
33
34 devbus-bootcs {
35 status = "okay";
36
37 /* Device Bus parameters are required */
38
39 /* Read parameters */
40 devbus,bus-width = <8>;
41 devbus,turn-off-ps = <60000>;
42 devbus,badr-skew-ps = <0>;
43 devbus,acc-first-ps = <124000>;
44 devbus,acc-next-ps = <248000>;
45 devbus,rd-setup-ps = <0>;
46 devbus,rd-hold-ps = <0>;
47
48 /* Write parameters */
49 devbus,sync-enable = <0>;
50 devbus,wr-high-ps = <60000>;
51 devbus,wr-low-ps = <60000>;
52 devbus,ale-wr-ps = <60000>;
53
54 /* NOR 128 MiB */
55 nor@0 {
56 compatible = "cfi-flash";
57 reg = <0 0x8000000>;
58 bank-width = <2>;
59 };
60 };
61
62 pcie-controller {
63 status = "okay";
64 /* Internal mini-PCIe connector */
65 pcie@1,0 {
66 /* Port 0, Lane 0 */
67 status = "okay";
68 };
69 };
33 70
34 internal-regs { 71 internal-regs {
35 serial@12000 { 72 serial@12000 {
@@ -148,49 +185,6 @@
148 usb@51000 { 185 usb@51000 {
149 status = "okay"; 186 status = "okay";
150 }; 187 };
151
152 /* USB interface in the mini-PCIe connector */
153 usb@52000 {
154 status = "okay";
155 };
156
157 devbus-bootcs@10400 {
158 status = "okay";
159 ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
160
161 /* Device Bus parameters are required */
162
163 /* Read parameters */
164 devbus,bus-width = <8>;
165 devbus,turn-off-ps = <60000>;
166 devbus,badr-skew-ps = <0>;
167 devbus,acc-first-ps = <124000>;
168 devbus,acc-next-ps = <248000>;
169 devbus,rd-setup-ps = <0>;
170 devbus,rd-hold-ps = <0>;
171
172 /* Write parameters */
173 devbus,sync-enable = <0>;
174 devbus,wr-high-ps = <60000>;
175 devbus,wr-low-ps = <60000>;
176 devbus,ale-wr-ps = <60000>;
177
178 /* NOR 128 MiB */
179 nor@0 {
180 compatible = "cfi-flash";
181 reg = <0 0x8000000>;
182 bank-width = <2>;
183 };
184 };
185
186 pcie-controller {
187 status = "okay";
188 /* Internal mini-PCIe connector */
189 pcie@1,0 {
190 /* Port 0, Lane 0 */
191 status = "okay";
192 };
193 };
194 }; 188 };
195 }; 189 };
196}; 190};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 416eb9481844..def125c0eeaa 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -16,7 +16,7 @@
16 * common to all Armada SoCs. 16 * common to all Armada SoCs.
17 */ 17 */
18 18
19/include/ "armada-370-xp.dtsi" 19#include "armada-370-xp.dtsi"
20 20
21/ { 21/ {
22 model = "Marvell Armada XP family SoC"; 22 model = "Marvell Armada XP family SoC";
@@ -27,6 +27,13 @@
27 }; 27 };
28 28
29 soc { 29 soc {
30 compatible = "marvell,armadaxp-mbus", "simple-bus";
31
32 bootrom {
33 compatible = "marvell,bootrom";
34 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
35 };
36
30 internal-regs { 37 internal-regs {
31 L2: l2-cache { 38 L2: l2-cache {
32 compatible = "marvell,aurora-system-cache"; 39 compatible = "marvell,aurora-system-cache";
@@ -62,7 +69,7 @@
62 }; 69 };
63 70
64 timer@20300 { 71 timer@20300 {
65 marvell,timer-25Mhz; 72 compatible = "marvell,armada-xp-timer";
66 }; 73 };
67 74
68 coreclk: mvebu-sar@18230 { 75 coreclk: mvebu-sar@18230 {
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index 5bce7cc55cf3..588ce58a2959 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -90,6 +90,17 @@
90 }; 90 };
91 }; 91 };
92 }; 92 };
93 mdio: mdio@1e24000 {
94 status = "okay";
95 pinctrl-names = "default";
96 pinctrl-0 = <&mdio_pins>;
97 bus_freq = <2200000>;
98 };
99 eth0: ethernet@1e20000 {
100 status = "okay";
101 pinctrl-names = "default";
102 pinctrl-0 = <&mii_pins>;
103 };
93 }; 104 };
94 nand_cs3@62000000 { 105 nand_cs3@62000000 {
95 status = "okay"; 106 status = "okay";
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index d70ba5504481..8d17346f9702 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -125,11 +125,33 @@
125 0x14 0x00000010 0x000000f0 125 0x14 0x00000010 0x000000f0
126 >; 126 >;
127 }; 127 };
128 mdio_pins: pinmux_mdio_pins {
129 pinctrl-single,bits = <
130 /* MDIO_CLK, MDIO_D */
131 0x10 0x00000088 0x000000ff
132 >;
133 };
134 mii_pins: pinmux_mii_pins {
135 pinctrl-single,bits = <
136 /*
137 * MII_TXEN, MII_TXCLK, MII_COL
138 * MII_TXD_3, MII_TXD_2, MII_TXD_1
139 * MII_TXD_0
140 */
141 0x8 0x88888880 0xfffffff0
142 /*
143 * MII_RXER, MII_CRS, MII_RXCLK
144 * MII_RXDV, MII_RXD_3, MII_RXD_2
145 * MII_RXD_1, MII_RXD_0
146 */
147 0xc 0x88888888 0xffffffff
148 >;
149 };
150
128 }; 151 };
129 serial0: serial@1c42000 { 152 serial0: serial@1c42000 {
130 compatible = "ns16550a"; 153 compatible = "ns16550a";
131 reg = <0x42000 0x100>; 154 reg = <0x42000 0x100>;
132 clock-frequency = <150000000>;
133 reg-shift = <2>; 155 reg-shift = <2>;
134 interrupts = <25>; 156 interrupts = <25>;
135 status = "disabled"; 157 status = "disabled";
@@ -137,7 +159,6 @@
137 serial1: serial@1d0c000 { 159 serial1: serial@1d0c000 {
138 compatible = "ns16550a"; 160 compatible = "ns16550a";
139 reg = <0x10c000 0x100>; 161 reg = <0x10c000 0x100>;
140 clock-frequency = <150000000>;
141 reg-shift = <2>; 162 reg-shift = <2>;
142 interrupts = <53>; 163 interrupts = <53>;
143 status = "disabled"; 164 status = "disabled";
@@ -145,7 +166,6 @@
145 serial2: serial@1d0d000 { 166 serial2: serial@1d0d000 {
146 compatible = "ns16550a"; 167 compatible = "ns16550a";
147 reg = <0x10d000 0x100>; 168 reg = <0x10d000 0x100>;
148 clock-frequency = <150000000>;
149 reg-shift = <2>; 169 reg-shift = <2>;
150 interrupts = <61>; 170 interrupts = <61>;
151 status = "disabled"; 171 status = "disabled";
@@ -216,6 +236,26 @@
216 interrupts = <56>; 236 interrupts = <56>;
217 status = "disabled"; 237 status = "disabled";
218 }; 238 };
239 mdio: mdio@1e24000 {
240 compatible = "ti,davinci_mdio";
241 #address-cells = <1>;
242 #size-cells = <0>;
243 reg = <0x224000 0x1000>;
244 };
245 eth0: ethernet@1e20000 {
246 compatible = "ti,davinci-dm6467-emac";
247 reg = <0x220000 0x4000>;
248 ti,davinci-ctrl-reg-offset = <0x3000>;
249 ti,davinci-ctrl-mod-reg-offset = <0x2000>;
250 ti,davinci-ctrl-ram-offset = <0>;
251 ti,davinci-ctrl-ram-size = <0x2000>;
252 local-mac-address = [ 00 00 00 00 00 00 ];
253 interrupts = <33
254 34
255 35
256 36
257 >;
258 };
219 }; 259 };
220 nand_cs3@62000000 { 260 nand_cs3@62000000 {
221 compatible = "ti,davinci-nand"; 261 compatible = "ti,davinci-nand";
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 701153992c69..737ed5da8f71 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -13,19 +13,35 @@
13 13
14/ { 14/ {
15 aliases { 15 aliases {
16 gpio0 = &gpio1;
17 gpio1 = &gpio2;
18 gpio2 = &gpio3;
19 gpio3 = &gpio4;
20 i2c0 = &i2c1;
21 i2c1 = &i2c2;
22 i2c2 = &i2c3;
16 serial0 = &uart1; 23 serial0 = &uart1;
17 serial1 = &uart2; 24 serial1 = &uart2;
18 serial2 = &uart3; 25 serial2 = &uart3;
19 serial3 = &uart4; 26 serial3 = &uart4;
20 serial4 = &uart5; 27 serial4 = &uart5;
21 gpio0 = &gpio1; 28 spi0 = &spi1;
22 gpio1 = &gpio2; 29 spi1 = &spi2;
23 gpio2 = &gpio3; 30 spi2 = &spi3;
24 gpio3 = &gpio4;
25 usb0 = &usbotg; 31 usb0 = &usbotg;
26 usb1 = &usbhost1; 32 usb1 = &usbhost1;
27 }; 33 };
28 34
35 cpus {
36 #address-cells = <0>;
37 #size-cells = <0>;
38
39 cpu {
40 compatible = "arm,arm926ej-s";
41 device_type = "cpu";
42 };
43 };
44
29 asic: asic-interrupt-controller@68000000 { 45 asic: asic-interrupt-controller@68000000 {
30 compatible = "fsl,imx25-asic", "fsl,avic"; 46 compatible = "fsl,imx25-asic", "fsl,avic";
31 interrupt-controller; 47 interrupt-controller;
@@ -377,7 +393,8 @@
377 status = "disabled"; 393 status = "disabled";
378 }; 394 };
379 395
380 lcdc@53fbc000 { 396 lcdc: lcdc@53fbc000 {
397 compatible = "fsl,imx25-fb", "fsl,imx21-fb";
381 reg = <0x53fbc000 0x4000>; 398 reg = <0x53fbc000 0x4000>;
382 interrupts = <39>; 399 interrupts = <39>;
383 clocks = <&clks 103>, <&clks 66>, <&clks 49>; 400 clocks = <&clks 103>, <&clks 66>, <&clks 49>;
@@ -424,6 +441,7 @@
424 reg = <0x53fd4000 0x4000>; 441 reg = <0x53fd4000 0x4000>;
425 clocks = <&clks 112>, <&clks 68>; 442 clocks = <&clks 112>, <&clks 68>;
426 clock-names = "ipg", "ahb"; 443 clock-names = "ipg", "ahb";
444 #dma-cells = <3>;
427 interrupts = <34>; 445 interrupts = <34>;
428 }; 446 };
429 447
@@ -444,6 +462,13 @@
444 interrupts = <26>; 462 interrupts = <26>;
445 }; 463 };
446 464
465 iim: iim@53ff0000 {
466 compatible = "fsl,imx25-iim", "fsl,imx27-iim";
467 reg = <0x53ff0000 0x4000>;
468 interrupts = <19>;
469 clocks = <&clks 99>;
470 };
471
447 usbphy1: usbphy@1 { 472 usbphy1: usbphy@1 {
448 compatible = "nop-usbphy"; 473 compatible = "nop-usbphy";
449 status = "disabled"; 474 status = "disabled";
diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts
index 66b8e1c1b0be..2a377ca1881a 100644
--- a/arch/arm/boot/dts/imx27-apf27dev.dts
+++ b/arch/arm/boot/dts/imx27-apf27dev.dts
@@ -53,6 +53,11 @@
53&i2c1 { 53&i2c1 {
54 clock-frequency = <400000>; 54 clock-frequency = <400000>;
55 status = "okay"; 55 status = "okay";
56
57 rtc@68 {
58 compatible = "dallas,ds1374";
59 reg = <0x68>;
60 };
56}; 61};
57 62
58&i2c2 { 63&i2c2 {
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
new file mode 100644
index 000000000000..5a31c776513f
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
@@ -0,0 +1,93 @@
1/*
2 * Copyright 2012 Markus Pargmann, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include "imx27-phytec-phycard-s-som.dts"
13
14/ {
15 model = "Phytec pca100 rapid development kit";
16 compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27";
17
18 display: display {
19 model = "Primeview-PD050VL1";
20 native-mode = <&timing0>;
21 bits-per-pixel = <16>; /* non-standard but required */
22 fsl,pcr = <0xf0c88080>; /* non-standard but required */
23 display-timings {
24 timing0: 640x480 {
25 hactive = <640>;
26 vactive = <480>;
27 hback-porch = <112>;
28 hfront-porch = <36>;
29 hsync-len = <32>;
30 vback-porch = <33>;
31 vfront-porch = <33>;
32 vsync-len = <2>;
33 clock-frequency = <25000000>;
34 };
35 };
36 };
37
38 regulators {
39 compatible = "simple-bus";
40
41 reg_3v3: 3v3 {
42 compatible = "regulator-fixed";
43 regulator-name = "3V3";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 regulator-always-on;
47 };
48 };
49};
50
51&fb {
52 display = <&display>;
53 status = "okay";
54};
55
56&i2c1 {
57 status = "okay";
58
59 rtc@51 {
60 compatible = "nxp,pcf8563";
61 reg = <0x51>;
62 };
63
64 adc@64 {
65 compatible = "maxim,max1037";
66 vcc-supply = <&reg_3v3>;
67 reg = <0x64>;
68 };
69};
70
71&owire {
72 status = "okay";
73};
74
75&sdhci2 {
76 cd-gpios = <&gpio3 29 0>;
77 status = "okay";
78};
79
80&uart1 {
81 fsl,uart-has-rtscts;
82 status = "okay";
83};
84
85&uart2 {
86 fsl,uart-has-rtscts;
87 status = "okay";
88};
89
90&uart3 {
91 fsl,uart-has-rtscts;
92 status = "okay";
93};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
new file mode 100644
index 000000000000..c8d57d1d0743
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
@@ -0,0 +1,44 @@
1/*
2 * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar
3 * and Markus Pargmann, Pengutronix
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14#include "imx27.dtsi"
15
16/ {
17 model = "Phytec pca100";
18 compatible = "phytec,imx27-pca100", "fsl,imx27";
19
20 memory {
21 reg = <0xa0000000 0x08000000>; /* 128MB */
22 };
23};
24
25&cspi1 {
26 fsl,spi-num-chipselects = <2>;
27 cs-gpios = <&gpio4 28 0>,
28 <&gpio4 27 0>;
29 status = "okay";
30};
31
32&fec {
33 status = "okay";
34};
35
36&i2c2 {
37 status = "okay";
38
39 at24@52 {
40 compatible = "at,24c32";
41 pagesize = <32>;
42 reg = <0x52>;
43 };
44};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
index e7ed9786920a..0fc6551786c6 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -35,3 +35,16 @@
35 fsl,uart-has-rtscts; 35 fsl,uart-has-rtscts;
36 status = "okay"; 36 status = "okay";
37}; 37};
38
39&weim {
40 can@d4000000 {
41 compatible = "nxp,sja1000";
42 reg = <4 0x00000000 0x00000100>;
43 interrupt-parent = <&gpio5>;
44 interrupts = <19 0x2>;
45 nxp,external-clock-frequency = <16000000>;
46 nxp,tx-output-config = <0x16>;
47 nxp,no-comparator-bypass;
48 fsl,weim-cs-timing = <0x0000dcf6 0x444a0301 0x44443302>;
49 };
50};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
index f0105651869d..4ec402c38945 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
@@ -17,49 +17,22 @@
17 compatible = "phytec,imx27-pcm038", "fsl,imx27"; 17 compatible = "phytec,imx27-pcm038", "fsl,imx27";
18 18
19 memory { 19 memory {
20 reg = <0x0 0x0>; 20 reg = <0xa0000000 0x08000000>;
21 }; 21 };
22};
22 23
23 soc { 24&audmux {
24 aipi@10000000 { /* aipi1 */ 25 status = "okay";
25 serial@1000a000 {
26 status = "okay";
27 };
28
29 i2c@1001d000 {
30 clock-frequency = <400000>;
31 status = "okay";
32 at24@52 {
33 compatible = "at,24c32";
34 pagesize = <32>;
35 reg = <0x52>;
36 };
37 pcf8563@51 {
38 compatible = "nxp,pcf8563";
39 reg = <0x51>;
40 };
41 lm75@4a {
42 compatible = "national,lm75";
43 reg = <0x4a>;
44 };
45 };
46 };
47 26
48 aipi@10020000 { /* aipi2 */ 27 /* SSI0 <=> PINS_4 (MC13783 Audio) */
49 ethernet@1002b000 { 28 ssi0 {
50 phy-reset-gpios = <&gpio3 30 0>; 29 fsl,audmux-port = <0>;
51 status = "okay"; 30 fsl,port-config = <0xcb205000>;
52 };
53 };
54 }; 31 };
55 32
56 nor_flash@c0000000 { 33 pins4 {
57 compatible = "cfi-flash"; 34 fsl,audmux-port = <2>;
58 bank-width = <2>; 35 fsl,port-config = <0x00001000>;
59 reg = <0xc0000000 0x02000000>;
60 linux,mtd-name = "physmap-flash.0";
61 #address-cells = <1>;
62 #size-cells = <1>;
63 }; 36 };
64}; 37};
65 38
@@ -80,28 +53,16 @@
80 fsl,mc13xxx-uses-rtc; 53 fsl,mc13xxx-uses-rtc;
81 54
82 regulators { 55 regulators {
83 sw1a_reg: sw1a { 56 /* SW1A and SW1B joined operation */
57 sw1_reg: sw1a {
84 regulator-min-microvolt = <1200000>; 58 regulator-min-microvolt = <1200000>;
85 regulator-max-microvolt = <1200000>; 59 regulator-max-microvolt = <1520000>;
86 regulator-always-on; 60 regulator-always-on;
87 regulator-boot-on; 61 regulator-boot-on;
88 }; 62 };
89 63
90 sw1b_reg: sw1b { 64 /* SW2A and SW2B joined operation */
91 regulator-min-microvolt = <1200000>; 65 sw2_reg: sw2a {
92 regulator-max-microvolt = <1200000>;
93 regulator-always-on;
94 regulator-boot-on;
95 };
96
97 sw2a_reg: sw2a {
98 regulator-min-microvolt = <1800000>;
99 regulator-max-microvolt = <1800000>;
100 regulator-always-on;
101 regulator-boot-on;
102 };
103
104 sw2b_reg: sw2b {
105 regulator-min-microvolt = <1800000>; 66 regulator-min-microvolt = <1800000>;
106 regulator-max-microvolt = <1800000>; 67 regulator-max-microvolt = <1800000>;
107 regulator-always-on; 68 regulator-always-on;
@@ -172,8 +133,62 @@
172 }; 133 };
173}; 134};
174 135
136&fec {
137 phy-reset-gpios = <&gpio3 30 0>;
138 status = "okay";
139};
140
141&i2c2 {
142 clock-frequency = <400000>;
143 status = "okay";
144
145 at24@52 {
146 compatible = "at,24c32";
147 pagesize = <32>;
148 reg = <0x52>;
149 };
150
151 pcf8563@51 {
152 compatible = "nxp,pcf8563";
153 reg = <0x51>;
154 };
155
156 lm75@4a {
157 compatible = "national,lm75";
158 reg = <0x4a>;
159 };
160};
161
175&nfc { 162&nfc {
176 nand-bus-width = <8>; 163 nand-bus-width = <8>;
177 nand-ecc-mode = "hw"; 164 nand-ecc-mode = "hw";
178 status = "okay"; 165 status = "okay";
179}; 166};
167
168&uart1 {
169 status = "okay";
170};
171
172&weim {
173 status = "okay";
174
175 nor: nor@c0000000 {
176 compatible = "cfi-flash";
177 reg = <0 0x00000000 0x02000000>;
178 bank-width = <2>;
179 linux,mtd-name = "physmap-flash.0";
180 fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>;
181 #address-cells = <1>;
182 #size-cells = <1>;
183 };
184
185 sram: sram@c8000000 {
186 compatible = "mtd-ram";
187 reg = <1 0x00000000 0x00800000>;
188 bank-width = <2>;
189 linux,mtd-name = "mtd-ram.0";
190 fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>;
191 #address-cells = <1>;
192 #size-cells = <1>;
193 };
194};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 0695264ddf1b..c037c223619a 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -13,25 +13,27 @@
13 13
14/ { 14/ {
15 aliases { 15 aliases {
16 serial0 = &uart1;
17 serial1 = &uart2;
18 serial2 = &uart3;
19 serial3 = &uart4;
20 serial4 = &uart5;
21 serial5 = &uart6;
22 gpio0 = &gpio1; 16 gpio0 = &gpio1;
23 gpio1 = &gpio2; 17 gpio1 = &gpio2;
24 gpio2 = &gpio3; 18 gpio2 = &gpio3;
25 gpio3 = &gpio4; 19 gpio3 = &gpio4;
26 gpio4 = &gpio5; 20 gpio4 = &gpio5;
27 gpio5 = &gpio6; 21 gpio5 = &gpio6;
22 i2c0 = &i2c1;
23 i2c1 = &i2c2;
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 serial3 = &uart4;
28 serial4 = &uart5;
29 serial5 = &uart6;
28 spi0 = &cspi1; 30 spi0 = &cspi1;
29 spi1 = &cspi2; 31 spi1 = &cspi2;
30 spi2 = &cspi3; 32 spi2 = &cspi3;
31 }; 33 };
32 34
33 avic: avic-interrupt-controller@e0000000 { 35 aitc: aitc-interrupt-controller@e0000000 {
34 compatible = "fsl,imx27-avic", "fsl,avic"; 36 compatible = "fsl,imx27-aitc", "fsl,avic";
35 interrupt-controller; 37 interrupt-controller;
36 #interrupt-cells = <1>; 38 #interrupt-cells = <1>;
37 reg = <0x10040000 0x1000>; 39 reg = <0x10040000 0x1000>;
@@ -47,11 +49,29 @@
47 }; 49 };
48 }; 50 };
49 51
52 cpus {
53 #size-cells = <0>;
54 #address-cells = <1>;
55
56 cpu: cpu@0 {
57 device_type = "cpu";
58 compatible = "arm,arm926ej-s";
59 operating-points = <
60 /* kHz uV */
61 266000 1300000
62 399000 1450000
63 >;
64 clock-latency = <62500>;
65 clocks = <&clks 18>;
66 voltage-tolerance = <5>;
67 };
68 };
69
50 soc { 70 soc {
51 #address-cells = <1>; 71 #address-cells = <1>;
52 #size-cells = <1>; 72 #size-cells = <1>;
53 compatible = "simple-bus"; 73 compatible = "simple-bus";
54 interrupt-parent = <&avic>; 74 interrupt-parent = <&aitc>;
55 ranges; 75 ranges;
56 76
57 aipi@10000000 { /* AIPI1 */ 77 aipi@10000000 { /* AIPI1 */
@@ -75,7 +95,7 @@
75 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; 95 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
76 reg = <0x10002000 0x1000>; 96 reg = <0x10002000 0x1000>;
77 interrupts = <27>; 97 interrupts = <27>;
78 clocks = <&clks 0>; 98 clocks = <&clks 74>;
79 }; 99 };
80 100
81 gpt1: timer@10003000 { 101 gpt1: timer@10003000 {
@@ -102,7 +122,7 @@
102 clock-names = "ipg", "per"; 122 clock-names = "ipg", "per";
103 }; 123 };
104 124
105 pwm0: pwm@10006000 { 125 pwm: pwm@10006000 {
106 compatible = "fsl,imx27-pwm"; 126 compatible = "fsl,imx27-pwm";
107 reg = <0x10006000 0x1000>; 127 reg = <0x10006000 0x1000>;
108 interrupts = <23>; 128 interrupts = <23>;
@@ -110,6 +130,21 @@
110 clock-names = "ipg", "per"; 130 clock-names = "ipg", "per";
111 }; 131 };
112 132
133 kpp: kpp@10008000 {
134 compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
135 reg = <0x10008000 0x1000>;
136 interrupts = <21>;
137 clocks = <&clks 37>;
138 status = "disabled";
139 };
140
141 owire: owire@10009000 {
142 compatible = "fsl,imx27-owire", "fsl,imx21-owire";
143 reg = <0x10009000 0x1000>;
144 clocks = <&clks 35>;
145 status = "disabled";
146 };
147
113 uart1: serial@1000a000 { 148 uart1: serial@1000a000 {
114 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 149 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
115 reg = <0x1000a000 0x1000>; 150 reg = <0x1000a000 0x1000>;
@@ -260,6 +295,14 @@
260 #interrupt-cells = <2>; 295 #interrupt-cells = <2>;
261 }; 296 };
262 297
298 audmux: audmux@10016000 {
299 compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
300 reg = <0x10016000 0x1000>;
301 clocks = <&clks 0>;
302 clock-names = "audmux";
303 status = "disabled";
304 };
305
263 cspi3: cspi@10017000 { 306 cspi3: cspi@10017000 {
264 #address-cells = <1>; 307 #address-cells = <1>;
265 #size-cells = <0>; 308 #size-cells = <0>;
@@ -342,6 +385,15 @@
342 reg = <0x10020000 0x20000>; 385 reg = <0x10020000 0x20000>;
343 ranges; 386 ranges;
344 387
388 fb: fb@10021000 {
389 compatible = "fsl,imx27-fb", "fsl,imx21-fb";
390 interrupts = <61>;
391 reg = <0x10021000 0x1000>;
392 clocks = <&clks 36>, <&clks 65>, <&clks 59>;
393 clock-names = "ipg", "ahb", "per";
394 status = "disabled";
395 };
396
345 coda: coda@10023000 { 397 coda: coda@10023000 {
346 compatible = "fsl,imx27-vpu"; 398 compatible = "fsl,imx27-vpu";
347 reg = <0x10023000 0x0200>; 399 reg = <0x10023000 0x0200>;
@@ -351,27 +403,37 @@
351 iram = <&iram>; 403 iram = <&iram>;
352 }; 404 };
353 405
406 sahara2: sahara@10025000 {
407 compatible = "fsl,imx27-sahara";
408 reg = <0x10025000 0x1000>;
409 interrupts = <59>;
410 clocks = <&clks 32>, <&clks 64>;
411 clock-names = "ipg", "ahb";
412 };
413
354 clks: ccm@10027000{ 414 clks: ccm@10027000{
355 compatible = "fsl,imx27-ccm"; 415 compatible = "fsl,imx27-ccm";
356 reg = <0x10027000 0x1000>; 416 reg = <0x10027000 0x1000>;
357 #clock-cells = <1>; 417 #clock-cells = <1>;
358 }; 418 };
359 419
420 iim: iim@10028000 {
421 compatible = "fsl,imx27-iim";
422 reg = <0x10028000 0x1000>;
423 interrupts = <62>;
424 clocks = <&clks 38>;
425 };
426
360 fec: ethernet@1002b000 { 427 fec: ethernet@1002b000 {
361 compatible = "fsl,imx27-fec"; 428 compatible = "fsl,imx27-fec";
362 reg = <0x1002b000 0x4000>; 429 reg = <0x1002b000 0x4000>;
363 interrupts = <50>; 430 interrupts = <50>;
364 clocks = <&clks 48>, <&clks 67>, <&clks 0>; 431 clocks = <&clks 48>, <&clks 67>;
365 clock-names = "ipg", "ahb", "ptp"; 432 clock-names = "ipg", "ahb";
366 status = "disabled"; 433 status = "disabled";
367 }; 434 };
368 }; 435 };
369 436
370 iram: iram@ffff4c00 {
371 compatible = "mmio-sram";
372 reg = <0xffff4c00 0xb400>;
373 };
374
375 nfc: nand@d8000000 { 437 nfc: nand@d8000000 {
376 #address-cells = <1>; 438 #address-cells = <1>;
377 #size-cells = <1>; 439 #size-cells = <1>;
@@ -381,5 +443,27 @@
381 clocks = <&clks 54>; 443 clocks = <&clks 54>;
382 status = "disabled"; 444 status = "disabled";
383 }; 445 };
446
447 weim: weim@d8002000 {
448 #address-cells = <2>;
449 #size-cells = <1>;
450 compatible = "fsl,imx27-weim";
451 reg = <0xd8002000 0x1000>;
452 clocks = <&clks 0>;
453 ranges = <
454 0 0 0xc0000000 0x08000000
455 1 0 0xc8000000 0x08000000
456 2 0 0xd0000000 0x02000000
457 3 0 0xd2000000 0x02000000
458 4 0 0xd4000000 0x02000000
459 5 0 0xd6000000 0x02000000
460 >;
461 status = "disabled";
462 };
463
464 iram: iram@ffff4c00 {
465 compatible = "mmio-sram";
466 reg = <0xffff4c00 0xb400>;
467 };
384 }; 468 };
385}; 469};
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
index c5449257ad9a..c34f82581248 100644
--- a/arch/arm/boot/dts/imx31.dtsi
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -20,6 +20,16 @@
20 serial4 = &uart5; 20 serial4 = &uart5;
21 }; 21 };
22 22
23 cpus {
24 #address-cells = <0>;
25 #size-cells = <0>;
26
27 cpu {
28 compatible = "arm,arm1136";
29 device_type = "cpu";
30 };
31 };
32
23 avic: avic-interrupt-controller@60000000 { 33 avic: avic-interrupt-controller@60000000 {
24 compatible = "fsl,imx31-avic", "fsl,avic"; 34 compatible = "fsl,imx31-avic", "fsl,avic";
25 interrupt-controller; 35 interrupt-controller;
@@ -94,6 +104,13 @@
94 status = "disabled"; 104 status = "disabled";
95 }; 105 };
96 106
107 iim: iim@5001c000 {
108 compatible = "fsl,imx31-iim", "fsl,imx27-iim";
109 reg = <0x5001c000 0x1000>;
110 interrupts = <19>;
111 clocks = <&clks 25>;
112 };
113
97 clks: ccm@53f80000{ 114 clks: ccm@53f80000{
98 compatible = "fsl,imx31-ccm"; 115 compatible = "fsl,imx31-ccm";
99 reg = <0x53f80000 0x4000>; 116 reg = <0x53f80000 0x4000>;
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
index 8f7f9ac0b989..b3606993f2e8 100644
--- a/arch/arm/boot/dts/imx51-apf51.dts
+++ b/arch/arm/boot/dts/imx51-apf51.dts
@@ -26,10 +26,6 @@
26 }; 26 };
27 27
28 clocks { 28 clocks {
29 ckih1 {
30 clock-frequency = <0>;
31 };
32
33 osc { 29 osc {
34 clock-frequency = <33554432>; 30 clock-frequency = <33554432>;
35 }; 31 };
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index ad3471ca17c7..1d337d99ecd5 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -63,6 +63,10 @@
63 }; 63 };
64 64
65 clocks { 65 clocks {
66 ckih1 {
67 clock-frequency = <22579200>;
68 };
69
66 clk_26M: codec_clock { 70 clk_26M: codec_clock {
67 compatible = "fixed-clock"; 71 compatible = "fixed-clock";
68 reg=<0>; 72 reg=<0>;
@@ -108,6 +112,7 @@
108 #size-cells = <0>; 112 #size-cells = <0>;
109 compatible = "fsl,mc13892"; 113 compatible = "fsl,mc13892";
110 spi-max-frequency = <6000000>; 114 spi-max-frequency = <6000000>;
115 spi-cs-high;
111 reg = <0>; 116 reg = <0>;
112 interrupt-parent = <&gpio1>; 117 interrupt-parent = <&gpio1>;
113 interrupts = <8 0x4>; 118 interrupts = <8 0x4>;
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 25764b505a61..a85abb424c34 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -15,13 +15,18 @@
15 15
16/ { 16/ {
17 aliases { 17 aliases {
18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
21 gpio0 = &gpio1; 18 gpio0 = &gpio1;
22 gpio1 = &gpio2; 19 gpio1 = &gpio2;
23 gpio2 = &gpio3; 20 gpio2 = &gpio3;
24 gpio3 = &gpio4; 21 gpio3 = &gpio4;
22 i2c0 = &i2c1;
23 i2c1 = &i2c2;
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 spi0 = &ecspi1;
28 spi1 = &ecspi2;
29 spi2 = &cspi;
25 }; 30 };
26 31
27 tzic: tz-interrupt-controller@e0000000 { 32 tzic: tz-interrupt-controller@e0000000 {
@@ -42,7 +47,7 @@
42 47
43 ckih1 { 48 ckih1 {
44 compatible = "fsl,imx-ckih1", "fixed-clock"; 49 compatible = "fsl,imx-ckih1", "fixed-clock";
45 clock-frequency = <22579200>; 50 clock-frequency = <0>;
46 }; 51 };
47 52
48 ckih2 { 53 ckih2 {
@@ -149,6 +154,9 @@
149 reg = <0x70014000 0x4000>; 154 reg = <0x70014000 0x4000>;
150 interrupts = <30>; 155 interrupts = <30>;
151 clocks = <&clks 49>; 156 clocks = <&clks 49>;
157 dmas = <&sdma 24 1 0>,
158 <&sdma 25 1 0>;
159 dma-names = "rx", "tx";
152 fsl,fifo-depth = <15>; 160 fsl,fifo-depth = <15>;
153 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ 161 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
154 status = "disabled"; 162 status = "disabled";
@@ -300,275 +308,6 @@
300 iomuxc: iomuxc@73fa8000 { 308 iomuxc: iomuxc@73fa8000 {
301 compatible = "fsl,imx51-iomuxc"; 309 compatible = "fsl,imx51-iomuxc";
302 reg = <0x73fa8000 0x4000>; 310 reg = <0x73fa8000 0x4000>;
303
304 audmux {
305 pinctrl_audmux_1: audmuxgrp-1 {
306 fsl,pins = <
307 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
308 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
309 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
310 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
311 >;
312 };
313 };
314
315 fec {
316 pinctrl_fec_1: fecgrp-1 {
317 fsl,pins = <
318 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
319 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
320 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
321 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
322 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
323 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
324 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
325 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
326 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
327 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
328 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
329 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
330 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
331 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
332 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
333 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
334 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
335 >;
336 };
337
338 pinctrl_fec_2: fecgrp-2 {
339 fsl,pins = <
340 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
341 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
342 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
343 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
344 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
345 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
346 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
347 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
348 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
349 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
350 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
351 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
352 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
353 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
354 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
355 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
356 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
357 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
358 >;
359 };
360 };
361
362 ecspi1 {
363 pinctrl_ecspi1_1: ecspi1grp-1 {
364 fsl,pins = <
365 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
366 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
367 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
368 >;
369 };
370 };
371
372 ecspi2 {
373 pinctrl_ecspi2_1: ecspi2grp-1 {
374 fsl,pins = <
375 MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
376 MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
377 MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
378 >;
379 };
380 };
381
382 esdhc1 {
383 pinctrl_esdhc1_1: esdhc1grp-1 {
384 fsl,pins = <
385 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
386 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
387 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
388 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
389 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
390 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
391 >;
392 };
393 };
394
395 esdhc2 {
396 pinctrl_esdhc2_1: esdhc2grp-1 {
397 fsl,pins = <
398 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
399 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
400 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
401 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
402 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
403 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
404 >;
405 };
406 };
407
408 i2c2 {
409 pinctrl_i2c2_1: i2c2grp-1 {
410 fsl,pins = <
411 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
412 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
413 >;
414 };
415
416 pinctrl_i2c2_2: i2c2grp-2 {
417 fsl,pins = <
418 MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
419 MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
420 >;
421 };
422 };
423
424 ipu_disp1 {
425 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
426 fsl,pins = <
427 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
428 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
429 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
430 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
431 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
432 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
433 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
434 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
435 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
436 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
437 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
438 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
439 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
440 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
441 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
442 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
443 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
444 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
445 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
446 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
447 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
448 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
449 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
450 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
451 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
452 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
453 >;
454 };
455 };
456
457 ipu_disp2 {
458 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
459 fsl,pins = <
460 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
461 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
462 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
463 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
464 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
465 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
466 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
467 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
468 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
469 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
470 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
471 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
472 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
473 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
474 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
475 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
476 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
477 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
478 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
479 MX51_PAD_DI_GP4__DI2_PIN15 0x5
480 >;
481 };
482 };
483
484 pata {
485 pinctrl_pata_1: patagrp-1 {
486 fsl,pins = <
487 MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
488 MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
489 MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
490 MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
491 MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
492 MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
493 MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
494 MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
495 MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
496 MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
497 MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
498 MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
499 MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
500 MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
501 MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
502 MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
503 MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
504 MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
505 MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
506 MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
507 MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
508 MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
509 MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
510 MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
511 MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
512 MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
513 MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
514 MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
515 MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
516 >;
517 };
518 };
519
520 uart1 {
521 pinctrl_uart1_1: uart1grp-1 {
522 fsl,pins = <
523 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
524 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
525 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
526 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
527 >;
528 };
529 };
530
531 uart2 {
532 pinctrl_uart2_1: uart2grp-1 {
533 fsl,pins = <
534 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
535 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
536 >;
537 };
538 };
539
540 uart3 {
541 pinctrl_uart3_1: uart3grp-1 {
542 fsl,pins = <
543 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
544 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
545 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
546 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
547 >;
548 };
549
550 pinctrl_uart3_2: uart3grp-2 {
551 fsl,pins = <
552 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
553 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
554 >;
555 };
556 };
557
558 kpp {
559 pinctrl_kpp_1: kppgrp-1 {
560 fsl,pins = <
561 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
562 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
563 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
564 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
565 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
566 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
567 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
568 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
569 >;
570 };
571 };
572 }; 311 };
573 312
574 pwm1: pwm@73fb4000 { 313 pwm1: pwm@73fb4000 {
@@ -628,6 +367,13 @@
628 reg = <0x80000000 0x10000000>; 367 reg = <0x80000000 0x10000000>;
629 ranges; 368 ranges;
630 369
370 iim: iim@83f98000 {
371 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
372 reg = <0x83f98000 0x4000>;
373 interrupts = <69>;
374 clocks = <&clks 107>;
375 };
376
631 ecspi2: ecspi@83fac000 { 377 ecspi2: ecspi@83fac000 {
632 #address-cells = <1>; 378 #address-cells = <1>;
633 #size-cells = <0>; 379 #size-cells = <0>;
@@ -645,6 +391,7 @@
645 interrupts = <6>; 391 interrupts = <6>;
646 clocks = <&clks 56>, <&clks 56>; 392 clocks = <&clks 56>, <&clks 56>;
647 clock-names = "ipg", "ahb"; 393 clock-names = "ipg", "ahb";
394 #dma-cells = <3>;
648 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; 395 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
649 }; 396 };
650 397
@@ -684,6 +431,9 @@
684 reg = <0x83fcc000 0x4000>; 431 reg = <0x83fcc000 0x4000>;
685 interrupts = <29>; 432 interrupts = <29>;
686 clocks = <&clks 48>; 433 clocks = <&clks 48>;
434 dmas = <&sdma 28 0 0>,
435 <&sdma 29 0 0>;
436 dma-names = "rx", "tx";
687 fsl,fifo-depth = <15>; 437 fsl,fifo-depth = <15>;
688 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ 438 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
689 status = "disabled"; 439 status = "disabled";
@@ -695,6 +445,23 @@
695 status = "disabled"; 445 status = "disabled";
696 }; 446 };
697 447
448 weim: weim@83fda000 {
449 #address-cells = <2>;
450 #size-cells = <1>;
451 compatible = "fsl,imx51-weim";
452 reg = <0x83fda000 0x1000>;
453 clocks = <&clks 57>;
454 ranges = <
455 0 0 0xb0000000 0x08000000
456 1 0 0xb8000000 0x08000000
457 2 0 0xc0000000 0x08000000
458 3 0 0xc8000000 0x04000000
459 4 0 0xcc000000 0x02000000
460 5 0 0xce000000 0x02000000
461 >;
462 status = "disabled";
463 };
464
698 nfc: nand@83fdb000 { 465 nfc: nand@83fdb000 {
699 compatible = "fsl,imx51-nand"; 466 compatible = "fsl,imx51-nand";
700 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; 467 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
@@ -716,6 +483,9 @@
716 reg = <0x83fe8000 0x4000>; 483 reg = <0x83fe8000 0x4000>;
717 interrupts = <96>; 484 interrupts = <96>;
718 clocks = <&clks 50>; 485 clocks = <&clks 50>;
486 dmas = <&sdma 46 0 0>,
487 <&sdma 47 0 0>;
488 dma-names = "rx", "tx";
719 fsl,fifo-depth = <15>; 489 fsl,fifo-depth = <15>;
720 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */ 490 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
721 status = "disabled"; 491 status = "disabled";
@@ -732,3 +502,319 @@
732 }; 502 };
733 }; 503 };
734}; 504};
505
506&iomuxc {
507 audmux {
508 pinctrl_audmux_1: audmuxgrp-1 {
509 fsl,pins = <
510 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
511 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
512 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
513 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
514 >;
515 };
516 };
517
518 fec {
519 pinctrl_fec_1: fecgrp-1 {
520 fsl,pins = <
521 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
522 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
523 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
524 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
525 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
526 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
527 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
528 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
529 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
530 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
531 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
532 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
533 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
534 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
535 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
536 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
537 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
538 >;
539 };
540
541 pinctrl_fec_2: fecgrp-2 {
542 fsl,pins = <
543 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
544 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
545 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
546 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
547 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
548 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
549 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
550 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
551 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
552 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
553 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
554 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
555 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
556 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
557 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
558 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
559 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
560 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
561 >;
562 };
563 };
564
565 ecspi1 {
566 pinctrl_ecspi1_1: ecspi1grp-1 {
567 fsl,pins = <
568 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
569 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
570 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
571 >;
572 };
573 };
574
575 ecspi2 {
576 pinctrl_ecspi2_1: ecspi2grp-1 {
577 fsl,pins = <
578 MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
579 MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
580 MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
581 >;
582 };
583 };
584
585 esdhc1 {
586 pinctrl_esdhc1_1: esdhc1grp-1 {
587 fsl,pins = <
588 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
589 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
590 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
591 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
592 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
593 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
594 >;
595 };
596 };
597
598 esdhc2 {
599 pinctrl_esdhc2_1: esdhc2grp-1 {
600 fsl,pins = <
601 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
602 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
603 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
604 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
605 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
606 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
607 >;
608 };
609 };
610
611 i2c2 {
612 pinctrl_i2c2_1: i2c2grp-1 {
613 fsl,pins = <
614 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
615 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
616 >;
617 };
618
619 pinctrl_i2c2_2: i2c2grp-2 {
620 fsl,pins = <
621 MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
622 MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
623 >;
624 };
625
626 pinctrl_i2c2_3: i2c2grp-3 {
627 fsl,pins = <
628 MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed
629 MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
630 >;
631 };
632 };
633
634 ipu_disp1 {
635 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
636 fsl,pins = <
637 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
638 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
639 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
640 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
641 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
642 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
643 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
644 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
645 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
646 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
647 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
648 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
649 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
650 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
651 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
652 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
653 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
654 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
655 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
656 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
657 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
658 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
659 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
660 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
661 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
662 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
663 >;
664 };
665 };
666
667 ipu_disp2 {
668 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
669 fsl,pins = <
670 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
671 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
672 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
673 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
674 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
675 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
676 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
677 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
678 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
679 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
680 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
681 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
682 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
683 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
684 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
685 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
686 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
687 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
688 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 /* CLK */
689 MX51_PAD_DI_GP4__DI2_PIN15 0x5 /* DE */
690 >;
691 };
692 };
693
694 kpp {
695 pinctrl_kpp_1: kppgrp-1 {
696 fsl,pins = <
697 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
698 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
699 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
700 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
701 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
702 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
703 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
704 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
705 >;
706 };
707 };
708
709 pata {
710 pinctrl_pata_1: patagrp-1 {
711 fsl,pins = <
712 MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
713 MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
714 MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
715 MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
716 MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
717 MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
718 MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
719 MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
720 MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
721 MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
722 MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
723 MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
724 MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
725 MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
726 MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
727 MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
728 MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
729 MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
730 MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
731 MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
732 MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
733 MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
734 MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
735 MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
736 MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
737 MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
738 MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
739 MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
740 MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
741 >;
742 };
743 };
744
745 uart1 {
746 pinctrl_uart1_1: uart1grp-1 {
747 fsl,pins = <
748 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
749 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
750 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
751 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
752 >;
753 };
754 };
755
756 uart2 {
757 pinctrl_uart2_1: uart2grp-1 {
758 fsl,pins = <
759 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
760 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
761 >;
762 };
763 };
764
765 uart3 {
766 pinctrl_uart3_1: uart3grp-1 {
767 fsl,pins = <
768 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
769 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
770 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
771 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
772 >;
773 };
774
775 pinctrl_uart3_2: uart3grp-2 {
776 fsl,pins = <
777 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
778 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
779 >;
780 };
781 };
782
783 usbh1 {
784 pinctrl_usbh1_1: usbh1grp-1 {
785 fsl,pins = <
786 MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
787 MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
788 MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
789 MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
790 MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
791 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
792 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
793 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
794 MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
795 MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
796 MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
797 MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
798 >;
799 };
800 };
801
802 usbh2 {
803 pinctrl_usbh2_1: usbh2grp-1 {
804 fsl,pins = <
805 MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5
806 MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5
807 MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5
808 MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5
809 MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5
810 MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5
811 MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5
812 MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5
813 MX51_PAD_EIM_A24__USBH2_CLK 0x1e5
814 MX51_PAD_EIM_A25__USBH2_DIR 0x1e5
815 MX51_PAD_EIM_A27__USBH2_NXT 0x1e5
816 MX51_PAD_EIM_A26__USBH2_STP 0x1e5
817 >;
818 };
819 };
820};
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 512a1f608253..e97ddae09d74 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -93,6 +93,15 @@
93 regulator-max-microvolt = <3200000>; 93 regulator-max-microvolt = <3200000>;
94 regulator-always-on; 94 regulator-always-on;
95 }; 95 };
96
97 reg_usb_vbus: usb_vbus {
98 compatible = "regulator-fixed";
99 regulator-name = "usb_vbus";
100 regulator-min-microvolt = <5000000>;
101 regulator-max-microvolt = <5000000>;
102 gpio = <&gpio7 8 0>;
103 enable-active-high;
104 };
96 }; 105 };
97 106
98 sound { 107 sound {
@@ -145,6 +154,7 @@
145 MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 154 MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
146 MX53_PAD_EIM_DA13__GPIO3_13 0x80000000 155 MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
147 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 156 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
157 MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000
148 MX53_PAD_GPIO_16__GPIO7_11 0x80000000 158 MX53_PAD_GPIO_16__GPIO7_11 0x80000000
149 >; 159 >;
150 }; 160 };
@@ -297,8 +307,14 @@
297 status = "okay"; 307 status = "okay";
298}; 308};
299 309
310&vpu {
311 status = "okay";
312};
313
300&usbh1 { 314&usbh1 {
301 status = "okay"; 315 vbus-supply = <&reg_usb_vbus>;
316 phy_type = "utmi";
317 status = "okay";
302}; 318};
303 319
304&usbotg { 320&usbotg {
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 569aa9f2c4ed..4307e80b2d2e 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -15,11 +15,6 @@
15 15
16/ { 16/ {
17 aliases { 17 aliases {
18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
21 serial3 = &uart4;
22 serial4 = &uart5;
23 gpio0 = &gpio1; 18 gpio0 = &gpio1;
24 gpio1 = &gpio2; 19 gpio1 = &gpio2;
25 gpio2 = &gpio3; 20 gpio2 = &gpio3;
@@ -30,6 +25,24 @@
30 i2c0 = &i2c1; 25 i2c0 = &i2c1;
31 i2c1 = &i2c2; 26 i2c1 = &i2c2;
32 i2c2 = &i2c3; 27 i2c2 = &i2c3;
28 serial0 = &uart1;
29 serial1 = &uart2;
30 serial2 = &uart3;
31 serial3 = &uart4;
32 serial4 = &uart5;
33 spi0 = &ecspi1;
34 spi1 = &ecspi2;
35 spi2 = &cspi;
36 };
37
38 cpus {
39 #address-cells = <1>;
40 #size-cells = <0>;
41 cpu@0 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a8";
44 reg = <0x0>;
45 };
33 }; 46 };
34 47
35 tzic: tz-interrupt-controller@0fffc000 { 48 tzic: tz-interrupt-controller@0fffc000 {
@@ -140,6 +153,9 @@
140 reg = <0x50014000 0x4000>; 153 reg = <0x50014000 0x4000>;
141 interrupts = <30>; 154 interrupts = <30>;
142 clocks = <&clks 49>; 155 clocks = <&clks 49>;
156 dmas = <&sdma 24 1 0>,
157 <&sdma 25 1 0>;
158 dma-names = "rx", "tx";
143 fsl,fifo-depth = <15>; 159 fsl,fifo-depth = <15>;
144 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ 160 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
145 status = "disabled"; 161 status = "disabled";
@@ -957,6 +973,13 @@
957 reg = <0x60000000 0x10000000>; 973 reg = <0x60000000 0x10000000>;
958 ranges; 974 ranges;
959 975
976 iim: iim@63f98000 {
977 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
978 reg = <0x63f98000 0x4000>;
979 interrupts = <69>;
980 clocks = <&clks 107>;
981 };
982
960 uart5: serial@63f90000 { 983 uart5: serial@63f90000 {
961 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 984 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
962 reg = <0x63f90000 0x4000>; 985 reg = <0x63f90000 0x4000>;
@@ -990,6 +1013,7 @@
990 interrupts = <6>; 1013 interrupts = <6>;
991 clocks = <&clks 56>, <&clks 56>; 1014 clocks = <&clks 56>, <&clks 56>;
992 clock-names = "ipg", "ahb"; 1015 clock-names = "ipg", "ahb";
1016 #dma-cells = <3>;
993 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; 1017 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
994 }; 1018 };
995 1019
@@ -1029,6 +1053,9 @@
1029 reg = <0x63fcc000 0x4000>; 1053 reg = <0x63fcc000 0x4000>;
1030 interrupts = <29>; 1054 interrupts = <29>;
1031 clocks = <&clks 48>; 1055 clocks = <&clks 48>;
1056 dmas = <&sdma 28 0 0>,
1057 <&sdma 29 0 0>;
1058 dma-names = "rx", "tx";
1032 fsl,fifo-depth = <15>; 1059 fsl,fifo-depth = <15>;
1033 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ 1060 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
1034 status = "disabled"; 1061 status = "disabled";
@@ -1053,6 +1080,9 @@
1053 reg = <0x63fe8000 0x4000>; 1080 reg = <0x63fe8000 0x4000>;
1054 interrupts = <96>; 1081 interrupts = <96>;
1055 clocks = <&clks 50>; 1082 clocks = <&clks 50>;
1083 dmas = <&sdma 46 0 0>,
1084 <&sdma 47 0 0>;
1085 dma-names = "rx", "tx";
1056 fsl,fifo-depth = <15>; 1086 fsl,fifo-depth = <15>;
1057 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */ 1087 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
1058 status = "disabled"; 1088 status = "disabled";
@@ -1076,6 +1106,22 @@
1076 crtcs = <&ipu 1>; 1106 crtcs = <&ipu 1>;
1077 status = "disabled"; 1107 status = "disabled";
1078 }; 1108 };
1109
1110 vpu: vpu@63ff4000 {
1111 compatible = "fsl,imx53-vpu";
1112 reg = <0x63ff4000 0x1000>;
1113 interrupts = <9>;
1114 clocks = <&clks 63>, <&clks 63>;
1115 clock-names = "per", "ahb";
1116 iram = <&ocram>;
1117 status = "disabled";
1118 };
1119 };
1120
1121 ocram: sram@f8000000 {
1122 compatible = "mmio-sram";
1123 reg = <0xf8000000 0x20000>;
1124 clocks = <&clks 186>;
1079 }; 1125 };
1080 }; 1126 };
1081}; 1127};
diff --git a/arch/arm/boot/dts/imx6dl-pinfunc.h b/arch/arm/boot/dts/imx6dl-pinfunc.h
index 9aab950ec269..b81a7a4ebab6 100644
--- a/arch/arm/boot/dts/imx6dl-pinfunc.h
+++ b/arch/arm/boot/dts/imx6dl-pinfunc.h
@@ -14,1072 +14,1076 @@
14 * The pin function ID is a tuple of 14 * The pin function ID is a tuple of
15 * <mux_reg conf_reg input_reg mux_mode input_val> 15 * <mux_reg conf_reg input_reg mux_mode input_val>
16 */ 16 */
17#define MX6DL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0 17#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
18#define MX6DL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0 18#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
19#define MX6DL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0 19#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
20#define MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0 20#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
21#define MX6DL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0 21#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
22#define MX6DL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0 22#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
23#define MX6DL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0 23#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
24#define MX6DL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0 24#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
25#define MX6DL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0 25#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
26#define MX6DL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0 26#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
27#define MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x050 0x364 0x8fc 0x3 0x1 27#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x050 0x364 0x8fc 0x3 0x1
28#define MX6DL_PAD_CSI0_DAT11__UART1_TX_DATA 0x050 0x364 0x000 0x3 0x0 28#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x050 0x364 0x000 0x3 0x0
29#define MX6DL_PAD_CSI0_DAT11__GPIO5_IO29 0x050 0x364 0x000 0x5 0x0 29#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x050 0x364 0x000 0x5 0x0
30#define MX6DL_PAD_CSI0_DAT11__ARM_TRACE08 0x050 0x364 0x000 0x7 0x0 30#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x050 0x364 0x000 0x7 0x0
31#define MX6DL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x054 0x368 0x000 0x0 0x0 31#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x054 0x368 0x000 0x0 0x0
32#define MX6DL_PAD_CSI0_DAT12__EIM_DATA08 0x054 0x368 0x000 0x1 0x0 32#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x054 0x368 0x000 0x1 0x0
33#define MX6DL_PAD_CSI0_DAT12__UART4_TX_DATA 0x054 0x368 0x000 0x3 0x0 33#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x054 0x368 0x000 0x3 0x0
34#define MX6DL_PAD_CSI0_DAT12__UART4_RX_DATA 0x054 0x368 0x914 0x3 0x0 34#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x054 0x368 0x914 0x3 0x0
35#define MX6DL_PAD_CSI0_DAT12__GPIO5_IO30 0x054 0x368 0x000 0x5 0x0 35#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x054 0x368 0x000 0x5 0x0
36#define MX6DL_PAD_CSI0_DAT12__ARM_TRACE09 0x054 0x368 0x000 0x7 0x0 36#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x054 0x368 0x000 0x7 0x0
37#define MX6DL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x058 0x36c 0x000 0x0 0x0 37#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x058 0x36c 0x000 0x0 0x0
38#define MX6DL_PAD_CSI0_DAT13__EIM_DATA09 0x058 0x36c 0x000 0x1 0x0 38#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x058 0x36c 0x000 0x1 0x0
39#define MX6DL_PAD_CSI0_DAT13__UART4_RX_DATA 0x058 0x36c 0x914 0x3 0x1 39#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x058 0x36c 0x914 0x3 0x1
40#define MX6DL_PAD_CSI0_DAT13__UART4_TX_DATA 0x058 0x36c 0x000 0x3 0x0 40#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x058 0x36c 0x000 0x3 0x0
41#define MX6DL_PAD_CSI0_DAT13__GPIO5_IO31 0x058 0x36c 0x000 0x5 0x0 41#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x058 0x36c 0x000 0x5 0x0
42#define MX6DL_PAD_CSI0_DAT13__ARM_TRACE10 0x058 0x36c 0x000 0x7 0x0 42#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x058 0x36c 0x000 0x7 0x0
43#define MX6DL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x05c 0x370 0x000 0x0 0x0 43#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x05c 0x370 0x000 0x0 0x0
44#define MX6DL_PAD_CSI0_DAT14__EIM_DATA10 0x05c 0x370 0x000 0x1 0x0 44#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x05c 0x370 0x000 0x1 0x0
45#define MX6DL_PAD_CSI0_DAT14__UART5_TX_DATA 0x05c 0x370 0x000 0x3 0x0 45#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x05c 0x370 0x000 0x3 0x0
46#define MX6DL_PAD_CSI0_DAT14__UART5_RX_DATA 0x05c 0x370 0x91c 0x3 0x0 46#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x05c 0x370 0x91c 0x3 0x0
47#define MX6DL_PAD_CSI0_DAT14__GPIO6_IO00 0x05c 0x370 0x000 0x5 0x0 47#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x05c 0x370 0x000 0x5 0x0
48#define MX6DL_PAD_CSI0_DAT14__ARM_TRACE11 0x05c 0x370 0x000 0x7 0x0 48#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x05c 0x370 0x000 0x7 0x0
49#define MX6DL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x060 0x374 0x000 0x0 0x0 49#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x060 0x374 0x000 0x0 0x0
50#define MX6DL_PAD_CSI0_DAT15__EIM_DATA11 0x060 0x374 0x000 0x1 0x0 50#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x060 0x374 0x000 0x1 0x0
51#define MX6DL_PAD_CSI0_DAT15__UART5_RX_DATA 0x060 0x374 0x91c 0x3 0x1 51#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x060 0x374 0x91c 0x3 0x1
52#define MX6DL_PAD_CSI0_DAT15__UART5_TX_DATA 0x060 0x374 0x000 0x3 0x0 52#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x060 0x374 0x000 0x3 0x0
53#define MX6DL_PAD_CSI0_DAT15__GPIO6_IO01 0x060 0x374 0x000 0x5 0x0 53#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x060 0x374 0x000 0x5 0x0
54#define MX6DL_PAD_CSI0_DAT15__ARM_TRACE12 0x060 0x374 0x000 0x7 0x0 54#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x060 0x374 0x000 0x7 0x0
55#define MX6DL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x064 0x378 0x000 0x0 0x0 55#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x064 0x378 0x000 0x0 0x0
56#define MX6DL_PAD_CSI0_DAT16__EIM_DATA12 0x064 0x378 0x000 0x1 0x0 56#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x064 0x378 0x000 0x1 0x0
57#define MX6DL_PAD_CSI0_DAT16__UART4_RTS_B 0x064 0x378 0x910 0x3 0x0 57#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x064 0x378 0x910 0x3 0x0
58#define MX6DL_PAD_CSI0_DAT16__UART4_CTS_B 0x064 0x378 0x000 0x3 0x0 58#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x064 0x378 0x000 0x3 0x0
59#define MX6DL_PAD_CSI0_DAT16__GPIO6_IO02 0x064 0x378 0x000 0x5 0x0 59#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x064 0x378 0x000 0x5 0x0
60#define MX6DL_PAD_CSI0_DAT16__ARM_TRACE13 0x064 0x378 0x000 0x7 0x0 60#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x064 0x378 0x000 0x7 0x0
61#define MX6DL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x068 0x37c 0x000 0x0 0x0 61#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x068 0x37c 0x000 0x0 0x0
62#define MX6DL_PAD_CSI0_DAT17__EIM_DATA13 0x068 0x37c 0x000 0x1 0x0 62#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x068 0x37c 0x000 0x1 0x0
63#define MX6DL_PAD_CSI0_DAT17__UART4_CTS_B 0x068 0x37c 0x000 0x3 0x0 63#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x068 0x37c 0x000 0x3 0x0
64#define MX6DL_PAD_CSI0_DAT17__UART4_RTS_B 0x068 0x37c 0x910 0x3 0x1 64#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x068 0x37c 0x910 0x3 0x1
65#define MX6DL_PAD_CSI0_DAT17__GPIO6_IO03 0x068 0x37c 0x000 0x5 0x0 65#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x068 0x37c 0x000 0x5 0x0
66#define MX6DL_PAD_CSI0_DAT17__ARM_TRACE14 0x068 0x37c 0x000 0x7 0x0 66#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x068 0x37c 0x000 0x7 0x0
67#define MX6DL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x06c 0x380 0x000 0x0 0x0 67#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x06c 0x380 0x000 0x0 0x0
68#define MX6DL_PAD_CSI0_DAT18__EIM_DATA14 0x06c 0x380 0x000 0x1 0x0 68#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x06c 0x380 0x000 0x1 0x0
69#define MX6DL_PAD_CSI0_DAT18__UART5_RTS_B 0x06c 0x380 0x918 0x3 0x0 69#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x06c 0x380 0x918 0x3 0x0
70#define MX6DL_PAD_CSI0_DAT18__UART5_CTS_B 0x06c 0x380 0x000 0x3 0x0 70#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x06c 0x380 0x000 0x3 0x0
71#define MX6DL_PAD_CSI0_DAT18__GPIO6_IO04 0x06c 0x380 0x000 0x5 0x0 71#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x06c 0x380 0x000 0x5 0x0
72#define MX6DL_PAD_CSI0_DAT18__ARM_TRACE15 0x06c 0x380 0x000 0x7 0x0 72#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x06c 0x380 0x000 0x7 0x0
73#define MX6DL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x070 0x384 0x000 0x0 0x0 73#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x070 0x384 0x000 0x0 0x0
74#define MX6DL_PAD_CSI0_DAT19__EIM_DATA15 0x070 0x384 0x000 0x1 0x0 74#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x070 0x384 0x000 0x1 0x0
75#define MX6DL_PAD_CSI0_DAT19__UART5_CTS_B 0x070 0x384 0x000 0x3 0x0 75#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x070 0x384 0x000 0x3 0x0
76#define MX6DL_PAD_CSI0_DAT19__UART5_RTS_B 0x070 0x384 0x918 0x3 0x1 76#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x070 0x384 0x918 0x3 0x1
77#define MX6DL_PAD_CSI0_DAT19__GPIO6_IO05 0x070 0x384 0x000 0x5 0x0 77#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x070 0x384 0x000 0x5 0x0
78#define MX6DL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x074 0x388 0x000 0x0 0x0 78#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x074 0x388 0x000 0x0 0x0
79#define MX6DL_PAD_CSI0_DAT4__EIM_DATA02 0x074 0x388 0x000 0x1 0x0 79#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x074 0x388 0x000 0x1 0x0
80#define MX6DL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x074 0x388 0x7d8 0x2 0x0 80#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x074 0x388 0x7d8 0x2 0x0
81#define MX6DL_PAD_CSI0_DAT4__KEY_COL5 0x074 0x388 0x8c0 0x3 0x0 81#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x074 0x388 0x8c0 0x3 0x0
82#define MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x074 0x388 0x000 0x4 0x0 82#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x074 0x388 0x000 0x4 0x0
83#define MX6DL_PAD_CSI0_DAT4__GPIO5_IO22 0x074 0x388 0x000 0x5 0x0 83#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x074 0x388 0x000 0x5 0x0
84#define MX6DL_PAD_CSI0_DAT4__ARM_TRACE01 0x074 0x388 0x000 0x7 0x0 84#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x074 0x388 0x000 0x7 0x0
85#define MX6DL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x078 0x38c 0x000 0x0 0x0 85#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x078 0x38c 0x000 0x0 0x0
86#define MX6DL_PAD_CSI0_DAT5__EIM_DATA03 0x078 0x38c 0x000 0x1 0x0 86#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x078 0x38c 0x000 0x1 0x0
87#define MX6DL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x078 0x38c 0x7e0 0x2 0x0 87#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x078 0x38c 0x7e0 0x2 0x0
88#define MX6DL_PAD_CSI0_DAT5__KEY_ROW5 0x078 0x38c 0x8cc 0x3 0x0 88#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x078 0x38c 0x8cc 0x3 0x0
89#define MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x078 0x38c 0x000 0x4 0x0 89#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x078 0x38c 0x000 0x4 0x0
90#define MX6DL_PAD_CSI0_DAT5__GPIO5_IO23 0x078 0x38c 0x000 0x5 0x0 90#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x078 0x38c 0x000 0x5 0x0
91#define MX6DL_PAD_CSI0_DAT5__ARM_TRACE02 0x078 0x38c 0x000 0x7 0x0 91#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x078 0x38c 0x000 0x7 0x0
92#define MX6DL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x07c 0x390 0x000 0x0 0x0 92#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x07c 0x390 0x000 0x0 0x0
93#define MX6DL_PAD_CSI0_DAT6__EIM_DATA04 0x07c 0x390 0x000 0x1 0x0 93#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x07c 0x390 0x000 0x1 0x0
94#define MX6DL_PAD_CSI0_DAT6__ECSPI1_MISO 0x07c 0x390 0x7dc 0x2 0x0 94#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x07c 0x390 0x7dc 0x2 0x0
95#define MX6DL_PAD_CSI0_DAT6__KEY_COL6 0x07c 0x390 0x8c4 0x3 0x0 95#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x07c 0x390 0x8c4 0x3 0x0
96#define MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x07c 0x390 0x000 0x4 0x0 96#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x07c 0x390 0x000 0x4 0x0
97#define MX6DL_PAD_CSI0_DAT6__GPIO5_IO24 0x07c 0x390 0x000 0x5 0x0 97#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x07c 0x390 0x000 0x5 0x0
98#define MX6DL_PAD_CSI0_DAT6__ARM_TRACE03 0x07c 0x390 0x000 0x7 0x0 98#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x07c 0x390 0x000 0x7 0x0
99#define MX6DL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x080 0x394 0x000 0x0 0x0 99#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x080 0x394 0x000 0x0 0x0
100#define MX6DL_PAD_CSI0_DAT7__EIM_DATA05 0x080 0x394 0x000 0x1 0x0 100#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x080 0x394 0x000 0x1 0x0
101#define MX6DL_PAD_CSI0_DAT7__ECSPI1_SS0 0x080 0x394 0x7e4 0x2 0x0 101#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x080 0x394 0x7e4 0x2 0x0
102#define MX6DL_PAD_CSI0_DAT7__KEY_ROW6 0x080 0x394 0x8d0 0x3 0x0 102#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x080 0x394 0x8d0 0x3 0x0
103#define MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x080 0x394 0x000 0x4 0x0 103#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x080 0x394 0x000 0x4 0x0
104#define MX6DL_PAD_CSI0_DAT7__GPIO5_IO25 0x080 0x394 0x000 0x5 0x0 104#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x080 0x394 0x000 0x5 0x0
105#define MX6DL_PAD_CSI0_DAT7__ARM_TRACE04 0x080 0x394 0x000 0x7 0x0 105#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x080 0x394 0x000 0x7 0x0
106#define MX6DL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x084 0x398 0x000 0x0 0x0 106#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x084 0x398 0x000 0x0 0x0
107#define MX6DL_PAD_CSI0_DAT8__EIM_DATA06 0x084 0x398 0x000 0x1 0x0 107#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x084 0x398 0x000 0x1 0x0
108#define MX6DL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x084 0x398 0x7f4 0x2 0x0 108#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x084 0x398 0x7f4 0x2 0x0
109#define MX6DL_PAD_CSI0_DAT8__KEY_COL7 0x084 0x398 0x8c8 0x3 0x0 109#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x084 0x398 0x8c8 0x3 0x0
110#define MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x084 0x398 0x86c 0x4 0x0 110#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x084 0x398 0x86c 0x4 0x0
111#define MX6DL_PAD_CSI0_DAT8__GPIO5_IO26 0x084 0x398 0x000 0x5 0x0 111#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x084 0x398 0x000 0x5 0x0
112#define MX6DL_PAD_CSI0_DAT8__ARM_TRACE05 0x084 0x398 0x000 0x7 0x0 112#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x084 0x398 0x000 0x7 0x0
113#define MX6DL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x088 0x39c 0x000 0x0 0x0 113#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x088 0x39c 0x000 0x0 0x0
114#define MX6DL_PAD_CSI0_DAT9__EIM_DATA07 0x088 0x39c 0x000 0x1 0x0 114#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x088 0x39c 0x000 0x1 0x0
115#define MX6DL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x088 0x39c 0x7fc 0x2 0x0 115#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x088 0x39c 0x7fc 0x2 0x0
116#define MX6DL_PAD_CSI0_DAT9__KEY_ROW7 0x088 0x39c 0x8d4 0x3 0x0 116#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x088 0x39c 0x8d4 0x3 0x0
117#define MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x088 0x39c 0x868 0x4 0x0 117#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x088 0x39c 0x868 0x4 0x0
118#define MX6DL_PAD_CSI0_DAT9__GPIO5_IO27 0x088 0x39c 0x000 0x5 0x0 118#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x088 0x39c 0x000 0x5 0x0
119#define MX6DL_PAD_CSI0_DAT9__ARM_TRACE06 0x088 0x39c 0x000 0x7 0x0 119#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x088 0x39c 0x000 0x7 0x0
120#define MX6DL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x08c 0x3a0 0x000 0x0 0x0 120#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x08c 0x3a0 0x000 0x0 0x0
121#define MX6DL_PAD_CSI0_DATA_EN__EIM_DATA00 0x08c 0x3a0 0x000 0x1 0x0 121#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x08c 0x3a0 0x000 0x1 0x0
122#define MX6DL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x08c 0x3a0 0x000 0x5 0x0 122#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x08c 0x3a0 0x000 0x5 0x0
123#define MX6DL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x08c 0x3a0 0x000 0x7 0x0 123#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x08c 0x3a0 0x000 0x7 0x0
124#define MX6DL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x090 0x3a4 0x000 0x0 0x0 124#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x090 0x3a4 0x000 0x0 0x0
125#define MX6DL_PAD_CSI0_MCLK__CCM_CLKO1 0x090 0x3a4 0x000 0x3 0x0 125#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x090 0x3a4 0x000 0x3 0x0
126#define MX6DL_PAD_CSI0_MCLK__GPIO5_IO19 0x090 0x3a4 0x000 0x5 0x0 126#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x090 0x3a4 0x000 0x5 0x0
127#define MX6DL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x090 0x3a4 0x000 0x7 0x0 127#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x090 0x3a4 0x000 0x7 0x0
128#define MX6DL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x094 0x3a8 0x000 0x0 0x0 128#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x094 0x3a8 0x000 0x0 0x0
129#define MX6DL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x094 0x3a8 0x000 0x5 0x0 129#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x094 0x3a8 0x000 0x5 0x0
130#define MX6DL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x094 0x3a8 0x000 0x7 0x0 130#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x094 0x3a8 0x000 0x7 0x0
131#define MX6DL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x098 0x3ac 0x000 0x0 0x0 131#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x098 0x3ac 0x000 0x0 0x0
132#define MX6DL_PAD_CSI0_VSYNC__EIM_DATA01 0x098 0x3ac 0x000 0x1 0x0 132#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x098 0x3ac 0x000 0x1 0x0
133#define MX6DL_PAD_CSI0_VSYNC__GPIO5_IO21 0x098 0x3ac 0x000 0x5 0x0 133#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x098 0x3ac 0x000 0x5 0x0
134#define MX6DL_PAD_CSI0_VSYNC__ARM_TRACE00 0x098 0x3ac 0x000 0x7 0x0 134#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x098 0x3ac 0x000 0x7 0x0
135#define MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x09c 0x3b0 0x000 0x0 0x0 135#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x09c 0x3b0 0x000 0x0 0x0
136#define MX6DL_PAD_DI0_DISP_CLK__LCD_CLK 0x09c 0x3b0 0x000 0x1 0x0 136#define MX6QDL_PAD_DI0_DISP_CLK__LCD_CLK 0x09c 0x3b0 0x000 0x1 0x0
137#define MX6DL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x09c 0x3b0 0x000 0x5 0x0 137#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x09c 0x3b0 0x000 0x5 0x0
138#define MX6DL_PAD_DI0_DISP_CLK__LCD_WR_RWN 0x09c 0x3b0 0x000 0x8 0x0 138#define MX6QDL_PAD_DI0_DISP_CLK__LCD_WR_RWN 0x09c 0x3b0 0x000 0x8 0x0
139#define MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x0a0 0x3b4 0x000 0x0 0x0 139#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x0a0 0x3b4 0x000 0x0 0x0
140#define MX6DL_PAD_DI0_PIN15__LCD_ENABLE 0x0a0 0x3b4 0x000 0x1 0x0 140#define MX6QDL_PAD_DI0_PIN15__LCD_ENABLE 0x0a0 0x3b4 0x000 0x1 0x0
141#define MX6DL_PAD_DI0_PIN15__AUD6_TXC 0x0a0 0x3b4 0x000 0x2 0x0 141#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x0a0 0x3b4 0x000 0x2 0x0
142#define MX6DL_PAD_DI0_PIN15__GPIO4_IO17 0x0a0 0x3b4 0x000 0x5 0x0 142#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x0a0 0x3b4 0x000 0x5 0x0
143#define MX6DL_PAD_DI0_PIN15__LCD_RD_E 0x0a0 0x3b4 0x000 0x8 0x0 143#define MX6QDL_PAD_DI0_PIN15__LCD_RD_E 0x0a0 0x3b4 0x000 0x8 0x0
144#define MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x0a4 0x3b8 0x000 0x0 0x0 144#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x0a4 0x3b8 0x000 0x0 0x0
145#define MX6DL_PAD_DI0_PIN2__LCD_HSYNC 0x0a4 0x3b8 0x8d8 0x1 0x0 145#define MX6QDL_PAD_DI0_PIN2__LCD_HSYNC 0x0a4 0x3b8 0x8d8 0x1 0x0
146#define MX6DL_PAD_DI0_PIN2__AUD6_TXD 0x0a4 0x3b8 0x000 0x2 0x0 146#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x0a4 0x3b8 0x000 0x2 0x0
147#define MX6DL_PAD_DI0_PIN2__GPIO4_IO18 0x0a4 0x3b8 0x000 0x5 0x0 147#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x0a4 0x3b8 0x000 0x5 0x0
148#define MX6DL_PAD_DI0_PIN2__LCD_RS 0x0a4 0x3b8 0x000 0x8 0x0 148#define MX6QDL_PAD_DI0_PIN2__LCD_RS 0x0a4 0x3b8 0x000 0x8 0x0
149#define MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x0a8 0x3bc 0x000 0x0 0x0 149#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x0a8 0x3bc 0x000 0x0 0x0
150#define MX6DL_PAD_DI0_PIN3__LCD_VSYNC 0x0a8 0x3bc 0x000 0x1 0x0 150#define MX6QDL_PAD_DI0_PIN3__LCD_VSYNC 0x0a8 0x3bc 0x000 0x1 0x0
151#define MX6DL_PAD_DI0_PIN3__AUD6_TXFS 0x0a8 0x3bc 0x000 0x2 0x0 151#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x0a8 0x3bc 0x000 0x2 0x0
152#define MX6DL_PAD_DI0_PIN3__GPIO4_IO19 0x0a8 0x3bc 0x000 0x5 0x0 152#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x0a8 0x3bc 0x000 0x5 0x0
153#define MX6DL_PAD_DI0_PIN3__LCD_CS 0x0a8 0x3bc 0x000 0x8 0x0 153#define MX6QDL_PAD_DI0_PIN3__LCD_CS 0x0a8 0x3bc 0x000 0x8 0x0
154#define MX6DL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x0ac 0x3c0 0x000 0x0 0x0 154#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x0ac 0x3c0 0x000 0x0 0x0
155#define MX6DL_PAD_DI0_PIN4__LCD_BUSY 0x0ac 0x3c0 0x8d8 0x1 0x1 155#define MX6QDL_PAD_DI0_PIN4__LCD_BUSY 0x0ac 0x3c0 0x8d8 0x1 0x1
156#define MX6DL_PAD_DI0_PIN4__AUD6_RXD 0x0ac 0x3c0 0x000 0x2 0x0 156#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x0ac 0x3c0 0x000 0x2 0x0
157#define MX6DL_PAD_DI0_PIN4__SD1_WP 0x0ac 0x3c0 0x92c 0x3 0x0 157#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x0ac 0x3c0 0x92c 0x3 0x0
158#define MX6DL_PAD_DI0_PIN4__GPIO4_IO20 0x0ac 0x3c0 0x000 0x5 0x0 158#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0ac 0x3c0 0x000 0x5 0x0
159#define MX6DL_PAD_DI0_PIN4__LCD_RESET 0x0ac 0x3c0 0x000 0x8 0x0 159#define MX6QDL_PAD_DI0_PIN4__LCD_RESET 0x0ac 0x3c0 0x000 0x8 0x0
160#define MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x0b0 0x3c4 0x000 0x0 0x0 160#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x0b0 0x3c4 0x000 0x0 0x0
161#define MX6DL_PAD_DISP0_DAT0__LCD_DATA00 0x0b0 0x3c4 0x000 0x1 0x0 161#define MX6QDL_PAD_DISP0_DAT0__LCD_DATA00 0x0b0 0x3c4 0x000 0x1 0x0
162#define MX6DL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x0b0 0x3c4 0x000 0x2 0x0 162#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x0b0 0x3c4 0x000 0x2 0x0
163#define MX6DL_PAD_DISP0_DAT0__GPIO4_IO21 0x0b0 0x3c4 0x000 0x5 0x0 163#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x0b0 0x3c4 0x000 0x5 0x0
164#define MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x0b4 0x3c8 0x000 0x0 0x0 164#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x0b4 0x3c8 0x000 0x0 0x0
165#define MX6DL_PAD_DISP0_DAT1__LCD_DATA01 0x0b4 0x3c8 0x000 0x1 0x0 165#define MX6QDL_PAD_DISP0_DAT1__LCD_DATA01 0x0b4 0x3c8 0x000 0x1 0x0
166#define MX6DL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x0b4 0x3c8 0x000 0x2 0x0 166#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x0b4 0x3c8 0x000 0x2 0x0
167#define MX6DL_PAD_DISP0_DAT1__GPIO4_IO22 0x0b4 0x3c8 0x000 0x5 0x0 167#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x0b4 0x3c8 0x000 0x5 0x0
168#define MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x0b8 0x3cc 0x000 0x0 0x0 168#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x0b8 0x3cc 0x000 0x0 0x0
169#define MX6DL_PAD_DISP0_DAT10__LCD_DATA10 0x0b8 0x3cc 0x000 0x1 0x0 169#define MX6QDL_PAD_DISP0_DAT10__LCD_DATA10 0x0b8 0x3cc 0x000 0x1 0x0
170#define MX6DL_PAD_DISP0_DAT10__GPIO4_IO31 0x0b8 0x3cc 0x000 0x5 0x0 170#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x0b8 0x3cc 0x000 0x5 0x0
171#define MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x0bc 0x3d0 0x000 0x0 0x0 171#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x0bc 0x3d0 0x000 0x0 0x0
172#define MX6DL_PAD_DISP0_DAT11__LCD_DATA11 0x0bc 0x3d0 0x000 0x1 0x0 172#define MX6QDL_PAD_DISP0_DAT11__LCD_DATA11 0x0bc 0x3d0 0x000 0x1 0x0
173#define MX6DL_PAD_DISP0_DAT11__GPIO5_IO05 0x0bc 0x3d0 0x000 0x5 0x0 173#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0bc 0x3d0 0x000 0x5 0x0
174#define MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x0c0 0x3d4 0x000 0x0 0x0 174#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x0c0 0x3d4 0x000 0x0 0x0
175#define MX6DL_PAD_DISP0_DAT12__LCD_DATA12 0x0c0 0x3d4 0x000 0x1 0x0 175#define MX6QDL_PAD_DISP0_DAT12__LCD_DATA12 0x0c0 0x3d4 0x000 0x1 0x0
176#define MX6DL_PAD_DISP0_DAT12__GPIO5_IO06 0x0c0 0x3d4 0x000 0x5 0x0 176#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x0c0 0x3d4 0x000 0x5 0x0
177#define MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x0c4 0x3d8 0x000 0x0 0x0 177#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x0c4 0x3d8 0x000 0x0 0x0
178#define MX6DL_PAD_DISP0_DAT13__LCD_DATA13 0x0c4 0x3d8 0x000 0x1 0x0 178#define MX6QDL_PAD_DISP0_DAT13__LCD_DATA13 0x0c4 0x3d8 0x000 0x1 0x0
179#define MX6DL_PAD_DISP0_DAT13__AUD5_RXFS 0x0c4 0x3d8 0x7bc 0x3 0x0 179#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x0c4 0x3d8 0x7bc 0x3 0x0
180#define MX6DL_PAD_DISP0_DAT13__GPIO5_IO07 0x0c4 0x3d8 0x000 0x5 0x0 180#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x0c4 0x3d8 0x000 0x5 0x0
181#define MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x0c8 0x3dc 0x000 0x0 0x0 181#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x0c8 0x3dc 0x000 0x0 0x0
182#define MX6DL_PAD_DISP0_DAT14__LCD_DATA14 0x0c8 0x3dc 0x000 0x1 0x0 182#define MX6QDL_PAD_DISP0_DAT14__LCD_DATA14 0x0c8 0x3dc 0x000 0x1 0x0
183#define MX6DL_PAD_DISP0_DAT14__AUD5_RXC 0x0c8 0x3dc 0x7b8 0x3 0x0 183#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x0c8 0x3dc 0x7b8 0x3 0x0
184#define MX6DL_PAD_DISP0_DAT14__GPIO5_IO08 0x0c8 0x3dc 0x000 0x5 0x0 184#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x0c8 0x3dc 0x000 0x5 0x0
185#define MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x0cc 0x3e0 0x000 0x0 0x0 185#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x0cc 0x3e0 0x000 0x0 0x0
186#define MX6DL_PAD_DISP0_DAT15__LCD_DATA15 0x0cc 0x3e0 0x000 0x1 0x0 186#define MX6QDL_PAD_DISP0_DAT15__LCD_DATA15 0x0cc 0x3e0 0x000 0x1 0x0
187#define MX6DL_PAD_DISP0_DAT15__ECSPI1_SS1 0x0cc 0x3e0 0x7e8 0x2 0x0 187#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x0cc 0x3e0 0x7e8 0x2 0x0
188#define MX6DL_PAD_DISP0_DAT15__ECSPI2_SS1 0x0cc 0x3e0 0x804 0x3 0x0 188#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x0cc 0x3e0 0x804 0x3 0x0
189#define MX6DL_PAD_DISP0_DAT15__GPIO5_IO09 0x0cc 0x3e0 0x000 0x5 0x0 189#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x0cc 0x3e0 0x000 0x5 0x0
190#define MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x0d0 0x3e4 0x000 0x0 0x0 190#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x0d0 0x3e4 0x000 0x0 0x0
191#define MX6DL_PAD_DISP0_DAT16__LCD_DATA16 0x0d0 0x3e4 0x000 0x1 0x0 191#define MX6QDL_PAD_DISP0_DAT16__LCD_DATA16 0x0d0 0x3e4 0x000 0x1 0x0
192#define MX6DL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0d0 0x3e4 0x7fc 0x2 0x1 192#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0d0 0x3e4 0x7fc 0x2 0x1
193#define MX6DL_PAD_DISP0_DAT16__AUD5_TXC 0x0d0 0x3e4 0x7c0 0x3 0x0 193#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x0d0 0x3e4 0x7c0 0x3 0x0
194#define MX6DL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x0d0 0x3e4 0x8e8 0x4 0x0 194#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x0d0 0x3e4 0x8e8 0x4 0x0
195#define MX6DL_PAD_DISP0_DAT16__GPIO5_IO10 0x0d0 0x3e4 0x000 0x5 0x0 195#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x0d0 0x3e4 0x000 0x5 0x0
196#define MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x0d4 0x3e8 0x000 0x0 0x0 196#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x0d4 0x3e8 0x000 0x0 0x0
197#define MX6DL_PAD_DISP0_DAT17__LCD_DATA17 0x0d4 0x3e8 0x000 0x1 0x0 197#define MX6QDL_PAD_DISP0_DAT17__LCD_DATA17 0x0d4 0x3e8 0x000 0x1 0x0
198#define MX6DL_PAD_DISP0_DAT17__ECSPI2_MISO 0x0d4 0x3e8 0x7f8 0x2 0x1 198#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x0d4 0x3e8 0x7f8 0x2 0x1
199#define MX6DL_PAD_DISP0_DAT17__AUD5_TXD 0x0d4 0x3e8 0x7b4 0x3 0x0 199#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x0d4 0x3e8 0x7b4 0x3 0x0
200#define MX6DL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x0d4 0x3e8 0x8ec 0x4 0x0 200#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x0d4 0x3e8 0x8ec 0x4 0x0
201#define MX6DL_PAD_DISP0_DAT17__GPIO5_IO11 0x0d4 0x3e8 0x000 0x5 0x0 201#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0d4 0x3e8 0x000 0x5 0x0
202#define MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x0d8 0x3ec 0x000 0x0 0x0 202#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x0d8 0x3ec 0x000 0x0 0x0
203#define MX6DL_PAD_DISP0_DAT18__LCD_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 203#define MX6QDL_PAD_DISP0_DAT18__LCD_DATA18 0x0d8 0x3ec 0x000 0x1 0x0
204#define MX6DL_PAD_DISP0_DAT18__ECSPI2_SS0 0x0d8 0x3ec 0x800 0x2 0x1 204#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x0d8 0x3ec 0x800 0x2 0x1
205#define MX6DL_PAD_DISP0_DAT18__AUD5_TXFS 0x0d8 0x3ec 0x7c4 0x3 0x0 205#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x0d8 0x3ec 0x7c4 0x3 0x0
206#define MX6DL_PAD_DISP0_DAT18__AUD4_RXFS 0x0d8 0x3ec 0x7a4 0x4 0x0 206#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x0d8 0x3ec 0x7a4 0x4 0x0
207#define MX6DL_PAD_DISP0_DAT18__GPIO5_IO12 0x0d8 0x3ec 0x000 0x5 0x0 207#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0d8 0x3ec 0x000 0x5 0x0
208#define MX6DL_PAD_DISP0_DAT18__EIM_CS2_B 0x0d8 0x3ec 0x000 0x7 0x0 208#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x0d8 0x3ec 0x000 0x7 0x0
209#define MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x0dc 0x3f0 0x000 0x0 0x0 209#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x0dc 0x3f0 0x000 0x0 0x0
210#define MX6DL_PAD_DISP0_DAT19__LCD_DATA19 0x0dc 0x3f0 0x000 0x1 0x0 210#define MX6QDL_PAD_DISP0_DAT19__LCD_DATA19 0x0dc 0x3f0 0x000 0x1 0x0
211#define MX6DL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0dc 0x3f0 0x7f4 0x2 0x1 211#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0dc 0x3f0 0x7f4 0x2 0x1
212#define MX6DL_PAD_DISP0_DAT19__AUD5_RXD 0x0dc 0x3f0 0x7b0 0x3 0x0 212#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x0dc 0x3f0 0x7b0 0x3 0x0
213#define MX6DL_PAD_DISP0_DAT19__AUD4_RXC 0x0dc 0x3f0 0x7a0 0x4 0x0 213#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x0dc 0x3f0 0x7a0 0x4 0x0
214#define MX6DL_PAD_DISP0_DAT19__GPIO5_IO13 0x0dc 0x3f0 0x000 0x5 0x0 214#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0dc 0x3f0 0x000 0x5 0x0
215#define MX6DL_PAD_DISP0_DAT19__EIM_CS3_B 0x0dc 0x3f0 0x000 0x7 0x0 215#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x0dc 0x3f0 0x000 0x7 0x0
216#define MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x0e0 0x3f4 0x000 0x0 0x0 216#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x0e0 0x3f4 0x000 0x0 0x0
217#define MX6DL_PAD_DISP0_DAT2__LCD_DATA02 0x0e0 0x3f4 0x000 0x1 0x0 217#define MX6QDL_PAD_DISP0_DAT2__LCD_DATA02 0x0e0 0x3f4 0x000 0x1 0x0
218#define MX6DL_PAD_DISP0_DAT2__ECSPI3_MISO 0x0e0 0x3f4 0x000 0x2 0x0 218#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x0e0 0x3f4 0x000 0x2 0x0
219#define MX6DL_PAD_DISP0_DAT2__GPIO4_IO23 0x0e0 0x3f4 0x000 0x5 0x0 219#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x0e0 0x3f4 0x000 0x5 0x0
220#define MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x0e4 0x3f8 0x000 0x0 0x0 220#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x0e4 0x3f8 0x000 0x0 0x0
221#define MX6DL_PAD_DISP0_DAT20__LCD_DATA20 0x0e4 0x3f8 0x000 0x1 0x0 221#define MX6QDL_PAD_DISP0_DAT20__LCD_DATA20 0x0e4 0x3f8 0x000 0x1 0x0
222#define MX6DL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0e4 0x3f8 0x7d8 0x2 0x1 222#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0e4 0x3f8 0x7d8 0x2 0x1
223#define MX6DL_PAD_DISP0_DAT20__AUD4_TXC 0x0e4 0x3f8 0x7a8 0x3 0x0 223#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x0e4 0x3f8 0x7a8 0x3 0x0
224#define MX6DL_PAD_DISP0_DAT20__GPIO5_IO14 0x0e4 0x3f8 0x000 0x5 0x0 224#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x0e4 0x3f8 0x000 0x5 0x0
225#define MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x0e8 0x3fc 0x000 0x0 0x0 225#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x0e8 0x3fc 0x000 0x0 0x0
226#define MX6DL_PAD_DISP0_DAT21__LCD_DATA21 0x0e8 0x3fc 0x000 0x1 0x0 226#define MX6QDL_PAD_DISP0_DAT21__LCD_DATA21 0x0e8 0x3fc 0x000 0x1 0x0
227#define MX6DL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0e8 0x3fc 0x7e0 0x2 0x1 227#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0e8 0x3fc 0x7e0 0x2 0x1
228#define MX6DL_PAD_DISP0_DAT21__AUD4_TXD 0x0e8 0x3fc 0x79c 0x3 0x0 228#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x0e8 0x3fc 0x79c 0x3 0x0
229#define MX6DL_PAD_DISP0_DAT21__GPIO5_IO15 0x0e8 0x3fc 0x000 0x5 0x0 229#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0e8 0x3fc 0x000 0x5 0x0
230#define MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x0ec 0x400 0x000 0x0 0x0 230#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x0ec 0x400 0x000 0x0 0x0
231#define MX6DL_PAD_DISP0_DAT22__LCD_DATA22 0x0ec 0x400 0x000 0x1 0x0 231#define MX6QDL_PAD_DISP0_DAT22__LCD_DATA22 0x0ec 0x400 0x000 0x1 0x0
232#define MX6DL_PAD_DISP0_DAT22__ECSPI1_MISO 0x0ec 0x400 0x7dc 0x2 0x1 232#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x0ec 0x400 0x7dc 0x2 0x1
233#define MX6DL_PAD_DISP0_DAT22__AUD4_TXFS 0x0ec 0x400 0x7ac 0x3 0x0 233#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x0ec 0x400 0x7ac 0x3 0x0
234#define MX6DL_PAD_DISP0_DAT22__GPIO5_IO16 0x0ec 0x400 0x000 0x5 0x0 234#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0ec 0x400 0x000 0x5 0x0
235#define MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x0f0 0x404 0x000 0x0 0x0 235#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x0f0 0x404 0x000 0x0 0x0
236#define MX6DL_PAD_DISP0_DAT23__LCD_DATA23 0x0f0 0x404 0x000 0x1 0x0 236#define MX6QDL_PAD_DISP0_DAT23__LCD_DATA23 0x0f0 0x404 0x000 0x1 0x0
237#define MX6DL_PAD_DISP0_DAT23__ECSPI1_SS0 0x0f0 0x404 0x7e4 0x2 0x1 237#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x0f0 0x404 0x7e4 0x2 0x1
238#define MX6DL_PAD_DISP0_DAT23__AUD4_RXD 0x0f0 0x404 0x798 0x3 0x0 238#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x0f0 0x404 0x798 0x3 0x0
239#define MX6DL_PAD_DISP0_DAT23__GPIO5_IO17 0x0f0 0x404 0x000 0x5 0x0 239#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0f0 0x404 0x000 0x5 0x0
240#define MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x0f4 0x408 0x000 0x0 0x0 240#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x0f4 0x408 0x000 0x0 0x0
241#define MX6DL_PAD_DISP0_DAT3__LCD_DATA03 0x0f4 0x408 0x000 0x1 0x0 241#define MX6QDL_PAD_DISP0_DAT3__LCD_DATA03 0x0f4 0x408 0x000 0x1 0x0
242#define MX6DL_PAD_DISP0_DAT3__ECSPI3_SS0 0x0f4 0x408 0x000 0x2 0x0 242#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x0f4 0x408 0x000 0x2 0x0
243#define MX6DL_PAD_DISP0_DAT3__GPIO4_IO24 0x0f4 0x408 0x000 0x5 0x0 243#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x0f4 0x408 0x000 0x5 0x0
244#define MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x0f8 0x40c 0x000 0x0 0x0 244#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x0f8 0x40c 0x000 0x0 0x0
245#define MX6DL_PAD_DISP0_DAT4__LCD_DATA04 0x0f8 0x40c 0x000 0x1 0x0 245#define MX6QDL_PAD_DISP0_DAT4__LCD_DATA04 0x0f8 0x40c 0x000 0x1 0x0
246#define MX6DL_PAD_DISP0_DAT4__ECSPI3_SS1 0x0f8 0x40c 0x000 0x2 0x0 246#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x0f8 0x40c 0x000 0x2 0x0
247#define MX6DL_PAD_DISP0_DAT4__GPIO4_IO25 0x0f8 0x40c 0x000 0x5 0x0 247#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x0f8 0x40c 0x000 0x5 0x0
248#define MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x0fc 0x410 0x000 0x0 0x0 248#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x0fc 0x410 0x000 0x0 0x0
249#define MX6DL_PAD_DISP0_DAT5__LCD_DATA05 0x0fc 0x410 0x000 0x1 0x0 249#define MX6QDL_PAD_DISP0_DAT5__LCD_DATA05 0x0fc 0x410 0x000 0x1 0x0
250#define MX6DL_PAD_DISP0_DAT5__ECSPI3_SS2 0x0fc 0x410 0x000 0x2 0x0 250#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x0fc 0x410 0x000 0x2 0x0
251#define MX6DL_PAD_DISP0_DAT5__AUD6_RXFS 0x0fc 0x410 0x000 0x3 0x0 251#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x0fc 0x410 0x000 0x3 0x0
252#define MX6DL_PAD_DISP0_DAT5__GPIO4_IO26 0x0fc 0x410 0x000 0x5 0x0 252#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x0fc 0x410 0x000 0x5 0x0
253#define MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100 0x414 0x000 0x0 0x0 253#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100 0x414 0x000 0x0 0x0
254#define MX6DL_PAD_DISP0_DAT6__LCD_DATA06 0x100 0x414 0x000 0x1 0x0 254#define MX6QDL_PAD_DISP0_DAT6__LCD_DATA06 0x100 0x414 0x000 0x1 0x0
255#define MX6DL_PAD_DISP0_DAT6__ECSPI3_SS3 0x100 0x414 0x000 0x2 0x0 255#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x100 0x414 0x000 0x2 0x0
256#define MX6DL_PAD_DISP0_DAT6__AUD6_RXC 0x100 0x414 0x000 0x3 0x0 256#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x100 0x414 0x000 0x3 0x0
257#define MX6DL_PAD_DISP0_DAT6__GPIO4_IO27 0x100 0x414 0x000 0x5 0x0 257#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x100 0x414 0x000 0x5 0x0
258#define MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x104 0x418 0x000 0x0 0x0 258#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x104 0x418 0x000 0x0 0x0
259#define MX6DL_PAD_DISP0_DAT7__LCD_DATA07 0x104 0x418 0x000 0x1 0x0 259#define MX6QDL_PAD_DISP0_DAT7__LCD_DATA07 0x104 0x418 0x000 0x1 0x0
260#define MX6DL_PAD_DISP0_DAT7__ECSPI3_RDY 0x104 0x418 0x000 0x2 0x0 260#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x104 0x418 0x000 0x2 0x0
261#define MX6DL_PAD_DISP0_DAT7__GPIO4_IO28 0x104 0x418 0x000 0x5 0x0 261#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x104 0x418 0x000 0x5 0x0
262#define MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x108 0x41c 0x000 0x0 0x0 262#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x108 0x41c 0x000 0x0 0x0
263#define MX6DL_PAD_DISP0_DAT8__LCD_DATA08 0x108 0x41c 0x000 0x1 0x0 263#define MX6QDL_PAD_DISP0_DAT8__LCD_DATA08 0x108 0x41c 0x000 0x1 0x0
264#define MX6DL_PAD_DISP0_DAT8__PWM1_OUT 0x108 0x41c 0x000 0x2 0x0 264#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x108 0x41c 0x000 0x2 0x0
265#define MX6DL_PAD_DISP0_DAT8__WDOG1_B 0x108 0x41c 0x000 0x3 0x0 265#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x108 0x41c 0x000 0x3 0x0
266#define MX6DL_PAD_DISP0_DAT8__GPIO4_IO29 0x108 0x41c 0x000 0x5 0x0 266#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x108 0x41c 0x000 0x5 0x0
267#define MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10c 0x420 0x000 0x0 0x0 267#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10c 0x420 0x000 0x0 0x0
268#define MX6DL_PAD_DISP0_DAT9__LCD_DATA09 0x10c 0x420 0x000 0x1 0x0 268#define MX6QDL_PAD_DISP0_DAT9__LCD_DATA09 0x10c 0x420 0x000 0x1 0x0
269#define MX6DL_PAD_DISP0_DAT9__PWM2_OUT 0x10c 0x420 0x000 0x2 0x0 269#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x10c 0x420 0x000 0x2 0x0
270#define MX6DL_PAD_DISP0_DAT9__WDOG2_B 0x10c 0x420 0x000 0x3 0x0 270#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x10c 0x420 0x000 0x3 0x0
271#define MX6DL_PAD_DISP0_DAT9__GPIO4_IO30 0x10c 0x420 0x000 0x5 0x0 271#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x10c 0x420 0x000 0x5 0x0
272#define MX6DL_PAD_EIM_A16__EIM_ADDR16 0x110 0x4e0 0x000 0x0 0x0 272#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x110 0x4e0 0x000 0x0 0x0
273#define MX6DL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x110 0x4e0 0x000 0x1 0x0 273#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x110 0x4e0 0x000 0x1 0x0
274#define MX6DL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x110 0x4e0 0x8b8 0x2 0x0 274#define MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x110 0x4e0 0x8b8 0x2 0x0
275#define MX6DL_PAD_EIM_A16__GPIO2_IO22 0x110 0x4e0 0x000 0x5 0x0 275#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x110 0x4e0 0x000 0x5 0x0
276#define MX6DL_PAD_EIM_A16__SRC_BOOT_CFG16 0x110 0x4e0 0x000 0x7 0x0 276#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x110 0x4e0 0x000 0x7 0x0
277#define MX6DL_PAD_EIM_A16__EPDC_DATA00 0x110 0x4e0 0x000 0x8 0x0 277#define MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x110 0x4e0 0x000 0x8 0x0
278#define MX6DL_PAD_EIM_A17__EIM_ADDR17 0x114 0x4e4 0x000 0x0 0x0 278#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x114 0x4e4 0x000 0x0 0x0
279#define MX6DL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x114 0x4e4 0x000 0x1 0x0 279#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x114 0x4e4 0x000 0x1 0x0
280#define MX6DL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x114 0x4e4 0x890 0x2 0x0 280#define MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x114 0x4e4 0x890 0x2 0x0
281#define MX6DL_PAD_EIM_A17__GPIO2_IO21 0x114 0x4e4 0x000 0x5 0x0 281#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x114 0x4e4 0x000 0x5 0x0
282#define MX6DL_PAD_EIM_A17__SRC_BOOT_CFG17 0x114 0x4e4 0x000 0x7 0x0 282#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x114 0x4e4 0x000 0x7 0x0
283#define MX6DL_PAD_EIM_A17__EPDC_PWR_STAT 0x114 0x4e4 0x000 0x8 0x0 283#define MX6QDL_PAD_EIM_A17__EPDC_PWR_STAT 0x114 0x4e4 0x000 0x8 0x0
284#define MX6DL_PAD_EIM_A18__EIM_ADDR18 0x118 0x4e8 0x000 0x0 0x0 284#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x118 0x4e8 0x000 0x0 0x0
285#define MX6DL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x118 0x4e8 0x000 0x1 0x0 285#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x118 0x4e8 0x000 0x1 0x0
286#define MX6DL_PAD_EIM_A18__IPU1_CSI1_DATA13 0x118 0x4e8 0x894 0x2 0x0 286#define MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0x118 0x4e8 0x894 0x2 0x0
287#define MX6DL_PAD_EIM_A18__GPIO2_IO20 0x118 0x4e8 0x000 0x5 0x0 287#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x118 0x4e8 0x000 0x5 0x0
288#define MX6DL_PAD_EIM_A18__SRC_BOOT_CFG18 0x118 0x4e8 0x000 0x7 0x0 288#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x118 0x4e8 0x000 0x7 0x0
289#define MX6DL_PAD_EIM_A18__EPDC_PWR_CTRL0 0x118 0x4e8 0x000 0x8 0x0 289#define MX6QDL_PAD_EIM_A18__EPDC_PWR_CTRL0 0x118 0x4e8 0x000 0x8 0x0
290#define MX6DL_PAD_EIM_A19__EIM_ADDR19 0x11c 0x4ec 0x000 0x0 0x0 290#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x11c 0x4ec 0x000 0x0 0x0
291#define MX6DL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x11c 0x4ec 0x000 0x1 0x0 291#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x11c 0x4ec 0x000 0x1 0x0
292#define MX6DL_PAD_EIM_A19__IPU1_CSI1_DATA14 0x11c 0x4ec 0x898 0x2 0x0 292#define MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0x11c 0x4ec 0x898 0x2 0x0
293#define MX6DL_PAD_EIM_A19__GPIO2_IO19 0x11c 0x4ec 0x000 0x5 0x0 293#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x11c 0x4ec 0x000 0x5 0x0
294#define MX6DL_PAD_EIM_A19__SRC_BOOT_CFG19 0x11c 0x4ec 0x000 0x7 0x0 294#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x11c 0x4ec 0x000 0x7 0x0
295#define MX6DL_PAD_EIM_A19__EPDC_PWR_CTRL1 0x11c 0x4ec 0x000 0x8 0x0 295#define MX6QDL_PAD_EIM_A19__EPDC_PWR_CTRL1 0x11c 0x4ec 0x000 0x8 0x0
296#define MX6DL_PAD_EIM_A20__EIM_ADDR20 0x120 0x4f0 0x000 0x0 0x0 296#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x120 0x4f0 0x000 0x0 0x0
297#define MX6DL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x120 0x4f0 0x000 0x1 0x0 297#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x120 0x4f0 0x000 0x1 0x0
298#define MX6DL_PAD_EIM_A20__IPU1_CSI1_DATA15 0x120 0x4f0 0x89c 0x2 0x0 298#define MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0x120 0x4f0 0x89c 0x2 0x0
299#define MX6DL_PAD_EIM_A20__GPIO2_IO18 0x120 0x4f0 0x000 0x5 0x0 299#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x120 0x4f0 0x000 0x5 0x0
300#define MX6DL_PAD_EIM_A20__SRC_BOOT_CFG20 0x120 0x4f0 0x000 0x7 0x0 300#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x120 0x4f0 0x000 0x7 0x0
301#define MX6DL_PAD_EIM_A20__EPDC_PWR_CTRL2 0x120 0x4f0 0x000 0x8 0x0 301#define MX6QDL_PAD_EIM_A20__EPDC_PWR_CTRL2 0x120 0x4f0 0x000 0x8 0x0
302#define MX6DL_PAD_EIM_A21__EIM_ADDR21 0x124 0x4f4 0x000 0x0 0x0 302#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x124 0x4f4 0x000 0x0 0x0
303#define MX6DL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x124 0x4f4 0x000 0x1 0x0 303#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x124 0x4f4 0x000 0x1 0x0
304#define MX6DL_PAD_EIM_A21__IPU1_CSI1_DATA16 0x124 0x4f4 0x8a0 0x2 0x0 304#define MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0x124 0x4f4 0x8a0 0x2 0x0
305#define MX6DL_PAD_EIM_A21__GPIO2_IO17 0x124 0x4f4 0x000 0x5 0x0 305#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x124 0x4f4 0x000 0x5 0x0
306#define MX6DL_PAD_EIM_A21__SRC_BOOT_CFG21 0x124 0x4f4 0x000 0x7 0x0 306#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x124 0x4f4 0x000 0x7 0x0
307#define MX6DL_PAD_EIM_A21__EPDC_GDCLK 0x124 0x4f4 0x000 0x8 0x0 307#define MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x124 0x4f4 0x000 0x8 0x0
308#define MX6DL_PAD_EIM_A22__EIM_ADDR22 0x128 0x4f8 0x000 0x0 0x0 308#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x128 0x4f8 0x000 0x0 0x0
309#define MX6DL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x128 0x4f8 0x000 0x1 0x0 309#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x128 0x4f8 0x000 0x1 0x0
310#define MX6DL_PAD_EIM_A22__IPU1_CSI1_DATA17 0x128 0x4f8 0x8a4 0x2 0x0 310#define MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0x128 0x4f8 0x8a4 0x2 0x0
311#define MX6DL_PAD_EIM_A22__GPIO2_IO16 0x128 0x4f8 0x000 0x5 0x0 311#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x128 0x4f8 0x000 0x5 0x0
312#define MX6DL_PAD_EIM_A22__SRC_BOOT_CFG22 0x128 0x4f8 0x000 0x7 0x0 312#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x128 0x4f8 0x000 0x7 0x0
313#define MX6DL_PAD_EIM_A22__EPDC_GDSP 0x128 0x4f8 0x000 0x8 0x0 313#define MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x128 0x4f8 0x000 0x8 0x0
314#define MX6DL_PAD_EIM_A23__EIM_ADDR23 0x12c 0x4fc 0x000 0x0 0x0 314#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x12c 0x4fc 0x000 0x0 0x0
315#define MX6DL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x12c 0x4fc 0x000 0x1 0x0 315#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x12c 0x4fc 0x000 0x1 0x0
316#define MX6DL_PAD_EIM_A23__IPU1_CSI1_DATA18 0x12c 0x4fc 0x8a8 0x2 0x0 316#define MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0x12c 0x4fc 0x8a8 0x2 0x0
317#define MX6DL_PAD_EIM_A23__IPU1_SISG3 0x12c 0x4fc 0x000 0x4 0x0 317#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x12c 0x4fc 0x000 0x4 0x0
318#define MX6DL_PAD_EIM_A23__GPIO6_IO06 0x12c 0x4fc 0x000 0x5 0x0 318#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x12c 0x4fc 0x000 0x5 0x0
319#define MX6DL_PAD_EIM_A23__SRC_BOOT_CFG23 0x12c 0x4fc 0x000 0x7 0x0 319#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x12c 0x4fc 0x000 0x7 0x0
320#define MX6DL_PAD_EIM_A23__EPDC_GDOE 0x12c 0x4fc 0x000 0x8 0x0 320#define MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x12c 0x4fc 0x000 0x8 0x0
321#define MX6DL_PAD_EIM_A24__EIM_ADDR24 0x130 0x500 0x000 0x0 0x0 321#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x130 0x500 0x000 0x0 0x0
322#define MX6DL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x130 0x500 0x000 0x1 0x0 322#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x130 0x500 0x000 0x1 0x0
323#define MX6DL_PAD_EIM_A24__IPU1_CSI1_DATA19 0x130 0x500 0x8ac 0x2 0x0 323#define MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0x130 0x500 0x8ac 0x2 0x0
324#define MX6DL_PAD_EIM_A24__IPU1_SISG2 0x130 0x500 0x000 0x4 0x0 324#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x130 0x500 0x000 0x4 0x0
325#define MX6DL_PAD_EIM_A24__GPIO5_IO04 0x130 0x500 0x000 0x5 0x0 325#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x130 0x500 0x000 0x5 0x0
326#define MX6DL_PAD_EIM_A24__SRC_BOOT_CFG24 0x130 0x500 0x000 0x7 0x0 326#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x130 0x500 0x000 0x7 0x0
327#define MX6DL_PAD_EIM_A24__EPDC_GDRL 0x130 0x500 0x000 0x8 0x0 327#define MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x130 0x500 0x000 0x8 0x0
328#define MX6DL_PAD_EIM_A25__EIM_ADDR25 0x134 0x504 0x000 0x0 0x0 328#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x134 0x504 0x000 0x0 0x0
329#define MX6DL_PAD_EIM_A25__ECSPI4_SS1 0x134 0x504 0x000 0x1 0x0 329#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x134 0x504 0x000 0x1 0x0
330#define MX6DL_PAD_EIM_A25__ECSPI2_RDY 0x134 0x504 0x000 0x2 0x0 330#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x134 0x504 0x000 0x2 0x0
331#define MX6DL_PAD_EIM_A25__IPU1_DI1_PIN12 0x134 0x504 0x000 0x3 0x0 331#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x134 0x504 0x000 0x3 0x0
332#define MX6DL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x134 0x504 0x000 0x4 0x0 332#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x134 0x504 0x000 0x4 0x0
333#define MX6DL_PAD_EIM_A25__GPIO5_IO02 0x134 0x504 0x000 0x5 0x0 333#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x134 0x504 0x000 0x5 0x0
334#define MX6DL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x134 0x504 0x85c 0x6 0x0 334#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x134 0x504 0x85c 0x6 0x0
335#define MX6DL_PAD_EIM_A25__EPDC_DATA15 0x134 0x504 0x000 0x8 0x0 335#define MX6QDL_PAD_EIM_A25__EPDC_DATA15 0x134 0x504 0x000 0x8 0x0
336#define MX6DL_PAD_EIM_A25__EIM_ACLK_FREERUN 0x134 0x504 0x000 0x9 0x0 336#define MX6QDL_PAD_EIM_A25__EIM_ACLK_FREERUN 0x134 0x504 0x000 0x9 0x0
337#define MX6DL_PAD_EIM_BCLK__EIM_BCLK 0x138 0x508 0x000 0x0 0x0 337#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x138 0x508 0x000 0x0 0x0
338#define MX6DL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x138 0x508 0x000 0x1 0x0 338#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x138 0x508 0x000 0x1 0x0
339#define MX6DL_PAD_EIM_BCLK__GPIO6_IO31 0x138 0x508 0x000 0x5 0x0 339#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x138 0x508 0x000 0x5 0x0
340#define MX6DL_PAD_EIM_BCLK__EPDC_SDCE9 0x138 0x508 0x000 0x8 0x0 340#define MX6QDL_PAD_EIM_BCLK__EPDC_SDCE9 0x138 0x508 0x000 0x8 0x0
341#define MX6DL_PAD_EIM_CS0__EIM_CS0_B 0x13c 0x50c 0x000 0x0 0x0 341#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x13c 0x50c 0x000 0x0 0x0
342#define MX6DL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x13c 0x50c 0x000 0x1 0x0 342#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x13c 0x50c 0x000 0x1 0x0
343#define MX6DL_PAD_EIM_CS0__ECSPI2_SCLK 0x13c 0x50c 0x7f4 0x2 0x2 343#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x13c 0x50c 0x7f4 0x2 0x2
344#define MX6DL_PAD_EIM_CS0__GPIO2_IO23 0x13c 0x50c 0x000 0x5 0x0 344#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x13c 0x50c 0x000 0x5 0x0
345#define MX6DL_PAD_EIM_CS0__EPDC_DATA06 0x13c 0x50c 0x000 0x8 0x0 345#define MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x13c 0x50c 0x000 0x8 0x0
346#define MX6DL_PAD_EIM_CS1__EIM_CS1_B 0x140 0x510 0x000 0x0 0x0 346#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x140 0x510 0x000 0x0 0x0
347#define MX6DL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x140 0x510 0x000 0x1 0x0 347#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x140 0x510 0x000 0x1 0x0
348#define MX6DL_PAD_EIM_CS1__ECSPI2_MOSI 0x140 0x510 0x7fc 0x2 0x2 348#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x140 0x510 0x7fc 0x2 0x2
349#define MX6DL_PAD_EIM_CS1__GPIO2_IO24 0x140 0x510 0x000 0x5 0x0 349#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x140 0x510 0x000 0x5 0x0
350#define MX6DL_PAD_EIM_CS1__EPDC_DATA08 0x140 0x510 0x000 0x8 0x0 350#define MX6QDL_PAD_EIM_CS1__EPDC_DATA08 0x140 0x510 0x000 0x8 0x0
351#define MX6DL_PAD_EIM_D16__EIM_DATA16 0x144 0x514 0x000 0x0 0x0 351#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x144 0x514 0x000 0x0 0x0
352#define MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x144 0x514 0x7d8 0x1 0x2 352#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x144 0x514 0x7d8 0x1 0x2
353#define MX6DL_PAD_EIM_D16__IPU1_DI0_PIN05 0x144 0x514 0x000 0x2 0x0 353#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x144 0x514 0x000 0x2 0x0
354#define MX6DL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x144 0x514 0x8a8 0x3 0x1 354#define MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x144 0x514 0x8a8 0x3 0x1
355#define MX6DL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x144 0x514 0x864 0x4 0x0 355#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x144 0x514 0x864 0x4 0x0
356#define MX6DL_PAD_EIM_D16__GPIO3_IO16 0x144 0x514 0x000 0x5 0x0 356#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x144 0x514 0x000 0x5 0x0
357#define MX6DL_PAD_EIM_D16__I2C2_SDA 0x144 0x514 0x874 0x6 0x0 357#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x144 0x514 0x874 0x6 0x0
358#define MX6DL_PAD_EIM_D16__EPDC_DATA10 0x144 0x514 0x000 0x8 0x0 358#define MX6QDL_PAD_EIM_D16__EPDC_DATA10 0x144 0x514 0x000 0x8 0x0
359#define MX6DL_PAD_EIM_D17__EIM_DATA17 0x148 0x518 0x000 0x0 0x0 359#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x148 0x518 0x000 0x0 0x0
360#define MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x148 0x518 0x7dc 0x1 0x2 360#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x148 0x518 0x7dc 0x1 0x2
361#define MX6DL_PAD_EIM_D17__IPU1_DI0_PIN06 0x148 0x518 0x000 0x2 0x0 361#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x148 0x518 0x000 0x2 0x0
362#define MX6DL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x148 0x518 0x8b8 0x3 0x1 362#define MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x148 0x518 0x8b8 0x3 0x1
363#define MX6DL_PAD_EIM_D17__DCIC1_OUT 0x148 0x518 0x000 0x4 0x0 363#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x148 0x518 0x000 0x4 0x0
364#define MX6DL_PAD_EIM_D17__GPIO3_IO17 0x148 0x518 0x000 0x5 0x0 364#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x148 0x518 0x000 0x5 0x0
365#define MX6DL_PAD_EIM_D17__I2C3_SCL 0x148 0x518 0x878 0x6 0x0 365#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x148 0x518 0x878 0x6 0x0
366#define MX6DL_PAD_EIM_D17__EPDC_VCOM0 0x148 0x518 0x000 0x8 0x0 366#define MX6QDL_PAD_EIM_D17__EPDC_VCOM0 0x148 0x518 0x000 0x8 0x0
367#define MX6DL_PAD_EIM_D18__EIM_DATA18 0x14c 0x51c 0x000 0x0 0x0 367#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x14c 0x51c 0x000 0x0 0x0
368#define MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x14c 0x51c 0x7e0 0x1 0x2 368#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x14c 0x51c 0x7e0 0x1 0x2
369#define MX6DL_PAD_EIM_D18__IPU1_DI0_PIN07 0x14c 0x51c 0x000 0x2 0x0 369#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x14c 0x51c 0x000 0x2 0x0
370#define MX6DL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x14c 0x51c 0x8a4 0x3 0x1 370#define MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x14c 0x51c 0x8a4 0x3 0x1
371#define MX6DL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x14c 0x51c 0x000 0x4 0x0 371#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x14c 0x51c 0x000 0x4 0x0
372#define MX6DL_PAD_EIM_D18__GPIO3_IO18 0x14c 0x51c 0x000 0x5 0x0 372#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x14c 0x51c 0x000 0x5 0x0
373#define MX6DL_PAD_EIM_D18__I2C3_SDA 0x14c 0x51c 0x87c 0x6 0x0 373#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x14c 0x51c 0x87c 0x6 0x0
374#define MX6DL_PAD_EIM_D18__EPDC_VCOM1 0x14c 0x51c 0x000 0x8 0x0 374#define MX6QDL_PAD_EIM_D18__EPDC_VCOM1 0x14c 0x51c 0x000 0x8 0x0
375#define MX6DL_PAD_EIM_D19__EIM_DATA19 0x150 0x520 0x000 0x0 0x0 375#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x150 0x520 0x000 0x0 0x0
376#define MX6DL_PAD_EIM_D19__ECSPI1_SS1 0x150 0x520 0x7e8 0x1 0x1 376#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x150 0x520 0x7e8 0x1 0x1
377#define MX6DL_PAD_EIM_D19__IPU1_DI0_PIN08 0x150 0x520 0x000 0x2 0x0 377#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x150 0x520 0x000 0x2 0x0
378#define MX6DL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x150 0x520 0x8a0 0x3 0x1 378#define MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x150 0x520 0x8a0 0x3 0x1
379#define MX6DL_PAD_EIM_D19__UART1_CTS_B 0x150 0x520 0x000 0x4 0x0 379#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x150 0x520 0x000 0x4 0x0
380#define MX6DL_PAD_EIM_D19__UART1_RTS_B 0x150 0x520 0x8f8 0x4 0x0 380#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x150 0x520 0x8f8 0x4 0x0
381#define MX6DL_PAD_EIM_D19__GPIO3_IO19 0x150 0x520 0x000 0x5 0x0 381#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x150 0x520 0x000 0x5 0x0
382#define MX6DL_PAD_EIM_D19__EPIT1_OUT 0x150 0x520 0x000 0x6 0x0 382#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x150 0x520 0x000 0x6 0x0
383#define MX6DL_PAD_EIM_D19__EPDC_DATA12 0x150 0x520 0x000 0x8 0x0 383#define MX6QDL_PAD_EIM_D19__EPDC_DATA12 0x150 0x520 0x000 0x8 0x0
384#define MX6DL_PAD_EIM_D20__EIM_DATA20 0x154 0x524 0x000 0x0 0x0 384#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x154 0x524 0x000 0x0 0x0
385#define MX6DL_PAD_EIM_D20__ECSPI4_SS0 0x154 0x524 0x808 0x1 0x0 385#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x154 0x524 0x808 0x1 0x0
386#define MX6DL_PAD_EIM_D20__IPU1_DI0_PIN16 0x154 0x524 0x000 0x2 0x0 386#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x154 0x524 0x000 0x2 0x0
387#define MX6DL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x154 0x524 0x89c 0x3 0x1 387#define MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x154 0x524 0x89c 0x3 0x1
388#define MX6DL_PAD_EIM_D20__UART1_RTS_B 0x154 0x524 0x8f8 0x4 0x1 388#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x154 0x524 0x8f8 0x4 0x1
389#define MX6DL_PAD_EIM_D20__UART1_CTS_B 0x154 0x524 0x000 0x4 0x0 389#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x154 0x524 0x000 0x4 0x0
390#define MX6DL_PAD_EIM_D20__GPIO3_IO20 0x154 0x524 0x000 0x5 0x0 390#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x154 0x524 0x000 0x5 0x0
391#define MX6DL_PAD_EIM_D20__EPIT2_OUT 0x154 0x524 0x000 0x6 0x0 391#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x154 0x524 0x000 0x6 0x0
392#define MX6DL_PAD_EIM_D21__EIM_DATA21 0x158 0x528 0x000 0x0 0x0 392#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x158 0x528 0x000 0x0 0x0
393#define MX6DL_PAD_EIM_D21__ECSPI4_SCLK 0x158 0x528 0x000 0x1 0x0 393#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x158 0x528 0x000 0x1 0x0
394#define MX6DL_PAD_EIM_D21__IPU1_DI0_PIN17 0x158 0x528 0x000 0x2 0x0 394#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x158 0x528 0x000 0x2 0x0
395#define MX6DL_PAD_EIM_D21__IPU1_CSI1_DATA11 0x158 0x528 0x88c 0x3 0x0 395#define MX6QDL_PAD_EIM_D21__IPU1_CSI1_DATA11 0x158 0x528 0x88c 0x3 0x0
396#define MX6DL_PAD_EIM_D21__USB_OTG_OC 0x158 0x528 0x920 0x4 0x0 396#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x158 0x528 0x920 0x4 0x0
397#define MX6DL_PAD_EIM_D21__GPIO3_IO21 0x158 0x528 0x000 0x5 0x0 397#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x158 0x528 0x000 0x5 0x0
398#define MX6DL_PAD_EIM_D21__I2C1_SCL 0x158 0x528 0x868 0x6 0x1 398#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x158 0x528 0x868 0x6 0x1
399#define MX6DL_PAD_EIM_D21__SPDIF_IN 0x158 0x528 0x8f0 0x7 0x0 399#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x158 0x528 0x8f0 0x7 0x0
400#define MX6DL_PAD_EIM_D22__EIM_DATA22 0x15c 0x52c 0x000 0x0 0x0 400#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x15c 0x52c 0x000 0x0 0x0
401#define MX6DL_PAD_EIM_D22__ECSPI4_MISO 0x15c 0x52c 0x000 0x1 0x0 401#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x15c 0x52c 0x000 0x1 0x0
402#define MX6DL_PAD_EIM_D22__IPU1_DI0_PIN01 0x15c 0x52c 0x000 0x2 0x0 402#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x15c 0x52c 0x000 0x2 0x0
403#define MX6DL_PAD_EIM_D22__IPU1_CSI1_DATA10 0x15c 0x52c 0x888 0x3 0x0 403#define MX6QDL_PAD_EIM_D22__IPU1_CSI1_DATA10 0x15c 0x52c 0x888 0x3 0x0
404#define MX6DL_PAD_EIM_D22__USB_OTG_PWR 0x15c 0x52c 0x000 0x4 0x0 404#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x15c 0x52c 0x000 0x4 0x0
405#define MX6DL_PAD_EIM_D22__GPIO3_IO22 0x15c 0x52c 0x000 0x5 0x0 405#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x15c 0x52c 0x000 0x5 0x0
406#define MX6DL_PAD_EIM_D22__SPDIF_OUT 0x15c 0x52c 0x000 0x6 0x0 406#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x15c 0x52c 0x000 0x6 0x0
407#define MX6DL_PAD_EIM_D22__EPDC_SDCE6 0x15c 0x52c 0x000 0x8 0x0 407#define MX6QDL_PAD_EIM_D22__EPDC_SDCE6 0x15c 0x52c 0x000 0x8 0x0
408#define MX6DL_PAD_EIM_D23__EIM_DATA23 0x160 0x530 0x000 0x0 0x0 408#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x160 0x530 0x000 0x0 0x0
409#define MX6DL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x160 0x530 0x000 0x1 0x0 409#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x160 0x530 0x000 0x1 0x0
410#define MX6DL_PAD_EIM_D23__UART3_CTS_B 0x160 0x530 0x000 0x2 0x0 410#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x160 0x530 0x000 0x2 0x0
411#define MX6DL_PAD_EIM_D23__UART3_RTS_B 0x160 0x530 0x908 0x2 0x0 411#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x160 0x530 0x908 0x2 0x0
412#define MX6DL_PAD_EIM_D23__UART1_DCD_B 0x160 0x530 0x000 0x3 0x0 412#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x160 0x530 0x000 0x3 0x0
413#define MX6DL_PAD_EIM_D23__IPU1_CSI1_DATA_EN 0x160 0x530 0x8b0 0x4 0x0 413#define MX6QDL_PAD_EIM_D23__IPU1_CSI1_DATA_EN 0x160 0x530 0x8b0 0x4 0x0
414#define MX6DL_PAD_EIM_D23__GPIO3_IO23 0x160 0x530 0x000 0x5 0x0 414#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x160 0x530 0x000 0x5 0x0
415#define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN02 0x160 0x530 0x000 0x6 0x0 415#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x160 0x530 0x000 0x6 0x0
416#define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN14 0x160 0x530 0x000 0x7 0x0 416#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x160 0x530 0x000 0x7 0x0
417#define MX6DL_PAD_EIM_D23__EPDC_DATA11 0x160 0x530 0x000 0x8 0x0 417#define MX6QDL_PAD_EIM_D23__EPDC_DATA11 0x160 0x530 0x000 0x8 0x0
418#define MX6DL_PAD_EIM_D24__EIM_DATA24 0x164 0x534 0x000 0x0 0x0 418#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x164 0x534 0x000 0x0 0x0
419#define MX6DL_PAD_EIM_D24__ECSPI4_SS2 0x164 0x534 0x000 0x1 0x0 419#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x164 0x534 0x000 0x1 0x0
420#define MX6DL_PAD_EIM_D24__UART3_TX_DATA 0x164 0x534 0x000 0x2 0x0 420#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x164 0x534 0x000 0x2 0x0
421#define MX6DL_PAD_EIM_D24__UART3_RX_DATA 0x164 0x534 0x90c 0x2 0x0 421#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x164 0x534 0x90c 0x2 0x0
422#define MX6DL_PAD_EIM_D24__ECSPI1_SS2 0x164 0x534 0x7ec 0x3 0x0 422#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x164 0x534 0x7ec 0x3 0x0
423#define MX6DL_PAD_EIM_D24__ECSPI2_SS2 0x164 0x534 0x000 0x4 0x0 423#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x164 0x534 0x000 0x4 0x0
424#define MX6DL_PAD_EIM_D24__GPIO3_IO24 0x164 0x534 0x000 0x5 0x0 424#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x164 0x534 0x000 0x5 0x0
425#define MX6DL_PAD_EIM_D24__AUD5_RXFS 0x164 0x534 0x7bc 0x6 0x1 425#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x164 0x534 0x7bc 0x6 0x1
426#define MX6DL_PAD_EIM_D24__UART1_DTR_B 0x164 0x534 0x000 0x7 0x0 426#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x164 0x534 0x000 0x7 0x0
427#define MX6DL_PAD_EIM_D24__EPDC_SDCE7 0x164 0x534 0x000 0x8 0x0 427#define MX6QDL_PAD_EIM_D24__EPDC_SDCE7 0x164 0x534 0x000 0x8 0x0
428#define MX6DL_PAD_EIM_D25__EIM_DATA25 0x168 0x538 0x000 0x0 0x0 428#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x168 0x538 0x000 0x0 0x0
429#define MX6DL_PAD_EIM_D25__ECSPI4_SS3 0x168 0x538 0x000 0x1 0x0 429#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x168 0x538 0x000 0x1 0x0
430#define MX6DL_PAD_EIM_D25__UART3_RX_DATA 0x168 0x538 0x90c 0x2 0x1 430#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x168 0x538 0x90c 0x2 0x1
431#define MX6DL_PAD_EIM_D25__UART3_TX_DATA 0x168 0x538 0x000 0x2 0x0 431#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x168 0x538 0x000 0x2 0x0
432#define MX6DL_PAD_EIM_D25__ECSPI1_SS3 0x168 0x538 0x7f0 0x3 0x0 432#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x168 0x538 0x7f0 0x3 0x0
433#define MX6DL_PAD_EIM_D25__ECSPI2_SS3 0x168 0x538 0x000 0x4 0x0 433#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x168 0x538 0x000 0x4 0x0
434#define MX6DL_PAD_EIM_D25__GPIO3_IO25 0x168 0x538 0x000 0x5 0x0 434#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x168 0x538 0x000 0x5 0x0
435#define MX6DL_PAD_EIM_D25__AUD5_RXC 0x168 0x538 0x7b8 0x6 0x1 435#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x168 0x538 0x7b8 0x6 0x1
436#define MX6DL_PAD_EIM_D25__UART1_DSR_B 0x168 0x538 0x000 0x7 0x0 436#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x168 0x538 0x000 0x7 0x0
437#define MX6DL_PAD_EIM_D25__EPDC_SDCE8 0x168 0x538 0x000 0x8 0x0 437#define MX6QDL_PAD_EIM_D25__EPDC_SDCE8 0x168 0x538 0x000 0x8 0x0
438#define MX6DL_PAD_EIM_D26__EIM_DATA26 0x16c 0x53c 0x000 0x0 0x0 438#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x16c 0x53c 0x000 0x0 0x0
439#define MX6DL_PAD_EIM_D26__IPU1_DI1_PIN11 0x16c 0x53c 0x000 0x1 0x0 439#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x16c 0x53c 0x000 0x1 0x0
440#define MX6DL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x16c 0x53c 0x000 0x2 0x0 440#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x16c 0x53c 0x000 0x2 0x0
441#define MX6DL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x16c 0x53c 0x898 0x3 0x1 441#define MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x16c 0x53c 0x898 0x3 0x1
442#define MX6DL_PAD_EIM_D26__UART2_TX_DATA 0x16c 0x53c 0x000 0x4 0x0 442#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x16c 0x53c 0x000 0x4 0x0
443#define MX6DL_PAD_EIM_D26__UART2_RX_DATA 0x16c 0x53c 0x904 0x4 0x0 443#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x16c 0x53c 0x904 0x4 0x0
444#define MX6DL_PAD_EIM_D26__GPIO3_IO26 0x16c 0x53c 0x000 0x5 0x0 444#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x16c 0x53c 0x000 0x5 0x0
445#define MX6DL_PAD_EIM_D26__IPU1_SISG2 0x16c 0x53c 0x000 0x6 0x0 445#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x16c 0x53c 0x000 0x6 0x0
446#define MX6DL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x16c 0x53c 0x000 0x7 0x0 446#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x16c 0x53c 0x000 0x7 0x0
447#define MX6DL_PAD_EIM_D26__EPDC_SDOED 0x16c 0x53c 0x000 0x8 0x0 447#define MX6QDL_PAD_EIM_D26__EPDC_SDOED 0x16c 0x53c 0x000 0x8 0x0
448#define MX6DL_PAD_EIM_D27__EIM_DATA27 0x170 0x540 0x000 0x0 0x0 448#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x170 0x540 0x000 0x0 0x0
449#define MX6DL_PAD_EIM_D27__IPU1_DI1_PIN13 0x170 0x540 0x000 0x1 0x0 449#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x170 0x540 0x000 0x1 0x0
450#define MX6DL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x170 0x540 0x000 0x2 0x0 450#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x170 0x540 0x000 0x2 0x0
451#define MX6DL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x170 0x540 0x894 0x3 0x1 451#define MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x170 0x540 0x894 0x3 0x1
452#define MX6DL_PAD_EIM_D27__UART2_RX_DATA 0x170 0x540 0x904 0x4 0x1 452#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x170 0x540 0x904 0x4 0x1
453#define MX6DL_PAD_EIM_D27__UART2_TX_DATA 0x170 0x540 0x000 0x4 0x0 453#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x170 0x540 0x000 0x4 0x0
454#define MX6DL_PAD_EIM_D27__GPIO3_IO27 0x170 0x540 0x000 0x5 0x0 454#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x170 0x540 0x000 0x5 0x0
455#define MX6DL_PAD_EIM_D27__IPU1_SISG3 0x170 0x540 0x000 0x6 0x0 455#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x170 0x540 0x000 0x6 0x0
456#define MX6DL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x170 0x540 0x000 0x7 0x0 456#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x170 0x540 0x000 0x7 0x0
457#define MX6DL_PAD_EIM_D27__EPDC_SDOE 0x170 0x540 0x000 0x8 0x0 457#define MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x170 0x540 0x000 0x8 0x0
458#define MX6DL_PAD_EIM_D28__EIM_DATA28 0x174 0x544 0x000 0x0 0x0 458#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x174 0x544 0x000 0x0 0x0
459#define MX6DL_PAD_EIM_D28__I2C1_SDA 0x174 0x544 0x86c 0x1 0x1 459#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x174 0x544 0x86c 0x1 0x1
460#define MX6DL_PAD_EIM_D28__ECSPI4_MOSI 0x174 0x544 0x000 0x2 0x0 460#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x174 0x544 0x000 0x2 0x0
461#define MX6DL_PAD_EIM_D28__IPU1_CSI1_DATA12 0x174 0x544 0x890 0x3 0x1 461#define MX6QDL_PAD_EIM_D28__IPU1_CSI1_DATA12 0x174 0x544 0x890 0x3 0x1
462#define MX6DL_PAD_EIM_D28__UART2_CTS_B 0x174 0x544 0x000 0x4 0x0 462#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x174 0x544 0x000 0x4 0x0
463#define MX6DL_PAD_EIM_D28__UART2_RTS_B 0x174 0x544 0x900 0x4 0x0 463#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x174 0x544 0x900 0x4 0x0
464#define MX6DL_PAD_EIM_D28__GPIO3_IO28 0x174 0x544 0x000 0x5 0x0 464#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x174 0x544 0x900 0x4 0x0
465#define MX6DL_PAD_EIM_D28__IPU1_EXT_TRIG 0x174 0x544 0x000 0x6 0x0 465#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x174 0x544 0x000 0x4 0x0
466#define MX6DL_PAD_EIM_D28__IPU1_DI0_PIN13 0x174 0x544 0x000 0x7 0x0 466#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x174 0x544 0x000 0x5 0x0
467#define MX6DL_PAD_EIM_D28__EPDC_PWR_CTRL3 0x174 0x544 0x000 0x8 0x0 467#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x174 0x544 0x000 0x6 0x0
468#define MX6DL_PAD_EIM_D29__EIM_DATA29 0x178 0x548 0x000 0x0 0x0 468#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x174 0x544 0x000 0x7 0x0
469#define MX6DL_PAD_EIM_D29__IPU1_DI1_PIN15 0x178 0x548 0x000 0x1 0x0 469#define MX6QDL_PAD_EIM_D28__EPDC_PWR_CTRL3 0x174 0x544 0x000 0x8 0x0
470#define MX6DL_PAD_EIM_D29__ECSPI4_SS0 0x178 0x548 0x808 0x2 0x1 470#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x178 0x548 0x000 0x0 0x0
471#define MX6DL_PAD_EIM_D29__UART2_RTS_B 0x178 0x548 0x900 0x4 0x1 471#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x178 0x548 0x000 0x1 0x0
472#define MX6DL_PAD_EIM_D29__UART2_CTS_B 0x178 0x548 0x000 0x4 0x0 472#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x178 0x548 0x808 0x2 0x1
473#define MX6DL_PAD_EIM_D29__GPIO3_IO29 0x178 0x548 0x000 0x5 0x0 473#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x178 0x548 0x900 0x4 0x1
474#define MX6DL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x178 0x548 0x8bc 0x6 0x0 474#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x178 0x548 0x000 0x4 0x0
475#define MX6DL_PAD_EIM_D29__IPU1_DI0_PIN14 0x178 0x548 0x000 0x7 0x0 475#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x178 0x548 0x000 0x4 0x0
476#define MX6DL_PAD_EIM_D29__EPDC_PWR_WAKE 0x178 0x548 0x000 0x8 0x0 476#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x178 0x548 0x900 0x4 0x1
477#define MX6DL_PAD_EIM_D30__EIM_DATA30 0x17c 0x54c 0x000 0x0 0x0 477#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x178 0x548 0x000 0x5 0x0
478#define MX6DL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x17c 0x54c 0x000 0x1 0x0 478#define MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x178 0x548 0x8bc 0x6 0x0
479#define MX6DL_PAD_EIM_D30__IPU1_DI0_PIN11 0x17c 0x54c 0x000 0x2 0x0 479#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x178 0x548 0x000 0x7 0x0
480#define MX6DL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x17c 0x54c 0x000 0x3 0x0 480#define MX6QDL_PAD_EIM_D29__EPDC_PWR_WAKE 0x178 0x548 0x000 0x8 0x0
481#define MX6DL_PAD_EIM_D30__UART3_CTS_B 0x17c 0x54c 0x000 0x4 0x0 481#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x17c 0x54c 0x000 0x0 0x0
482#define MX6DL_PAD_EIM_D30__UART3_RTS_B 0x17c 0x54c 0x908 0x4 0x1 482#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x17c 0x54c 0x000 0x1 0x0
483#define MX6DL_PAD_EIM_D30__GPIO3_IO30 0x17c 0x54c 0x000 0x5 0x0 483#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x17c 0x54c 0x000 0x2 0x0
484#define MX6DL_PAD_EIM_D30__USB_H1_OC 0x17c 0x54c 0x924 0x6 0x0 484#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x17c 0x54c 0x000 0x3 0x0
485#define MX6DL_PAD_EIM_D30__EPDC_SDOEZ 0x17c 0x54c 0x000 0x8 0x0 485#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x17c 0x54c 0x000 0x4 0x0
486#define MX6DL_PAD_EIM_D31__EIM_DATA31 0x180 0x550 0x000 0x0 0x0 486#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x17c 0x54c 0x908 0x4 0x1
487#define MX6DL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x180 0x550 0x000 0x1 0x0 487#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x17c 0x54c 0x000 0x5 0x0
488#define MX6DL_PAD_EIM_D31__IPU1_DI0_PIN12 0x180 0x550 0x000 0x2 0x0 488#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x17c 0x54c 0x924 0x6 0x0
489#define MX6DL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x180 0x550 0x000 0x3 0x0 489#define MX6QDL_PAD_EIM_D30__EPDC_SDOEZ 0x17c 0x54c 0x000 0x8 0x0
490#define MX6DL_PAD_EIM_D31__UART3_RTS_B 0x180 0x550 0x908 0x4 0x2 490#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x180 0x550 0x000 0x0 0x0
491#define MX6DL_PAD_EIM_D31__UART3_CTS_B 0x180 0x550 0x000 0x4 0x0 491#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x180 0x550 0x000 0x1 0x0
492#define MX6DL_PAD_EIM_D31__GPIO3_IO31 0x180 0x550 0x000 0x5 0x0 492#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x180 0x550 0x000 0x2 0x0
493#define MX6DL_PAD_EIM_D31__USB_H1_PWR 0x180 0x550 0x000 0x6 0x0 493#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x180 0x550 0x000 0x3 0x0
494#define MX6DL_PAD_EIM_D31__EPDC_SDCLK_P 0x180 0x550 0x000 0x8 0x0 494#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x180 0x550 0x908 0x4 0x2
495#define MX6DL_PAD_EIM_D31__EIM_ACLK_FREERUN 0x180 0x550 0x000 0x9 0x0 495#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x180 0x550 0x000 0x4 0x0
496#define MX6DL_PAD_EIM_DA0__EIM_AD00 0x184 0x554 0x000 0x0 0x0 496#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x180 0x550 0x000 0x5 0x0
497#define MX6DL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x184 0x554 0x000 0x1 0x0 497#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x180 0x550 0x000 0x6 0x0
498#define MX6DL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0x184 0x554 0x000 0x2 0x0 498#define MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x180 0x550 0x000 0x8 0x0
499#define MX6DL_PAD_EIM_DA0__GPIO3_IO00 0x184 0x554 0x000 0x5 0x0 499#define MX6QDL_PAD_EIM_D31__EIM_ACLK_FREERUN 0x180 0x550 0x000 0x9 0x0
500#define MX6DL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x184 0x554 0x000 0x7 0x0 500#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x184 0x554 0x000 0x0 0x0
501#define MX6DL_PAD_EIM_DA0__EPDC_SDCLK_N 0x184 0x554 0x000 0x8 0x0 501#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x184 0x554 0x000 0x1 0x0
502#define MX6DL_PAD_EIM_DA1__EIM_AD01 0x188 0x558 0x000 0x0 0x0 502#define MX6QDL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0x184 0x554 0x000 0x2 0x0
503#define MX6DL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x188 0x558 0x000 0x1 0x0 503#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x184 0x554 0x000 0x5 0x0
504#define MX6DL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0x188 0x558 0x000 0x2 0x0 504#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x184 0x554 0x000 0x7 0x0
505#define MX6DL_PAD_EIM_DA1__GPIO3_IO01 0x188 0x558 0x000 0x5 0x0 505#define MX6QDL_PAD_EIM_DA0__EPDC_SDCLK_N 0x184 0x554 0x000 0x8 0x0
506#define MX6DL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x188 0x558 0x000 0x7 0x0 506#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x188 0x558 0x000 0x0 0x0
507#define MX6DL_PAD_EIM_DA1__EPDC_SDLE 0x188 0x558 0x000 0x8 0x0 507#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x188 0x558 0x000 0x1 0x0
508#define MX6DL_PAD_EIM_DA10__EIM_AD10 0x18c 0x55c 0x000 0x0 0x0 508#define MX6QDL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0x188 0x558 0x000 0x2 0x0
509#define MX6DL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x18c 0x55c 0x000 0x1 0x0 509#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x188 0x558 0x000 0x5 0x0
510#define MX6DL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0x18c 0x55c 0x8b0 0x2 0x1 510#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x188 0x558 0x000 0x7 0x0
511#define MX6DL_PAD_EIM_DA10__GPIO3_IO10 0x18c 0x55c 0x000 0x5 0x0 511#define MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x188 0x558 0x000 0x8 0x0
512#define MX6DL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x18c 0x55c 0x000 0x7 0x0 512#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x18c 0x55c 0x000 0x0 0x0
513#define MX6DL_PAD_EIM_DA10__EPDC_DATA01 0x18c 0x55c 0x000 0x8 0x0 513#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x18c 0x55c 0x000 0x1 0x0
514#define MX6DL_PAD_EIM_DA11__EIM_AD11 0x190 0x560 0x000 0x0 0x0 514#define MX6QDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0x18c 0x55c 0x8b0 0x2 0x1
515#define MX6DL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x190 0x560 0x000 0x1 0x0 515#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x18c 0x55c 0x000 0x5 0x0
516#define MX6DL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0x190 0x560 0x8b4 0x2 0x0 516#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x18c 0x55c 0x000 0x7 0x0
517#define MX6DL_PAD_EIM_DA11__GPIO3_IO11 0x190 0x560 0x000 0x5 0x0 517#define MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x18c 0x55c 0x000 0x8 0x0
518#define MX6DL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x190 0x560 0x000 0x7 0x0 518#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x190 0x560 0x000 0x0 0x0
519#define MX6DL_PAD_EIM_DA11__EPDC_DATA03 0x190 0x560 0x000 0x8 0x0 519#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x190 0x560 0x000 0x1 0x0
520#define MX6DL_PAD_EIM_DA12__EIM_AD12 0x194 0x564 0x000 0x0 0x0 520#define MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0x190 0x560 0x8b4 0x2 0x0
521#define MX6DL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x194 0x564 0x000 0x1 0x0 521#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x190 0x560 0x000 0x5 0x0
522#define MX6DL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0x194 0x564 0x8bc 0x2 0x1 522#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x190 0x560 0x000 0x7 0x0
523#define MX6DL_PAD_EIM_DA12__GPIO3_IO12 0x194 0x564 0x000 0x5 0x0 523#define MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x190 0x560 0x000 0x8 0x0
524#define MX6DL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x194 0x564 0x000 0x7 0x0 524#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x194 0x564 0x000 0x0 0x0
525#define MX6DL_PAD_EIM_DA12__EPDC_DATA02 0x194 0x564 0x000 0x8 0x0 525#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x194 0x564 0x000 0x1 0x0
526#define MX6DL_PAD_EIM_DA13__EIM_AD13 0x198 0x568 0x000 0x0 0x0 526#define MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0x194 0x564 0x8bc 0x2 0x1
527#define MX6DL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x198 0x568 0x000 0x1 0x0 527#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x194 0x564 0x000 0x5 0x0
528#define MX6DL_PAD_EIM_DA13__GPIO3_IO13 0x198 0x568 0x000 0x5 0x0 528#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x194 0x564 0x000 0x7 0x0
529#define MX6DL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x198 0x568 0x000 0x7 0x0 529#define MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x194 0x564 0x000 0x8 0x0
530#define MX6DL_PAD_EIM_DA13__EPDC_DATA13 0x198 0x568 0x000 0x8 0x0 530#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x198 0x568 0x000 0x0 0x0
531#define MX6DL_PAD_EIM_DA14__EIM_AD14 0x19c 0x56c 0x000 0x0 0x0 531#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x198 0x568 0x000 0x1 0x0
532#define MX6DL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x19c 0x56c 0x000 0x1 0x0 532#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x198 0x568 0x000 0x5 0x0
533#define MX6DL_PAD_EIM_DA14__GPIO3_IO14 0x19c 0x56c 0x000 0x5 0x0 533#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x198 0x568 0x000 0x7 0x0
534#define MX6DL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x19c 0x56c 0x000 0x7 0x0 534#define MX6QDL_PAD_EIM_DA13__EPDC_DATA13 0x198 0x568 0x000 0x8 0x0
535#define MX6DL_PAD_EIM_DA14__EPDC_DATA14 0x19c 0x56c 0x000 0x8 0x0 535#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x19c 0x56c 0x000 0x0 0x0
536#define MX6DL_PAD_EIM_DA15__EIM_AD15 0x1a0 0x570 0x000 0x0 0x0 536#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x19c 0x56c 0x000 0x1 0x0
537#define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x1a0 0x570 0x000 0x1 0x0 537#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x19c 0x56c 0x000 0x5 0x0
538#define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x1a0 0x570 0x000 0x2 0x0 538#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x19c 0x56c 0x000 0x7 0x0
539#define MX6DL_PAD_EIM_DA15__GPIO3_IO15 0x1a0 0x570 0x000 0x5 0x0 539#define MX6QDL_PAD_EIM_DA14__EPDC_DATA14 0x19c 0x56c 0x000 0x8 0x0
540#define MX6DL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x1a0 0x570 0x000 0x7 0x0 540#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x1a0 0x570 0x000 0x0 0x0
541#define MX6DL_PAD_EIM_DA15__EPDC_DATA09 0x1a0 0x570 0x000 0x8 0x0 541#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x1a0 0x570 0x000 0x1 0x0
542#define MX6DL_PAD_EIM_DA2__EIM_AD02 0x1a4 0x574 0x000 0x0 0x0 542#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x1a0 0x570 0x000 0x2 0x0
543#define MX6DL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x1a4 0x574 0x000 0x1 0x0 543#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1a0 0x570 0x000 0x5 0x0
544#define MX6DL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0x1a4 0x574 0x000 0x2 0x0 544#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x1a0 0x570 0x000 0x7 0x0
545#define MX6DL_PAD_EIM_DA2__GPIO3_IO02 0x1a4 0x574 0x000 0x5 0x0 545#define MX6QDL_PAD_EIM_DA15__EPDC_DATA09 0x1a0 0x570 0x000 0x8 0x0
546#define MX6DL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x1a4 0x574 0x000 0x7 0x0 546#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x1a4 0x574 0x000 0x0 0x0
547#define MX6DL_PAD_EIM_DA2__EPDC_BDR0 0x1a4 0x574 0x000 0x8 0x0 547#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x1a4 0x574 0x000 0x1 0x0
548#define MX6DL_PAD_EIM_DA3__EIM_AD03 0x1a8 0x578 0x000 0x0 0x0 548#define MX6QDL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0x1a4 0x574 0x000 0x2 0x0
549#define MX6DL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x1a8 0x578 0x000 0x1 0x0 549#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1a4 0x574 0x000 0x5 0x0
550#define MX6DL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0x1a8 0x578 0x000 0x2 0x0 550#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x1a4 0x574 0x000 0x7 0x0
551#define MX6DL_PAD_EIM_DA3__GPIO3_IO03 0x1a8 0x578 0x000 0x5 0x0 551#define MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x1a4 0x574 0x000 0x8 0x0
552#define MX6DL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x1a8 0x578 0x000 0x7 0x0 552#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x1a8 0x578 0x000 0x0 0x0
553#define MX6DL_PAD_EIM_DA3__EPDC_BDR1 0x1a8 0x578 0x000 0x8 0x0 553#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x1a8 0x578 0x000 0x1 0x0
554#define MX6DL_PAD_EIM_DA4__EIM_AD04 0x1ac 0x57c 0x000 0x0 0x0 554#define MX6QDL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0x1a8 0x578 0x000 0x2 0x0
555#define MX6DL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x1ac 0x57c 0x000 0x1 0x0 555#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1a8 0x578 0x000 0x5 0x0
556#define MX6DL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0x1ac 0x57c 0x000 0x2 0x0 556#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x1a8 0x578 0x000 0x7 0x0
557#define MX6DL_PAD_EIM_DA4__GPIO3_IO04 0x1ac 0x57c 0x000 0x5 0x0 557#define MX6QDL_PAD_EIM_DA3__EPDC_BDR1 0x1a8 0x578 0x000 0x8 0x0
558#define MX6DL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x1ac 0x57c 0x000 0x7 0x0 558#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x1ac 0x57c 0x000 0x0 0x0
559#define MX6DL_PAD_EIM_DA4__EPDC_SDCE0 0x1ac 0x57c 0x000 0x8 0x0 559#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x1ac 0x57c 0x000 0x1 0x0
560#define MX6DL_PAD_EIM_DA5__EIM_AD05 0x1b0 0x580 0x000 0x0 0x0 560#define MX6QDL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0x1ac 0x57c 0x000 0x2 0x0
561#define MX6DL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x1b0 0x580 0x000 0x1 0x0 561#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1ac 0x57c 0x000 0x5 0x0
562#define MX6DL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0x1b0 0x580 0x000 0x2 0x0 562#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x1ac 0x57c 0x000 0x7 0x0
563#define MX6DL_PAD_EIM_DA5__GPIO3_IO05 0x1b0 0x580 0x000 0x5 0x0 563#define MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x1ac 0x57c 0x000 0x8 0x0
564#define MX6DL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x1b0 0x580 0x000 0x7 0x0 564#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x1b0 0x580 0x000 0x0 0x0
565#define MX6DL_PAD_EIM_DA5__EPDC_SDCE1 0x1b0 0x580 0x000 0x8 0x0 565#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x1b0 0x580 0x000 0x1 0x0
566#define MX6DL_PAD_EIM_DA6__EIM_AD06 0x1b4 0x584 0x000 0x0 0x0 566#define MX6QDL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0x1b0 0x580 0x000 0x2 0x0
567#define MX6DL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x1b4 0x584 0x000 0x1 0x0 567#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0 0x580 0x000 0x5 0x0
568#define MX6DL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0x1b4 0x584 0x000 0x2 0x0 568#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x1b0 0x580 0x000 0x7 0x0
569#define MX6DL_PAD_EIM_DA6__GPIO3_IO06 0x1b4 0x584 0x000 0x5 0x0 569#define MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x1b0 0x580 0x000 0x8 0x0
570#define MX6DL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x1b4 0x584 0x000 0x7 0x0 570#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x1b4 0x584 0x000 0x0 0x0
571#define MX6DL_PAD_EIM_DA6__EPDC_SDCE2 0x1b4 0x584 0x000 0x8 0x0 571#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x1b4 0x584 0x000 0x1 0x0
572#define MX6DL_PAD_EIM_DA7__EIM_AD07 0x1b8 0x588 0x000 0x0 0x0 572#define MX6QDL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0x1b4 0x584 0x000 0x2 0x0
573#define MX6DL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x1b8 0x588 0x000 0x1 0x0 573#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b4 0x584 0x000 0x5 0x0
574#define MX6DL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0x1b8 0x588 0x000 0x2 0x0 574#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x1b4 0x584 0x000 0x7 0x0
575#define MX6DL_PAD_EIM_DA7__GPIO3_IO07 0x1b8 0x588 0x000 0x5 0x0 575#define MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x1b4 0x584 0x000 0x8 0x0
576#define MX6DL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x1b8 0x588 0x000 0x7 0x0 576#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x1b8 0x588 0x000 0x0 0x0
577#define MX6DL_PAD_EIM_DA7__EPDC_SDCE3 0x1b8 0x588 0x000 0x8 0x0 577#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x1b8 0x588 0x000 0x1 0x0
578#define MX6DL_PAD_EIM_DA8__EIM_AD08 0x1bc 0x58c 0x000 0x0 0x0 578#define MX6QDL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0x1b8 0x588 0x000 0x2 0x0
579#define MX6DL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x1bc 0x58c 0x000 0x1 0x0 579#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b8 0x588 0x000 0x5 0x0
580#define MX6DL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0x1bc 0x58c 0x000 0x2 0x0 580#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x1b8 0x588 0x000 0x7 0x0
581#define MX6DL_PAD_EIM_DA8__GPIO3_IO08 0x1bc 0x58c 0x000 0x5 0x0 581#define MX6QDL_PAD_EIM_DA7__EPDC_SDCE3 0x1b8 0x588 0x000 0x8 0x0
582#define MX6DL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x1bc 0x58c 0x000 0x7 0x0 582#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x1bc 0x58c 0x000 0x0 0x0
583#define MX6DL_PAD_EIM_DA8__EPDC_SDCE4 0x1bc 0x58c 0x000 0x8 0x0 583#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x1bc 0x58c 0x000 0x1 0x0
584#define MX6DL_PAD_EIM_DA9__EIM_AD09 0x1c0 0x590 0x000 0x0 0x0 584#define MX6QDL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0x1bc 0x58c 0x000 0x2 0x0
585#define MX6DL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x1c0 0x590 0x000 0x1 0x0 585#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1bc 0x58c 0x000 0x5 0x0
586#define MX6DL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0x1c0 0x590 0x000 0x2 0x0 586#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x1bc 0x58c 0x000 0x7 0x0
587#define MX6DL_PAD_EIM_DA9__GPIO3_IO09 0x1c0 0x590 0x000 0x5 0x0 587#define MX6QDL_PAD_EIM_DA8__EPDC_SDCE4 0x1bc 0x58c 0x000 0x8 0x0
588#define MX6DL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x1c0 0x590 0x000 0x7 0x0 588#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x1c0 0x590 0x000 0x0 0x0
589#define MX6DL_PAD_EIM_DA9__EPDC_SDCE5 0x1c0 0x590 0x000 0x8 0x0 589#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x1c0 0x590 0x000 0x1 0x0
590#define MX6DL_PAD_EIM_EB0__EIM_EB0_B 0x1c4 0x594 0x000 0x0 0x0 590#define MX6QDL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0x1c0 0x590 0x000 0x2 0x0
591#define MX6DL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x1c4 0x594 0x000 0x1 0x0 591#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1c0 0x590 0x000 0x5 0x0
592#define MX6DL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0x1c4 0x594 0x88c 0x2 0x1 592#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x1c0 0x590 0x000 0x7 0x0
593#define MX6DL_PAD_EIM_EB0__CCM_PMIC_READY 0x1c4 0x594 0x7d4 0x4 0x0 593#define MX6QDL_PAD_EIM_DA9__EPDC_SDCE5 0x1c0 0x590 0x000 0x8 0x0
594#define MX6DL_PAD_EIM_EB0__GPIO2_IO28 0x1c4 0x594 0x000 0x5 0x0 594#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x1c4 0x594 0x000 0x0 0x0
595#define MX6DL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x1c4 0x594 0x000 0x7 0x0 595#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x1c4 0x594 0x000 0x1 0x0
596#define MX6DL_PAD_EIM_EB0__EPDC_PWR_COM 0x1c4 0x594 0x000 0x8 0x0 596#define MX6QDL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0x1c4 0x594 0x88c 0x2 0x1
597#define MX6DL_PAD_EIM_EB1__EIM_EB1_B 0x1c8 0x598 0x000 0x0 0x0 597#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x1c4 0x594 0x7d4 0x4 0x0
598#define MX6DL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x1c8 0x598 0x000 0x1 0x0 598#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1c4 0x594 0x000 0x5 0x0
599#define MX6DL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0x1c8 0x598 0x888 0x2 0x1 599#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x1c4 0x594 0x000 0x7 0x0
600#define MX6DL_PAD_EIM_EB1__GPIO2_IO29 0x1c8 0x598 0x000 0x5 0x0 600#define MX6QDL_PAD_EIM_EB0__EPDC_PWR_COM 0x1c4 0x594 0x000 0x8 0x0
601#define MX6DL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x1c8 0x598 0x000 0x7 0x0 601#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x1c8 0x598 0x000 0x0 0x0
602#define MX6DL_PAD_EIM_EB1__EPDC_SDSHR 0x1c8 0x598 0x000 0x8 0x0 602#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x1c8 0x598 0x000 0x1 0x0
603#define MX6DL_PAD_EIM_EB2__EIM_EB2_B 0x1cc 0x59c 0x000 0x0 0x0 603#define MX6QDL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0x1c8 0x598 0x888 0x2 0x1
604#define MX6DL_PAD_EIM_EB2__ECSPI1_SS0 0x1cc 0x59c 0x7e4 0x1 0x2 604#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1c8 0x598 0x000 0x5 0x0
605#define MX6DL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1cc 0x59c 0x8ac 0x3 0x1 605#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x1c8 0x598 0x000 0x7 0x0
606#define MX6DL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x1cc 0x59c 0x860 0x4 0x0 606#define MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x1c8 0x598 0x000 0x8 0x0
607#define MX6DL_PAD_EIM_EB2__GPIO2_IO30 0x1cc 0x59c 0x000 0x5 0x0 607#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x1cc 0x59c 0x000 0x0 0x0
608#define MX6DL_PAD_EIM_EB2__I2C2_SCL 0x1cc 0x59c 0x870 0x6 0x0 608#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x1cc 0x59c 0x7e4 0x1 0x2
609#define MX6DL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x1cc 0x59c 0x000 0x7 0x0 609#define MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1cc 0x59c 0x8ac 0x3 0x1
610#define MX6DL_PAD_EIM_EB2__EPDC_DATA05 0x1cc 0x59c 0x000 0x8 0x0 610#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x1cc 0x59c 0x860 0x4 0x0
611#define MX6DL_PAD_EIM_EB3__EIM_EB3_B 0x1d0 0x5a0 0x000 0x0 0x0 611#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1cc 0x59c 0x000 0x5 0x0
612#define MX6DL_PAD_EIM_EB3__ECSPI4_RDY 0x1d0 0x5a0 0x000 0x1 0x0 612#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x1cc 0x59c 0x870 0x6 0x0
613#define MX6DL_PAD_EIM_EB3__UART3_RTS_B 0x1d0 0x5a0 0x908 0x2 0x3 613#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x1cc 0x59c 0x000 0x7 0x0
614#define MX6DL_PAD_EIM_EB3__UART3_CTS_B 0x1d0 0x5a0 0x000 0x2 0x0 614#define MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x1cc 0x59c 0x000 0x8 0x0
615#define MX6DL_PAD_EIM_EB3__UART1_RI_B 0x1d0 0x5a0 0x000 0x3 0x0 615#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x1d0 0x5a0 0x000 0x0 0x0
616#define MX6DL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1d0 0x5a0 0x8b4 0x4 0x1 616#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x1d0 0x5a0 0x000 0x1 0x0
617#define MX6DL_PAD_EIM_EB3__GPIO2_IO31 0x1d0 0x5a0 0x000 0x5 0x0 617#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1d0 0x5a0 0x908 0x2 0x3
618#define MX6DL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x1d0 0x5a0 0x000 0x6 0x0 618#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1d0 0x5a0 0x000 0x2 0x0
619#define MX6DL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x1d0 0x5a0 0x000 0x7 0x0 619#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x1d0 0x5a0 0x000 0x3 0x0
620#define MX6DL_PAD_EIM_EB3__EPDC_SDCE0 0x1d0 0x5a0 0x000 0x8 0x0 620#define MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1d0 0x5a0 0x8b4 0x4 0x1
621#define MX6DL_PAD_EIM_EB3__EIM_ACLK_FREERUN 0x1d0 0x5a0 0x000 0x9 0x0 621#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1d0 0x5a0 0x000 0x5 0x0
622#define MX6DL_PAD_EIM_LBA__EIM_LBA_B 0x1d4 0x5a4 0x000 0x0 0x0 622#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x1d0 0x5a0 0x000 0x6 0x0
623#define MX6DL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x1d4 0x5a4 0x000 0x1 0x0 623#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x1d0 0x5a0 0x000 0x7 0x0
624#define MX6DL_PAD_EIM_LBA__ECSPI2_SS1 0x1d4 0x5a4 0x804 0x2 0x1 624#define MX6QDL_PAD_EIM_EB3__EPDC_SDCE0 0x1d0 0x5a0 0x000 0x8 0x0
625#define MX6DL_PAD_EIM_LBA__GPIO2_IO27 0x1d4 0x5a4 0x000 0x5 0x0 625#define MX6QDL_PAD_EIM_EB3__EIM_ACLK_FREERUN 0x1d0 0x5a0 0x000 0x9 0x0
626#define MX6DL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x1d4 0x5a4 0x000 0x7 0x0 626#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x1d4 0x5a4 0x000 0x0 0x0
627#define MX6DL_PAD_EIM_LBA__EPDC_DATA04 0x1d4 0x5a4 0x000 0x8 0x0 627#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x1d4 0x5a4 0x000 0x1 0x0
628#define MX6DL_PAD_EIM_OE__EIM_OE_B 0x1d8 0x5a8 0x000 0x0 0x0 628#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x1d4 0x5a4 0x804 0x2 0x1
629#define MX6DL_PAD_EIM_OE__IPU1_DI1_PIN07 0x1d8 0x5a8 0x000 0x1 0x0 629#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1d4 0x5a4 0x000 0x5 0x0
630#define MX6DL_PAD_EIM_OE__ECSPI2_MISO 0x1d8 0x5a8 0x7f8 0x2 0x2 630#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x1d4 0x5a4 0x000 0x7 0x0
631#define MX6DL_PAD_EIM_OE__GPIO2_IO25 0x1d8 0x5a8 0x000 0x5 0x0 631#define MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x1d4 0x5a4 0x000 0x8 0x0
632#define MX6DL_PAD_EIM_OE__EPDC_PWR_IRQ 0x1d8 0x5a8 0x000 0x8 0x0 632#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x1d8 0x5a8 0x000 0x0 0x0
633#define MX6DL_PAD_EIM_RW__EIM_RW 0x1dc 0x5ac 0x000 0x0 0x0 633#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x1d8 0x5a8 0x000 0x1 0x0
634#define MX6DL_PAD_EIM_RW__IPU1_DI1_PIN08 0x1dc 0x5ac 0x000 0x1 0x0 634#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1d8 0x5a8 0x7f8 0x2 0x2
635#define MX6DL_PAD_EIM_RW__ECSPI2_SS0 0x1dc 0x5ac 0x800 0x2 0x2 635#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1d8 0x5a8 0x000 0x5 0x0
636#define MX6DL_PAD_EIM_RW__GPIO2_IO26 0x1dc 0x5ac 0x000 0x5 0x0 636#define MX6QDL_PAD_EIM_OE__EPDC_PWR_IRQ 0x1d8 0x5a8 0x000 0x8 0x0
637#define MX6DL_PAD_EIM_RW__SRC_BOOT_CFG29 0x1dc 0x5ac 0x000 0x7 0x0 637#define MX6QDL_PAD_EIM_RW__EIM_RW 0x1dc 0x5ac 0x000 0x0 0x0
638#define MX6DL_PAD_EIM_RW__EPDC_DATA07 0x1dc 0x5ac 0x000 0x8 0x0 638#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x1dc 0x5ac 0x000 0x1 0x0
639#define MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0x1e0 0x5b0 0x000 0x0 0x0 639#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x1dc 0x5ac 0x800 0x2 0x2
640#define MX6DL_PAD_EIM_WAIT__EIM_DTACK_B 0x1e0 0x5b0 0x000 0x1 0x0 640#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1dc 0x5ac 0x000 0x5 0x0
641#define MX6DL_PAD_EIM_WAIT__GPIO5_IO00 0x1e0 0x5b0 0x000 0x5 0x0 641#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x1dc 0x5ac 0x000 0x7 0x0
642#define MX6DL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x1e0 0x5b0 0x000 0x7 0x0 642#define MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x1dc 0x5ac 0x000 0x8 0x0
643#define MX6DL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1e4 0x5b4 0x828 0x1 0x0 643#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x1e0 0x5b0 0x000 0x0 0x0
644#define MX6DL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1e4 0x5b4 0x840 0x2 0x0 644#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x1e0 0x5b0 0x000 0x1 0x0
645#define MX6DL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1e4 0x5b4 0x8f4 0x3 0x0 645#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1e0 0x5b0 0x000 0x5 0x0
646#define MX6DL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1e4 0x5b4 0x000 0x5 0x0 646#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x1e0 0x5b0 0x000 0x7 0x0
647#define MX6DL_PAD_ENET_MDC__MLB_DATA 0x1e8 0x5b8 0x8e0 0x0 0x0 647#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1e4 0x5b4 0x828 0x1 0x0
648#define MX6DL_PAD_ENET_MDC__ENET_MDC 0x1e8 0x5b8 0x000 0x1 0x0 648#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1e4 0x5b4 0x840 0x2 0x0
649#define MX6DL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1e8 0x5b8 0x858 0x2 0x0 649#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1e4 0x5b4 0x8f4 0x3 0x0
650#define MX6DL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1e8 0x5b8 0x000 0x4 0x0 650#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1e4 0x5b4 0x000 0x5 0x0
651#define MX6DL_PAD_ENET_MDC__GPIO1_IO31 0x1e8 0x5b8 0x000 0x5 0x0 651#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1e8 0x5b8 0x8e0 0x0 0x0
652#define MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1ec 0x5bc 0x810 0x1 0x0 652#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1e8 0x5b8 0x000 0x1 0x0
653#define MX6DL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1ec 0x5bc 0x83c 0x2 0x0 653#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1e8 0x5b8 0x858 0x2 0x0
654#define MX6DL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1ec 0x5bc 0x000 0x4 0x0 654#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1e8 0x5b8 0x000 0x4 0x0
655#define MX6DL_PAD_ENET_MDIO__GPIO1_IO22 0x1ec 0x5bc 0x000 0x5 0x0 655#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1e8 0x5b8 0x000 0x5 0x0
656#define MX6DL_PAD_ENET_MDIO__SPDIF_LOCK 0x1ec 0x5bc 0x000 0x6 0x0 656#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1ec 0x5bc 0x810 0x1 0x0
657#define MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1f0 0x5c0 0x000 0x1 0x0 657#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1ec 0x5bc 0x83c 0x2 0x0
658#define MX6DL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1f0 0x5c0 0x82c 0x2 0x0 658#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1ec 0x5bc 0x000 0x4 0x0
659#define MX6DL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1f0 0x5c0 0x000 0x5 0x0 659#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1ec 0x5bc 0x000 0x5 0x0
660#define MX6DL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1f0 0x5c0 0x000 0x6 0x0 660#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1ec 0x5bc 0x000 0x6 0x0
661#define MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f4 0x5c4 0x790 0x0 0x0 661#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1f0 0x5c0 0x000 0x1 0x0
662#define MX6DL_PAD_ENET_RX_ER__ENET_RX_ER 0x1f4 0x5c4 0x000 0x1 0x0 662#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1f0 0x5c0 0x82c 0x2 0x0
663#define MX6DL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1f4 0x5c4 0x834 0x2 0x0 663#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1f0 0x5c0 0x000 0x5 0x0
664#define MX6DL_PAD_ENET_RX_ER__SPDIF_IN 0x1f4 0x5c4 0x8f0 0x3 0x1 664#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1f0 0x5c0 0x000 0x6 0x0
665#define MX6DL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0 665#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f4 0x5c4 0x790 0x0 0x0
666#define MX6DL_PAD_ENET_RX_ER__GPIO1_IO24 0x1f4 0x5c4 0x000 0x5 0x0 666#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1f4 0x5c4 0x000 0x1 0x0
667#define MX6DL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1f8 0x5c8 0x818 0x1 0x0 667#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1f4 0x5c4 0x834 0x2 0x0
668#define MX6DL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1f8 0x5c8 0x838 0x2 0x0 668#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1f4 0x5c4 0x8f0 0x3 0x1
669#define MX6DL_PAD_ENET_RXD0__SPDIF_OUT 0x1f8 0x5c8 0x000 0x3 0x0 669#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0
670#define MX6DL_PAD_ENET_RXD0__GPIO1_IO27 0x1f8 0x5c8 0x000 0x5 0x0 670#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1f4 0x5c4 0x000 0x5 0x0
671#define MX6DL_PAD_ENET_RXD1__MLB_SIG 0x1fc 0x5cc 0x8e4 0x0 0x0 671#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1f8 0x5c8 0x818 0x1 0x0
672#define MX6DL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1fc 0x5cc 0x81c 0x1 0x0 672#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1f8 0x5c8 0x838 0x2 0x0
673#define MX6DL_PAD_ENET_RXD1__ESAI_TX_FS 0x1fc 0x5cc 0x830 0x2 0x0 673#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1f8 0x5c8 0x000 0x3 0x0
674#define MX6DL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1fc 0x5cc 0x000 0x4 0x0 674#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1f8 0x5c8 0x000 0x5 0x0
675#define MX6DL_PAD_ENET_RXD1__GPIO1_IO26 0x1fc 0x5cc 0x000 0x5 0x0 675#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1fc 0x5cc 0x8e4 0x0 0x0
676#define MX6DL_PAD_ENET_TX_EN__ENET_TX_EN 0x200 0x5d0 0x000 0x1 0x0 676#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1fc 0x5cc 0x81c 0x1 0x0
677#define MX6DL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x200 0x5d0 0x850 0x2 0x0 677#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1fc 0x5cc 0x830 0x2 0x0
678#define MX6DL_PAD_ENET_TX_EN__GPIO1_IO28 0x200 0x5d0 0x000 0x5 0x0 678#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1fc 0x5cc 0x000 0x4 0x0
679#define MX6DL_PAD_ENET_TX_EN__I2C4_SCL 0x200 0x5d0 0x880 0x9 0x0 679#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1fc 0x5cc 0x000 0x5 0x0
680#define MX6DL_PAD_ENET_TXD0__ENET_TX_DATA0 0x204 0x5d4 0x000 0x1 0x0 680#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x200 0x5d0 0x000 0x1 0x0
681#define MX6DL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x204 0x5d4 0x854 0x2 0x0 681#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x200 0x5d0 0x850 0x2 0x0
682#define MX6DL_PAD_ENET_TXD0__GPIO1_IO30 0x204 0x5d4 0x000 0x5 0x0 682#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x200 0x5d0 0x000 0x5 0x0
683#define MX6DL_PAD_ENET_TXD1__MLB_CLK 0x208 0x5d8 0x8dc 0x0 0x0 683#define MX6QDL_PAD_ENET_TX_EN__I2C4_SCL 0x200 0x5d0 0x880 0x9 0x0
684#define MX6DL_PAD_ENET_TXD1__ENET_TX_DATA1 0x208 0x5d8 0x000 0x1 0x0 684#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x204 0x5d4 0x000 0x1 0x0
685#define MX6DL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x208 0x5d8 0x84c 0x2 0x0 685#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x204 0x5d4 0x854 0x2 0x0
686#define MX6DL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x208 0x5d8 0x000 0x4 0x0 686#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x204 0x5d4 0x000 0x5 0x0
687#define MX6DL_PAD_ENET_TXD1__GPIO1_IO29 0x208 0x5d8 0x000 0x5 0x0 687#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x208 0x5d8 0x8dc 0x0 0x0
688#define MX6DL_PAD_ENET_TXD1__I2C4_SDA 0x208 0x5d8 0x884 0x9 0x0 688#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x208 0x5d8 0x000 0x1 0x0
689#define MX6DL_PAD_GPIO_0__CCM_CLKO1 0x20c 0x5dc 0x000 0x0 0x0 689#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x208 0x5d8 0x84c 0x2 0x0
690#define MX6DL_PAD_GPIO_0__KEY_COL5 0x20c 0x5dc 0x8c0 0x2 0x1 690#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x208 0x5d8 0x000 0x4 0x0
691#define MX6DL_PAD_GPIO_0__ASRC_EXT_CLK 0x20c 0x5dc 0x794 0x3 0x0 691#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x208 0x5d8 0x000 0x5 0x0
692#define MX6DL_PAD_GPIO_0__EPIT1_OUT 0x20c 0x5dc 0x000 0x4 0x0 692#define MX6QDL_PAD_ENET_TXD1__I2C4_SDA 0x208 0x5d8 0x884 0x9 0x0
693#define MX6DL_PAD_GPIO_0__GPIO1_IO00 0x20c 0x5dc 0x000 0x5 0x0 693#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x20c 0x5dc 0x000 0x0 0x0
694#define MX6DL_PAD_GPIO_0__USB_H1_PWR 0x20c 0x5dc 0x000 0x6 0x0 694#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x20c 0x5dc 0x8c0 0x2 0x1
695#define MX6DL_PAD_GPIO_0__SNVS_VIO_5 0x20c 0x5dc 0x000 0x7 0x0 695#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x20c 0x5dc 0x794 0x3 0x0
696#define MX6DL_PAD_GPIO_1__ESAI_RX_CLK 0x210 0x5e0 0x83c 0x0 0x1 696#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x20c 0x5dc 0x000 0x4 0x0
697#define MX6DL_PAD_GPIO_1__WDOG2_B 0x210 0x5e0 0x000 0x1 0x0 697#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x20c 0x5dc 0x000 0x5 0x0
698#define MX6DL_PAD_GPIO_1__KEY_ROW5 0x210 0x5e0 0x8cc 0x2 0x1 698#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x20c 0x5dc 0x000 0x6 0x0
699#define MX6DL_PAD_GPIO_1__USB_OTG_ID 0x210 0x5e0 0x790 0x3 0x1 699#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x20c 0x5dc 0x000 0x7 0x0
700#define MX6DL_PAD_GPIO_1__PWM2_OUT 0x210 0x5e0 0x000 0x4 0x0 700#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x210 0x5e0 0x83c 0x0 0x1
701#define MX6DL_PAD_GPIO_1__GPIO1_IO01 0x210 0x5e0 0x000 0x5 0x0 701#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x210 0x5e0 0x000 0x1 0x0
702#define MX6DL_PAD_GPIO_1__SD1_CD_B 0x210 0x5e0 0x000 0x6 0x0 702#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x210 0x5e0 0x8cc 0x2 0x1
703#define MX6DL_PAD_GPIO_16__ESAI_TX3_RX2 0x214 0x5e4 0x850 0x0 0x1 703#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x210 0x5e0 0x790 0x3 0x1
704#define MX6DL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x214 0x5e4 0x000 0x1 0x0 704#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x210 0x5e0 0x000 0x4 0x0
705#define MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x214 0x5e4 0x80c 0x2 0x0 705#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x210 0x5e0 0x000 0x5 0x0
706#define MX6DL_PAD_GPIO_16__SD1_LCTL 0x214 0x5e4 0x000 0x3 0x0 706#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x210 0x5e0 0x000 0x6 0x0
707#define MX6DL_PAD_GPIO_16__SPDIF_IN 0x214 0x5e4 0x8f0 0x4 0x2 707#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x214 0x5e4 0x850 0x0 0x1
708#define MX6DL_PAD_GPIO_16__GPIO7_IO11 0x214 0x5e4 0x000 0x5 0x0 708#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x214 0x5e4 0x000 0x1 0x0
709#define MX6DL_PAD_GPIO_16__I2C3_SDA 0x214 0x5e4 0x87c 0x6 0x1 709#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x214 0x5e4 0x80c 0x2 0x0
710#define MX6DL_PAD_GPIO_16__JTAG_DE_B 0x214 0x5e4 0x000 0x7 0x0 710#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x214 0x5e4 0x000 0x3 0x0
711#define MX6DL_PAD_GPIO_17__ESAI_TX0 0x218 0x5e8 0x844 0x0 0x0 711#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x214 0x5e4 0x8f0 0x4 0x2
712#define MX6DL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x218 0x5e8 0x000 0x1 0x0 712#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x214 0x5e4 0x000 0x5 0x0
713#define MX6DL_PAD_GPIO_17__CCM_PMIC_READY 0x218 0x5e8 0x7d4 0x2 0x1 713#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x214 0x5e4 0x87c 0x6 0x1
714#define MX6DL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x218 0x5e8 0x8e8 0x3 0x1 714#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x214 0x5e4 0x000 0x7 0x0
715#define MX6DL_PAD_GPIO_17__SPDIF_OUT 0x218 0x5e8 0x000 0x4 0x0 715#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x218 0x5e8 0x844 0x0 0x0
716#define MX6DL_PAD_GPIO_17__GPIO7_IO12 0x218 0x5e8 0x000 0x5 0x0 716#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x218 0x5e8 0x000 0x1 0x0
717#define MX6DL_PAD_GPIO_18__ESAI_TX1 0x21c 0x5ec 0x848 0x0 0x0 717#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x218 0x5e8 0x7d4 0x2 0x1
718#define MX6DL_PAD_GPIO_18__ENET_RX_CLK 0x21c 0x5ec 0x814 0x1 0x0 718#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x218 0x5e8 0x8e8 0x3 0x1
719#define MX6DL_PAD_GPIO_18__SD3_VSELECT 0x21c 0x5ec 0x000 0x2 0x0 719#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x218 0x5e8 0x000 0x4 0x0
720#define MX6DL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x21c 0x5ec 0x8ec 0x3 0x1 720#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x218 0x5e8 0x000 0x5 0x0
721#define MX6DL_PAD_GPIO_18__ASRC_EXT_CLK 0x21c 0x5ec 0x794 0x4 0x1 721#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x21c 0x5ec 0x848 0x0 0x0
722#define MX6DL_PAD_GPIO_18__GPIO7_IO13 0x21c 0x5ec 0x000 0x5 0x0 722#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x21c 0x5ec 0x814 0x1 0x0
723#define MX6DL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x21c 0x5ec 0x000 0x6 0x0 723#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x21c 0x5ec 0x000 0x2 0x0
724#define MX6DL_PAD_GPIO_19__KEY_COL5 0x220 0x5f0 0x8c0 0x0 0x2 724#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x21c 0x5ec 0x8ec 0x3 0x1
725#define MX6DL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x220 0x5f0 0x000 0x1 0x0 725#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x21c 0x5ec 0x794 0x4 0x1
726#define MX6DL_PAD_GPIO_19__SPDIF_OUT 0x220 0x5f0 0x000 0x2 0x0 726#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x21c 0x5ec 0x000 0x5 0x0
727#define MX6DL_PAD_GPIO_19__CCM_CLKO1 0x220 0x5f0 0x000 0x3 0x0 727#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x21c 0x5ec 0x000 0x6 0x0
728#define MX6DL_PAD_GPIO_19__ECSPI1_RDY 0x220 0x5f0 0x000 0x4 0x0 728#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x220 0x5f0 0x8c0 0x0 0x2
729#define MX6DL_PAD_GPIO_19__GPIO4_IO05 0x220 0x5f0 0x000 0x5 0x0 729#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x220 0x5f0 0x000 0x1 0x0
730#define MX6DL_PAD_GPIO_19__ENET_TX_ER 0x220 0x5f0 0x000 0x6 0x0 730#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x220 0x5f0 0x000 0x2 0x0
731#define MX6DL_PAD_GPIO_2__ESAI_TX_FS 0x224 0x5f4 0x830 0x0 0x1 731#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x220 0x5f0 0x000 0x3 0x0
732#define MX6DL_PAD_GPIO_2__KEY_ROW6 0x224 0x5f4 0x8d0 0x2 0x1 732#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x220 0x5f0 0x000 0x4 0x0
733#define MX6DL_PAD_GPIO_2__GPIO1_IO02 0x224 0x5f4 0x000 0x5 0x0 733#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x220 0x5f0 0x000 0x5 0x0
734#define MX6DL_PAD_GPIO_2__SD2_WP 0x224 0x5f4 0x000 0x6 0x0 734#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x220 0x5f0 0x000 0x6 0x0
735#define MX6DL_PAD_GPIO_2__MLB_DATA 0x224 0x5f4 0x8e0 0x7 0x1 735#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x224 0x5f4 0x830 0x0 0x1
736#define MX6DL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x228 0x5f8 0x834 0x0 0x1 736#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x224 0x5f4 0x8d0 0x2 0x1
737#define MX6DL_PAD_GPIO_3__I2C3_SCL 0x228 0x5f8 0x878 0x2 0x1 737#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x224 0x5f4 0x000 0x5 0x0
738#define MX6DL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x228 0x5f8 0x000 0x3 0x0 738#define MX6QDL_PAD_GPIO_2__SD2_WP 0x224 0x5f4 0x000 0x6 0x0
739#define MX6DL_PAD_GPIO_3__CCM_CLKO2 0x228 0x5f8 0x000 0x4 0x0 739#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x224 0x5f4 0x8e0 0x7 0x1
740#define MX6DL_PAD_GPIO_3__GPIO1_IO03 0x228 0x5f8 0x000 0x5 0x0 740#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x228 0x5f8 0x834 0x0 0x1
741#define MX6DL_PAD_GPIO_3__USB_H1_OC 0x228 0x5f8 0x924 0x6 0x1 741#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x228 0x5f8 0x878 0x2 0x1
742#define MX6DL_PAD_GPIO_3__MLB_CLK 0x228 0x5f8 0x8dc 0x7 0x1 742#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x228 0x5f8 0x000 0x3 0x0
743#define MX6DL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x22c 0x5fc 0x838 0x0 0x1 743#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x228 0x5f8 0x000 0x4 0x0
744#define MX6DL_PAD_GPIO_4__KEY_COL7 0x22c 0x5fc 0x8c8 0x2 0x1 744#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x228 0x5f8 0x000 0x5 0x0
745#define MX6DL_PAD_GPIO_4__GPIO1_IO04 0x22c 0x5fc 0x000 0x5 0x0 745#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x228 0x5f8 0x924 0x6 0x1
746#define MX6DL_PAD_GPIO_4__SD2_CD_B 0x22c 0x5fc 0x000 0x6 0x0 746#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x228 0x5f8 0x8dc 0x7 0x1
747#define MX6DL_PAD_GPIO_5__ESAI_TX2_RX3 0x230 0x600 0x84c 0x0 0x1 747#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x22c 0x5fc 0x838 0x0 0x1
748#define MX6DL_PAD_GPIO_5__KEY_ROW7 0x230 0x600 0x8d4 0x2 0x1 748#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x22c 0x5fc 0x8c8 0x2 0x1
749#define MX6DL_PAD_GPIO_5__CCM_CLKO1 0x230 0x600 0x000 0x3 0x0 749#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x22c 0x5fc 0x000 0x5 0x0
750#define MX6DL_PAD_GPIO_5__GPIO1_IO05 0x230 0x600 0x000 0x5 0x0 750#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x22c 0x5fc 0x000 0x6 0x0
751#define MX6DL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2 751#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x230 0x600 0x84c 0x0 0x1
752#define MX6DL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0 752#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x230 0x600 0x8d4 0x2 0x1
753#define MX6DL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1 753#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x230 0x600 0x000 0x3 0x0
754#define MX6DL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2 754#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x230 0x600 0x000 0x5 0x0
755#define MX6DL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0 755#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2
756#define MX6DL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0 756#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0
757#define MX6DL_PAD_GPIO_6__MLB_SIG 0x234 0x604 0x8e4 0x7 0x1 757#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1
758#define MX6DL_PAD_GPIO_7__ESAI_TX4_RX1 0x238 0x608 0x854 0x0 0x1 758#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2
759#define MX6DL_PAD_GPIO_7__EPIT1_OUT 0x238 0x608 0x000 0x2 0x0 759#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0
760#define MX6DL_PAD_GPIO_7__FLEXCAN1_TX 0x238 0x608 0x000 0x3 0x0 760#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0
761#define MX6DL_PAD_GPIO_7__UART2_TX_DATA 0x238 0x608 0x000 0x4 0x0 761#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x234 0x604 0x8e4 0x7 0x1
762#define MX6DL_PAD_GPIO_7__UART2_RX_DATA 0x238 0x608 0x904 0x4 0x2 762#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x238 0x608 0x854 0x0 0x1
763#define MX6DL_PAD_GPIO_7__GPIO1_IO07 0x238 0x608 0x000 0x5 0x0 763#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x238 0x608 0x000 0x2 0x0
764#define MX6DL_PAD_GPIO_7__SPDIF_LOCK 0x238 0x608 0x000 0x6 0x0 764#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x238 0x608 0x000 0x3 0x0
765#define MX6DL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x238 0x608 0x000 0x7 0x0 765#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x238 0x608 0x000 0x4 0x0
766#define MX6DL_PAD_GPIO_7__I2C4_SCL 0x238 0x608 0x880 0x8 0x1 766#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x238 0x608 0x904 0x4 0x2
767#define MX6DL_PAD_GPIO_8__ESAI_TX5_RX0 0x23c 0x60c 0x858 0x0 0x1 767#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x238 0x608 0x000 0x5 0x0
768#define MX6DL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x23c 0x60c 0x000 0x1 0x0 768#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x238 0x608 0x000 0x6 0x0
769#define MX6DL_PAD_GPIO_8__EPIT2_OUT 0x23c 0x60c 0x000 0x2 0x0 769#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x238 0x608 0x000 0x7 0x0
770#define MX6DL_PAD_GPIO_8__FLEXCAN1_RX 0x23c 0x60c 0x7c8 0x3 0x0 770#define MX6QDL_PAD_GPIO_7__I2C4_SCL 0x238 0x608 0x880 0x8 0x1
771#define MX6DL_PAD_GPIO_8__UART2_RX_DATA 0x23c 0x60c 0x904 0x4 0x3 771#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x23c 0x60c 0x858 0x0 0x1
772#define MX6DL_PAD_GPIO_8__UART2_TX_DATA 0x23c 0x60c 0x000 0x4 0x0 772#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x23c 0x60c 0x000 0x1 0x0
773#define MX6DL_PAD_GPIO_8__GPIO1_IO08 0x23c 0x60c 0x000 0x5 0x0 773#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x23c 0x60c 0x000 0x2 0x0
774#define MX6DL_PAD_GPIO_8__SPDIF_SR_CLK 0x23c 0x60c 0x000 0x6 0x0 774#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x23c 0x60c 0x7c8 0x3 0x0
775#define MX6DL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x23c 0x60c 0x000 0x7 0x0 775#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x23c 0x60c 0x904 0x4 0x3
776#define MX6DL_PAD_GPIO_8__I2C4_SDA 0x23c 0x60c 0x884 0x8 0x1 776#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x23c 0x60c 0x000 0x4 0x0
777#define MX6DL_PAD_GPIO_9__ESAI_RX_FS 0x240 0x610 0x82c 0x0 0x1 777#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x23c 0x60c 0x000 0x5 0x0
778#define MX6DL_PAD_GPIO_9__WDOG1_B 0x240 0x610 0x000 0x1 0x0 778#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x23c 0x60c 0x000 0x6 0x0
779#define MX6DL_PAD_GPIO_9__KEY_COL6 0x240 0x610 0x8c4 0x2 0x1 779#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x23c 0x60c 0x000 0x7 0x0
780#define MX6DL_PAD_GPIO_9__CCM_REF_EN_B 0x240 0x610 0x000 0x3 0x0 780#define MX6QDL_PAD_GPIO_8__I2C4_SDA 0x23c 0x60c 0x884 0x8 0x1
781#define MX6DL_PAD_GPIO_9__PWM1_OUT 0x240 0x610 0x000 0x4 0x0 781#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x240 0x610 0x82c 0x0 0x1
782#define MX6DL_PAD_GPIO_9__GPIO1_IO09 0x240 0x610 0x000 0x5 0x0 782#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x240 0x610 0x000 0x1 0x0
783#define MX6DL_PAD_GPIO_9__SD1_WP 0x240 0x610 0x92c 0x6 0x1 783#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x240 0x610 0x8c4 0x2 0x1
784#define MX6DL_PAD_KEY_COL0__ECSPI1_SCLK 0x244 0x62c 0x7d8 0x0 0x3 784#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x240 0x610 0x000 0x3 0x0
785#define MX6DL_PAD_KEY_COL0__ENET_RX_DATA3 0x244 0x62c 0x824 0x1 0x0 785#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x240 0x610 0x000 0x4 0x0
786#define MX6DL_PAD_KEY_COL0__AUD5_TXC 0x244 0x62c 0x7c0 0x2 0x1 786#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x240 0x610 0x000 0x5 0x0
787#define MX6DL_PAD_KEY_COL0__KEY_COL0 0x244 0x62c 0x000 0x3 0x0 787#define MX6QDL_PAD_GPIO_9__SD1_WP 0x240 0x610 0x92c 0x6 0x1
788#define MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x244 0x62c 0x000 0x4 0x0 788#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x244 0x62c 0x7d8 0x0 0x3
789#define MX6DL_PAD_KEY_COL0__UART4_RX_DATA 0x244 0x62c 0x914 0x4 0x2 789#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x244 0x62c 0x824 0x1 0x0
790#define MX6DL_PAD_KEY_COL0__GPIO4_IO06 0x244 0x62c 0x000 0x5 0x0 790#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x244 0x62c 0x7c0 0x2 0x1
791#define MX6DL_PAD_KEY_COL0__DCIC1_OUT 0x244 0x62c 0x000 0x6 0x0 791#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x244 0x62c 0x000 0x3 0x0
792#define MX6DL_PAD_KEY_COL1__ECSPI1_MISO 0x248 0x630 0x7dc 0x0 0x3 792#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x244 0x62c 0x000 0x4 0x0
793#define MX6DL_PAD_KEY_COL1__ENET_MDIO 0x248 0x630 0x810 0x1 0x1 793#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x244 0x62c 0x914 0x4 0x2
794#define MX6DL_PAD_KEY_COL1__AUD5_TXFS 0x248 0x630 0x7c4 0x2 0x1 794#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x244 0x62c 0x000 0x5 0x0
795#define MX6DL_PAD_KEY_COL1__KEY_COL1 0x248 0x630 0x000 0x3 0x0 795#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x244 0x62c 0x000 0x6 0x0
796#define MX6DL_PAD_KEY_COL1__UART5_TX_DATA 0x248 0x630 0x000 0x4 0x0 796#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x248 0x630 0x7dc 0x0 0x3
797#define MX6DL_PAD_KEY_COL1__UART5_RX_DATA 0x248 0x630 0x91c 0x4 0x2 797#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x248 0x630 0x810 0x1 0x1
798#define MX6DL_PAD_KEY_COL1__GPIO4_IO08 0x248 0x630 0x000 0x5 0x0 798#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x248 0x630 0x7c4 0x2 0x1
799#define MX6DL_PAD_KEY_COL1__SD1_VSELECT 0x248 0x630 0x000 0x6 0x0 799#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x248 0x630 0x000 0x3 0x0
800#define MX6DL_PAD_KEY_COL2__ECSPI1_SS1 0x24c 0x634 0x7e8 0x0 0x2 800#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x248 0x630 0x000 0x4 0x0
801#define MX6DL_PAD_KEY_COL2__ENET_RX_DATA2 0x24c 0x634 0x820 0x1 0x0 801#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x248 0x630 0x91c 0x4 0x2
802#define MX6DL_PAD_KEY_COL2__FLEXCAN1_TX 0x24c 0x634 0x000 0x2 0x0 802#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x248 0x630 0x000 0x5 0x0
803#define MX6DL_PAD_KEY_COL2__KEY_COL2 0x24c 0x634 0x000 0x3 0x0 803#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x248 0x630 0x000 0x6 0x0
804#define MX6DL_PAD_KEY_COL2__ENET_MDC 0x24c 0x634 0x000 0x4 0x0 804#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x24c 0x634 0x7e8 0x0 0x2
805#define MX6DL_PAD_KEY_COL2__GPIO4_IO10 0x24c 0x634 0x000 0x5 0x0 805#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x24c 0x634 0x820 0x1 0x0
806#define MX6DL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x24c 0x634 0x000 0x6 0x0 806#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x24c 0x634 0x000 0x2 0x0
807#define MX6DL_PAD_KEY_COL3__ECSPI1_SS3 0x250 0x638 0x7f0 0x0 0x1 807#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x24c 0x634 0x000 0x3 0x0
808#define MX6DL_PAD_KEY_COL3__ENET_CRS 0x250 0x638 0x000 0x1 0x0 808#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x24c 0x634 0x000 0x4 0x0
809#define MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x250 0x638 0x860 0x2 0x1 809#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x24c 0x634 0x000 0x5 0x0
810#define MX6DL_PAD_KEY_COL3__KEY_COL3 0x250 0x638 0x000 0x3 0x0 810#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x24c 0x634 0x000 0x6 0x0
811#define MX6DL_PAD_KEY_COL3__I2C2_SCL 0x250 0x638 0x870 0x4 0x1 811#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x250 0x638 0x7f0 0x0 0x1
812#define MX6DL_PAD_KEY_COL3__GPIO4_IO12 0x250 0x638 0x000 0x5 0x0 812#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x250 0x638 0x000 0x1 0x0
813#define MX6DL_PAD_KEY_COL3__SPDIF_IN 0x250 0x638 0x8f0 0x6 0x3 813#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x250 0x638 0x860 0x2 0x1
814#define MX6DL_PAD_KEY_COL4__FLEXCAN2_TX 0x254 0x63c 0x000 0x0 0x0 814#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x250 0x638 0x000 0x3 0x0
815#define MX6DL_PAD_KEY_COL4__IPU1_SISG4 0x254 0x63c 0x000 0x1 0x0 815#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x250 0x638 0x870 0x4 0x1
816#define MX6DL_PAD_KEY_COL4__USB_OTG_OC 0x254 0x63c 0x920 0x2 0x1 816#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x250 0x638 0x000 0x5 0x0
817#define MX6DL_PAD_KEY_COL4__KEY_COL4 0x254 0x63c 0x000 0x3 0x0 817#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x250 0x638 0x8f0 0x6 0x3
818#define MX6DL_PAD_KEY_COL4__UART5_RTS_B 0x254 0x63c 0x918 0x4 0x2 818#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x254 0x63c 0x000 0x0 0x0
819#define MX6DL_PAD_KEY_COL4__UART5_CTS_B 0x254 0x63c 0x000 0x4 0x0 819#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x254 0x63c 0x000 0x1 0x0
820#define MX6DL_PAD_KEY_COL4__GPIO4_IO14 0x254 0x63c 0x000 0x5 0x0 820#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x254 0x63c 0x920 0x2 0x1
821#define MX6DL_PAD_KEY_ROW0__ECSPI1_MOSI 0x258 0x640 0x7e0 0x0 0x3 821#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x254 0x63c 0x000 0x3 0x0
822#define MX6DL_PAD_KEY_ROW0__ENET_TX_DATA3 0x258 0x640 0x000 0x1 0x0 822#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x254 0x63c 0x918 0x4 0x2
823#define MX6DL_PAD_KEY_ROW0__AUD5_TXD 0x258 0x640 0x7b4 0x2 0x1 823#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x254 0x63c 0x000 0x4 0x0
824#define MX6DL_PAD_KEY_ROW0__KEY_ROW0 0x258 0x640 0x000 0x3 0x0 824#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x254 0x63c 0x000 0x5 0x0
825#define MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x258 0x640 0x914 0x4 0x3 825#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x258 0x640 0x7e0 0x0 0x3
826#define MX6DL_PAD_KEY_ROW0__UART4_TX_DATA 0x258 0x640 0x000 0x4 0x0 826#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x258 0x640 0x000 0x1 0x0
827#define MX6DL_PAD_KEY_ROW0__GPIO4_IO07 0x258 0x640 0x000 0x5 0x0 827#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x258 0x640 0x7b4 0x2 0x1
828#define MX6DL_PAD_KEY_ROW0__DCIC2_OUT 0x258 0x640 0x000 0x6 0x0 828#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x258 0x640 0x000 0x3 0x0
829#define MX6DL_PAD_KEY_ROW1__ECSPI1_SS0 0x25c 0x644 0x7e4 0x0 0x3 829#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x258 0x640 0x914 0x4 0x3
830#define MX6DL_PAD_KEY_ROW1__ENET_COL 0x25c 0x644 0x000 0x1 0x0 830#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x258 0x640 0x000 0x4 0x0
831#define MX6DL_PAD_KEY_ROW1__AUD5_RXD 0x25c 0x644 0x7b0 0x2 0x1 831#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x258 0x640 0x000 0x5 0x0
832#define MX6DL_PAD_KEY_ROW1__KEY_ROW1 0x25c 0x644 0x000 0x3 0x0 832#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x258 0x640 0x000 0x6 0x0
833#define MX6DL_PAD_KEY_ROW1__UART5_RX_DATA 0x25c 0x644 0x91c 0x4 0x3 833#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x25c 0x644 0x7e4 0x0 0x3
834#define MX6DL_PAD_KEY_ROW1__UART5_TX_DATA 0x25c 0x644 0x000 0x4 0x0 834#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x25c 0x644 0x000 0x1 0x0
835#define MX6DL_PAD_KEY_ROW1__GPIO4_IO09 0x25c 0x644 0x000 0x5 0x0 835#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x25c 0x644 0x7b0 0x2 0x1
836#define MX6DL_PAD_KEY_ROW1__SD2_VSELECT 0x25c 0x644 0x000 0x6 0x0 836#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x25c 0x644 0x000 0x3 0x0
837#define MX6DL_PAD_KEY_ROW2__ECSPI1_SS2 0x260 0x648 0x7ec 0x0 0x1 837#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x25c 0x644 0x91c 0x4 0x3
838#define MX6DL_PAD_KEY_ROW2__ENET_TX_DATA2 0x260 0x648 0x000 0x1 0x0 838#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x25c 0x644 0x000 0x4 0x0
839#define MX6DL_PAD_KEY_ROW2__FLEXCAN1_RX 0x260 0x648 0x7c8 0x2 0x1 839#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x25c 0x644 0x000 0x5 0x0
840#define MX6DL_PAD_KEY_ROW2__KEY_ROW2 0x260 0x648 0x000 0x3 0x0 840#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x25c 0x644 0x000 0x6 0x0
841#define MX6DL_PAD_KEY_ROW2__SD2_VSELECT 0x260 0x648 0x000 0x4 0x0 841#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x260 0x648 0x7ec 0x0 0x1
842#define MX6DL_PAD_KEY_ROW2__GPIO4_IO11 0x260 0x648 0x000 0x5 0x0 842#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x260 0x648 0x000 0x1 0x0
843#define MX6DL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x260 0x648 0x85c 0x6 0x1 843#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x260 0x648 0x7c8 0x2 0x1
844#define MX6DL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x264 0x64c 0x794 0x1 0x2 844#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x260 0x648 0x000 0x3 0x0
845#define MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x264 0x64c 0x864 0x2 0x1 845#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x260 0x648 0x000 0x4 0x0
846#define MX6DL_PAD_KEY_ROW3__KEY_ROW3 0x264 0x64c 0x000 0x3 0x0 846#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x260 0x648 0x000 0x5 0x0
847#define MX6DL_PAD_KEY_ROW3__I2C2_SDA 0x264 0x64c 0x874 0x4 0x1 847#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x260 0x648 0x85c 0x6 0x1
848#define MX6DL_PAD_KEY_ROW3__GPIO4_IO13 0x264 0x64c 0x000 0x5 0x0 848#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x264 0x64c 0x794 0x1 0x2
849#define MX6DL_PAD_KEY_ROW3__SD1_VSELECT 0x264 0x64c 0x000 0x6 0x0 849#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x264 0x64c 0x864 0x2 0x1
850#define MX6DL_PAD_KEY_ROW4__FLEXCAN2_RX 0x268 0x650 0x7cc 0x0 0x0 850#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x264 0x64c 0x000 0x3 0x0
851#define MX6DL_PAD_KEY_ROW4__IPU1_SISG5 0x268 0x650 0x000 0x1 0x0 851#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x264 0x64c 0x874 0x4 0x1
852#define MX6DL_PAD_KEY_ROW4__USB_OTG_PWR 0x268 0x650 0x000 0x2 0x0 852#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x264 0x64c 0x000 0x5 0x0
853#define MX6DL_PAD_KEY_ROW4__KEY_ROW4 0x268 0x650 0x000 0x3 0x0 853#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x264 0x64c 0x000 0x6 0x0
854#define MX6DL_PAD_KEY_ROW4__UART5_CTS_B 0x268 0x650 0x000 0x4 0x0 854#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x268 0x650 0x7cc 0x0 0x0
855#define MX6DL_PAD_KEY_ROW4__UART5_RTS_B 0x268 0x650 0x918 0x4 0x3 855#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x268 0x650 0x000 0x1 0x0
856#define MX6DL_PAD_KEY_ROW4__GPIO4_IO15 0x268 0x650 0x000 0x5 0x0 856#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x268 0x650 0x000 0x2 0x0
857#define MX6DL_PAD_NANDF_ALE__NAND_ALE 0x26c 0x654 0x000 0x0 0x0 857#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x268 0x650 0x000 0x3 0x0
858#define MX6DL_PAD_NANDF_ALE__SD4_RESET 0x26c 0x654 0x000 0x1 0x0 858#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x268 0x650 0x000 0x4 0x0
859#define MX6DL_PAD_NANDF_ALE__GPIO6_IO08 0x26c 0x654 0x000 0x5 0x0 859#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x268 0x650 0x918 0x4 0x3
860#define MX6DL_PAD_NANDF_CLE__NAND_CLE 0x270 0x658 0x000 0x0 0x0 860#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x268 0x650 0x000 0x5 0x0
861#define MX6DL_PAD_NANDF_CLE__GPIO6_IO07 0x270 0x658 0x000 0x5 0x0 861#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x26c 0x654 0x000 0x0 0x0
862#define MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0x274 0x65c 0x000 0x0 0x0 862#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x26c 0x654 0x000 0x1 0x0
863#define MX6DL_PAD_NANDF_CS0__GPIO6_IO11 0x274 0x65c 0x000 0x5 0x0 863#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x26c 0x654 0x000 0x5 0x0
864#define MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0x278 0x660 0x000 0x0 0x0 864#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x270 0x658 0x000 0x0 0x0
865#define MX6DL_PAD_NANDF_CS1__SD4_VSELECT 0x278 0x660 0x000 0x1 0x0 865#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x270 0x658 0x000 0x5 0x0
866#define MX6DL_PAD_NANDF_CS1__SD3_VSELECT 0x278 0x660 0x000 0x2 0x0 866#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x274 0x65c 0x000 0x0 0x0
867#define MX6DL_PAD_NANDF_CS1__GPIO6_IO14 0x278 0x660 0x000 0x5 0x0 867#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x274 0x65c 0x000 0x5 0x0
868#define MX6DL_PAD_NANDF_CS2__NAND_CE2_B 0x27c 0x664 0x000 0x0 0x0 868#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x278 0x660 0x000 0x0 0x0
869#define MX6DL_PAD_NANDF_CS2__IPU1_SISG0 0x27c 0x664 0x000 0x1 0x0 869#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x278 0x660 0x000 0x1 0x0
870#define MX6DL_PAD_NANDF_CS2__ESAI_TX0 0x27c 0x664 0x844 0x2 0x1 870#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x278 0x660 0x000 0x2 0x0
871#define MX6DL_PAD_NANDF_CS2__EIM_CRE 0x27c 0x664 0x000 0x3 0x0 871#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x278 0x660 0x000 0x5 0x0
872#define MX6DL_PAD_NANDF_CS2__CCM_CLKO2 0x27c 0x664 0x000 0x4 0x0 872#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x27c 0x664 0x000 0x0 0x0
873#define MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x27c 0x664 0x000 0x5 0x0 873#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x27c 0x664 0x000 0x1 0x0
874#define MX6DL_PAD_NANDF_CS3__NAND_CE3_B 0x280 0x668 0x000 0x0 0x0 874#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x27c 0x664 0x844 0x2 0x1
875#define MX6DL_PAD_NANDF_CS3__IPU1_SISG1 0x280 0x668 0x000 0x1 0x0 875#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x27c 0x664 0x000 0x3 0x0
876#define MX6DL_PAD_NANDF_CS3__ESAI_TX1 0x280 0x668 0x848 0x2 0x1 876#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x27c 0x664 0x000 0x4 0x0
877#define MX6DL_PAD_NANDF_CS3__EIM_ADDR26 0x280 0x668 0x000 0x3 0x0 877#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x27c 0x664 0x000 0x5 0x0
878#define MX6DL_PAD_NANDF_CS3__GPIO6_IO16 0x280 0x668 0x000 0x5 0x0 878#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x280 0x668 0x000 0x0 0x0
879#define MX6DL_PAD_NANDF_CS3__I2C4_SDA 0x280 0x668 0x884 0x9 0x2 879#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x280 0x668 0x000 0x1 0x0
880#define MX6DL_PAD_NANDF_D0__NAND_DATA00 0x284 0x66c 0x000 0x0 0x0 880#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x280 0x668 0x848 0x2 0x1
881#define MX6DL_PAD_NANDF_D0__SD1_DATA4 0x284 0x66c 0x000 0x1 0x0 881#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x280 0x668 0x000 0x3 0x0
882#define MX6DL_PAD_NANDF_D0__GPIO2_IO00 0x284 0x66c 0x000 0x5 0x0 882#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x280 0x668 0x000 0x5 0x0
883#define MX6DL_PAD_NANDF_D1__NAND_DATA01 0x288 0x670 0x000 0x0 0x0 883#define MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0x280 0x668 0x884 0x9 0x2
884#define MX6DL_PAD_NANDF_D1__SD1_DATA5 0x288 0x670 0x000 0x1 0x0 884#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x284 0x66c 0x000 0x0 0x0
885#define MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x288 0x670 0x000 0x5 0x0 885#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x284 0x66c 0x000 0x1 0x0
886#define MX6DL_PAD_NANDF_D2__NAND_DATA02 0x28c 0x674 0x000 0x0 0x0 886#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x284 0x66c 0x000 0x5 0x0
887#define MX6DL_PAD_NANDF_D2__SD1_DATA6 0x28c 0x674 0x000 0x1 0x0 887#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x288 0x670 0x000 0x0 0x0
888#define MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x28c 0x674 0x000 0x5 0x0 888#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x288 0x670 0x000 0x1 0x0
889#define MX6DL_PAD_NANDF_D3__NAND_DATA03 0x290 0x678 0x000 0x0 0x0 889#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x288 0x670 0x000 0x5 0x0
890#define MX6DL_PAD_NANDF_D3__SD1_DATA7 0x290 0x678 0x000 0x1 0x0 890#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x28c 0x674 0x000 0x0 0x0
891#define MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x290 0x678 0x000 0x5 0x0 891#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x28c 0x674 0x000 0x1 0x0
892#define MX6DL_PAD_NANDF_D4__NAND_DATA04 0x294 0x67c 0x000 0x0 0x0 892#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x28c 0x674 0x000 0x5 0x0
893#define MX6DL_PAD_NANDF_D4__SD2_DATA4 0x294 0x67c 0x000 0x1 0x0 893#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x290 0x678 0x000 0x0 0x0
894#define MX6DL_PAD_NANDF_D4__GPIO2_IO04 0x294 0x67c 0x000 0x5 0x0 894#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x290 0x678 0x000 0x1 0x0
895#define MX6DL_PAD_NANDF_D5__NAND_DATA05 0x298 0x680 0x000 0x0 0x0 895#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x290 0x678 0x000 0x5 0x0
896#define MX6DL_PAD_NANDF_D5__SD2_DATA5 0x298 0x680 0x000 0x1 0x0 896#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x294 0x67c 0x000 0x0 0x0
897#define MX6DL_PAD_NANDF_D5__GPIO2_IO05 0x298 0x680 0x000 0x5 0x0 897#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x294 0x67c 0x000 0x1 0x0
898#define MX6DL_PAD_NANDF_D6__NAND_DATA06 0x29c 0x684 0x000 0x0 0x0 898#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x294 0x67c 0x000 0x5 0x0
899#define MX6DL_PAD_NANDF_D6__SD2_DATA6 0x29c 0x684 0x000 0x1 0x0 899#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x298 0x680 0x000 0x0 0x0
900#define MX6DL_PAD_NANDF_D6__GPIO2_IO06 0x29c 0x684 0x000 0x5 0x0 900#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x298 0x680 0x000 0x1 0x0
901#define MX6DL_PAD_NANDF_D7__NAND_DATA07 0x2a0 0x688 0x000 0x0 0x0 901#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x298 0x680 0x000 0x5 0x0
902#define MX6DL_PAD_NANDF_D7__SD2_DATA7 0x2a0 0x688 0x000 0x1 0x0 902#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x29c 0x684 0x000 0x0 0x0
903#define MX6DL_PAD_NANDF_D7__GPIO2_IO07 0x2a0 0x688 0x000 0x5 0x0 903#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x29c 0x684 0x000 0x1 0x0
904#define MX6DL_PAD_NANDF_RB0__NAND_READY_B 0x2a4 0x68c 0x000 0x0 0x0 904#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x29c 0x684 0x000 0x5 0x0
905#define MX6DL_PAD_NANDF_RB0__GPIO6_IO10 0x2a4 0x68c 0x000 0x5 0x0 905#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x2a0 0x688 0x000 0x0 0x0
906#define MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0x2a8 0x690 0x000 0x0 0x0 906#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x2a0 0x688 0x000 0x1 0x0
907#define MX6DL_PAD_NANDF_WP_B__GPIO6_IO09 0x2a8 0x690 0x000 0x5 0x0 907#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x2a0 0x688 0x000 0x5 0x0
908#define MX6DL_PAD_NANDF_WP_B__I2C4_SCL 0x2a8 0x690 0x880 0x9 0x2 908#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2a4 0x68c 0x000 0x0 0x0
909#define MX6DL_PAD_RGMII_RD0__HSI_RX_READY 0x2ac 0x694 0x000 0x0 0x0 909#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2a4 0x68c 0x000 0x5 0x0
910#define MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x2ac 0x694 0x818 0x1 0x1 910#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2a8 0x690 0x000 0x0 0x0
911#define MX6DL_PAD_RGMII_RD0__GPIO6_IO25 0x2ac 0x694 0x000 0x5 0x0 911#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2a8 0x690 0x000 0x5 0x0
912#define MX6DL_PAD_RGMII_RD1__HSI_TX_FLAG 0x2b0 0x698 0x000 0x0 0x0 912#define MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0x2a8 0x690 0x880 0x9 0x2
913#define MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x2b0 0x698 0x81c 0x1 0x1 913#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x2ac 0x694 0x000 0x0 0x0
914#define MX6DL_PAD_RGMII_RD1__GPIO6_IO27 0x2b0 0x698 0x000 0x5 0x0 914#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x2ac 0x694 0x818 0x1 0x1
915#define MX6DL_PAD_RGMII_RD2__HSI_TX_DATA 0x2b4 0x69c 0x000 0x0 0x0 915#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x2ac 0x694 0x000 0x5 0x0
916#define MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x2b4 0x69c 0x820 0x1 0x1 916#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x2b0 0x698 0x000 0x0 0x0
917#define MX6DL_PAD_RGMII_RD2__GPIO6_IO28 0x2b4 0x69c 0x000 0x5 0x0 917#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x2b0 0x698 0x81c 0x1 0x1
918#define MX6DL_PAD_RGMII_RD3__HSI_TX_WAKE 0x2b8 0x6a0 0x000 0x0 0x0 918#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x2b0 0x698 0x000 0x5 0x0
919#define MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x2b8 0x6a0 0x824 0x1 0x1 919#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x2b4 0x69c 0x000 0x0 0x0
920#define MX6DL_PAD_RGMII_RD3__GPIO6_IO29 0x2b8 0x6a0 0x000 0x5 0x0 920#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x2b4 0x69c 0x820 0x1 0x1
921#define MX6DL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x2bc 0x6a4 0x000 0x0 0x0 921#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x2b4 0x69c 0x000 0x5 0x0
922#define MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x2bc 0x6a4 0x828 0x1 0x1 922#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x2b8 0x6a0 0x000 0x0 0x0
923#define MX6DL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x2bc 0x6a4 0x000 0x5 0x0 923#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x2b8 0x6a0 0x824 0x1 0x1
924#define MX6DL_PAD_RGMII_RXC__USB_H3_STROBE 0x2c0 0x6a8 0x000 0x0 0x0 924#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x2b8 0x6a0 0x000 0x5 0x0
925#define MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x2c0 0x6a8 0x814 0x1 0x1 925#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x2bc 0x6a4 0x000 0x0 0x0
926#define MX6DL_PAD_RGMII_RXC__GPIO6_IO30 0x2c0 0x6a8 0x000 0x5 0x0 926#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x2bc 0x6a4 0x828 0x1 0x1
927#define MX6DL_PAD_RGMII_TD0__HSI_TX_READY 0x2c4 0x6ac 0x000 0x0 0x0 927#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x2bc 0x6a4 0x000 0x5 0x0
928#define MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x2c4 0x6ac 0x000 0x1 0x0 928#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x2c0 0x6a8 0x000 0x0 0x0
929#define MX6DL_PAD_RGMII_TD0__GPIO6_IO20 0x2c4 0x6ac 0x000 0x5 0x0 929#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x2c0 0x6a8 0x814 0x1 0x1
930#define MX6DL_PAD_RGMII_TD1__HSI_RX_FLAG 0x2c8 0x6b0 0x000 0x0 0x0 930#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x2c0 0x6a8 0x000 0x5 0x0
931#define MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x2c8 0x6b0 0x000 0x1 0x0 931#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x2c4 0x6ac 0x000 0x0 0x0
932#define MX6DL_PAD_RGMII_TD1__GPIO6_IO21 0x2c8 0x6b0 0x000 0x5 0x0 932#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x2c4 0x6ac 0x000 0x1 0x0
933#define MX6DL_PAD_RGMII_TD2__HSI_RX_DATA 0x2cc 0x6b4 0x000 0x0 0x0 933#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x2c4 0x6ac 0x000 0x5 0x0
934#define MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x2cc 0x6b4 0x000 0x1 0x0 934#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x2c8 0x6b0 0x000 0x0 0x0
935#define MX6DL_PAD_RGMII_TD2__GPIO6_IO22 0x2cc 0x6b4 0x000 0x5 0x0 935#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x2c8 0x6b0 0x000 0x1 0x0
936#define MX6DL_PAD_RGMII_TD3__HSI_RX_WAKE 0x2d0 0x6b8 0x000 0x0 0x0 936#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x2c8 0x6b0 0x000 0x5 0x0
937#define MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x2d0 0x6b8 0x000 0x1 0x0 937#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x2cc 0x6b4 0x000 0x0 0x0
938#define MX6DL_PAD_RGMII_TD3__GPIO6_IO23 0x2d0 0x6b8 0x000 0x5 0x0 938#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x2cc 0x6b4 0x000 0x1 0x0
939#define MX6DL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x2d4 0x6bc 0x000 0x0 0x0 939#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x2cc 0x6b4 0x000 0x5 0x0
940#define MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x2d4 0x6bc 0x000 0x1 0x0 940#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x2d0 0x6b8 0x000 0x0 0x0
941#define MX6DL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x2d4 0x6bc 0x000 0x5 0x0 941#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x2d0 0x6b8 0x000 0x1 0x0
942#define MX6DL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x2d4 0x6bc 0x80c 0x7 0x1 942#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x2d0 0x6b8 0x000 0x5 0x0
943#define MX6DL_PAD_RGMII_TXC__USB_H2_DATA 0x2d8 0x6c0 0x000 0x0 0x0 943#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x2d4 0x6bc 0x000 0x0 0x0
944#define MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x2d8 0x6c0 0x000 0x1 0x0 944#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x2d4 0x6bc 0x000 0x1 0x0
945#define MX6DL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x2d8 0x6c0 0x8f4 0x2 0x1 945#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x2d4 0x6bc 0x000 0x5 0x0
946#define MX6DL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0 946#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x2d4 0x6bc 0x80c 0x7 0x1
947#define MX6DL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0 947#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x2d8 0x6c0 0x000 0x0 0x0
948#define MX6DL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1 948#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x2d8 0x6c0 0x000 0x1 0x0
949#define MX6DL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0 949#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x2d8 0x6c0 0x8f4 0x2 0x1
950#define MX6DL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0 950#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0
951#define MX6DL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0 951#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0
952#define MX6DL_PAD_SD1_CMD__PWM4_OUT 0x2e0 0x6c8 0x000 0x2 0x0 952#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1
953#define MX6DL_PAD_SD1_CMD__GPT_COMPARE1 0x2e0 0x6c8 0x000 0x3 0x0 953#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0
954#define MX6DL_PAD_SD1_CMD__GPIO1_IO18 0x2e0 0x6c8 0x000 0x5 0x0 954#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0
955#define MX6DL_PAD_SD1_DAT0__SD1_DATA0 0x2e4 0x6cc 0x000 0x0 0x0 955#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0
956#define MX6DL_PAD_SD1_DAT0__GPT_CAPTURE1 0x2e4 0x6cc 0x000 0x3 0x0 956#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x2e0 0x6c8 0x000 0x2 0x0
957#define MX6DL_PAD_SD1_DAT0__GPIO1_IO16 0x2e4 0x6cc 0x000 0x5 0x0 957#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x2e0 0x6c8 0x000 0x3 0x0
958#define MX6DL_PAD_SD1_DAT1__SD1_DATA1 0x2e8 0x6d0 0x000 0x0 0x0 958#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x2e0 0x6c8 0x000 0x5 0x0
959#define MX6DL_PAD_SD1_DAT1__PWM3_OUT 0x2e8 0x6d0 0x000 0x2 0x0 959#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x2e4 0x6cc 0x000 0x0 0x0
960#define MX6DL_PAD_SD1_DAT1__GPT_CAPTURE2 0x2e8 0x6d0 0x000 0x3 0x0 960#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x2e4 0x6cc 0x000 0x3 0x0
961#define MX6DL_PAD_SD1_DAT1__GPIO1_IO17 0x2e8 0x6d0 0x000 0x5 0x0 961#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x2e4 0x6cc 0x000 0x5 0x0
962#define MX6DL_PAD_SD1_DAT2__SD1_DATA2 0x2ec 0x6d4 0x000 0x0 0x0 962#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x2e8 0x6d0 0x000 0x0 0x0
963#define MX6DL_PAD_SD1_DAT2__GPT_COMPARE2 0x2ec 0x6d4 0x000 0x2 0x0 963#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x2e8 0x6d0 0x000 0x2 0x0
964#define MX6DL_PAD_SD1_DAT2__PWM2_OUT 0x2ec 0x6d4 0x000 0x3 0x0 964#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x2e8 0x6d0 0x000 0x3 0x0
965#define MX6DL_PAD_SD1_DAT2__WDOG1_B 0x2ec 0x6d4 0x000 0x4 0x0 965#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x2e8 0x6d0 0x000 0x5 0x0
966#define MX6DL_PAD_SD1_DAT2__GPIO1_IO19 0x2ec 0x6d4 0x000 0x5 0x0 966#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x2ec 0x6d4 0x000 0x0 0x0
967#define MX6DL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x2ec 0x6d4 0x000 0x6 0x0 967#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x2ec 0x6d4 0x000 0x2 0x0
968#define MX6DL_PAD_SD1_DAT3__SD1_DATA3 0x2f0 0x6d8 0x000 0x0 0x0 968#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x2ec 0x6d4 0x000 0x3 0x0
969#define MX6DL_PAD_SD1_DAT3__GPT_COMPARE3 0x2f0 0x6d8 0x000 0x2 0x0 969#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x2ec 0x6d4 0x000 0x4 0x0
970#define MX6DL_PAD_SD1_DAT3__PWM1_OUT 0x2f0 0x6d8 0x000 0x3 0x0 970#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x2ec 0x6d4 0x000 0x5 0x0
971#define MX6DL_PAD_SD1_DAT3__WDOG2_B 0x2f0 0x6d8 0x000 0x4 0x0 971#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x2ec 0x6d4 0x000 0x6 0x0
972#define MX6DL_PAD_SD1_DAT3__GPIO1_IO21 0x2f0 0x6d8 0x000 0x5 0x0 972#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x2f0 0x6d8 0x000 0x0 0x0
973#define MX6DL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x2f0 0x6d8 0x000 0x6 0x0 973#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x2f0 0x6d8 0x000 0x2 0x0
974#define MX6DL_PAD_SD2_CLK__SD2_CLK 0x2f4 0x6dc 0x930 0x0 0x1 974#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x2f0 0x6d8 0x000 0x3 0x0
975#define MX6DL_PAD_SD2_CLK__KEY_COL5 0x2f4 0x6dc 0x8c0 0x2 0x3 975#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x2f0 0x6d8 0x000 0x4 0x0
976#define MX6DL_PAD_SD2_CLK__AUD4_RXFS 0x2f4 0x6dc 0x7a4 0x3 0x1 976#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x2f0 0x6d8 0x000 0x5 0x0
977#define MX6DL_PAD_SD2_CLK__GPIO1_IO10 0x2f4 0x6dc 0x000 0x5 0x0 977#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x2f0 0x6d8 0x000 0x6 0x0
978#define MX6DL_PAD_SD2_CMD__SD2_CMD 0x2f8 0x6e0 0x000 0x0 0x0 978#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x2f4 0x6dc 0x930 0x0 0x1
979#define MX6DL_PAD_SD2_CMD__KEY_ROW5 0x2f8 0x6e0 0x8cc 0x2 0x2 979#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x2f4 0x6dc 0x8c0 0x2 0x3
980#define MX6DL_PAD_SD2_CMD__AUD4_RXC 0x2f8 0x6e0 0x7a0 0x3 0x1 980#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x2f4 0x6dc 0x7a4 0x3 0x1
981#define MX6DL_PAD_SD2_CMD__GPIO1_IO11 0x2f8 0x6e0 0x000 0x5 0x0 981#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x2f4 0x6dc 0x000 0x5 0x0
982#define MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x2fc 0x6e4 0x000 0x0 0x0 982#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x2f8 0x6e0 0x000 0x0 0x0
983#define MX6DL_PAD_SD2_DAT0__AUD4_RXD 0x2fc 0x6e4 0x798 0x3 0x1 983#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x2f8 0x6e0 0x8cc 0x2 0x2
984#define MX6DL_PAD_SD2_DAT0__KEY_ROW7 0x2fc 0x6e4 0x8d4 0x4 0x2 984#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x2f8 0x6e0 0x7a0 0x3 0x1
985#define MX6DL_PAD_SD2_DAT0__GPIO1_IO15 0x2fc 0x6e4 0x000 0x5 0x0 985#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x2f8 0x6e0 0x000 0x5 0x0
986#define MX6DL_PAD_SD2_DAT0__DCIC2_OUT 0x2fc 0x6e4 0x000 0x6 0x0 986#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x2fc 0x6e4 0x000 0x0 0x0
987#define MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x300 0x6e8 0x000 0x0 0x0 987#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x2fc 0x6e4 0x798 0x3 0x1
988#define MX6DL_PAD_SD2_DAT1__EIM_CS2_B 0x300 0x6e8 0x000 0x2 0x0 988#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x2fc 0x6e4 0x8d4 0x4 0x2
989#define MX6DL_PAD_SD2_DAT1__AUD4_TXFS 0x300 0x6e8 0x7ac 0x3 0x1 989#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x2fc 0x6e4 0x000 0x5 0x0
990#define MX6DL_PAD_SD2_DAT1__KEY_COL7 0x300 0x6e8 0x8c8 0x4 0x2 990#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x2fc 0x6e4 0x000 0x6 0x0
991#define MX6DL_PAD_SD2_DAT1__GPIO1_IO14 0x300 0x6e8 0x000 0x5 0x0 991#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x300 0x6e8 0x000 0x0 0x0
992#define MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x304 0x6ec 0x000 0x0 0x0 992#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x300 0x6e8 0x000 0x2 0x0
993#define MX6DL_PAD_SD2_DAT2__EIM_CS3_B 0x304 0x6ec 0x000 0x2 0x0 993#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x300 0x6e8 0x7ac 0x3 0x1
994#define MX6DL_PAD_SD2_DAT2__AUD4_TXD 0x304 0x6ec 0x79c 0x3 0x1 994#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x300 0x6e8 0x8c8 0x4 0x2
995#define MX6DL_PAD_SD2_DAT2__KEY_ROW6 0x304 0x6ec 0x8d0 0x4 0x2 995#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x300 0x6e8 0x000 0x5 0x0
996#define MX6DL_PAD_SD2_DAT2__GPIO1_IO13 0x304 0x6ec 0x000 0x5 0x0 996#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x304 0x6ec 0x000 0x0 0x0
997#define MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x308 0x6f0 0x000 0x0 0x0 997#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x304 0x6ec 0x000 0x2 0x0
998#define MX6DL_PAD_SD2_DAT3__KEY_COL6 0x308 0x6f0 0x8c4 0x2 0x2 998#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x304 0x6ec 0x79c 0x3 0x1
999#define MX6DL_PAD_SD2_DAT3__AUD4_TXC 0x308 0x6f0 0x7a8 0x3 0x1 999#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x304 0x6ec 0x8d0 0x4 0x2
1000#define MX6DL_PAD_SD2_DAT3__GPIO1_IO12 0x308 0x6f0 0x000 0x5 0x0 1000#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x304 0x6ec 0x000 0x5 0x0
1001#define MX6DL_PAD_SD3_CLK__SD3_CLK 0x30c 0x6f4 0x934 0x0 0x1 1001#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x308 0x6f0 0x000 0x0 0x0
1002#define MX6DL_PAD_SD3_CLK__UART2_RTS_B 0x30c 0x6f4 0x900 0x1 0x2 1002#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x308 0x6f0 0x8c4 0x2 0x2
1003#define MX6DL_PAD_SD3_CLK__UART2_CTS_B 0x30c 0x6f4 0x000 0x1 0x0 1003#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x308 0x6f0 0x7a8 0x3 0x1
1004#define MX6DL_PAD_SD3_CLK__FLEXCAN1_RX 0x30c 0x6f4 0x7c8 0x2 0x2 1004#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x308 0x6f0 0x000 0x5 0x0
1005#define MX6DL_PAD_SD3_CLK__GPIO7_IO03 0x30c 0x6f4 0x000 0x5 0x0 1005#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x30c 0x6f4 0x934 0x0 0x1
1006#define MX6DL_PAD_SD3_CMD__SD3_CMD 0x310 0x6f8 0x000 0x0 0x0 1006#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x30c 0x6f4 0x900 0x1 0x2
1007#define MX6DL_PAD_SD3_CMD__UART2_CTS_B 0x310 0x6f8 0x000 0x1 0x0 1007#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x30c 0x6f4 0x000 0x1 0x0
1008#define MX6DL_PAD_SD3_CMD__UART2_RTS_B 0x310 0x6f8 0x900 0x1 0x3 1008#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x30c 0x6f4 0x7c8 0x2 0x2
1009#define MX6DL_PAD_SD3_CMD__FLEXCAN1_TX 0x310 0x6f8 0x000 0x2 0x0 1009#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x30c 0x6f4 0x000 0x5 0x0
1010#define MX6DL_PAD_SD3_CMD__GPIO7_IO02 0x310 0x6f8 0x000 0x5 0x0 1010#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x310 0x6f8 0x000 0x0 0x0
1011#define MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x314 0x6fc 0x000 0x0 0x0 1011#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x310 0x6f8 0x000 0x1 0x0
1012#define MX6DL_PAD_SD3_DAT0__UART1_CTS_B 0x314 0x6fc 0x000 0x1 0x0 1012#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x310 0x6f8 0x900 0x1 0x3
1013#define MX6DL_PAD_SD3_DAT0__UART1_RTS_B 0x314 0x6fc 0x8f8 0x1 0x2 1013#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x310 0x6f8 0x000 0x2 0x0
1014#define MX6DL_PAD_SD3_DAT0__FLEXCAN2_TX 0x314 0x6fc 0x000 0x2 0x0 1014#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x310 0x6f8 0x000 0x5 0x0
1015#define MX6DL_PAD_SD3_DAT0__GPIO7_IO04 0x314 0x6fc 0x000 0x5 0x0 1015#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x314 0x6fc 0x000 0x0 0x0
1016#define MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x318 0x700 0x000 0x0 0x0 1016#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x314 0x6fc 0x000 0x1 0x0
1017#define MX6DL_PAD_SD3_DAT1__UART1_RTS_B 0x318 0x700 0x8f8 0x1 0x3 1017#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x314 0x6fc 0x8f8 0x1 0x2
1018#define MX6DL_PAD_SD3_DAT1__UART1_CTS_B 0x318 0x700 0x000 0x1 0x0 1018#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x314 0x6fc 0x000 0x2 0x0
1019#define MX6DL_PAD_SD3_DAT1__FLEXCAN2_RX 0x318 0x700 0x7cc 0x2 0x1 1019#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x314 0x6fc 0x000 0x5 0x0
1020#define MX6DL_PAD_SD3_DAT1__GPIO7_IO05 0x318 0x700 0x000 0x5 0x0 1020#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x318 0x700 0x000 0x0 0x0
1021#define MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x31c 0x704 0x000 0x0 0x0 1021#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x318 0x700 0x8f8 0x1 0x3
1022#define MX6DL_PAD_SD3_DAT2__GPIO7_IO06 0x31c 0x704 0x000 0x5 0x0 1022#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x318 0x700 0x000 0x1 0x0
1023#define MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x320 0x708 0x000 0x0 0x0 1023#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x318 0x700 0x7cc 0x2 0x1
1024#define MX6DL_PAD_SD3_DAT3__UART3_CTS_B 0x320 0x708 0x000 0x1 0x0 1024#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x318 0x700 0x000 0x5 0x0
1025#define MX6DL_PAD_SD3_DAT3__UART3_RTS_B 0x320 0x708 0x908 0x1 0x4 1025#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x31c 0x704 0x000 0x0 0x0
1026#define MX6DL_PAD_SD3_DAT3__GPIO7_IO07 0x320 0x708 0x000 0x5 0x0 1026#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x31c 0x704 0x000 0x5 0x0
1027#define MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x324 0x70c 0x000 0x0 0x0 1027#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x320 0x708 0x000 0x0 0x0
1028#define MX6DL_PAD_SD3_DAT4__UART2_RX_DATA 0x324 0x70c 0x904 0x1 0x4 1028#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x320 0x708 0x000 0x1 0x0
1029#define MX6DL_PAD_SD3_DAT4__UART2_TX_DATA 0x324 0x70c 0x000 0x1 0x0 1029#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x320 0x708 0x908 0x1 0x4
1030#define MX6DL_PAD_SD3_DAT4__GPIO7_IO01 0x324 0x70c 0x000 0x5 0x0 1030#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x320 0x708 0x000 0x5 0x0
1031#define MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x328 0x710 0x000 0x0 0x0 1031#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x324 0x70c 0x000 0x0 0x0
1032#define MX6DL_PAD_SD3_DAT5__UART2_TX_DATA 0x328 0x710 0x000 0x1 0x0 1032#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x324 0x70c 0x904 0x1 0x4
1033#define MX6DL_PAD_SD3_DAT5__UART2_RX_DATA 0x328 0x710 0x904 0x1 0x5 1033#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x324 0x70c 0x000 0x1 0x0
1034#define MX6DL_PAD_SD3_DAT5__GPIO7_IO00 0x328 0x710 0x000 0x5 0x0 1034#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x324 0x70c 0x000 0x5 0x0
1035#define MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x32c 0x714 0x000 0x0 0x0 1035#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x328 0x710 0x000 0x0 0x0
1036#define MX6DL_PAD_SD3_DAT6__UART1_RX_DATA 0x32c 0x714 0x8fc 0x1 0x2 1036#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x328 0x710 0x000 0x1 0x0
1037#define MX6DL_PAD_SD3_DAT6__UART1_TX_DATA 0x32c 0x714 0x000 0x1 0x0 1037#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x328 0x710 0x904 0x1 0x5
1038#define MX6DL_PAD_SD3_DAT6__GPIO6_IO18 0x32c 0x714 0x000 0x5 0x0 1038#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x328 0x710 0x000 0x5 0x0
1039#define MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x330 0x718 0x000 0x0 0x0 1039#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x32c 0x714 0x000 0x0 0x0
1040#define MX6DL_PAD_SD3_DAT7__UART1_TX_DATA 0x330 0x718 0x000 0x1 0x0 1040#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x32c 0x714 0x8fc 0x1 0x2
1041#define MX6DL_PAD_SD3_DAT7__UART1_RX_DATA 0x330 0x718 0x8fc 0x1 0x3 1041#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x32c 0x714 0x000 0x1 0x0
1042#define MX6DL_PAD_SD3_DAT7__GPIO6_IO17 0x330 0x718 0x000 0x5 0x0 1042#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x32c 0x714 0x000 0x5 0x0
1043#define MX6DL_PAD_SD3_RST__SD3_RESET 0x334 0x71c 0x000 0x0 0x0 1043#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x330 0x718 0x000 0x0 0x0
1044#define MX6DL_PAD_SD3_RST__UART3_RTS_B 0x334 0x71c 0x908 0x1 0x5 1044#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x330 0x718 0x000 0x1 0x0
1045#define MX6DL_PAD_SD3_RST__UART3_CTS_B 0x334 0x71c 0x000 0x1 0x0 1045#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x330 0x718 0x8fc 0x1 0x3
1046#define MX6DL_PAD_SD3_RST__GPIO7_IO08 0x334 0x71c 0x000 0x5 0x0 1046#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x330 0x718 0x000 0x5 0x0
1047#define MX6DL_PAD_SD4_CLK__SD4_CLK 0x338 0x720 0x938 0x0 0x1 1047#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x334 0x71c 0x000 0x0 0x0
1048#define MX6DL_PAD_SD4_CLK__NAND_WE_B 0x338 0x720 0x000 0x1 0x0 1048#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x334 0x71c 0x908 0x1 0x5
1049#define MX6DL_PAD_SD4_CLK__UART3_RX_DATA 0x338 0x720 0x90c 0x2 0x2 1049#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x334 0x71c 0x000 0x1 0x0
1050#define MX6DL_PAD_SD4_CLK__UART3_TX_DATA 0x338 0x720 0x000 0x2 0x0 1050#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x334 0x71c 0x000 0x5 0x0
1051#define MX6DL_PAD_SD4_CLK__GPIO7_IO10 0x338 0x720 0x000 0x5 0x0 1051#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x338 0x720 0x938 0x0 0x1
1052#define MX6DL_PAD_SD4_CMD__SD4_CMD 0x33c 0x724 0x000 0x0 0x0 1052#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x338 0x720 0x000 0x1 0x0
1053#define MX6DL_PAD_SD4_CMD__NAND_RE_B 0x33c 0x724 0x000 0x1 0x0 1053#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x338 0x720 0x90c 0x2 0x2
1054#define MX6DL_PAD_SD4_CMD__UART3_TX_DATA 0x33c 0x724 0x000 0x2 0x0 1054#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x338 0x720 0x000 0x2 0x0
1055#define MX6DL_PAD_SD4_CMD__UART3_RX_DATA 0x33c 0x724 0x90c 0x2 0x3 1055#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x338 0x720 0x000 0x5 0x0
1056#define MX6DL_PAD_SD4_CMD__GPIO7_IO09 0x33c 0x724 0x000 0x5 0x0 1056#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x33c 0x724 0x000 0x0 0x0
1057#define MX6DL_PAD_SD4_DAT0__SD4_DATA0 0x340 0x728 0x000 0x1 0x0 1057#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x33c 0x724 0x000 0x1 0x0
1058#define MX6DL_PAD_SD4_DAT0__NAND_DQS 0x340 0x728 0x000 0x2 0x0 1058#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x33c 0x724 0x000 0x2 0x0
1059#define MX6DL_PAD_SD4_DAT0__GPIO2_IO08 0x340 0x728 0x000 0x5 0x0 1059#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x33c 0x724 0x90c 0x2 0x3
1060#define MX6DL_PAD_SD4_DAT1__SD4_DATA1 0x344 0x72c 0x000 0x1 0x0 1060#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x33c 0x724 0x000 0x5 0x0
1061#define MX6DL_PAD_SD4_DAT1__PWM3_OUT 0x344 0x72c 0x000 0x2 0x0 1061#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x340 0x728 0x000 0x1 0x0
1062#define MX6DL_PAD_SD4_DAT1__GPIO2_IO09 0x344 0x72c 0x000 0x5 0x0 1062#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x340 0x728 0x000 0x2 0x0
1063#define MX6DL_PAD_SD4_DAT2__SD4_DATA2 0x348 0x730 0x000 0x1 0x0 1063#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x340 0x728 0x000 0x5 0x0
1064#define MX6DL_PAD_SD4_DAT2__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 1064#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x344 0x72c 0x000 0x1 0x0
1065#define MX6DL_PAD_SD4_DAT2__GPIO2_IO10 0x348 0x730 0x000 0x5 0x0 1065#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x344 0x72c 0x000 0x2 0x0
1066#define MX6DL_PAD_SD4_DAT3__SD4_DATA3 0x34c 0x734 0x000 0x1 0x0 1066#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x344 0x72c 0x000 0x5 0x0
1067#define MX6DL_PAD_SD4_DAT3__GPIO2_IO11 0x34c 0x734 0x000 0x5 0x0 1067#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x348 0x730 0x000 0x1 0x0
1068#define MX6DL_PAD_SD4_DAT4__SD4_DATA4 0x350 0x738 0x000 0x1 0x0 1068#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x348 0x730 0x000 0x2 0x0
1069#define MX6DL_PAD_SD4_DAT4__UART2_RX_DATA 0x350 0x738 0x904 0x2 0x6 1069#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x348 0x730 0x000 0x5 0x0
1070#define MX6DL_PAD_SD4_DAT4__UART2_TX_DATA 0x350 0x738 0x000 0x2 0x0 1070#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x34c 0x734 0x000 0x1 0x0
1071#define MX6DL_PAD_SD4_DAT4__GPIO2_IO12 0x350 0x738 0x000 0x5 0x0 1071#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x34c 0x734 0x000 0x5 0x0
1072#define MX6DL_PAD_SD4_DAT5__SD4_DATA5 0x354 0x73c 0x000 0x1 0x0 1072#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x350 0x738 0x000 0x1 0x0
1073#define MX6DL_PAD_SD4_DAT5__UART2_RTS_B 0x354 0x73c 0x900 0x2 0x4 1073#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x350 0x738 0x904 0x2 0x6
1074#define MX6DL_PAD_SD4_DAT5__UART2_CTS_B 0x354 0x73c 0x000 0x2 0x0 1074#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x350 0x738 0x000 0x2 0x0
1075#define MX6DL_PAD_SD4_DAT5__GPIO2_IO13 0x354 0x73c 0x000 0x5 0x0 1075#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x350 0x738 0x000 0x5 0x0
1076#define MX6DL_PAD_SD4_DAT6__SD4_DATA6 0x358 0x740 0x000 0x1 0x0 1076#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x354 0x73c 0x000 0x1 0x0
1077#define MX6DL_PAD_SD4_DAT6__UART2_CTS_B 0x358 0x740 0x000 0x2 0x0 1077#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x354 0x73c 0x900 0x2 0x4
1078#define MX6DL_PAD_SD4_DAT6__UART2_RTS_B 0x358 0x740 0x900 0x2 0x5 1078#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x354 0x73c 0x000 0x2 0x0
1079#define MX6DL_PAD_SD4_DAT6__GPIO2_IO14 0x358 0x740 0x000 0x5 0x0 1079#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x354 0x73c 0x000 0x5 0x0
1080#define MX6DL_PAD_SD4_DAT7__SD4_DATA7 0x35c 0x744 0x000 0x1 0x0 1080#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x358 0x740 0x000 0x1 0x0
1081#define MX6DL_PAD_SD4_DAT7__UART2_TX_DATA 0x35c 0x744 0x000 0x2 0x0 1081#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x358 0x740 0x000 0x2 0x0
1082#define MX6DL_PAD_SD4_DAT7__UART2_RX_DATA 0x35c 0x744 0x904 0x2 0x7 1082#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x358 0x740 0x900 0x2 0x5
1083#define MX6DL_PAD_SD4_DAT7__GPIO2_IO15 0x35c 0x744 0x000 0x5 0x0 1083#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x358 0x740 0x000 0x5 0x0
1084#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x35c 0x744 0x000 0x1 0x0
1085#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x35c 0x744 0x000 0x2 0x0
1086#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x35c 0x744 0x904 0x2 0x7
1087#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x35c 0x744 0x000 0x5 0x0
1084 1088
1085#endif /* __DTS_IMX6DL_PINFUNC_H */ 1089#endif /* __DTS_IMX6DL_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts
index 95da71185a4a..a6ce7b487ad7 100644
--- a/arch/arm/boot/dts/imx6dl-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts
@@ -15,25 +15,3 @@
15 model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board"; 15 model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board";
16 compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl"; 16 compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
17}; 17};
18
19&iomuxc {
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_hog>;
22
23 hog {
24 pinctrl_hog: hoggrp {
25 fsl,pins = <
26 MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
27 MX6DL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
28 >;
29 };
30 };
31
32 ecspi1 {
33 pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
34 fsl,pins = <
35 MX6DL_PAD_EIM_D19__GPIO3_IO19 0x80000000
36 >;
37 };
38 };
39};
diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts
index 8989df2b89e5..1e45f2f9d0b6 100644
--- a/arch/arm/boot/dts/imx6dl-sabresd.dts
+++ b/arch/arm/boot/dts/imx6dl-sabresd.dts
@@ -15,22 +15,3 @@
15 model = "Freescale i.MX6 DualLite SABRE Smart Device Board"; 15 model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
16 compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl"; 16 compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
17}; 17};
18
19&iomuxc {
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_hog>;
22
23 hog {
24 pinctrl_hog: hoggrp {
25 fsl,pins = <
26 MX6DL_PAD_GPIO_4__GPIO1_IO04 0x80000000
27 MX6DL_PAD_GPIO_5__GPIO1_IO05 0x80000000
28 MX6DL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
29 MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
30 MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
31 MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
32 MX6DL_PAD_GPIO_0__CCM_CLKO1 0x130b0
33 >;
34 };
35 };
36};
diff --git a/arch/arm/boot/dts/imx6dl-wandboard.dts b/arch/arm/boot/dts/imx6dl-wandboard.dts
index bfc59c3566a4..e672891c1626 100644
--- a/arch/arm/boot/dts/imx6dl-wandboard.dts
+++ b/arch/arm/boot/dts/imx6dl-wandboard.dts
@@ -10,6 +10,7 @@
10 */ 10 */
11/dts-v1/; 11/dts-v1/;
12#include "imx6dl.dtsi" 12#include "imx6dl.dtsi"
13#include "imx6qdl-wandboard.dtsi"
13 14
14/ { 15/ {
15 model = "Wandboard i.MX6 Dual Lite Board"; 16 model = "Wandboard i.MX6 Dual Lite Board";
@@ -19,26 +20,3 @@
19 reg = <0x10000000 0x40000000>; 20 reg = <0x10000000 0x40000000>;
20 }; 21 };
21}; 22};
22
23&fec {
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_enet_1>;
26 phy-mode = "rgmii";
27 status = "okay";
28};
29
30&uart1 {
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_uart1_1>;
33 status = "okay";
34};
35
36&usbh1 {
37 status = "okay";
38};
39
40&usdhc3 {
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_usdhc3_2>;
43 status = "okay";
44};
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 2b3ecd679350..9e8ae118fdd4 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -8,8 +8,8 @@
8 * 8 *
9 */ 9 */
10 10
11#include "imx6qdl.dtsi"
12#include "imx6dl-pinfunc.h" 11#include "imx6dl-pinfunc.h"
12#include "imx6qdl.dtsi"
13 13
14/ { 14/ {
15 cpus { 15 cpus {
@@ -32,238 +32,15 @@
32 }; 32 };
33 33
34 soc { 34 soc {
35 ocram: sram@00900000 {
36 compatible = "mmio-sram";
37 reg = <0x00900000 0x20000>;
38 clocks = <&clks 142>;
39 };
40
35 aips1: aips-bus@02000000 { 41 aips1: aips-bus@02000000 {
36 iomuxc: iomuxc@020e0000 { 42 iomuxc: iomuxc@020e0000 {
37 compatible = "fsl,imx6dl-iomuxc"; 43 compatible = "fsl,imx6dl-iomuxc";
38 reg = <0x020e0000 0x4000>;
39
40 audmux {
41 pinctrl_audmux_2: audmux-2 {
42 fsl,pins = <
43 MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
44 MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
45 MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
46 MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
47 >;
48 };
49 };
50
51 ecspi1 {
52 pinctrl_ecspi1_1: ecspi1grp-1 {
53 fsl,pins = <
54 MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
55 MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
56 MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
57 >;
58 };
59 };
60
61 enet {
62 pinctrl_enet_1: enetgrp-1 {
63 fsl,pins = <
64 MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
65 MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
66 MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
67 MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
68 MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
69 MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
70 MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
71 MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
72 MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
73 MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
74 MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
75 MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
76 MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
77 MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
78 MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
79 MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
80 >;
81 };
82
83 pinctrl_enet_2: enetgrp-2 {
84 fsl,pins = <
85 MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
86 MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
87 MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
88 MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
89 MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
90 MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
91 MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
92 MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
93 MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
94 MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
95 MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
96 MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
97 MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
98 MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
99 MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
100 >;
101 };
102 };
103
104 gpmi-nand {
105 pinctrl_gpmi_nand_1: gpmi-nand-1 {
106 fsl,pins = <
107 MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
108 MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
109 MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
110 MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
111 MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
112 MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
113 MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
114 MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
115 MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
116 MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
117 MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
118 MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
119 MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
120 MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
121 MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
122 MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
123 MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1
124 >;
125 };
126 };
127
128 i2c1 {
129 pinctrl_i2c1_2: i2c1grp-2 {
130 fsl,pins = <
131 MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
132 MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
133 >;
134 };
135 };
136
137 uart1 {
138 pinctrl_uart1_1: uart1grp-1 {
139 fsl,pins = <
140 MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
141 MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
142 >;
143 };
144 };
145
146 uart4 {
147 pinctrl_uart4_1: uart4grp-1 {
148 fsl,pins = <
149 MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
150 MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
151 >;
152 };
153 };
154
155 usbotg {
156 pinctrl_usbotg_2: usbotggrp-2 {
157 fsl,pins = <
158 MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
159 >;
160 };
161 };
162
163 usdhc2 {
164 pinctrl_usdhc2_1: usdhc2grp-1 {
165 fsl,pins = <
166 MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059
167 MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059
168 MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
169 MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
170 MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
171 MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
172 MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
173 MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
174 MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
175 MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
176 >;
177 };
178 };
179
180 usdhc3 {
181 pinctrl_usdhc3_1: usdhc3grp-1 {
182 fsl,pins = <
183 MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
184 MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
185 MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
186 MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
187 MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
188 MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
189 MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
190 MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
191 MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
192 MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
193 >;
194 };
195
196 pinctrl_usdhc3_2: usdhc3grp_2 {
197 fsl,pins = <
198 MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
199 MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
200 MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
201 MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
202 MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
203 MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
204 >;
205 };
206 };
207
208 weim {
209 pinctrl_weim_cs0_1: weim_cs0grp-1 {
210 fsl,pins = <
211 MX6DL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
212 >;
213 };
214
215 pinctrl_weim_nor_1: weim_norgrp-1 {
216 fsl,pins = <
217 MX6DL_PAD_EIM_OE__EIM_OE_B 0xb0b1
218 MX6DL_PAD_EIM_RW__EIM_RW 0xb0b1
219 MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
220 /* data */
221 MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
222 MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
223 MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
224 MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
225 MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
226 MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
227 MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
228 MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
229 MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
230 MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
231 MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
232 MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
233 MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
234 MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
235 MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
236 MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
237 /* address */
238 MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
239 MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
240 MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
241 MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
242 MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
243 MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
244 MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
245 MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
246 MX6DL_PAD_EIM_DA15__EIM_AD15 0xb0b1
247 MX6DL_PAD_EIM_DA14__EIM_AD14 0xb0b1
248 MX6DL_PAD_EIM_DA13__EIM_AD13 0xb0b1
249 MX6DL_PAD_EIM_DA12__EIM_AD12 0xb0b1
250 MX6DL_PAD_EIM_DA11__EIM_AD11 0xb0b1
251 MX6DL_PAD_EIM_DA10__EIM_AD10 0xb0b1
252 MX6DL_PAD_EIM_DA9__EIM_AD09 0xb0b1
253 MX6DL_PAD_EIM_DA8__EIM_AD08 0xb0b1
254 MX6DL_PAD_EIM_DA7__EIM_AD07 0xb0b1
255 MX6DL_PAD_EIM_DA6__EIM_AD06 0xb0b1
256 MX6DL_PAD_EIM_DA5__EIM_AD05 0xb0b1
257 MX6DL_PAD_EIM_DA4__EIM_AD04 0xb0b1
258 MX6DL_PAD_EIM_DA3__EIM_AD03 0xb0b1
259 MX6DL_PAD_EIM_DA2__EIM_AD02 0xb0b1
260 MX6DL_PAD_EIM_DA1__EIM_AD01 0xb0b1
261 MX6DL_PAD_EIM_DA0__EIM_AD00 0xb0b1
262 >;
263 };
264
265 };
266
267 }; 44 };
268 45
269 pxp: pxp@020f0000 { 46 pxp: pxp@020f0000 {
@@ -294,3 +71,20 @@
294 }; 71 };
295 }; 72 };
296}; 73};
74
75&ldb {
76 clocks = <&clks 33>, <&clks 34>,
77 <&clks 39>, <&clks 40>,
78 <&clks 135>, <&clks 136>;
79 clock-names = "di0_pll", "di1_pll",
80 "di0_sel", "di1_sel",
81 "di0", "di1";
82
83 lvds-channel@0 {
84 crtcs = <&ipu1 0>, <&ipu1 1>;
85 };
86
87 lvds-channel@1 {
88 crtcs = <&ipu1 0>, <&ipu1 1>;
89 };
90};
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index 4e54fde591bd..edf1bd967164 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -57,7 +57,7 @@
57 hog { 57 hog {
58 pinctrl_hog: hoggrp { 58 pinctrl_hog: hoggrp {
59 fsl,pins = < 59 fsl,pins = <
60 MX6Q_PAD_EIM_D25__GPIO3_IO25 0x80000000 60 MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000
61 >; 61 >;
62 }; 62 };
63 }; 63 };
@@ -65,8 +65,8 @@
65 arm2 { 65 arm2 {
66 pinctrl_usdhc3_arm2: usdhc3grp-arm2 { 66 pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
67 fsl,pins = < 67 fsl,pins = <
68 MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 68 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
69 MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 69 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
70 >; 70 >;
71 }; 71 };
72 }; 72 };
@@ -97,6 +97,14 @@
97 status = "okay"; 97 status = "okay";
98}; 98};
99 99
100&uart2 {
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_uart2_2>;
103 fsl,dte-mode;
104 fsl,uart-has-rtscts;
105 status = "okay";
106};
107
100&uart4 { 108&uart4 {
101 pinctrl-names = "default"; 109 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_uart4_1>; 110 pinctrl-0 = <&pinctrl_uart4_1>;
diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
index f5e1981025ed..1a3b50d4d8fa 100644
--- a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
@@ -20,6 +20,110 @@
20 }; 20 };
21}; 21};
22 22
23&ecspi3 {
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_ecspi3_1>;
26 status = "okay";
27 fsl,spi-num-chipselects = <1>;
28 cs-gpios = <&gpio4 24 0>;
29
30 flash@0 {
31 compatible = "m25p80";
32 spi-max-frequency = <20000000>;
33 reg = <0>;
34 };
35};
36
37&i2c1 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_i2c1_1>;
40 status = "okay";
41
42 eeprom@50 {
43 compatible = "atmel,24c32";
44 reg = <0x50>;
45 };
46
47 pmic@58 {
48 compatible = "dialog,da9063";
49 reg = <0x58>;
50 interrupt-parent = <&gpio4>;
51 interrupts = <17 0x8>; /* active-low GPIO4_17 */
52
53 regulators {
54 vddcore_reg: bcore1 {
55 regulator-min-microvolt = <730000>;
56 regulator-max-microvolt = <1380000>;
57 regulator-always-on;
58 };
59
60 vddsoc_reg: bcore2 {
61 regulator-min-microvolt = <730000>;
62 regulator-max-microvolt = <1380000>;
63 regulator-always-on;
64 };
65
66 vdd_ddr3_reg: bpro {
67 regulator-min-microvolt = <1500000>;
68 regulator-max-microvolt = <1500000>;
69 regulator-always-on;
70 };
71
72 vdd_3v3_reg: bperi {
73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>;
75 regulator-always-on;
76 };
77
78 vdd_buckmem_reg: bmem {
79 regulator-min-microvolt = <3300000>;
80 regulator-max-microvolt = <3300000>;
81 regulator-always-on;
82 };
83
84 vdd_eth_reg: bio {
85 regulator-min-microvolt = <1200000>;
86 regulator-max-microvolt = <1200000>;
87 regulator-always-on;
88 };
89
90 vdd_eth_io_reg: ldo4 {
91 regulator-min-microvolt = <2500000>;
92 regulator-max-microvolt = <2500000>;
93 regulator-always-on;
94 };
95
96 vdd_mx6_snvs_reg: ldo5 {
97 regulator-min-microvolt = <3000000>;
98 regulator-max-microvolt = <3000000>;
99 regulator-always-on;
100 };
101
102 vdd_3v3_pmic_io_reg: ldo6 {
103 regulator-min-microvolt = <3300000>;
104 regulator-max-microvolt = <3300000>;
105 regulator-always-on;
106 };
107
108 vdd_sd0_reg: ldo9 {
109 regulator-min-microvolt = <3300000>;
110 regulator-max-microvolt = <3300000>;
111 };
112
113 vdd_sd1_reg: ldo10 {
114 regulator-min-microvolt = <3300000>;
115 regulator-max-microvolt = <3300000>;
116 };
117
118 vdd_mx6_high_reg: ldo11 {
119 regulator-min-microvolt = <3000000>;
120 regulator-max-microvolt = <3000000>;
121 regulator-always-on;
122 };
123 };
124 };
125};
126
23&iomuxc { 127&iomuxc {
24 pinctrl-names = "default"; 128 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_hog>; 129 pinctrl-0 = <&pinctrl_hog>;
@@ -27,7 +131,9 @@
27 hog { 131 hog {
28 pinctrl_hog: hoggrp { 132 pinctrl_hog: hoggrp {
29 fsl,pins = < 133 fsl,pins = <
30 MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000 134 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
135 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
136 MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */
31 >; 137 >;
32 }; 138 };
33 }; 139 };
@@ -35,8 +141,8 @@
35 pfla02 { 141 pfla02 {
36 pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 { 142 pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 {
37 fsl,pins = < 143 fsl,pins = <
38 MX6Q_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 144 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
39 MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 145 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
40 >; 146 >;
41 }; 147 };
42 }; 148 };
diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h
index faea6e1ada00..c0e38a45e4bb 100644
--- a/arch/arm/boot/dts/imx6q-pinfunc.h
+++ b/arch/arm/boot/dts/imx6q-pinfunc.h
@@ -14,1028 +14,1032 @@
14 * The pin function ID is a tuple of 14 * The pin function ID is a tuple of
15 * <mux_reg conf_reg input_reg mux_mode input_val> 15 * <mux_reg conf_reg input_reg mux_mode input_val>
16 */ 16 */
17#define MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 17#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
18#define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 18#define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
19#define MX6Q_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 19#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
20#define MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 20#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
21#define MX6Q_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 21#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
22#define MX6Q_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 22#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
23#define MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 23#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
24#define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 24#define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
25#define MX6Q_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 25#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
26#define MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 26#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
27#define MX6Q_PAD_SD2_DAT2__KEY_ROW6 0x050 0x364 0x8f8 0x4 0x0 27#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x050 0x364 0x8f8 0x4 0x0
28#define MX6Q_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0 28#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0
29#define MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x054 0x368 0x000 0x0 0x0 29#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x054 0x368 0x000 0x0 0x0
30#define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0 30#define MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0
31#define MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x054 0x368 0x7b4 0x3 0x0 31#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x054 0x368 0x7b4 0x3 0x0
32#define MX6Q_PAD_SD2_DAT0__KEY_ROW7 0x054 0x368 0x8fc 0x4 0x0 32#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x054 0x368 0x8fc 0x4 0x0
33#define MX6Q_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0 33#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0
34#define MX6Q_PAD_SD2_DAT0__DCIC2_OUT 0x054 0x368 0x000 0x6 0x0 34#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x054 0x368 0x000 0x6 0x0
35#define MX6Q_PAD_RGMII_TXC__USB_H2_DATA 0x058 0x36c 0x000 0x0 0x0 35#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x058 0x36c 0x000 0x0 0x0
36#define MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0 36#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0
37#define MX6Q_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0 37#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0
38#define MX6Q_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0 38#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0
39#define MX6Q_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x058 0x36c 0x000 0x7 0x0 39#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x058 0x36c 0x000 0x7 0x0
40#define MX6Q_PAD_RGMII_TD0__HSI_TX_READY 0x05c 0x370 0x000 0x0 0x0 40#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x05c 0x370 0x000 0x0 0x0
41#define MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0 41#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0
42#define MX6Q_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0 42#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0
43#define MX6Q_PAD_RGMII_TD1__HSI_RX_FLAG 0x060 0x374 0x000 0x0 0x0 43#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x060 0x374 0x000 0x0 0x0
44#define MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0 44#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0
45#define MX6Q_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0 45#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0
46#define MX6Q_PAD_RGMII_TD2__HSI_RX_DATA 0x064 0x378 0x000 0x0 0x0 46#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x064 0x378 0x000 0x0 0x0
47#define MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0 47#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0
48#define MX6Q_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0 48#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0
49#define MX6Q_PAD_RGMII_TD3__HSI_RX_WAKE 0x068 0x37c 0x000 0x0 0x0 49#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x068 0x37c 0x000 0x0 0x0
50#define MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0 50#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0
51#define MX6Q_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0 51#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0
52#define MX6Q_PAD_RGMII_RX_CTL__USB_H3_DATA 0x06c 0x380 0x000 0x0 0x0 52#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x06c 0x380 0x000 0x0 0x0
53#define MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0 53#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0
54#define MX6Q_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0 54#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0
55#define MX6Q_PAD_RGMII_RD0__HSI_RX_READY 0x070 0x384 0x000 0x0 0x0 55#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x070 0x384 0x000 0x0 0x0
56#define MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0 56#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0
57#define MX6Q_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 0x0 57#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 0x0
58#define MX6Q_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x074 0x388 0x000 0x0 0x0 58#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x074 0x388 0x000 0x0 0x0
59#define MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x074 0x388 0x000 0x1 0x0 59#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x074 0x388 0x000 0x1 0x0
60#define MX6Q_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0 60#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0
61#define MX6Q_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x074 0x388 0x83c 0x7 0x0 61#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x074 0x388 0x83c 0x7 0x0
62#define MX6Q_PAD_RGMII_RD1__HSI_TX_FLAG 0x078 0x38c 0x000 0x0 0x0 62#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x078 0x38c 0x000 0x0 0x0
63#define MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0 63#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0
64#define MX6Q_PAD_RGMII_RD1__GPIO6_IO27 0x078 0x38c 0x000 0x5 0x0 64#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x078 0x38c 0x000 0x5 0x0
65#define MX6Q_PAD_RGMII_RD2__HSI_TX_DATA 0x07c 0x390 0x000 0x0 0x0 65#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x07c 0x390 0x000 0x0 0x0
66#define MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0 66#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0
67#define MX6Q_PAD_RGMII_RD2__GPIO6_IO28 0x07c 0x390 0x000 0x5 0x0 67#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x07c 0x390 0x000 0x5 0x0
68#define MX6Q_PAD_RGMII_RD3__HSI_TX_WAKE 0x080 0x394 0x000 0x0 0x0 68#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x080 0x394 0x000 0x0 0x0
69#define MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x080 0x394 0x854 0x1 0x0 69#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x080 0x394 0x854 0x1 0x0
70#define MX6Q_PAD_RGMII_RD3__GPIO6_IO29 0x080 0x394 0x000 0x5 0x0 70#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x080 0x394 0x000 0x5 0x0
71#define MX6Q_PAD_RGMII_RXC__USB_H3_STROBE 0x084 0x398 0x000 0x0 0x0 71#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x084 0x398 0x000 0x0 0x0
72#define MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x084 0x398 0x844 0x1 0x0 72#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x084 0x398 0x844 0x1 0x0
73#define MX6Q_PAD_RGMII_RXC__GPIO6_IO30 0x084 0x398 0x000 0x5 0x0 73#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x084 0x398 0x000 0x5 0x0
74#define MX6Q_PAD_EIM_A25__EIM_ADDR25 0x088 0x39c 0x000 0x0 0x0 74#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x088 0x39c 0x000 0x0 0x0
75#define MX6Q_PAD_EIM_A25__ECSPI4_SS1 0x088 0x39c 0x000 0x1 0x0 75#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x088 0x39c 0x000 0x1 0x0
76#define MX6Q_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0 76#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0
77#define MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 0x088 0x39c 0x000 0x3 0x0 77#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x088 0x39c 0x000 0x3 0x0
78#define MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS 0x088 0x39c 0x000 0x4 0x0 78#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x088 0x39c 0x000 0x4 0x0
79#define MX6Q_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0 79#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0
80#define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0 80#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0
81#define MX6Q_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0 81#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0
82#define MX6Q_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0 82#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0
83#define MX6Q_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0 83#define MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0
84#define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0 84#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0
85#define MX6Q_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0 85#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0
86#define MX6Q_PAD_EIM_EB2__I2C2_SCL 0x08c 0x3a0 0x8a0 0x6 0x0 86#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x08c 0x3a0 0x8a0 0x6 0x0
87#define MX6Q_PAD_EIM_EB2__SRC_BOOT_CFG30 0x08c 0x3a0 0x000 0x7 0x0 87#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x08c 0x3a0 0x000 0x7 0x0
88#define MX6Q_PAD_EIM_D16__EIM_DATA16 0x090 0x3a4 0x000 0x0 0x0 88#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x090 0x3a4 0x000 0x0 0x0
89#define MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x090 0x3a4 0x7f4 0x1 0x0 89#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x090 0x3a4 0x7f4 0x1 0x0
90#define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0 90#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0
91#define MX6Q_PAD_EIM_D16__IPU2_CSI1_DATA18 0x090 0x3a4 0x8d0 0x3 0x0 91#define MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x090 0x3a4 0x8d0 0x3 0x0
92#define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x090 0x3a4 0x894 0x4 0x0 92#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x090 0x3a4 0x894 0x4 0x0
93#define MX6Q_PAD_EIM_D16__GPIO3_IO16 0x090 0x3a4 0x000 0x5 0x0 93#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x090 0x3a4 0x000 0x5 0x0
94#define MX6Q_PAD_EIM_D16__I2C2_SDA 0x090 0x3a4 0x8a4 0x6 0x0 94#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x090 0x3a4 0x8a4 0x6 0x0
95#define MX6Q_PAD_EIM_D17__EIM_DATA17 0x094 0x3a8 0x000 0x0 0x0 95#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x094 0x3a8 0x000 0x0 0x0
96#define MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x094 0x3a8 0x7f8 0x1 0x0 96#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x094 0x3a8 0x7f8 0x1 0x0
97#define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0 97#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0
98#define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x094 0x3a8 0x8e0 0x3 0x0 98#define MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x094 0x3a8 0x8e0 0x3 0x0
99#define MX6Q_PAD_EIM_D17__DCIC1_OUT 0x094 0x3a8 0x000 0x4 0x0 99#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x094 0x3a8 0x000 0x4 0x0
100#define MX6Q_PAD_EIM_D17__GPIO3_IO17 0x094 0x3a8 0x000 0x5 0x0 100#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x094 0x3a8 0x000 0x5 0x0
101#define MX6Q_PAD_EIM_D17__I2C3_SCL 0x094 0x3a8 0x8a8 0x6 0x0 101#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x094 0x3a8 0x8a8 0x6 0x0
102#define MX6Q_PAD_EIM_D18__EIM_DATA18 0x098 0x3ac 0x000 0x0 0x0 102#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x098 0x3ac 0x000 0x0 0x0
103#define MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x098 0x3ac 0x7fc 0x1 0x0 103#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x098 0x3ac 0x7fc 0x1 0x0
104#define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0 104#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0
105#define MX6Q_PAD_EIM_D18__IPU2_CSI1_DATA17 0x098 0x3ac 0x8cc 0x3 0x0 105#define MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x098 0x3ac 0x8cc 0x3 0x0
106#define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS 0x098 0x3ac 0x000 0x4 0x0 106#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x098 0x3ac 0x000 0x4 0x0
107#define MX6Q_PAD_EIM_D18__GPIO3_IO18 0x098 0x3ac 0x000 0x5 0x0 107#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x098 0x3ac 0x000 0x5 0x0
108#define MX6Q_PAD_EIM_D18__I2C3_SDA 0x098 0x3ac 0x8ac 0x6 0x0 108#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x098 0x3ac 0x8ac 0x6 0x0
109#define MX6Q_PAD_EIM_D19__EIM_DATA19 0x09c 0x3b0 0x000 0x0 0x0 109#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x09c 0x3b0 0x000 0x0 0x0
110#define MX6Q_PAD_EIM_D19__ECSPI1_SS1 0x09c 0x3b0 0x804 0x1 0x0 110#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x09c 0x3b0 0x804 0x1 0x0
111#define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0 111#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0
112#define MX6Q_PAD_EIM_D19__IPU2_CSI1_DATA16 0x09c 0x3b0 0x8c8 0x3 0x0 112#define MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x09c 0x3b0 0x8c8 0x3 0x0
113#define MX6Q_PAD_EIM_D19__UART1_CTS_B 0x09c 0x3b0 0x000 0x4 0x0 113#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x09c 0x3b0 0x000 0x4 0x0
114#define MX6Q_PAD_EIM_D19__UART1_RTS_B 0x09c 0x3b0 0x91c 0x4 0x0 114#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x09c 0x3b0 0x91c 0x4 0x0
115#define MX6Q_PAD_EIM_D19__GPIO3_IO19 0x09c 0x3b0 0x000 0x5 0x0 115#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x09c 0x3b0 0x000 0x5 0x0
116#define MX6Q_PAD_EIM_D19__EPIT1_OUT 0x09c 0x3b0 0x000 0x6 0x0 116#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x09c 0x3b0 0x000 0x6 0x0
117#define MX6Q_PAD_EIM_D20__EIM_DATA20 0x0a0 0x3b4 0x000 0x0 0x0 117#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x0a0 0x3b4 0x000 0x0 0x0
118#define MX6Q_PAD_EIM_D20__ECSPI4_SS0 0x0a0 0x3b4 0x824 0x1 0x0 118#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x0a0 0x3b4 0x824 0x1 0x0
119#define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0 119#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0
120#define MX6Q_PAD_EIM_D20__IPU2_CSI1_DATA15 0x0a0 0x3b4 0x8c4 0x3 0x0 120#define MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x0a0 0x3b4 0x8c4 0x3 0x0
121#define MX6Q_PAD_EIM_D20__UART1_RTS_B 0x0a0 0x3b4 0x91c 0x4 0x1 121#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x0a0 0x3b4 0x91c 0x4 0x1
122#define MX6Q_PAD_EIM_D20__UART1_CTS_B 0x0a0 0x3b4 0x000 0x4 0x0 122#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0a0 0x3b4 0x000 0x4 0x0
123#define MX6Q_PAD_EIM_D20__GPIO3_IO20 0x0a0 0x3b4 0x000 0x5 0x0 123#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0a0 0x3b4 0x000 0x5 0x0
124#define MX6Q_PAD_EIM_D20__EPIT2_OUT 0x0a0 0x3b4 0x000 0x6 0x0 124#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x0a0 0x3b4 0x000 0x6 0x0
125#define MX6Q_PAD_EIM_D21__EIM_DATA21 0x0a4 0x3b8 0x000 0x0 0x0 125#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x0a4 0x3b8 0x000 0x0 0x0
126#define MX6Q_PAD_EIM_D21__ECSPI4_SCLK 0x0a4 0x3b8 0x000 0x1 0x0 126#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x0a4 0x3b8 0x000 0x1 0x0
127#define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0 127#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0
128#define MX6Q_PAD_EIM_D21__IPU2_CSI1_DATA11 0x0a4 0x3b8 0x8b4 0x3 0x0 128#define MX6QDL_PAD_EIM_D21__IPU2_CSI1_DATA11 0x0a4 0x3b8 0x8b4 0x3 0x0
129#define MX6Q_PAD_EIM_D21__USB_OTG_OC 0x0a4 0x3b8 0x944 0x4 0x0 129#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0a4 0x3b8 0x944 0x4 0x0
130#define MX6Q_PAD_EIM_D21__GPIO3_IO21 0x0a4 0x3b8 0x000 0x5 0x0 130#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x0a4 0x3b8 0x000 0x5 0x0
131#define MX6Q_PAD_EIM_D21__I2C1_SCL 0x0a4 0x3b8 0x898 0x6 0x0 131#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x0a4 0x3b8 0x898 0x6 0x0
132#define MX6Q_PAD_EIM_D21__SPDIF_IN 0x0a4 0x3b8 0x914 0x7 0x0 132#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x0a4 0x3b8 0x914 0x7 0x0
133#define MX6Q_PAD_EIM_D22__EIM_DATA22 0x0a8 0x3bc 0x000 0x0 0x0 133#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x0a8 0x3bc 0x000 0x0 0x0
134#define MX6Q_PAD_EIM_D22__ECSPI4_MISO 0x0a8 0x3bc 0x000 0x1 0x0 134#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x0a8 0x3bc 0x000 0x1 0x0
135#define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0 135#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0
136#define MX6Q_PAD_EIM_D22__IPU2_CSI1_DATA10 0x0a8 0x3bc 0x8b0 0x3 0x0 136#define MX6QDL_PAD_EIM_D22__IPU2_CSI1_DATA10 0x0a8 0x3bc 0x8b0 0x3 0x0
137#define MX6Q_PAD_EIM_D22__USB_OTG_PWR 0x0a8 0x3bc 0x000 0x4 0x0 137#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0a8 0x3bc 0x000 0x4 0x0
138#define MX6Q_PAD_EIM_D22__GPIO3_IO22 0x0a8 0x3bc 0x000 0x5 0x0 138#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0a8 0x3bc 0x000 0x5 0x0
139#define MX6Q_PAD_EIM_D22__SPDIF_OUT 0x0a8 0x3bc 0x000 0x6 0x0 139#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x0a8 0x3bc 0x000 0x6 0x0
140#define MX6Q_PAD_EIM_D23__EIM_DATA23 0x0ac 0x3c0 0x000 0x0 0x0 140#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x0ac 0x3c0 0x000 0x0 0x0
141#define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS 0x0ac 0x3c0 0x000 0x1 0x0 141#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x0ac 0x3c0 0x000 0x1 0x0
142#define MX6Q_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0 142#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0
143#define MX6Q_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0 143#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0
144#define MX6Q_PAD_EIM_D23__UART1_DCD_B 0x0ac 0x3c0 0x000 0x3 0x0 144#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x0ac 0x3c0 0x000 0x3 0x0
145#define MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN 0x0ac 0x3c0 0x8d8 0x4 0x0 145#define MX6QDL_PAD_EIM_D23__IPU2_CSI1_DATA_EN 0x0ac 0x3c0 0x8d8 0x4 0x0
146#define MX6Q_PAD_EIM_D23__GPIO3_IO23 0x0ac 0x3c0 0x000 0x5 0x0 146#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0ac 0x3c0 0x000 0x5 0x0
147#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN02 0x0ac 0x3c0 0x000 0x6 0x0 147#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x0ac 0x3c0 0x000 0x6 0x0
148#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 0x0ac 0x3c0 0x000 0x7 0x0 148#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x0ac 0x3c0 0x000 0x7 0x0
149#define MX6Q_PAD_EIM_EB3__EIM_EB3_B 0x0b0 0x3c4 0x000 0x0 0x0 149#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x0b0 0x3c4 0x000 0x0 0x0
150#define MX6Q_PAD_EIM_EB3__ECSPI4_RDY 0x0b0 0x3c4 0x000 0x1 0x0 150#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x0b0 0x3c4 0x000 0x1 0x0
151#define MX6Q_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1 151#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1
152#define MX6Q_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0 152#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0
153#define MX6Q_PAD_EIM_EB3__UART1_RI_B 0x0b0 0x3c4 0x000 0x3 0x0 153#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x0b0 0x3c4 0x000 0x3 0x0
154#define MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x0b0 0x3c4 0x8dc 0x4 0x0 154#define MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x0b0 0x3c4 0x8dc 0x4 0x0
155#define MX6Q_PAD_EIM_EB3__GPIO2_IO31 0x0b0 0x3c4 0x000 0x5 0x0 155#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0 0x3c4 0x000 0x5 0x0
156#define MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN03 0x0b0 0x3c4 0x000 0x6 0x0 156#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x0b0 0x3c4 0x000 0x6 0x0
157#define MX6Q_PAD_EIM_EB3__SRC_BOOT_CFG31 0x0b0 0x3c4 0x000 0x7 0x0 157#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x0b0 0x3c4 0x000 0x7 0x0
158#define MX6Q_PAD_EIM_D24__EIM_DATA24 0x0b4 0x3c8 0x000 0x0 0x0 158#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x0b4 0x3c8 0x000 0x0 0x0
159#define MX6Q_PAD_EIM_D24__ECSPI4_SS2 0x0b4 0x3c8 0x000 0x1 0x0 159#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x0b4 0x3c8 0x000 0x1 0x0
160#define MX6Q_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0 160#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0
161#define MX6Q_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0 161#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0
162#define MX6Q_PAD_EIM_D24__ECSPI1_SS2 0x0b4 0x3c8 0x808 0x3 0x0 162#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x0b4 0x3c8 0x808 0x3 0x0
163#define MX6Q_PAD_EIM_D24__ECSPI2_SS2 0x0b4 0x3c8 0x000 0x4 0x0 163#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x0b4 0x3c8 0x000 0x4 0x0
164#define MX6Q_PAD_EIM_D24__GPIO3_IO24 0x0b4 0x3c8 0x000 0x5 0x0 164#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0b4 0x3c8 0x000 0x5 0x0
165#define MX6Q_PAD_EIM_D24__AUD5_RXFS 0x0b4 0x3c8 0x7d8 0x6 0x0 165#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x0b4 0x3c8 0x7d8 0x6 0x0
166#define MX6Q_PAD_EIM_D24__UART1_DTR_B 0x0b4 0x3c8 0x000 0x7 0x0 166#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x0b4 0x3c8 0x000 0x7 0x0
167#define MX6Q_PAD_EIM_D25__EIM_DATA25 0x0b8 0x3cc 0x000 0x0 0x0 167#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x0b8 0x3cc 0x000 0x0 0x0
168#define MX6Q_PAD_EIM_D25__ECSPI4_SS3 0x0b8 0x3cc 0x000 0x1 0x0 168#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x0b8 0x3cc 0x000 0x1 0x0
169#define MX6Q_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1 169#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1
170#define MX6Q_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0 170#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0
171#define MX6Q_PAD_EIM_D25__ECSPI1_SS3 0x0b8 0x3cc 0x80c 0x3 0x0 171#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x0b8 0x3cc 0x80c 0x3 0x0
172#define MX6Q_PAD_EIM_D25__ECSPI2_SS3 0x0b8 0x3cc 0x000 0x4 0x0 172#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x0b8 0x3cc 0x000 0x4 0x0
173#define MX6Q_PAD_EIM_D25__GPIO3_IO25 0x0b8 0x3cc 0x000 0x5 0x0 173#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0b8 0x3cc 0x000 0x5 0x0
174#define MX6Q_PAD_EIM_D25__AUD5_RXC 0x0b8 0x3cc 0x7d4 0x6 0x0 174#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x0b8 0x3cc 0x7d4 0x6 0x0
175#define MX6Q_PAD_EIM_D25__UART1_DSR_B 0x0b8 0x3cc 0x000 0x7 0x0 175#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x0b8 0x3cc 0x000 0x7 0x0
176#define MX6Q_PAD_EIM_D26__EIM_DATA26 0x0bc 0x3d0 0x000 0x0 0x0 176#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x0bc 0x3d0 0x000 0x0 0x0
177#define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 0x0bc 0x3d0 0x000 0x1 0x0 177#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x0bc 0x3d0 0x000 0x1 0x0
178#define MX6Q_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0 178#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0
179#define MX6Q_PAD_EIM_D26__IPU2_CSI1_DATA14 0x0bc 0x3d0 0x8c0 0x3 0x0 179#define MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x0bc 0x3d0 0x8c0 0x3 0x0
180#define MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x0bc 0x3d0 0x000 0x4 0x0 180#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x0bc 0x3d0 0x000 0x4 0x0
181#define MX6Q_PAD_EIM_D26__UART2_RX_DATA 0x0bc 0x3d0 0x928 0x4 0x0 181#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0bc 0x3d0 0x928 0x4 0x0
182#define MX6Q_PAD_EIM_D26__GPIO3_IO26 0x0bc 0x3d0 0x000 0x5 0x0 182#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0bc 0x3d0 0x000 0x5 0x0
183#define MX6Q_PAD_EIM_D26__IPU1_SISG2 0x0bc 0x3d0 0x000 0x6 0x0 183#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x0bc 0x3d0 0x000 0x6 0x0
184#define MX6Q_PAD_EIM_D26__IPU1_DISP1_DATA22 0x0bc 0x3d0 0x000 0x7 0x0 184#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x0bc 0x3d0 0x000 0x7 0x0
185#define MX6Q_PAD_EIM_D27__EIM_DATA27 0x0c0 0x3d4 0x000 0x0 0x0 185#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x0c0 0x3d4 0x000 0x0 0x0
186#define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 0x0c0 0x3d4 0x000 0x1 0x0 186#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x0c0 0x3d4 0x000 0x1 0x0
187#define MX6Q_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0 187#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0
188#define MX6Q_PAD_EIM_D27__IPU2_CSI1_DATA13 0x0c0 0x3d4 0x8bc 0x3 0x0 188#define MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x0c0 0x3d4 0x8bc 0x3 0x0
189#define MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x0c0 0x3d4 0x928 0x4 0x1 189#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x0c0 0x3d4 0x928 0x4 0x1
190#define MX6Q_PAD_EIM_D27__UART2_TX_DATA 0x0c0 0x3d4 0x000 0x4 0x0 190#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0c0 0x3d4 0x000 0x4 0x0
191#define MX6Q_PAD_EIM_D27__GPIO3_IO27 0x0c0 0x3d4 0x000 0x5 0x0 191#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0c0 0x3d4 0x000 0x5 0x0
192#define MX6Q_PAD_EIM_D27__IPU1_SISG3 0x0c0 0x3d4 0x000 0x6 0x0 192#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x0c0 0x3d4 0x000 0x6 0x0
193#define MX6Q_PAD_EIM_D27__IPU1_DISP1_DATA23 0x0c0 0x3d4 0x000 0x7 0x0 193#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x0c0 0x3d4 0x000 0x7 0x0
194#define MX6Q_PAD_EIM_D28__EIM_DATA28 0x0c4 0x3d8 0x000 0x0 0x0 194#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x0c4 0x3d8 0x000 0x0 0x0
195#define MX6Q_PAD_EIM_D28__I2C1_SDA 0x0c4 0x3d8 0x89c 0x1 0x0 195#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x0c4 0x3d8 0x89c 0x1 0x0
196#define MX6Q_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0 196#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0
197#define MX6Q_PAD_EIM_D28__IPU2_CSI1_DATA12 0x0c4 0x3d8 0x8b8 0x3 0x0 197#define MX6QDL_PAD_EIM_D28__IPU2_CSI1_DATA12 0x0c4 0x3d8 0x8b8 0x3 0x0
198#define MX6Q_PAD_EIM_D28__UART2_CTS_B 0x0c4 0x3d8 0x000 0x4 0x0 198#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x0c4 0x3d8 0x000 0x4 0x0
199#define MX6Q_PAD_EIM_D28__UART2_RTS_B 0x0c4 0x3d8 0x924 0x4 0x0 199#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0c4 0x3d8 0x924 0x4 0x0
200#define MX6Q_PAD_EIM_D28__GPIO3_IO28 0x0c4 0x3d8 0x000 0x5 0x0 200#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x0c4 0x3d8 0x924 0x4 0x0
201#define MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG 0x0c4 0x3d8 0x000 0x6 0x0 201#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x0c4 0x3d8 0x000 0x4 0x0
202#define MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 0x0c4 0x3d8 0x000 0x7 0x0 202#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0c4 0x3d8 0x000 0x5 0x0
203#define MX6Q_PAD_EIM_D29__EIM_DATA29 0x0c8 0x3dc 0x000 0x0 0x0 203#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x0c4 0x3d8 0x000 0x6 0x0
204#define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 0x0c8 0x3dc 0x000 0x1 0x0 204#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x0c4 0x3d8 0x000 0x7 0x0
205#define MX6Q_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1 205#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x0c8 0x3dc 0x000 0x0 0x0
206#define MX6Q_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1 206#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x0c8 0x3dc 0x000 0x1 0x0
207#define MX6Q_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0 207#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1
208#define MX6Q_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0 208#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1
209#define MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0 209#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0
210#define MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0 210#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c4 0x3dc 0x000 0x4 0x0
211#define MX6Q_PAD_EIM_D30__EIM_DATA30 0x0cc 0x3e0 0x000 0x0 0x0 211#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c4 0x3dc 0x924 0x4 0x1
212#define MX6Q_PAD_EIM_D30__IPU1_DISP1_DATA21 0x0cc 0x3e0 0x000 0x1 0x0 212#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0
213#define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0 213#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0
214#define MX6Q_PAD_EIM_D30__IPU1_CSI0_DATA03 0x0cc 0x3e0 0x000 0x3 0x0 214#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0
215#define MX6Q_PAD_EIM_D30__UART3_CTS_B 0x0cc 0x3e0 0x000 0x4 0x0 215#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x0cc 0x3e0 0x000 0x0 0x0
216#define MX6Q_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2 216#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x0cc 0x3e0 0x000 0x1 0x0
217#define MX6Q_PAD_EIM_D30__GPIO3_IO30 0x0cc 0x3e0 0x000 0x5 0x0 217#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0
218#define MX6Q_PAD_EIM_D30__USB_H1_OC 0x0cc 0x3e0 0x948 0x6 0x0 218#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x0cc 0x3e0 0x000 0x3 0x0
219#define MX6Q_PAD_EIM_D31__EIM_DATA31 0x0d0 0x3e4 0x000 0x0 0x0 219#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x0cc 0x3e0 0x000 0x4 0x0
220#define MX6Q_PAD_EIM_D31__IPU1_DISP1_DATA20 0x0d0 0x3e4 0x000 0x1 0x0 220#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2
221#define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0 221#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0cc 0x3e0 0x000 0x5 0x0
222#define MX6Q_PAD_EIM_D31__IPU1_CSI0_DATA02 0x0d0 0x3e4 0x000 0x3 0x0 222#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0cc 0x3e0 0x948 0x6 0x0
223#define MX6Q_PAD_EIM_D31__UART3_RTS_B 0x0d0 0x3e4 0x92c 0x4 0x3 223#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x0d0 0x3e4 0x000 0x0 0x0
224#define MX6Q_PAD_EIM_D31__UART3_CTS_B 0x0d0 0x3e4 0x000 0x4 0x0 224#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x0d0 0x3e4 0x000 0x1 0x0
225#define MX6Q_PAD_EIM_D31__GPIO3_IO31 0x0d0 0x3e4 0x000 0x5 0x0 225#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0
226#define MX6Q_PAD_EIM_D31__USB_H1_PWR 0x0d0 0x3e4 0x000 0x6 0x0 226#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x0d0 0x3e4 0x000 0x3 0x0
227#define MX6Q_PAD_EIM_A24__EIM_ADDR24 0x0d4 0x3e8 0x000 0x0 0x0 227#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x0d0 0x3e4 0x92c 0x4 0x3
228#define MX6Q_PAD_EIM_A24__IPU1_DISP1_DATA19 0x0d4 0x3e8 0x000 0x1 0x0 228#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x0d0 0x3e4 0x000 0x4 0x0
229#define MX6Q_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1 229#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0d0 0x3e4 0x000 0x5 0x0
230#define MX6Q_PAD_EIM_A24__IPU2_SISG2 0x0d4 0x3e8 0x000 0x3 0x0 230#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x0d0 0x3e4 0x000 0x6 0x0
231#define MX6Q_PAD_EIM_A24__IPU1_SISG2 0x0d4 0x3e8 0x000 0x4 0x0 231#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x0d4 0x3e8 0x000 0x0 0x0
232#define MX6Q_PAD_EIM_A24__GPIO5_IO04 0x0d4 0x3e8 0x000 0x5 0x0 232#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x0d4 0x3e8 0x000 0x1 0x0
233#define MX6Q_PAD_EIM_A24__SRC_BOOT_CFG24 0x0d4 0x3e8 0x000 0x7 0x0 233#define MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1
234#define MX6Q_PAD_EIM_A23__EIM_ADDR23 0x0d8 0x3ec 0x000 0x0 0x0 234#define MX6QDL_PAD_EIM_A24__IPU2_SISG2 0x0d4 0x3e8 0x000 0x3 0x0
235#define MX6Q_PAD_EIM_A23__IPU1_DISP1_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 235#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x0d4 0x3e8 0x000 0x4 0x0
236#define MX6Q_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1 236#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0d4 0x3e8 0x000 0x5 0x0
237#define MX6Q_PAD_EIM_A23__IPU2_SISG3 0x0d8 0x3ec 0x000 0x3 0x0 237#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x0d4 0x3e8 0x000 0x7 0x0
238#define MX6Q_PAD_EIM_A23__IPU1_SISG3 0x0d8 0x3ec 0x000 0x4 0x0 238#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x0d8 0x3ec 0x000 0x0 0x0
239#define MX6Q_PAD_EIM_A23__GPIO6_IO06 0x0d8 0x3ec 0x000 0x5 0x0 239#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x0d8 0x3ec 0x000 0x1 0x0
240#define MX6Q_PAD_EIM_A23__SRC_BOOT_CFG23 0x0d8 0x3ec 0x000 0x7 0x0 240#define MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1
241#define MX6Q_PAD_EIM_A22__EIM_ADDR22 0x0dc 0x3f0 0x000 0x0 0x0 241#define MX6QDL_PAD_EIM_A23__IPU2_SISG3 0x0d8 0x3ec 0x000 0x3 0x0
242#define MX6Q_PAD_EIM_A22__IPU1_DISP1_DATA17 0x0dc 0x3f0 0x000 0x1 0x0 242#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x0d8 0x3ec 0x000 0x4 0x0
243#define MX6Q_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1 243#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x0d8 0x3ec 0x000 0x5 0x0
244#define MX6Q_PAD_EIM_A22__GPIO2_IO16 0x0dc 0x3f0 0x000 0x5 0x0 244#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x0d8 0x3ec 0x000 0x7 0x0
245#define MX6Q_PAD_EIM_A22__SRC_BOOT_CFG22 0x0dc 0x3f0 0x000 0x7 0x0 245#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x0dc 0x3f0 0x000 0x0 0x0
246#define MX6Q_PAD_EIM_A21__EIM_ADDR21 0x0e0 0x3f4 0x000 0x0 0x0 246#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x0dc 0x3f0 0x000 0x1 0x0
247#define MX6Q_PAD_EIM_A21__IPU1_DISP1_DATA16 0x0e0 0x3f4 0x000 0x1 0x0 247#define MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1
248#define MX6Q_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1 248#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x0dc 0x3f0 0x000 0x5 0x0
249#define MX6Q_PAD_EIM_A21__GPIO2_IO17 0x0e0 0x3f4 0x000 0x5 0x0 249#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x0dc 0x3f0 0x000 0x7 0x0
250#define MX6Q_PAD_EIM_A21__SRC_BOOT_CFG21 0x0e0 0x3f4 0x000 0x7 0x0 250#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x0e0 0x3f4 0x000 0x0 0x0
251#define MX6Q_PAD_EIM_A20__EIM_ADDR20 0x0e4 0x3f8 0x000 0x0 0x0 251#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x0e0 0x3f4 0x000 0x1 0x0
252#define MX6Q_PAD_EIM_A20__IPU1_DISP1_DATA15 0x0e4 0x3f8 0x000 0x1 0x0 252#define MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1
253#define MX6Q_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1 253#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x0e0 0x3f4 0x000 0x5 0x0
254#define MX6Q_PAD_EIM_A20__GPIO2_IO18 0x0e4 0x3f8 0x000 0x5 0x0 254#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x0e0 0x3f4 0x000 0x7 0x0
255#define MX6Q_PAD_EIM_A20__SRC_BOOT_CFG20 0x0e4 0x3f8 0x000 0x7 0x0 255#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x0e4 0x3f8 0x000 0x0 0x0
256#define MX6Q_PAD_EIM_A19__EIM_ADDR19 0x0e8 0x3fc 0x000 0x0 0x0 256#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x0e4 0x3f8 0x000 0x1 0x0
257#define MX6Q_PAD_EIM_A19__IPU1_DISP1_DATA14 0x0e8 0x3fc 0x000 0x1 0x0 257#define MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1
258#define MX6Q_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1 258#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x0e4 0x3f8 0x000 0x5 0x0
259#define MX6Q_PAD_EIM_A19__GPIO2_IO19 0x0e8 0x3fc 0x000 0x5 0x0 259#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x0e4 0x3f8 0x000 0x7 0x0
260#define MX6Q_PAD_EIM_A19__SRC_BOOT_CFG19 0x0e8 0x3fc 0x000 0x7 0x0 260#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x0e8 0x3fc 0x000 0x0 0x0
261#define MX6Q_PAD_EIM_A18__EIM_ADDR18 0x0ec 0x400 0x000 0x0 0x0 261#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x0e8 0x3fc 0x000 0x1 0x0
262#define MX6Q_PAD_EIM_A18__IPU1_DISP1_DATA13 0x0ec 0x400 0x000 0x1 0x0 262#define MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1
263#define MX6Q_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1 263#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x0e8 0x3fc 0x000 0x5 0x0
264#define MX6Q_PAD_EIM_A18__GPIO2_IO20 0x0ec 0x400 0x000 0x5 0x0 264#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x0e8 0x3fc 0x000 0x7 0x0
265#define MX6Q_PAD_EIM_A18__SRC_BOOT_CFG18 0x0ec 0x400 0x000 0x7 0x0 265#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x0ec 0x400 0x000 0x0 0x0
266#define MX6Q_PAD_EIM_A17__EIM_ADDR17 0x0f0 0x404 0x000 0x0 0x0 266#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x0ec 0x400 0x000 0x1 0x0
267#define MX6Q_PAD_EIM_A17__IPU1_DISP1_DATA12 0x0f0 0x404 0x000 0x1 0x0 267#define MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1
268#define MX6Q_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1 268#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x0ec 0x400 0x000 0x5 0x0
269#define MX6Q_PAD_EIM_A17__GPIO2_IO21 0x0f0 0x404 0x000 0x5 0x0 269#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x0ec 0x400 0x000 0x7 0x0
270#define MX6Q_PAD_EIM_A17__SRC_BOOT_CFG17 0x0f0 0x404 0x000 0x7 0x0 270#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x0f0 0x404 0x000 0x0 0x0
271#define MX6Q_PAD_EIM_A16__EIM_ADDR16 0x0f4 0x408 0x000 0x0 0x0 271#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x0f0 0x404 0x000 0x1 0x0
272#define MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x0f4 0x408 0x000 0x1 0x0 272#define MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1
273#define MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1 273#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x0f0 0x404 0x000 0x5 0x0
274#define MX6Q_PAD_EIM_A16__GPIO2_IO22 0x0f4 0x408 0x000 0x5 0x0 274#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x0f0 0x404 0x000 0x7 0x0
275#define MX6Q_PAD_EIM_A16__SRC_BOOT_CFG16 0x0f4 0x408 0x000 0x7 0x0 275#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x0f4 0x408 0x000 0x0 0x0
276#define MX6Q_PAD_EIM_CS0__EIM_CS0_B 0x0f8 0x40c 0x000 0x0 0x0 276#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x0f4 0x408 0x000 0x1 0x0
277#define MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN05 0x0f8 0x40c 0x000 0x1 0x0 277#define MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1
278#define MX6Q_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0 278#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x0f4 0x408 0x000 0x5 0x0
279#define MX6Q_PAD_EIM_CS0__GPIO2_IO23 0x0f8 0x40c 0x000 0x5 0x0 279#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x0f4 0x408 0x000 0x7 0x0
280#define MX6Q_PAD_EIM_CS1__EIM_CS1_B 0x0fc 0x410 0x000 0x0 0x0 280#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x0f8 0x40c 0x000 0x0 0x0
281#define MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN06 0x0fc 0x410 0x000 0x1 0x0 281#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x0f8 0x40c 0x000 0x1 0x0
282#define MX6Q_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0 282#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0
283#define MX6Q_PAD_EIM_CS1__GPIO2_IO24 0x0fc 0x410 0x000 0x5 0x0 283#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0f8 0x40c 0x000 0x5 0x0
284#define MX6Q_PAD_EIM_OE__EIM_OE_B 0x100 0x414 0x000 0x0 0x0 284#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x0fc 0x410 0x000 0x0 0x0
285#define MX6Q_PAD_EIM_OE__IPU1_DI1_PIN07 0x100 0x414 0x000 0x1 0x0 285#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x0fc 0x410 0x000 0x1 0x0
286#define MX6Q_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0 286#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0
287#define MX6Q_PAD_EIM_OE__GPIO2_IO25 0x100 0x414 0x000 0x5 0x0 287#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0fc 0x410 0x000 0x5 0x0
288#define MX6Q_PAD_EIM_RW__EIM_RW 0x104 0x418 0x000 0x0 0x0 288#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x100 0x414 0x000 0x0 0x0
289#define MX6Q_PAD_EIM_RW__IPU1_DI1_PIN08 0x104 0x418 0x000 0x1 0x0 289#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x100 0x414 0x000 0x1 0x0
290#define MX6Q_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0 290#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0
291#define MX6Q_PAD_EIM_RW__GPIO2_IO26 0x104 0x418 0x000 0x5 0x0 291#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x100 0x414 0x000 0x5 0x0
292#define MX6Q_PAD_EIM_RW__SRC_BOOT_CFG29 0x104 0x418 0x000 0x7 0x0 292#define MX6QDL_PAD_EIM_RW__EIM_RW 0x104 0x418 0x000 0x0 0x0
293#define MX6Q_PAD_EIM_LBA__EIM_LBA_B 0x108 0x41c 0x000 0x0 0x0 293#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x104 0x418 0x000 0x1 0x0
294#define MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 0x108 0x41c 0x000 0x1 0x0 294#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0
295#define MX6Q_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0 295#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x104 0x418 0x000 0x5 0x0
296#define MX6Q_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0 296#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x104 0x418 0x000 0x7 0x0
297#define MX6Q_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0 297#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x108 0x41c 0x000 0x0 0x0
298#define MX6Q_PAD_EIM_EB0__EIM_EB0_B 0x10c 0x420 0x000 0x0 0x0 298#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x108 0x41c 0x000 0x1 0x0
299#define MX6Q_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x10c 0x420 0x000 0x1 0x0 299#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0
300#define MX6Q_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1 300#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0
301#define MX6Q_PAD_EIM_EB0__CCM_PMIC_READY 0x10c 0x420 0x7f0 0x4 0x0 301#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0
302#define MX6Q_PAD_EIM_EB0__GPIO2_IO28 0x10c 0x420 0x000 0x5 0x0 302#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x10c 0x420 0x000 0x0 0x0
303#define MX6Q_PAD_EIM_EB0__SRC_BOOT_CFG27 0x10c 0x420 0x000 0x7 0x0 303#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x10c 0x420 0x000 0x1 0x0
304#define MX6Q_PAD_EIM_EB1__EIM_EB1_B 0x110 0x424 0x000 0x0 0x0 304#define MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1
305#define MX6Q_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x110 0x424 0x000 0x1 0x0 305#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x10c 0x420 0x7f0 0x4 0x0
306#define MX6Q_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1 306#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x10c 0x420 0x000 0x5 0x0
307#define MX6Q_PAD_EIM_EB1__GPIO2_IO29 0x110 0x424 0x000 0x5 0x0 307#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x10c 0x420 0x000 0x7 0x0
308#define MX6Q_PAD_EIM_EB1__SRC_BOOT_CFG28 0x110 0x424 0x000 0x7 0x0 308#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x110 0x424 0x000 0x0 0x0
309#define MX6Q_PAD_EIM_DA0__EIM_AD00 0x114 0x428 0x000 0x0 0x0 309#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x110 0x424 0x000 0x1 0x0
310#define MX6Q_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x114 0x428 0x000 0x1 0x0 310#define MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1
311#define MX6Q_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0 311#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x110 0x424 0x000 0x5 0x0
312#define MX6Q_PAD_EIM_DA0__GPIO3_IO00 0x114 0x428 0x000 0x5 0x0 312#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x110 0x424 0x000 0x7 0x0
313#define MX6Q_PAD_EIM_DA0__SRC_BOOT_CFG00 0x114 0x428 0x000 0x7 0x0 313#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x114 0x428 0x000 0x0 0x0
314#define MX6Q_PAD_EIM_DA1__EIM_AD01 0x118 0x42c 0x000 0x0 0x0 314#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x114 0x428 0x000 0x1 0x0
315#define MX6Q_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x118 0x42c 0x000 0x1 0x0 315#define MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0
316#define MX6Q_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0 316#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x114 0x428 0x000 0x5 0x0
317#define MX6Q_PAD_EIM_DA1__GPIO3_IO01 0x118 0x42c 0x000 0x5 0x0 317#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x114 0x428 0x000 0x7 0x0
318#define MX6Q_PAD_EIM_DA1__SRC_BOOT_CFG01 0x118 0x42c 0x000 0x7 0x0 318#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x118 0x42c 0x000 0x0 0x0
319#define MX6Q_PAD_EIM_DA2__EIM_AD02 0x11c 0x430 0x000 0x0 0x0 319#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x118 0x42c 0x000 0x1 0x0
320#define MX6Q_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x11c 0x430 0x000 0x1 0x0 320#define MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0
321#define MX6Q_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0 321#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x118 0x42c 0x000 0x5 0x0
322#define MX6Q_PAD_EIM_DA2__GPIO3_IO02 0x11c 0x430 0x000 0x5 0x0 322#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x118 0x42c 0x000 0x7 0x0
323#define MX6Q_PAD_EIM_DA2__SRC_BOOT_CFG02 0x11c 0x430 0x000 0x7 0x0 323#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x11c 0x430 0x000 0x0 0x0
324#define MX6Q_PAD_EIM_DA3__EIM_AD03 0x120 0x434 0x000 0x0 0x0 324#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x11c 0x430 0x000 0x1 0x0
325#define MX6Q_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x120 0x434 0x000 0x1 0x0 325#define MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0
326#define MX6Q_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0 326#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x11c 0x430 0x000 0x5 0x0
327#define MX6Q_PAD_EIM_DA3__GPIO3_IO03 0x120 0x434 0x000 0x5 0x0 327#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x11c 0x430 0x000 0x7 0x0
328#define MX6Q_PAD_EIM_DA3__SRC_BOOT_CFG03 0x120 0x434 0x000 0x7 0x0 328#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x120 0x434 0x000 0x0 0x0
329#define MX6Q_PAD_EIM_DA4__EIM_AD04 0x124 0x438 0x000 0x0 0x0 329#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x120 0x434 0x000 0x1 0x0
330#define MX6Q_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x124 0x438 0x000 0x1 0x0 330#define MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0
331#define MX6Q_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0 331#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x120 0x434 0x000 0x5 0x0
332#define MX6Q_PAD_EIM_DA4__GPIO3_IO04 0x124 0x438 0x000 0x5 0x0 332#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x120 0x434 0x000 0x7 0x0
333#define MX6Q_PAD_EIM_DA4__SRC_BOOT_CFG04 0x124 0x438 0x000 0x7 0x0 333#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x124 0x438 0x000 0x0 0x0
334#define MX6Q_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0 334#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x124 0x438 0x000 0x1 0x0
335#define MX6Q_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0 335#define MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0
336#define MX6Q_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0 336#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x124 0x438 0x000 0x5 0x0
337#define MX6Q_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0 337#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x124 0x438 0x000 0x7 0x0
338#define MX6Q_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0 338#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0
339#define MX6Q_PAD_EIM_DA6__EIM_AD06 0x12c 0x440 0x000 0x0 0x0 339#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0
340#define MX6Q_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x12c 0x440 0x000 0x1 0x0 340#define MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0
341#define MX6Q_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0 341#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0
342#define MX6Q_PAD_EIM_DA6__GPIO3_IO06 0x12c 0x440 0x000 0x5 0x0 342#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0
343#define MX6Q_PAD_EIM_DA6__SRC_BOOT_CFG06 0x12c 0x440 0x000 0x7 0x0 343#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x12c 0x440 0x000 0x0 0x0
344#define MX6Q_PAD_EIM_DA7__EIM_AD07 0x130 0x444 0x000 0x0 0x0 344#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x12c 0x440 0x000 0x1 0x0
345#define MX6Q_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x130 0x444 0x000 0x1 0x0 345#define MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0
346#define MX6Q_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0 346#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x12c 0x440 0x000 0x5 0x0
347#define MX6Q_PAD_EIM_DA7__GPIO3_IO07 0x130 0x444 0x000 0x5 0x0 347#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x12c 0x440 0x000 0x7 0x0
348#define MX6Q_PAD_EIM_DA7__SRC_BOOT_CFG07 0x130 0x444 0x000 0x7 0x0 348#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x130 0x444 0x000 0x0 0x0
349#define MX6Q_PAD_EIM_DA8__EIM_AD08 0x134 0x448 0x000 0x0 0x0 349#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x130 0x444 0x000 0x1 0x0
350#define MX6Q_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x134 0x448 0x000 0x1 0x0 350#define MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0
351#define MX6Q_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0 351#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x130 0x444 0x000 0x5 0x0
352#define MX6Q_PAD_EIM_DA8__GPIO3_IO08 0x134 0x448 0x000 0x5 0x0 352#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x130 0x444 0x000 0x7 0x0
353#define MX6Q_PAD_EIM_DA8__SRC_BOOT_CFG08 0x134 0x448 0x000 0x7 0x0 353#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x134 0x448 0x000 0x0 0x0
354#define MX6Q_PAD_EIM_DA9__EIM_AD09 0x138 0x44c 0x000 0x0 0x0 354#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x134 0x448 0x000 0x1 0x0
355#define MX6Q_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x138 0x44c 0x000 0x1 0x0 355#define MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0
356#define MX6Q_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0 356#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x134 0x448 0x000 0x5 0x0
357#define MX6Q_PAD_EIM_DA9__GPIO3_IO09 0x138 0x44c 0x000 0x5 0x0 357#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x134 0x448 0x000 0x7 0x0
358#define MX6Q_PAD_EIM_DA9__SRC_BOOT_CFG09 0x138 0x44c 0x000 0x7 0x0 358#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x138 0x44c 0x000 0x0 0x0
359#define MX6Q_PAD_EIM_DA10__EIM_AD10 0x13c 0x450 0x000 0x0 0x0 359#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x138 0x44c 0x000 0x1 0x0
360#define MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 0x13c 0x450 0x000 0x1 0x0 360#define MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0
361#define MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1 361#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x138 0x44c 0x000 0x5 0x0
362#define MX6Q_PAD_EIM_DA10__GPIO3_IO10 0x13c 0x450 0x000 0x5 0x0 362#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x138 0x44c 0x000 0x7 0x0
363#define MX6Q_PAD_EIM_DA10__SRC_BOOT_CFG10 0x13c 0x450 0x000 0x7 0x0 363#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x13c 0x450 0x000 0x0 0x0
364#define MX6Q_PAD_EIM_DA11__EIM_AD11 0x140 0x454 0x000 0x0 0x0 364#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x13c 0x450 0x000 0x1 0x0
365#define MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN02 0x140 0x454 0x000 0x1 0x0 365#define MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1
366#define MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1 366#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x13c 0x450 0x000 0x5 0x0
367#define MX6Q_PAD_EIM_DA11__GPIO3_IO11 0x140 0x454 0x000 0x5 0x0 367#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x13c 0x450 0x000 0x7 0x0
368#define MX6Q_PAD_EIM_DA11__SRC_BOOT_CFG11 0x140 0x454 0x000 0x7 0x0 368#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x140 0x454 0x000 0x0 0x0
369#define MX6Q_PAD_EIM_DA12__EIM_AD12 0x144 0x458 0x000 0x0 0x0 369#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x140 0x454 0x000 0x1 0x0
370#define MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN03 0x144 0x458 0x000 0x1 0x0 370#define MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1
371#define MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1 371#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x140 0x454 0x000 0x5 0x0
372#define MX6Q_PAD_EIM_DA12__GPIO3_IO12 0x144 0x458 0x000 0x5 0x0 372#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x140 0x454 0x000 0x7 0x0
373#define MX6Q_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0 373#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x144 0x458 0x000 0x0 0x0
374#define MX6Q_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0 374#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x144 0x458 0x000 0x1 0x0
375#define MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0 375#define MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1
376#define MX6Q_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0 376#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x144 0x458 0x000 0x5 0x0
377#define MX6Q_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0 377#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0
378#define MX6Q_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0 378#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0
379#define MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0 379#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0
380#define MX6Q_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0 380#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0
381#define MX6Q_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0 381#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0
382#define MX6Q_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0 382#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0
383#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN01 0x150 0x464 0x000 0x1 0x0 383#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0
384#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0 384#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0
385#define MX6Q_PAD_EIM_DA15__GPIO3_IO15 0x150 0x464 0x000 0x5 0x0 385#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0
386#define MX6Q_PAD_EIM_DA15__SRC_BOOT_CFG15 0x150 0x464 0x000 0x7 0x0 386#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0
387#define MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0x154 0x468 0x000 0x0 0x0 387#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x150 0x464 0x000 0x1 0x0
388#define MX6Q_PAD_EIM_WAIT__EIM_DTACK_B 0x154 0x468 0x000 0x1 0x0 388#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0
389#define MX6Q_PAD_EIM_WAIT__GPIO5_IO00 0x154 0x468 0x000 0x5 0x0 389#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x150 0x464 0x000 0x5 0x0
390#define MX6Q_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x154 0x468 0x000 0x7 0x0 390#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x150 0x464 0x000 0x7 0x0
391#define MX6Q_PAD_EIM_BCLK__EIM_BCLK 0x158 0x46c 0x000 0x0 0x0 391#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x154 0x468 0x000 0x0 0x0
392#define MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x158 0x46c 0x000 0x1 0x0 392#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x154 0x468 0x000 0x1 0x0
393#define MX6Q_PAD_EIM_BCLK__GPIO6_IO31 0x158 0x46c 0x000 0x5 0x0 393#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x154 0x468 0x000 0x5 0x0
394#define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x15c 0x470 0x000 0x0 0x0 394#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x154 0x468 0x000 0x7 0x0
395#define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x15c 0x470 0x000 0x1 0x0 395#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x158 0x46c 0x000 0x0 0x0
396#define MX6Q_PAD_DI0_DISP_CLK__GPIO4_IO16 0x15c 0x470 0x000 0x5 0x0 396#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x158 0x46c 0x000 0x1 0x0
397#define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x160 0x474 0x000 0x0 0x0 397#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x158 0x46c 0x000 0x5 0x0
398#define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x160 0x474 0x000 0x1 0x0 398#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x15c 0x470 0x000 0x0 0x0
399#define MX6Q_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0 399#define MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x15c 0x470 0x000 0x1 0x0
400#define MX6Q_PAD_DI0_PIN15__GPIO4_IO17 0x160 0x474 0x000 0x5 0x0 400#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x15c 0x470 0x000 0x5 0x0
401#define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x164 0x478 0x000 0x0 0x0 401#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x160 0x474 0x000 0x0 0x0
402#define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x164 0x478 0x000 0x1 0x0 402#define MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x160 0x474 0x000 0x1 0x0
403#define MX6Q_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0 403#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0
404#define MX6Q_PAD_DI0_PIN2__GPIO4_IO18 0x164 0x478 0x000 0x5 0x0 404#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x160 0x474 0x000 0x5 0x0
405#define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x168 0x47c 0x000 0x0 0x0 405#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x164 0x478 0x000 0x0 0x0
406#define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x168 0x47c 0x000 0x1 0x0 406#define MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x164 0x478 0x000 0x1 0x0
407#define MX6Q_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0 407#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0
408#define MX6Q_PAD_DI0_PIN3__GPIO4_IO19 0x168 0x47c 0x000 0x5 0x0 408#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x164 0x478 0x000 0x5 0x0
409#define MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x16c 0x480 0x000 0x0 0x0 409#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x168 0x47c 0x000 0x0 0x0
410#define MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x16c 0x480 0x000 0x1 0x0 410#define MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x168 0x47c 0x000 0x1 0x0
411#define MX6Q_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0 411#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0
412#define MX6Q_PAD_DI0_PIN4__SD1_WP 0x16c 0x480 0x94c 0x3 0x0 412#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x168 0x47c 0x000 0x5 0x0
413#define MX6Q_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0 413#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x16c 0x480 0x000 0x0 0x0
414#define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x170 0x484 0x000 0x0 0x0 414#define MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x16c 0x480 0x000 0x1 0x0
415#define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x170 0x484 0x000 0x1 0x0 415#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0
416#define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0 416#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x16c 0x480 0x94c 0x3 0x0
417#define MX6Q_PAD_DISP0_DAT0__GPIO4_IO21 0x170 0x484 0x000 0x5 0x0 417#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0
418#define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x174 0x488 0x000 0x0 0x0 418#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x170 0x484 0x000 0x0 0x0
419#define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x174 0x488 0x000 0x1 0x0 419#define MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x170 0x484 0x000 0x1 0x0
420#define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0 420#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0
421#define MX6Q_PAD_DISP0_DAT1__GPIO4_IO22 0x174 0x488 0x000 0x5 0x0 421#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x170 0x484 0x000 0x5 0x0
422#define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x178 0x48c 0x000 0x0 0x0 422#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x174 0x488 0x000 0x0 0x0
423#define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x178 0x48c 0x000 0x1 0x0 423#define MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x174 0x488 0x000 0x1 0x0
424#define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0 424#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0
425#define MX6Q_PAD_DISP0_DAT2__GPIO4_IO23 0x178 0x48c 0x000 0x5 0x0 425#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x174 0x488 0x000 0x5 0x0
426#define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x17c 0x490 0x000 0x0 0x0 426#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x178 0x48c 0x000 0x0 0x0
427#define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x17c 0x490 0x000 0x1 0x0 427#define MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x178 0x48c 0x000 0x1 0x0
428#define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0 428#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0
429#define MX6Q_PAD_DISP0_DAT3__GPIO4_IO24 0x17c 0x490 0x000 0x5 0x0 429#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x178 0x48c 0x000 0x5 0x0
430#define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x180 0x494 0x000 0x0 0x0 430#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x17c 0x490 0x000 0x0 0x0
431#define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x180 0x494 0x000 0x1 0x0 431#define MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x17c 0x490 0x000 0x1 0x0
432#define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0 432#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0
433#define MX6Q_PAD_DISP0_DAT4__GPIO4_IO25 0x180 0x494 0x000 0x5 0x0 433#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x17c 0x490 0x000 0x5 0x0
434#define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x184 0x498 0x000 0x0 0x0 434#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x180 0x494 0x000 0x0 0x0
435#define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x184 0x498 0x000 0x1 0x0 435#define MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x180 0x494 0x000 0x1 0x0
436#define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0 436#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0
437#define MX6Q_PAD_DISP0_DAT5__AUD6_RXFS 0x184 0x498 0x000 0x3 0x0 437#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x180 0x494 0x000 0x5 0x0
438#define MX6Q_PAD_DISP0_DAT5__GPIO4_IO26 0x184 0x498 0x000 0x5 0x0 438#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x184 0x498 0x000 0x0 0x0
439#define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x188 0x49c 0x000 0x0 0x0 439#define MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x184 0x498 0x000 0x1 0x0
440#define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x188 0x49c 0x000 0x1 0x0 440#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0
441#define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0 441#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x184 0x498 0x000 0x3 0x0
442#define MX6Q_PAD_DISP0_DAT6__AUD6_RXC 0x188 0x49c 0x000 0x3 0x0 442#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x184 0x498 0x000 0x5 0x0
443#define MX6Q_PAD_DISP0_DAT6__GPIO4_IO27 0x188 0x49c 0x000 0x5 0x0 443#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x188 0x49c 0x000 0x0 0x0
444#define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x18c 0x4a0 0x000 0x0 0x0 444#define MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x188 0x49c 0x000 0x1 0x0
445#define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x18c 0x4a0 0x000 0x1 0x0 445#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0
446#define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0 446#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x188 0x49c 0x000 0x3 0x0
447#define MX6Q_PAD_DISP0_DAT7__GPIO4_IO28 0x18c 0x4a0 0x000 0x5 0x0 447#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x188 0x49c 0x000 0x5 0x0
448#define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x190 0x4a4 0x000 0x0 0x0 448#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x18c 0x4a0 0x000 0x0 0x0
449#define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x190 0x4a4 0x000 0x1 0x0 449#define MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x18c 0x4a0 0x000 0x1 0x0
450#define MX6Q_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0 450#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0
451#define MX6Q_PAD_DISP0_DAT8__WDOG1_B 0x190 0x4a4 0x000 0x3 0x0 451#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x18c 0x4a0 0x000 0x5 0x0
452#define MX6Q_PAD_DISP0_DAT8__GPIO4_IO29 0x190 0x4a4 0x000 0x5 0x0 452#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x190 0x4a4 0x000 0x0 0x0
453#define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x194 0x4a8 0x000 0x0 0x0 453#define MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x190 0x4a4 0x000 0x1 0x0
454#define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x194 0x4a8 0x000 0x1 0x0 454#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0
455#define MX6Q_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0 455#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x190 0x4a4 0x000 0x3 0x0
456#define MX6Q_PAD_DISP0_DAT9__WDOG2_B 0x194 0x4a8 0x000 0x3 0x0 456#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x190 0x4a4 0x000 0x5 0x0
457#define MX6Q_PAD_DISP0_DAT9__GPIO4_IO30 0x194 0x4a8 0x000 0x5 0x0 457#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x194 0x4a8 0x000 0x0 0x0
458#define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x198 0x4ac 0x000 0x0 0x0 458#define MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x194 0x4a8 0x000 0x1 0x0
459#define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x198 0x4ac 0x000 0x1 0x0 459#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0
460#define MX6Q_PAD_DISP0_DAT10__GPIO4_IO31 0x198 0x4ac 0x000 0x5 0x0 460#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x194 0x4a8 0x000 0x3 0x0
461#define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x19c 0x4b0 0x000 0x0 0x0 461#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x194 0x4a8 0x000 0x5 0x0
462#define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x19c 0x4b0 0x000 0x1 0x0 462#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x198 0x4ac 0x000 0x0 0x0
463#define MX6Q_PAD_DISP0_DAT11__GPIO5_IO05 0x19c 0x4b0 0x000 0x5 0x0 463#define MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x198 0x4ac 0x000 0x1 0x0
464#define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x1a0 0x4b4 0x000 0x0 0x0 464#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x198 0x4ac 0x000 0x5 0x0
465#define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x1a0 0x4b4 0x000 0x1 0x0 465#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x19c 0x4b0 0x000 0x0 0x0
466#define MX6Q_PAD_DISP0_DAT12__GPIO5_IO06 0x1a0 0x4b4 0x000 0x5 0x0 466#define MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x19c 0x4b0 0x000 0x1 0x0
467#define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x1a4 0x4b8 0x000 0x0 0x0 467#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x19c 0x4b0 0x000 0x5 0x0
468#define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x1a4 0x4b8 0x000 0x1 0x0 468#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x1a0 0x4b4 0x000 0x0 0x0
469#define MX6Q_PAD_DISP0_DAT13__AUD5_RXFS 0x1a4 0x4b8 0x7d8 0x3 0x1 469#define MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x1a0 0x4b4 0x000 0x1 0x0
470#define MX6Q_PAD_DISP0_DAT13__GPIO5_IO07 0x1a4 0x4b8 0x000 0x5 0x0 470#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1a0 0x4b4 0x000 0x5 0x0
471#define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x1a8 0x4bc 0x000 0x0 0x0 471#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x1a4 0x4b8 0x000 0x0 0x0
472#define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x1a8 0x4bc 0x000 0x1 0x0 472#define MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x1a4 0x4b8 0x000 0x1 0x0
473#define MX6Q_PAD_DISP0_DAT14__AUD5_RXC 0x1a8 0x4bc 0x7d4 0x3 0x1 473#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x1a4 0x4b8 0x7d8 0x3 0x1
474#define MX6Q_PAD_DISP0_DAT14__GPIO5_IO08 0x1a8 0x4bc 0x000 0x5 0x0 474#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1a4 0x4b8 0x000 0x5 0x0
475#define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x1ac 0x4c0 0x000 0x0 0x0 475#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x1a8 0x4bc 0x000 0x0 0x0
476#define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x1ac 0x4c0 0x000 0x1 0x0 476#define MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x1a8 0x4bc 0x000 0x1 0x0
477#define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1 477#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x1a8 0x4bc 0x7d4 0x3 0x1
478#define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1 478#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1a8 0x4bc 0x000 0x5 0x0
479#define MX6Q_PAD_DISP0_DAT15__GPIO5_IO09 0x1ac 0x4c0 0x000 0x5 0x0 479#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x1ac 0x4c0 0x000 0x0 0x0
480#define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x1b0 0x4c4 0x000 0x0 0x0 480#define MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x1ac 0x4c0 0x000 0x1 0x0
481#define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x1b0 0x4c4 0x000 0x1 0x0 481#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1
482#define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1 482#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1
483#define MX6Q_PAD_DISP0_DAT16__AUD5_TXC 0x1b0 0x4c4 0x7dc 0x3 0x0 483#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1ac 0x4c0 0x000 0x5 0x0
484#define MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x1b0 0x4c4 0x90c 0x4 0x0 484#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x1b0 0x4c4 0x000 0x0 0x0
485#define MX6Q_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0 0x4c4 0x000 0x5 0x0 485#define MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x1b0 0x4c4 0x000 0x1 0x0
486#define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x1b4 0x4c8 0x000 0x0 0x0 486#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1
487#define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x1b4 0x4c8 0x000 0x1 0x0 487#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x1b0 0x4c4 0x7dc 0x3 0x0
488#define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1 488#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x1b0 0x4c4 0x90c 0x4 0x0
489#define MX6Q_PAD_DISP0_DAT17__AUD5_TXD 0x1b4 0x4c8 0x7d0 0x3 0x0 489#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0 0x4c4 0x000 0x5 0x0
490#define MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x1b4 0x4c8 0x910 0x4 0x0 490#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x1b4 0x4c8 0x000 0x0 0x0
491#define MX6Q_PAD_DISP0_DAT17__GPIO5_IO11 0x1b4 0x4c8 0x000 0x5 0x0 491#define MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x1b4 0x4c8 0x000 0x1 0x0
492#define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x1b8 0x4cc 0x000 0x0 0x0 492#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1
493#define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x1b8 0x4cc 0x000 0x1 0x0 493#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x1b4 0x4c8 0x7d0 0x3 0x0
494#define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1 494#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x1b4 0x4c8 0x910 0x4 0x0
495#define MX6Q_PAD_DISP0_DAT18__AUD5_TXFS 0x1b8 0x4cc 0x7e0 0x3 0x0 495#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b4 0x4c8 0x000 0x5 0x0
496#define MX6Q_PAD_DISP0_DAT18__AUD4_RXFS 0x1b8 0x4cc 0x7c0 0x4 0x0 496#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x1b8 0x4cc 0x000 0x0 0x0
497#define MX6Q_PAD_DISP0_DAT18__GPIO5_IO12 0x1b8 0x4cc 0x000 0x5 0x0 497#define MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x1b8 0x4cc 0x000 0x1 0x0
498#define MX6Q_PAD_DISP0_DAT18__EIM_CS2_B 0x1b8 0x4cc 0x000 0x7 0x0 498#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1
499#define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x1bc 0x4d0 0x000 0x0 0x0 499#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x1b8 0x4cc 0x7e0 0x3 0x0
500#define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x1bc 0x4d0 0x000 0x1 0x0 500#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x1b8 0x4cc 0x7c0 0x4 0x0
501#define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1 501#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b8 0x4cc 0x000 0x5 0x0
502#define MX6Q_PAD_DISP0_DAT19__AUD5_RXD 0x1bc 0x4d0 0x7cc 0x3 0x0 502#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x1b8 0x4cc 0x000 0x7 0x0
503#define MX6Q_PAD_DISP0_DAT19__AUD4_RXC 0x1bc 0x4d0 0x7bc 0x4 0x0 503#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x1bc 0x4d0 0x000 0x0 0x0
504#define MX6Q_PAD_DISP0_DAT19__GPIO5_IO13 0x1bc 0x4d0 0x000 0x5 0x0 504#define MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x1bc 0x4d0 0x000 0x1 0x0
505#define MX6Q_PAD_DISP0_DAT19__EIM_CS3_B 0x1bc 0x4d0 0x000 0x7 0x0 505#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1
506#define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x1c0 0x4d4 0x000 0x0 0x0 506#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x1bc 0x4d0 0x7cc 0x3 0x0
507#define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x1c0 0x4d4 0x000 0x1 0x0 507#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x1bc 0x4d0 0x7bc 0x4 0x0
508#define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1 508#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1bc 0x4d0 0x000 0x5 0x0
509#define MX6Q_PAD_DISP0_DAT20__AUD4_TXC 0x1c0 0x4d4 0x7c4 0x3 0x0 509#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x1bc 0x4d0 0x000 0x7 0x0
510#define MX6Q_PAD_DISP0_DAT20__GPIO5_IO14 0x1c0 0x4d4 0x000 0x5 0x0 510#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x1c0 0x4d4 0x000 0x0 0x0
511#define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x1c4 0x4d8 0x000 0x0 0x0 511#define MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x1c0 0x4d4 0x000 0x1 0x0
512#define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x1c4 0x4d8 0x000 0x1 0x0 512#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1
513#define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1 513#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x1c0 0x4d4 0x7c4 0x3 0x0
514#define MX6Q_PAD_DISP0_DAT21__AUD4_TXD 0x1c4 0x4d8 0x7b8 0x3 0x1 514#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1c0 0x4d4 0x000 0x5 0x0
515#define MX6Q_PAD_DISP0_DAT21__GPIO5_IO15 0x1c4 0x4d8 0x000 0x5 0x0 515#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x1c4 0x4d8 0x000 0x0 0x0
516#define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x1c8 0x4dc 0x000 0x0 0x0 516#define MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x1c4 0x4d8 0x000 0x1 0x0
517#define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x1c8 0x4dc 0x000 0x1 0x0 517#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1
518#define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1 518#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x1c4 0x4d8 0x7b8 0x3 0x1
519#define MX6Q_PAD_DISP0_DAT22__AUD4_TXFS 0x1c8 0x4dc 0x7c8 0x3 0x1 519#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1c4 0x4d8 0x000 0x5 0x0
520#define MX6Q_PAD_DISP0_DAT22__GPIO5_IO16 0x1c8 0x4dc 0x000 0x5 0x0 520#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x1c8 0x4dc 0x000 0x0 0x0
521#define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x1cc 0x4e0 0x000 0x0 0x0 521#define MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x1c8 0x4dc 0x000 0x1 0x0
522#define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x1cc 0x4e0 0x000 0x1 0x0 522#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1
523#define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1 523#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x1c8 0x4dc 0x7c8 0x3 0x1
524#define MX6Q_PAD_DISP0_DAT23__AUD4_RXD 0x1cc 0x4e0 0x7b4 0x3 0x1 524#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1c8 0x4dc 0x000 0x5 0x0
525#define MX6Q_PAD_DISP0_DAT23__GPIO5_IO17 0x1cc 0x4e0 0x000 0x5 0x0 525#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x1cc 0x4e0 0x000 0x0 0x0
526#define MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1d0 0x4e4 0x840 0x1 0x0 526#define MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x1cc 0x4e0 0x000 0x1 0x0
527#define MX6Q_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0 527#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1
528#define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1d0 0x4e4 0x000 0x4 0x0 528#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x1cc 0x4e0 0x7b4 0x3 0x1
529#define MX6Q_PAD_ENET_MDIO__GPIO1_IO22 0x1d0 0x4e4 0x000 0x5 0x0 529#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1cc 0x4e0 0x000 0x5 0x0
530#define MX6Q_PAD_ENET_MDIO__SPDIF_LOCK 0x1d0 0x4e4 0x000 0x6 0x0 530#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1d0 0x4e4 0x840 0x1 0x0
531#define MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1d4 0x4e8 0x000 0x1 0x0 531#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0
532#define MX6Q_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0 532#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1d0 0x4e4 0x000 0x4 0x0
533#define MX6Q_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0 533#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1d0 0x4e4 0x000 0x5 0x0
534#define MX6Q_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0 534#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1d0 0x4e4 0x000 0x6 0x0
535#define MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x000 0x0 0x0 535#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1d4 0x4e8 0x000 0x1 0x0
536#define MX6Q_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0 536#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0
537#define MX6Q_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0 537#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0
538#define MX6Q_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1 538#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0
539#define MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0 539#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x000 0x0 0x0
540#define MX6Q_PAD_ENET_RX_ER__GPIO1_IO24 0x1d8 0x4ec 0x000 0x5 0x0 540#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0
541#define MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN 0x1dc 0x4f0 0x858 0x1 0x1 541#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0
542#define MX6Q_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0 542#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1
543#define MX6Q_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1dc 0x4f0 0x918 0x3 0x1 543#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0
544#define MX6Q_PAD_ENET_CRS_DV__GPIO1_IO25 0x1dc 0x4f0 0x000 0x5 0x0 544#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1d8 0x4ec 0x000 0x5 0x0
545#define MX6Q_PAD_ENET_RXD1__MLB_SIG 0x1e0 0x4f4 0x908 0x0 0x0 545#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1dc 0x4f0 0x858 0x1 0x1
546#define MX6Q_PAD_ENET_RXD1__ENET_RX_DATA1 0x1e0 0x4f4 0x84c 0x1 0x1 546#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0
547#define MX6Q_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0 547#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1dc 0x4f0 0x918 0x3 0x1
548#define MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0 548#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1dc 0x4f0 0x000 0x5 0x0
549#define MX6Q_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0 549#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1e0 0x4f4 0x908 0x0 0x0
550#define MX6Q_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1 550#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1e0 0x4f4 0x84c 0x1 0x1
551#define MX6Q_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0 551#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0
552#define MX6Q_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0 552#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0
553#define MX6Q_PAD_ENET_RXD0__GPIO1_IO27 0x1e4 0x4f8 0x000 0x5 0x0 553#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0
554#define MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1e8 0x4fc 0x000 0x1 0x0 554#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1
555#define MX6Q_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0 555#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0
556#define MX6Q_PAD_ENET_TX_EN__GPIO1_IO28 0x1e8 0x4fc 0x000 0x5 0x0 556#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0
557#define MX6Q_PAD_ENET_TXD1__MLB_CLK 0x1ec 0x500 0x900 0x0 0x0 557#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1e4 0x4f8 0x000 0x5 0x0
558#define MX6Q_PAD_ENET_TXD1__ENET_TX_DATA1 0x1ec 0x500 0x000 0x1 0x0 558#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1e8 0x4fc 0x000 0x1 0x0
559#define MX6Q_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0 559#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0
560#define MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x1ec 0x500 0x000 0x4 0x0 560#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1e8 0x4fc 0x000 0x5 0x0
561#define MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x1ec 0x500 0x000 0x5 0x0 561#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x1ec 0x500 0x900 0x0 0x0
562#define MX6Q_PAD_ENET_TXD0__ENET_TX_DATA0 0x1f0 0x504 0x000 0x1 0x0 562#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1ec 0x500 0x000 0x1 0x0
563#define MX6Q_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0 563#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0
564#define MX6Q_PAD_ENET_TXD0__GPIO1_IO30 0x1f0 0x504 0x000 0x5 0x0 564#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x1ec 0x500 0x000 0x4 0x0
565#define MX6Q_PAD_ENET_MDC__MLB_DATA 0x1f4 0x508 0x904 0x0 0x0 565#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1ec 0x500 0x000 0x5 0x0
566#define MX6Q_PAD_ENET_MDC__ENET_MDC 0x1f4 0x508 0x000 0x1 0x0 566#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1f0 0x504 0x000 0x1 0x0
567#define MX6Q_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0 567#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0
568#define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1f4 0x508 0x000 0x4 0x0 568#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1f0 0x504 0x000 0x5 0x0
569#define MX6Q_PAD_ENET_MDC__GPIO1_IO31 0x1f4 0x508 0x000 0x5 0x0 569#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1f4 0x508 0x904 0x0 0x0
570#define MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2 570#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1f4 0x508 0x000 0x1 0x0
571#define MX6Q_PAD_KEY_COL0__ENET_RX_DATA3 0x1f8 0x5c8 0x854 0x1 0x1 571#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0
572#define MX6Q_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1 572#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1f4 0x508 0x000 0x4 0x0
573#define MX6Q_PAD_KEY_COL0__KEY_COL0 0x1f8 0x5c8 0x000 0x3 0x0 573#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f4 0x508 0x000 0x5 0x0
574#define MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1f8 0x5c8 0x000 0x4 0x0 574#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2
575#define MX6Q_PAD_KEY_COL0__UART4_RX_DATA 0x1f8 0x5c8 0x938 0x4 0x0 575#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1f8 0x5c8 0x854 0x1 0x1
576#define MX6Q_PAD_KEY_COL0__GPIO4_IO06 0x1f8 0x5c8 0x000 0x5 0x0 576#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1
577#define MX6Q_PAD_KEY_COL0__DCIC1_OUT 0x1f8 0x5c8 0x000 0x6 0x0 577#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x1f8 0x5c8 0x000 0x3 0x0
578#define MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2 578#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1f8 0x5c8 0x000 0x4 0x0
579#define MX6Q_PAD_KEY_ROW0__ENET_TX_DATA3 0x1fc 0x5cc 0x000 0x1 0x0 579#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1f8 0x5c8 0x938 0x4 0x0
580#define MX6Q_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1 580#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1f8 0x5c8 0x000 0x5 0x0
581#define MX6Q_PAD_KEY_ROW0__KEY_ROW0 0x1fc 0x5cc 0x000 0x3 0x0 581#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x1f8 0x5c8 0x000 0x6 0x0
582#define MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1fc 0x5cc 0x938 0x4 0x1 582#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2
583#define MX6Q_PAD_KEY_ROW0__UART4_TX_DATA 0x1fc 0x5cc 0x000 0x4 0x0 583#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1fc 0x5cc 0x000 0x1 0x0
584#define MX6Q_PAD_KEY_ROW0__GPIO4_IO07 0x1fc 0x5cc 0x000 0x5 0x0 584#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1
585#define MX6Q_PAD_KEY_ROW0__DCIC2_OUT 0x1fc 0x5cc 0x000 0x6 0x0 585#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x1fc 0x5cc 0x000 0x3 0x0
586#define MX6Q_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2 586#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1fc 0x5cc 0x938 0x4 0x1
587#define MX6Q_PAD_KEY_COL1__ENET_MDIO 0x200 0x5d0 0x840 0x1 0x1 587#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1fc 0x5cc 0x000 0x4 0x0
588#define MX6Q_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1 588#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1fc 0x5cc 0x000 0x5 0x0
589#define MX6Q_PAD_KEY_COL1__KEY_COL1 0x200 0x5d0 0x000 0x3 0x0 589#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x1fc 0x5cc 0x000 0x6 0x0
590#define MX6Q_PAD_KEY_COL1__UART5_TX_DATA 0x200 0x5d0 0x000 0x4 0x0 590#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2
591#define MX6Q_PAD_KEY_COL1__UART5_RX_DATA 0x200 0x5d0 0x940 0x4 0x0 591#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x200 0x5d0 0x840 0x1 0x1
592#define MX6Q_PAD_KEY_COL1__GPIO4_IO08 0x200 0x5d0 0x000 0x5 0x0 592#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1
593#define MX6Q_PAD_KEY_COL1__SD1_VSELECT 0x200 0x5d0 0x000 0x6 0x0 593#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x200 0x5d0 0x000 0x3 0x0
594#define MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2 594#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x200 0x5d0 0x000 0x4 0x0
595#define MX6Q_PAD_KEY_ROW1__ENET_COL 0x204 0x5d4 0x000 0x1 0x0 595#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x200 0x5d0 0x940 0x4 0x0
596#define MX6Q_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1 596#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x200 0x5d0 0x000 0x5 0x0
597#define MX6Q_PAD_KEY_ROW1__KEY_ROW1 0x204 0x5d4 0x000 0x3 0x0 597#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x200 0x5d0 0x000 0x6 0x0
598#define MX6Q_PAD_KEY_ROW1__UART5_RX_DATA 0x204 0x5d4 0x940 0x4 0x1 598#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2
599#define MX6Q_PAD_KEY_ROW1__UART5_TX_DATA 0x204 0x5d4 0x000 0x4 0x0 599#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x204 0x5d4 0x000 0x1 0x0
600#define MX6Q_PAD_KEY_ROW1__GPIO4_IO09 0x204 0x5d4 0x000 0x5 0x0 600#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1
601#define MX6Q_PAD_KEY_ROW1__SD2_VSELECT 0x204 0x5d4 0x000 0x6 0x0 601#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x204 0x5d4 0x000 0x3 0x0
602#define MX6Q_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2 602#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x204 0x5d4 0x940 0x4 0x1
603#define MX6Q_PAD_KEY_COL2__ENET_RX_DATA2 0x208 0x5d8 0x850 0x1 0x1 603#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x204 0x5d4 0x000 0x4 0x0
604#define MX6Q_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0 604#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x204 0x5d4 0x000 0x5 0x0
605#define MX6Q_PAD_KEY_COL2__KEY_COL2 0x208 0x5d8 0x000 0x3 0x0 605#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x204 0x5d4 0x000 0x6 0x0
606#define MX6Q_PAD_KEY_COL2__ENET_MDC 0x208 0x5d8 0x000 0x4 0x0 606#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2
607#define MX6Q_PAD_KEY_COL2__GPIO4_IO10 0x208 0x5d8 0x000 0x5 0x0 607#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x208 0x5d8 0x850 0x1 0x1
608#define MX6Q_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x208 0x5d8 0x000 0x6 0x0 608#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0
609#define MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 0x20c 0x5dc 0x808 0x0 0x1 609#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x208 0x5d8 0x000 0x3 0x0
610#define MX6Q_PAD_KEY_ROW2__ENET_TX_DATA2 0x20c 0x5dc 0x000 0x1 0x0 610#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x208 0x5d8 0x000 0x4 0x0
611#define MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0 611#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x208 0x5d8 0x000 0x5 0x0
612#define MX6Q_PAD_KEY_ROW2__KEY_ROW2 0x20c 0x5dc 0x000 0x3 0x0 612#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x208 0x5d8 0x000 0x6 0x0
613#define MX6Q_PAD_KEY_ROW2__SD2_VSELECT 0x20c 0x5dc 0x000 0x4 0x0 613#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x20c 0x5dc 0x808 0x0 0x1
614#define MX6Q_PAD_KEY_ROW2__GPIO4_IO11 0x20c 0x5dc 0x000 0x5 0x0 614#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x20c 0x5dc 0x000 0x1 0x0
615#define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x20c 0x5dc 0x88c 0x6 0x1 615#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0
616#define MX6Q_PAD_KEY_COL3__ECSPI1_SS3 0x210 0x5e0 0x80c 0x0 0x1 616#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x20c 0x5dc 0x000 0x3 0x0
617#define MX6Q_PAD_KEY_COL3__ENET_CRS 0x210 0x5e0 0x000 0x1 0x0 617#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x20c 0x5dc 0x000 0x4 0x0
618#define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1 618#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x20c 0x5dc 0x000 0x5 0x0
619#define MX6Q_PAD_KEY_COL3__KEY_COL3 0x210 0x5e0 0x000 0x3 0x0 619#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x20c 0x5dc 0x88c 0x6 0x1
620#define MX6Q_PAD_KEY_COL3__I2C2_SCL 0x210 0x5e0 0x8a0 0x4 0x1 620#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x210 0x5e0 0x80c 0x0 0x1
621#define MX6Q_PAD_KEY_COL3__GPIO4_IO12 0x210 0x5e0 0x000 0x5 0x0 621#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x210 0x5e0 0x000 0x1 0x0
622#define MX6Q_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2 622#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1
623#define MX6Q_PAD_KEY_ROW3__ASRC_EXT_CLK 0x214 0x5e4 0x7b0 0x1 0x0 623#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x210 0x5e0 0x000 0x3 0x0
624#define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1 624#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x210 0x5e0 0x8a0 0x4 0x1
625#define MX6Q_PAD_KEY_ROW3__KEY_ROW3 0x214 0x5e4 0x000 0x3 0x0 625#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x210 0x5e0 0x000 0x5 0x0
626#define MX6Q_PAD_KEY_ROW3__I2C2_SDA 0x214 0x5e4 0x8a4 0x4 0x1 626#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2
627#define MX6Q_PAD_KEY_ROW3__GPIO4_IO13 0x214 0x5e4 0x000 0x5 0x0 627#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x214 0x5e4 0x7b0 0x1 0x0
628#define MX6Q_PAD_KEY_ROW3__SD1_VSELECT 0x214 0x5e4 0x000 0x6 0x0 628#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1
629#define MX6Q_PAD_KEY_COL4__FLEXCAN2_TX 0x218 0x5e8 0x000 0x0 0x0 629#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x214 0x5e4 0x000 0x3 0x0
630#define MX6Q_PAD_KEY_COL4__IPU1_SISG4 0x218 0x5e8 0x000 0x1 0x0 630#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x214 0x5e4 0x8a4 0x4 0x1
631#define MX6Q_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1 631#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x214 0x5e4 0x000 0x5 0x0
632#define MX6Q_PAD_KEY_COL4__KEY_COL4 0x218 0x5e8 0x000 0x3 0x0 632#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x214 0x5e4 0x000 0x6 0x0
633#define MX6Q_PAD_KEY_COL4__UART5_RTS_B 0x218 0x5e8 0x93c 0x4 0x0 633#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x218 0x5e8 0x000 0x0 0x0
634#define MX6Q_PAD_KEY_COL4__UART5_CTS_B 0x218 0x5e8 0x000 0x4 0x0 634#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x218 0x5e8 0x000 0x1 0x0
635#define MX6Q_PAD_KEY_COL4__GPIO4_IO14 0x218 0x5e8 0x000 0x5 0x0 635#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1
636#define MX6Q_PAD_KEY_ROW4__FLEXCAN2_RX 0x21c 0x5ec 0x7e8 0x0 0x0 636#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x218 0x5e8 0x000 0x3 0x0
637#define MX6Q_PAD_KEY_ROW4__IPU1_SISG5 0x21c 0x5ec 0x000 0x1 0x0 637#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x218 0x5e8 0x93c 0x4 0x0
638#define MX6Q_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0 638#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x218 0x5e8 0x000 0x4 0x0
639#define MX6Q_PAD_KEY_ROW4__KEY_ROW4 0x21c 0x5ec 0x000 0x3 0x0 639#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x218 0x5e8 0x000 0x5 0x0
640#define MX6Q_PAD_KEY_ROW4__UART5_CTS_B 0x21c 0x5ec 0x000 0x4 0x0 640#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x21c 0x5ec 0x7e8 0x0 0x0
641#define MX6Q_PAD_KEY_ROW4__UART5_RTS_B 0x21c 0x5ec 0x93c 0x4 0x1 641#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x21c 0x5ec 0x000 0x1 0x0
642#define MX6Q_PAD_KEY_ROW4__GPIO4_IO15 0x21c 0x5ec 0x000 0x5 0x0 642#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0
643#define MX6Q_PAD_GPIO_0__CCM_CLKO1 0x220 0x5f0 0x000 0x0 0x0 643#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x21c 0x5ec 0x000 0x3 0x0
644#define MX6Q_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0 644#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x21c 0x5ec 0x000 0x4 0x0
645#define MX6Q_PAD_GPIO_0__ASRC_EXT_CLK 0x220 0x5f0 0x7b0 0x3 0x1 645#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x21c 0x5ec 0x93c 0x4 0x1
646#define MX6Q_PAD_GPIO_0__EPIT1_OUT 0x220 0x5f0 0x000 0x4 0x0 646#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x21c 0x5ec 0x000 0x5 0x0
647#define MX6Q_PAD_GPIO_0__GPIO1_IO00 0x220 0x5f0 0x000 0x5 0x0 647#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x220 0x5f0 0x000 0x0 0x0
648#define MX6Q_PAD_GPIO_0__USB_H1_PWR 0x220 0x5f0 0x000 0x6 0x0 648#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0
649#define MX6Q_PAD_GPIO_0__SNVS_VIO_5 0x220 0x5f0 0x000 0x7 0x0 649#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x220 0x5f0 0x7b0 0x3 0x1
650#define MX6Q_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1 650#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x220 0x5f0 0x000 0x4 0x0
651#define MX6Q_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0 651#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x220 0x5f0 0x000 0x5 0x0
652#define MX6Q_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0 652#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x220 0x5f0 0x000 0x6 0x0
653#define MX6Q_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x000 0x3 0x0 653#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x220 0x5f0 0x000 0x7 0x0
654#define MX6Q_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0 654#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1
655#define MX6Q_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0 655#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0
656#define MX6Q_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0 656#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0
657#define MX6Q_PAD_GPIO_9__ESAI_RX_FS 0x228 0x5f8 0x85c 0x0 0x1 657#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x000 0x3 0x0
658#define MX6Q_PAD_GPIO_9__WDOG1_B 0x228 0x5f8 0x000 0x1 0x0 658#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0
659#define MX6Q_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0 659#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0
660#define MX6Q_PAD_GPIO_9__CCM_REF_EN_B 0x228 0x5f8 0x000 0x3 0x0 660#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0
661#define MX6Q_PAD_GPIO_9__PWM1_OUT 0x228 0x5f8 0x000 0x4 0x0 661#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x228 0x5f8 0x85c 0x0 0x1
662#define MX6Q_PAD_GPIO_9__GPIO1_IO09 0x228 0x5f8 0x000 0x5 0x0 662#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x228 0x5f8 0x000 0x1 0x0
663#define MX6Q_PAD_GPIO_9__SD1_WP 0x228 0x5f8 0x94c 0x6 0x1 663#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0
664#define MX6Q_PAD_GPIO_3__ESAI_RX_HF_CLK 0x22c 0x5fc 0x864 0x0 0x1 664#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x228 0x5f8 0x000 0x3 0x0
665#define MX6Q_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1 665#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x228 0x5f8 0x000 0x4 0x0
666#define MX6Q_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x22c 0x5fc 0x000 0x3 0x0 666#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x228 0x5f8 0x000 0x5 0x0
667#define MX6Q_PAD_GPIO_3__CCM_CLKO2 0x22c 0x5fc 0x000 0x4 0x0 667#define MX6QDL_PAD_GPIO_9__SD1_WP 0x228 0x5f8 0x94c 0x6 0x1
668#define MX6Q_PAD_GPIO_3__GPIO1_IO03 0x22c 0x5fc 0x000 0x5 0x0 668#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x22c 0x5fc 0x864 0x0 0x1
669#define MX6Q_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1 669#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1
670#define MX6Q_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1 670#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x22c 0x5fc 0x000 0x3 0x0
671#define MX6Q_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1 671#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x22c 0x5fc 0x000 0x4 0x0
672#define MX6Q_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1 672#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x22c 0x5fc 0x000 0x5 0x0
673#define MX6Q_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0 673#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1
674#define MX6Q_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0 674#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1
675#define MX6Q_PAD_GPIO_6__MLB_SIG 0x230 0x600 0x908 0x7 0x1 675#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1
676#define MX6Q_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1 676#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1
677#define MX6Q_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1 677#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0
678#define MX6Q_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0 678#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0
679#define MX6Q_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0 679#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x230 0x600 0x908 0x7 0x1
680#define MX6Q_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1 680#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1
681#define MX6Q_PAD_GPIO_4__ESAI_TX_HF_CLK 0x238 0x608 0x868 0x0 0x1 681#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1
682#define MX6Q_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1 682#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0
683#define MX6Q_PAD_GPIO_4__GPIO1_IO04 0x238 0x608 0x000 0x5 0x0 683#define MX6QDL_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0
684#define MX6Q_PAD_GPIO_4__SD2_CD_B 0x238 0x608 0x000 0x6 0x0 684#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1
685#define MX6Q_PAD_GPIO_5__ESAI_TX2_RX3 0x23c 0x60c 0x87c 0x0 0x1 685#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x238 0x608 0x868 0x0 0x1
686#define MX6Q_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1 686#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1
687#define MX6Q_PAD_GPIO_5__CCM_CLKO1 0x23c 0x60c 0x000 0x3 0x0 687#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x238 0x608 0x000 0x5 0x0
688#define MX6Q_PAD_GPIO_5__GPIO1_IO05 0x23c 0x60c 0x000 0x5 0x0 688#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x238 0x608 0x000 0x6 0x0
689#define MX6Q_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2 689#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x23c 0x60c 0x87c 0x0 0x1
690#define MX6Q_PAD_GPIO_5__ARM_EVENTI 0x23c 0x60c 0x000 0x7 0x0 690#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1
691#define MX6Q_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1 691#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x23c 0x60c 0x000 0x3 0x0
692#define MX6Q_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0 692#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x23c 0x60c 0x000 0x5 0x0
693#define MX6Q_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0 693#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2
694#define MX6Q_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0 694#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x23c 0x60c 0x000 0x7 0x0
695#define MX6Q_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0 695#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1
696#define MX6Q_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2 696#define MX6QDL_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0
697#define MX6Q_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0 697#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0
698#define MX6Q_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0 698#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0
699#define MX6Q_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0 699#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0
700#define MX6Q_PAD_GPIO_8__ESAI_TX5_RX0 0x244 0x614 0x888 0x0 0x1 700#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2
701#define MX6Q_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x244 0x614 0x000 0x1 0x0 701#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0
702#define MX6Q_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0 702#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0
703#define MX6Q_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1 703#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0
704#define MX6Q_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3 704#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x244 0x614 0x888 0x0 0x1
705#define MX6Q_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0 705#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x244 0x614 0x000 0x1 0x0
706#define MX6Q_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0 706#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0
707#define MX6Q_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0 707#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1
708#define MX6Q_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0 708#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3
709#define MX6Q_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1 709#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0
710#define MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0 710#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0
711#define MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1 711#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0
712#define MX6Q_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0 712#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0
713#define MX6Q_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3 713#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1
714#define MX6Q_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0 714#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0
715#define MX6Q_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2 715#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1
716#define MX6Q_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0 716#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0
717#define MX6Q_PAD_GPIO_17__ESAI_TX0 0x24c 0x61c 0x874 0x0 0x0 717#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3
718#define MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x24c 0x61c 0x000 0x1 0x0 718#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0
719#define MX6Q_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1 719#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2
720#define MX6Q_PAD_GPIO_17__SDMA_EXT_EVENT0 0x24c 0x61c 0x90c 0x3 0x1 720#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0
721#define MX6Q_PAD_GPIO_17__SPDIF_OUT 0x24c 0x61c 0x000 0x4 0x0 721#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x24c 0x61c 0x874 0x0 0x0
722#define MX6Q_PAD_GPIO_17__GPIO7_IO12 0x24c 0x61c 0x000 0x5 0x0 722#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x24c 0x61c 0x000 0x1 0x0
723#define MX6Q_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0 723#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1
724#define MX6Q_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1 724#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x24c 0x61c 0x90c 0x3 0x1
725#define MX6Q_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0 725#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x24c 0x61c 0x000 0x4 0x0
726#define MX6Q_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1 726#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x24c 0x61c 0x000 0x5 0x0
727#define MX6Q_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2 727#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0
728#define MX6Q_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0 728#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1
729#define MX6Q_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0 729#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0
730#define MX6Q_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1 730#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1
731#define MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0 731#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2
732#define MX6Q_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0 732#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0
733#define MX6Q_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0 733#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0
734#define MX6Q_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0 734#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1
735#define MX6Q_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0 735#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0
736#define MX6Q_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0 736#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0
737#define MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x258 0x628 0x000 0x0 0x0 737#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0
738#define MX6Q_PAD_CSI0_PIXCLK__GPIO5_IO18 0x258 0x628 0x000 0x5 0x0 738#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0
739#define MX6Q_PAD_CSI0_PIXCLK__ARM_EVENTO 0x258 0x628 0x000 0x7 0x0 739#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0
740#define MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x25c 0x62c 0x000 0x0 0x0 740#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0
741#define MX6Q_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0 741#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x258 0x628 0x000 0x0 0x0
742#define MX6Q_PAD_CSI0_MCLK__GPIO5_IO19 0x25c 0x62c 0x000 0x5 0x0 742#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x258 0x628 0x000 0x5 0x0
743#define MX6Q_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x25c 0x62c 0x000 0x7 0x0 743#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x258 0x628 0x000 0x7 0x0
744#define MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x260 0x630 0x000 0x0 0x0 744#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x25c 0x62c 0x000 0x0 0x0
745#define MX6Q_PAD_CSI0_DATA_EN__EIM_DATA00 0x260 0x630 0x000 0x1 0x0 745#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0
746#define MX6Q_PAD_CSI0_DATA_EN__GPIO5_IO20 0x260 0x630 0x000 0x5 0x0 746#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x25c 0x62c 0x000 0x5 0x0
747#define MX6Q_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x260 0x630 0x000 0x7 0x0 747#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x25c 0x62c 0x000 0x7 0x0
748#define MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x264 0x634 0x000 0x0 0x0 748#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x260 0x630 0x000 0x0 0x0
749#define MX6Q_PAD_CSI0_VSYNC__EIM_DATA01 0x264 0x634 0x000 0x1 0x0 749#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x260 0x630 0x000 0x1 0x0
750#define MX6Q_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0 750#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x260 0x630 0x000 0x5 0x0
751#define MX6Q_PAD_CSI0_VSYNC__ARM_TRACE00 0x264 0x634 0x000 0x7 0x0 751#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x260 0x630 0x000 0x7 0x0
752#define MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x268 0x638 0x000 0x0 0x0 752#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x264 0x634 0x000 0x0 0x0
753#define MX6Q_PAD_CSI0_DAT4__EIM_DATA02 0x268 0x638 0x000 0x1 0x0 753#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x264 0x634 0x000 0x1 0x0
754#define MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3 754#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0
755#define MX6Q_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2 755#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x264 0x634 0x000 0x7 0x0
756#define MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x268 0x638 0x000 0x4 0x0 756#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x268 0x638 0x000 0x0 0x0
757#define MX6Q_PAD_CSI0_DAT4__GPIO5_IO22 0x268 0x638 0x000 0x5 0x0 757#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x268 0x638 0x000 0x1 0x0
758#define MX6Q_PAD_CSI0_DAT4__ARM_TRACE01 0x268 0x638 0x000 0x7 0x0 758#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3
759#define MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x26c 0x63c 0x000 0x0 0x0 759#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2
760#define MX6Q_PAD_CSI0_DAT5__EIM_DATA03 0x26c 0x63c 0x000 0x1 0x0 760#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x268 0x638 0x000 0x4 0x0
761#define MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3 761#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x268 0x638 0x000 0x5 0x0
762#define MX6Q_PAD_CSI0_DAT5__KEY_ROW5 0x26c 0x63c 0x8f4 0x3 0x1 762#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x268 0x638 0x000 0x7 0x0
763#define MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x26c 0x63c 0x000 0x4 0x0 763#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x26c 0x63c 0x000 0x0 0x0
764#define MX6Q_PAD_CSI0_DAT5__GPIO5_IO23 0x26c 0x63c 0x000 0x5 0x0 764#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x26c 0x63c 0x000 0x1 0x0
765#define MX6Q_PAD_CSI0_DAT5__ARM_TRACE02 0x26c 0x63c 0x000 0x7 0x0 765#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3
766#define MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x270 0x640 0x000 0x0 0x0 766#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x26c 0x63c 0x8f4 0x3 0x1
767#define MX6Q_PAD_CSI0_DAT6__EIM_DATA04 0x270 0x640 0x000 0x1 0x0 767#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x26c 0x63c 0x000 0x4 0x0
768#define MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3 768#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x26c 0x63c 0x000 0x5 0x0
769#define MX6Q_PAD_CSI0_DAT6__KEY_COL6 0x270 0x640 0x8ec 0x3 0x1 769#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x26c 0x63c 0x000 0x7 0x0
770#define MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x270 0x640 0x000 0x4 0x0 770#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x270 0x640 0x000 0x0 0x0
771#define MX6Q_PAD_CSI0_DAT6__GPIO5_IO24 0x270 0x640 0x000 0x5 0x0 771#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x270 0x640 0x000 0x1 0x0
772#define MX6Q_PAD_CSI0_DAT6__ARM_TRACE03 0x270 0x640 0x000 0x7 0x0 772#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3
773#define MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x274 0x644 0x000 0x0 0x0 773#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x270 0x640 0x8ec 0x3 0x1
774#define MX6Q_PAD_CSI0_DAT7__EIM_DATA05 0x274 0x644 0x000 0x1 0x0 774#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x270 0x640 0x000 0x4 0x0
775#define MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3 775#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x270 0x640 0x000 0x5 0x0
776#define MX6Q_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2 776#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x270 0x640 0x000 0x7 0x0
777#define MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x274 0x644 0x000 0x4 0x0 777#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x274 0x644 0x000 0x0 0x0
778#define MX6Q_PAD_CSI0_DAT7__GPIO5_IO25 0x274 0x644 0x000 0x5 0x0 778#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x274 0x644 0x000 0x1 0x0
779#define MX6Q_PAD_CSI0_DAT7__ARM_TRACE04 0x274 0x644 0x000 0x7 0x0 779#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3
780#define MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x278 0x648 0x000 0x0 0x0 780#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2
781#define MX6Q_PAD_CSI0_DAT8__EIM_DATA06 0x278 0x648 0x000 0x1 0x0 781#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x274 0x644 0x000 0x4 0x0
782#define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2 782#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x274 0x644 0x000 0x5 0x0
783#define MX6Q_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2 783#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x274 0x644 0x000 0x7 0x0
784#define MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x278 0x648 0x89c 0x4 0x1 784#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x278 0x648 0x000 0x0 0x0
785#define MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 0x278 0x648 0x000 0x5 0x0 785#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x278 0x648 0x000 0x1 0x0
786#define MX6Q_PAD_CSI0_DAT8__ARM_TRACE05 0x278 0x648 0x000 0x7 0x0 786#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2
787#define MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x27c 0x64c 0x000 0x0 0x0 787#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2
788#define MX6Q_PAD_CSI0_DAT9__EIM_DATA07 0x27c 0x64c 0x000 0x1 0x0 788#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x278 0x648 0x89c 0x4 0x1
789#define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2 789#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x278 0x648 0x000 0x5 0x0
790#define MX6Q_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2 790#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x278 0x648 0x000 0x7 0x0
791#define MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x27c 0x64c 0x898 0x4 0x1 791#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x27c 0x64c 0x000 0x0 0x0
792#define MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 0x27c 0x64c 0x000 0x5 0x0 792#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x27c 0x64c 0x000 0x1 0x0
793#define MX6Q_PAD_CSI0_DAT9__ARM_TRACE06 0x27c 0x64c 0x000 0x7 0x0 793#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2
794#define MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x280 0x650 0x000 0x0 0x0 794#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2
795#define MX6Q_PAD_CSI0_DAT10__AUD3_RXC 0x280 0x650 0x000 0x1 0x0 795#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x27c 0x64c 0x898 0x4 0x1
796#define MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2 796#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x27c 0x64c 0x000 0x5 0x0
797#define MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x280 0x650 0x000 0x3 0x0 797#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x27c 0x64c 0x000 0x7 0x0
798#define MX6Q_PAD_CSI0_DAT10__UART1_RX_DATA 0x280 0x650 0x920 0x3 0x0 798#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x280 0x650 0x000 0x0 0x0
799#define MX6Q_PAD_CSI0_DAT10__GPIO5_IO28 0x280 0x650 0x000 0x5 0x0 799#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x280 0x650 0x000 0x1 0x0
800#define MX6Q_PAD_CSI0_DAT10__ARM_TRACE07 0x280 0x650 0x000 0x7 0x0 800#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2
801#define MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x284 0x654 0x000 0x0 0x0 801#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x280 0x650 0x000 0x3 0x0
802#define MX6Q_PAD_CSI0_DAT11__AUD3_RXFS 0x284 0x654 0x000 0x1 0x0 802#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x280 0x650 0x920 0x3 0x0
803#define MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2 803#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x280 0x650 0x000 0x5 0x0
804#define MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x284 0x654 0x920 0x3 0x1 804#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x280 0x650 0x000 0x7 0x0
805#define MX6Q_PAD_CSI0_DAT11__UART1_TX_DATA 0x284 0x654 0x000 0x3 0x0 805#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x284 0x654 0x000 0x0 0x0
806#define MX6Q_PAD_CSI0_DAT11__GPIO5_IO29 0x284 0x654 0x000 0x5 0x0 806#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x284 0x654 0x000 0x1 0x0
807#define MX6Q_PAD_CSI0_DAT11__ARM_TRACE08 0x284 0x654 0x000 0x7 0x0 807#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2
808#define MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x288 0x658 0x000 0x0 0x0 808#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x284 0x654 0x920 0x3 0x1
809#define MX6Q_PAD_CSI0_DAT12__EIM_DATA08 0x288 0x658 0x000 0x1 0x0 809#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x284 0x654 0x000 0x3 0x0
810#define MX6Q_PAD_CSI0_DAT12__UART4_TX_DATA 0x288 0x658 0x000 0x3 0x0 810#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x284 0x654 0x000 0x5 0x0
811#define MX6Q_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2 811#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x284 0x654 0x000 0x7 0x0
812#define MX6Q_PAD_CSI0_DAT12__GPIO5_IO30 0x288 0x658 0x000 0x5 0x0 812#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x288 0x658 0x000 0x0 0x0
813#define MX6Q_PAD_CSI0_DAT12__ARM_TRACE09 0x288 0x658 0x000 0x7 0x0 813#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x288 0x658 0x000 0x1 0x0
814#define MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x28c 0x65c 0x000 0x0 0x0 814#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x288 0x658 0x000 0x3 0x0
815#define MX6Q_PAD_CSI0_DAT13__EIM_DATA09 0x28c 0x65c 0x000 0x1 0x0 815#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2
816#define MX6Q_PAD_CSI0_DAT13__UART4_RX_DATA 0x28c 0x65c 0x938 0x3 0x3 816#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x288 0x658 0x000 0x5 0x0
817#define MX6Q_PAD_CSI0_DAT13__UART4_TX_DATA 0x28c 0x65c 0x000 0x3 0x0 817#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x288 0x658 0x000 0x7 0x0
818#define MX6Q_PAD_CSI0_DAT13__GPIO5_IO31 0x28c 0x65c 0x000 0x5 0x0 818#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x28c 0x65c 0x000 0x0 0x0
819#define MX6Q_PAD_CSI0_DAT13__ARM_TRACE10 0x28c 0x65c 0x000 0x7 0x0 819#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x28c 0x65c 0x000 0x1 0x0
820#define MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x290 0x660 0x000 0x0 0x0 820#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x28c 0x65c 0x938 0x3 0x3
821#define MX6Q_PAD_CSI0_DAT14__EIM_DATA10 0x290 0x660 0x000 0x1 0x0 821#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x28c 0x65c 0x000 0x3 0x0
822#define MX6Q_PAD_CSI0_DAT14__UART5_TX_DATA 0x290 0x660 0x000 0x3 0x0 822#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x28c 0x65c 0x000 0x5 0x0
823#define MX6Q_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2 823#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x28c 0x65c 0x000 0x7 0x0
824#define MX6Q_PAD_CSI0_DAT14__GPIO6_IO00 0x290 0x660 0x000 0x5 0x0 824#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x290 0x660 0x000 0x0 0x0
825#define MX6Q_PAD_CSI0_DAT14__ARM_TRACE11 0x290 0x660 0x000 0x7 0x0 825#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x290 0x660 0x000 0x1 0x0
826#define MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x294 0x664 0x000 0x0 0x0 826#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x290 0x660 0x000 0x3 0x0
827#define MX6Q_PAD_CSI0_DAT15__EIM_DATA11 0x294 0x664 0x000 0x1 0x0 827#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2
828#define MX6Q_PAD_CSI0_DAT15__UART5_RX_DATA 0x294 0x664 0x940 0x3 0x3 828#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x290 0x660 0x000 0x5 0x0
829#define MX6Q_PAD_CSI0_DAT15__UART5_TX_DATA 0x294 0x664 0x000 0x3 0x0 829#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x290 0x660 0x000 0x7 0x0
830#define MX6Q_PAD_CSI0_DAT15__GPIO6_IO01 0x294 0x664 0x000 0x5 0x0 830#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x294 0x664 0x000 0x0 0x0
831#define MX6Q_PAD_CSI0_DAT15__ARM_TRACE12 0x294 0x664 0x000 0x7 0x0 831#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x294 0x664 0x000 0x1 0x0
832#define MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x298 0x668 0x000 0x0 0x0 832#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x294 0x664 0x940 0x3 0x3
833#define MX6Q_PAD_CSI0_DAT16__EIM_DATA12 0x298 0x668 0x000 0x1 0x0 833#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x294 0x664 0x000 0x3 0x0
834#define MX6Q_PAD_CSI0_DAT16__UART4_RTS_B 0x298 0x668 0x934 0x3 0x0 834#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x294 0x664 0x000 0x5 0x0
835#define MX6Q_PAD_CSI0_DAT16__UART4_CTS_B 0x298 0x668 0x000 0x3 0x0 835#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x294 0x664 0x000 0x7 0x0
836#define MX6Q_PAD_CSI0_DAT16__GPIO6_IO02 0x298 0x668 0x000 0x5 0x0 836#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x298 0x668 0x000 0x0 0x0
837#define MX6Q_PAD_CSI0_DAT16__ARM_TRACE13 0x298 0x668 0x000 0x7 0x0 837#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x298 0x668 0x000 0x1 0x0
838#define MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x29c 0x66c 0x000 0x0 0x0 838#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x298 0x668 0x934 0x3 0x0
839#define MX6Q_PAD_CSI0_DAT17__EIM_DATA13 0x29c 0x66c 0x000 0x1 0x0 839#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x298 0x668 0x000 0x3 0x0
840#define MX6Q_PAD_CSI0_DAT17__UART4_CTS_B 0x29c 0x66c 0x000 0x3 0x0 840#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x298 0x668 0x000 0x5 0x0
841#define MX6Q_PAD_CSI0_DAT17__UART4_RTS_B 0x29c 0x66c 0x934 0x3 0x1 841#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x298 0x668 0x000 0x7 0x0
842#define MX6Q_PAD_CSI0_DAT17__GPIO6_IO03 0x29c 0x66c 0x000 0x5 0x0 842#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x29c 0x66c 0x000 0x0 0x0
843#define MX6Q_PAD_CSI0_DAT17__ARM_TRACE14 0x29c 0x66c 0x000 0x7 0x0 843#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x29c 0x66c 0x000 0x1 0x0
844#define MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x2a0 0x670 0x000 0x0 0x0 844#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x29c 0x66c 0x000 0x3 0x0
845#define MX6Q_PAD_CSI0_DAT18__EIM_DATA14 0x2a0 0x670 0x000 0x1 0x0 845#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x29c 0x66c 0x934 0x3 0x1
846#define MX6Q_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2 846#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x29c 0x66c 0x000 0x5 0x0
847#define MX6Q_PAD_CSI0_DAT18__UART5_CTS_B 0x2a0 0x670 0x000 0x3 0x0 847#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x29c 0x66c 0x000 0x7 0x0
848#define MX6Q_PAD_CSI0_DAT18__GPIO6_IO04 0x2a0 0x670 0x000 0x5 0x0 848#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x2a0 0x670 0x000 0x0 0x0
849#define MX6Q_PAD_CSI0_DAT18__ARM_TRACE15 0x2a0 0x670 0x000 0x7 0x0 849#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x2a0 0x670 0x000 0x1 0x0
850#define MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x2a4 0x674 0x000 0x0 0x0 850#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2
851#define MX6Q_PAD_CSI0_DAT19__EIM_DATA15 0x2a4 0x674 0x000 0x1 0x0 851#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x2a0 0x670 0x000 0x3 0x0
852#define MX6Q_PAD_CSI0_DAT19__UART5_CTS_B 0x2a4 0x674 0x000 0x3 0x0 852#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x2a0 0x670 0x000 0x5 0x0
853#define MX6Q_PAD_CSI0_DAT19__UART5_RTS_B 0x2a4 0x674 0x93c 0x3 0x3 853#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x2a0 0x670 0x000 0x7 0x0
854#define MX6Q_PAD_CSI0_DAT19__GPIO6_IO05 0x2a4 0x674 0x000 0x5 0x0 854#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x2a4 0x674 0x000 0x0 0x0
855#define MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x2a8 0x690 0x000 0x0 0x0 855#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x2a4 0x674 0x000 0x1 0x0
856#define MX6Q_PAD_SD3_DAT7__UART1_TX_DATA 0x2a8 0x690 0x000 0x1 0x0 856#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x2a4 0x674 0x000 0x3 0x0
857#define MX6Q_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2 857#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x2a4 0x674 0x93c 0x3 0x3
858#define MX6Q_PAD_SD3_DAT7__GPIO6_IO17 0x2a8 0x690 0x000 0x5 0x0 858#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x2a4 0x674 0x000 0x5 0x0
859#define MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x2ac 0x694 0x000 0x0 0x0 859#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x2a8 0x690 0x000 0x0 0x0
860#define MX6Q_PAD_SD3_DAT6__UART1_RX_DATA 0x2ac 0x694 0x920 0x1 0x3 860#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x2a8 0x690 0x000 0x1 0x0
861#define MX6Q_PAD_SD3_DAT6__UART1_TX_DATA 0x2ac 0x694 0x000 0x1 0x0 861#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2
862#define MX6Q_PAD_SD3_DAT6__GPIO6_IO18 0x2ac 0x694 0x000 0x5 0x0 862#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x2a8 0x690 0x000 0x5 0x0
863#define MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x2b0 0x698 0x000 0x0 0x0 863#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x2ac 0x694 0x000 0x0 0x0
864#define MX6Q_PAD_SD3_DAT5__UART2_TX_DATA 0x2b0 0x698 0x000 0x1 0x0 864#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x2ac 0x694 0x920 0x1 0x3
865#define MX6Q_PAD_SD3_DAT5__UART2_RX_DATA 0x2b0 0x698 0x928 0x1 0x4 865#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x2ac 0x694 0x000 0x1 0x0
866#define MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x2b0 0x698 0x000 0x5 0x0 866#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x2ac 0x694 0x000 0x5 0x0
867#define MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x2b4 0x69c 0x000 0x0 0x0 867#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x2b0 0x698 0x000 0x0 0x0
868#define MX6Q_PAD_SD3_DAT4__UART2_RX_DATA 0x2b4 0x69c 0x928 0x1 0x5 868#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x2b0 0x698 0x000 0x1 0x0
869#define MX6Q_PAD_SD3_DAT4__UART2_TX_DATA 0x2b4 0x69c 0x000 0x1 0x0 869#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x2b0 0x698 0x928 0x1 0x4
870#define MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x2b4 0x69c 0x000 0x5 0x0 870#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x2b0 0x698 0x000 0x5 0x0
871#define MX6Q_PAD_SD3_CMD__SD3_CMD 0x2b8 0x6a0 0x000 0x0 0x0 871#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x2b4 0x69c 0x000 0x0 0x0
872#define MX6Q_PAD_SD3_CMD__UART2_CTS_B 0x2b8 0x6a0 0x000 0x1 0x0 872#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x2b4 0x69c 0x928 0x1 0x5
873#define MX6Q_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2 873#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x2b4 0x69c 0x000 0x1 0x0
874#define MX6Q_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0 874#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x2b4 0x69c 0x000 0x5 0x0
875#define MX6Q_PAD_SD3_CMD__GPIO7_IO02 0x2b8 0x6a0 0x000 0x5 0x0 875#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x2b8 0x6a0 0x000 0x0 0x0
876#define MX6Q_PAD_SD3_CLK__SD3_CLK 0x2bc 0x6a4 0x000 0x0 0x0 876#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x2b8 0x6a0 0x000 0x1 0x0
877#define MX6Q_PAD_SD3_CLK__UART2_RTS_B 0x2bc 0x6a4 0x924 0x1 0x3 877#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2
878#define MX6Q_PAD_SD3_CLK__UART2_CTS_B 0x2bc 0x6a4 0x000 0x1 0x0 878#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0
879#define MX6Q_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2 879#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x2b8 0x6a0 0x000 0x5 0x0
880#define MX6Q_PAD_SD3_CLK__GPIO7_IO03 0x2bc 0x6a4 0x000 0x5 0x0 880#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x2bc 0x6a4 0x000 0x0 0x0
881#define MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x2c0 0x6a8 0x000 0x0 0x0 881#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x2bc 0x6a4 0x924 0x1 0x3
882#define MX6Q_PAD_SD3_DAT0__UART1_CTS_B 0x2c0 0x6a8 0x000 0x1 0x0 882#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x2bc 0x6a4 0x000 0x1 0x0
883#define MX6Q_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2 883#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2
884#define MX6Q_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0 884#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x2bc 0x6a4 0x000 0x5 0x0
885#define MX6Q_PAD_SD3_DAT0__GPIO7_IO04 0x2c0 0x6a8 0x000 0x5 0x0 885#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x2c0 0x6a8 0x000 0x0 0x0
886#define MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x2c4 0x6ac 0x000 0x0 0x0 886#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x2c0 0x6a8 0x000 0x1 0x0
887#define MX6Q_PAD_SD3_DAT1__UART1_RTS_B 0x2c4 0x6ac 0x91c 0x1 0x3 887#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2
888#define MX6Q_PAD_SD3_DAT1__UART1_CTS_B 0x2c4 0x6ac 0x000 0x1 0x0 888#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0
889#define MX6Q_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1 889#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x2c0 0x6a8 0x000 0x5 0x0
890#define MX6Q_PAD_SD3_DAT1__GPIO7_IO05 0x2c4 0x6ac 0x000 0x5 0x0 890#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x2c4 0x6ac 0x000 0x0 0x0
891#define MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x2c8 0x6b0 0x000 0x0 0x0 891#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x2c4 0x6ac 0x91c 0x1 0x3
892#define MX6Q_PAD_SD3_DAT2__GPIO7_IO06 0x2c8 0x6b0 0x000 0x5 0x0 892#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x2c4 0x6ac 0x000 0x1 0x0
893#define MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x2cc 0x6b4 0x000 0x0 0x0 893#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1
894#define MX6Q_PAD_SD3_DAT3__UART3_CTS_B 0x2cc 0x6b4 0x000 0x1 0x0 894#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x2c4 0x6ac 0x000 0x5 0x0
895#define MX6Q_PAD_SD3_DAT3__UART3_RTS_B 0x2cc 0x6b4 0x92c 0x1 0x4 895#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x2c8 0x6b0 0x000 0x0 0x0
896#define MX6Q_PAD_SD3_DAT3__GPIO7_IO07 0x2cc 0x6b4 0x000 0x5 0x0 896#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x2c8 0x6b0 0x000 0x5 0x0
897#define MX6Q_PAD_SD3_RST__SD3_RESET 0x2d0 0x6b8 0x000 0x0 0x0 897#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x2cc 0x6b4 0x000 0x0 0x0
898#define MX6Q_PAD_SD3_RST__UART3_RTS_B 0x2d0 0x6b8 0x92c 0x1 0x5 898#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x2cc 0x6b4 0x000 0x1 0x0
899#define MX6Q_PAD_SD3_RST__UART3_CTS_B 0x2d0 0x6b8 0x000 0x1 0x0 899#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x2cc 0x6b4 0x92c 0x1 0x4
900#define MX6Q_PAD_SD3_RST__GPIO7_IO08 0x2d0 0x6b8 0x000 0x5 0x0 900#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x2cc 0x6b4 0x000 0x5 0x0
901#define MX6Q_PAD_NANDF_CLE__NAND_CLE 0x2d4 0x6bc 0x000 0x0 0x0 901#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x2d0 0x6b8 0x000 0x0 0x0
902#define MX6Q_PAD_NANDF_CLE__IPU2_SISG4 0x2d4 0x6bc 0x000 0x1 0x0 902#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x2d0 0x6b8 0x92c 0x1 0x5
903#define MX6Q_PAD_NANDF_CLE__GPIO6_IO07 0x2d4 0x6bc 0x000 0x5 0x0 903#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x2d0 0x6b8 0x000 0x1 0x0
904#define MX6Q_PAD_NANDF_ALE__NAND_ALE 0x2d8 0x6c0 0x000 0x0 0x0 904#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x2d0 0x6b8 0x000 0x5 0x0
905#define MX6Q_PAD_NANDF_ALE__SD4_RESET 0x2d8 0x6c0 0x000 0x1 0x0 905#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x2d4 0x6bc 0x000 0x0 0x0
906#define MX6Q_PAD_NANDF_ALE__GPIO6_IO08 0x2d8 0x6c0 0x000 0x5 0x0 906#define MX6QDL_PAD_NANDF_CLE__IPU2_SISG4 0x2d4 0x6bc 0x000 0x1 0x0
907#define MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0x2dc 0x6c4 0x000 0x0 0x0 907#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x2d4 0x6bc 0x000 0x5 0x0
908#define MX6Q_PAD_NANDF_WP_B__IPU2_SISG5 0x2dc 0x6c4 0x000 0x1 0x0 908#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x2d8 0x6c0 0x000 0x0 0x0
909#define MX6Q_PAD_NANDF_WP_B__GPIO6_IO09 0x2dc 0x6c4 0x000 0x5 0x0 909#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x2d8 0x6c0 0x000 0x1 0x0
910#define MX6Q_PAD_NANDF_RB0__NAND_READY_B 0x2e0 0x6c8 0x000 0x0 0x0 910#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x2d8 0x6c0 0x000 0x5 0x0
911#define MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN01 0x2e0 0x6c8 0x000 0x1 0x0 911#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2dc 0x6c4 0x000 0x0 0x0
912#define MX6Q_PAD_NANDF_RB0__GPIO6_IO10 0x2e0 0x6c8 0x000 0x5 0x0 912#define MX6QDL_PAD_NANDF_WP_B__IPU2_SISG5 0x2dc 0x6c4 0x000 0x1 0x0
913#define MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0x2e4 0x6cc 0x000 0x0 0x0 913#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2dc 0x6c4 0x000 0x5 0x0
914#define MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x2e4 0x6cc 0x000 0x5 0x0 914#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2e0 0x6c8 0x000 0x0 0x0
915#define MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0x2e8 0x6d0 0x000 0x0 0x0 915#define MX6QDL_PAD_NANDF_RB0__IPU2_DI0_PIN01 0x2e0 0x6c8 0x000 0x1 0x0
916#define MX6Q_PAD_NANDF_CS1__SD4_VSELECT 0x2e8 0x6d0 0x000 0x1 0x0 916#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2e0 0x6c8 0x000 0x5 0x0
917#define MX6Q_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0 917#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x2e4 0x6cc 0x000 0x0 0x0
918#define MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x2e8 0x6d0 0x000 0x5 0x0 918#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x2e4 0x6cc 0x000 0x5 0x0
919#define MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0x2ec 0x6d4 0x000 0x0 0x0 919#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x2e8 0x6d0 0x000 0x0 0x0
920#define MX6Q_PAD_NANDF_CS2__IPU1_SISG0 0x2ec 0x6d4 0x000 0x1 0x0 920#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x2e8 0x6d0 0x000 0x1 0x0
921#define MX6Q_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1 921#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0
922#define MX6Q_PAD_NANDF_CS2__EIM_CRE 0x2ec 0x6d4 0x000 0x3 0x0 922#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x2e8 0x6d0 0x000 0x5 0x0
923#define MX6Q_PAD_NANDF_CS2__CCM_CLKO2 0x2ec 0x6d4 0x000 0x4 0x0 923#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x2ec 0x6d4 0x000 0x0 0x0
924#define MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x2ec 0x6d4 0x000 0x5 0x0 924#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x2ec 0x6d4 0x000 0x1 0x0
925#define MX6Q_PAD_NANDF_CS2__IPU2_SISG0 0x2ec 0x6d4 0x000 0x6 0x0 925#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1
926#define MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0x2f0 0x6d8 0x000 0x0 0x0 926#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x2ec 0x6d4 0x000 0x3 0x0
927#define MX6Q_PAD_NANDF_CS3__IPU1_SISG1 0x2f0 0x6d8 0x000 0x1 0x0 927#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x2ec 0x6d4 0x000 0x4 0x0
928#define MX6Q_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1 928#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x2ec 0x6d4 0x000 0x5 0x0
929#define MX6Q_PAD_NANDF_CS3__EIM_ADDR26 0x2f0 0x6d8 0x000 0x3 0x0 929#define MX6QDL_PAD_NANDF_CS2__IPU2_SISG0 0x2ec 0x6d4 0x000 0x6 0x0
930#define MX6Q_PAD_NANDF_CS3__GPIO6_IO16 0x2f0 0x6d8 0x000 0x5 0x0 930#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x2f0 0x6d8 0x000 0x0 0x0
931#define MX6Q_PAD_NANDF_CS3__IPU2_SISG1 0x2f0 0x6d8 0x000 0x6 0x0 931#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x2f0 0x6d8 0x000 0x1 0x0
932#define MX6Q_PAD_SD4_CMD__SD4_CMD 0x2f4 0x6dc 0x000 0x0 0x0 932#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1
933#define MX6Q_PAD_SD4_CMD__NAND_RE_B 0x2f4 0x6dc 0x000 0x1 0x0 933#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x2f0 0x6d8 0x000 0x3 0x0
934#define MX6Q_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0 934#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x2f0 0x6d8 0x000 0x5 0x0
935#define MX6Q_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2 935#define MX6QDL_PAD_NANDF_CS3__IPU2_SISG1 0x2f0 0x6d8 0x000 0x6 0x0
936#define MX6Q_PAD_SD4_CMD__GPIO7_IO09 0x2f4 0x6dc 0x000 0x5 0x0 936#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x2f4 0x6dc 0x000 0x0 0x0
937#define MX6Q_PAD_SD4_CLK__SD4_CLK 0x2f8 0x6e0 0x000 0x0 0x0 937#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x2f4 0x6dc 0x000 0x1 0x0
938#define MX6Q_PAD_SD4_CLK__NAND_WE_B 0x2f8 0x6e0 0x000 0x1 0x0 938#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0
939#define MX6Q_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3 939#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2
940#define MX6Q_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0 940#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x2f4 0x6dc 0x000 0x5 0x0
941#define MX6Q_PAD_SD4_CLK__GPIO7_IO10 0x2f8 0x6e0 0x000 0x5 0x0 941#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x2f8 0x6e0 0x000 0x0 0x0
942#define MX6Q_PAD_NANDF_D0__NAND_DATA00 0x2fc 0x6e4 0x000 0x0 0x0 942#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x2f8 0x6e0 0x000 0x1 0x0
943#define MX6Q_PAD_NANDF_D0__SD1_DATA4 0x2fc 0x6e4 0x000 0x1 0x0 943#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3
944#define MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x2fc 0x6e4 0x000 0x5 0x0 944#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0
945#define MX6Q_PAD_NANDF_D1__NAND_DATA01 0x300 0x6e8 0x000 0x0 0x0 945#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x2f8 0x6e0 0x000 0x5 0x0
946#define MX6Q_PAD_NANDF_D1__SD1_DATA5 0x300 0x6e8 0x000 0x1 0x0 946#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x2fc 0x6e4 0x000 0x0 0x0
947#define MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x300 0x6e8 0x000 0x5 0x0 947#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x2fc 0x6e4 0x000 0x1 0x0
948#define MX6Q_PAD_NANDF_D2__NAND_DATA02 0x304 0x6ec 0x000 0x0 0x0 948#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x2fc 0x6e4 0x000 0x5 0x0
949#define MX6Q_PAD_NANDF_D2__SD1_DATA6 0x304 0x6ec 0x000 0x1 0x0 949#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x300 0x6e8 0x000 0x0 0x0
950#define MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x304 0x6ec 0x000 0x5 0x0 950#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x300 0x6e8 0x000 0x1 0x0
951#define MX6Q_PAD_NANDF_D3__NAND_DATA03 0x308 0x6f0 0x000 0x0 0x0 951#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x300 0x6e8 0x000 0x5 0x0
952#define MX6Q_PAD_NANDF_D3__SD1_DATA7 0x308 0x6f0 0x000 0x1 0x0 952#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x304 0x6ec 0x000 0x0 0x0
953#define MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x308 0x6f0 0x000 0x5 0x0 953#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x304 0x6ec 0x000 0x1 0x0
954#define MX6Q_PAD_NANDF_D4__NAND_DATA04 0x30c 0x6f4 0x000 0x0 0x0 954#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x304 0x6ec 0x000 0x5 0x0
955#define MX6Q_PAD_NANDF_D4__SD2_DATA4 0x30c 0x6f4 0x000 0x1 0x0 955#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x308 0x6f0 0x000 0x0 0x0
956#define MX6Q_PAD_NANDF_D4__GPIO2_IO04 0x30c 0x6f4 0x000 0x5 0x0 956#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x308 0x6f0 0x000 0x1 0x0
957#define MX6Q_PAD_NANDF_D5__NAND_DATA05 0x310 0x6f8 0x000 0x0 0x0 957#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x308 0x6f0 0x000 0x5 0x0
958#define MX6Q_PAD_NANDF_D5__SD2_DATA5 0x310 0x6f8 0x000 0x1 0x0 958#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x30c 0x6f4 0x000 0x0 0x0
959#define MX6Q_PAD_NANDF_D5__GPIO2_IO05 0x310 0x6f8 0x000 0x5 0x0 959#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x30c 0x6f4 0x000 0x1 0x0
960#define MX6Q_PAD_NANDF_D6__NAND_DATA06 0x314 0x6fc 0x000 0x0 0x0 960#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30c 0x6f4 0x000 0x5 0x0
961#define MX6Q_PAD_NANDF_D6__SD2_DATA6 0x314 0x6fc 0x000 0x1 0x0 961#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x310 0x6f8 0x000 0x0 0x0
962#define MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x314 0x6fc 0x000 0x5 0x0 962#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x310 0x6f8 0x000 0x1 0x0
963#define MX6Q_PAD_NANDF_D7__NAND_DATA07 0x318 0x700 0x000 0x0 0x0 963#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x310 0x6f8 0x000 0x5 0x0
964#define MX6Q_PAD_NANDF_D7__SD2_DATA7 0x318 0x700 0x000 0x1 0x0 964#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x314 0x6fc 0x000 0x0 0x0
965#define MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x318 0x700 0x000 0x5 0x0 965#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x314 0x6fc 0x000 0x1 0x0
966#define MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x31c 0x704 0x000 0x1 0x0 966#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x314 0x6fc 0x000 0x5 0x0
967#define MX6Q_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0 967#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x318 0x700 0x000 0x0 0x0
968#define MX6Q_PAD_SD4_DAT0__GPIO2_IO08 0x31c 0x704 0x000 0x5 0x0 968#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x318 0x700 0x000 0x1 0x0
969#define MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x320 0x708 0x000 0x1 0x0 969#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x318 0x700 0x000 0x5 0x0
970#define MX6Q_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0 970#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x31c 0x704 0x000 0x1 0x0
971#define MX6Q_PAD_SD4_DAT1__GPIO2_IO09 0x320 0x708 0x000 0x5 0x0 971#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0
972#define MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x324 0x70c 0x000 0x1 0x0 972#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x31c 0x704 0x000 0x5 0x0
973#define MX6Q_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0 973#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x320 0x708 0x000 0x1 0x0
974#define MX6Q_PAD_SD4_DAT2__GPIO2_IO10 0x324 0x70c 0x000 0x5 0x0 974#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0
975#define MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x328 0x710 0x000 0x1 0x0 975#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x320 0x708 0x000 0x5 0x0
976#define MX6Q_PAD_SD4_DAT3__GPIO2_IO11 0x328 0x710 0x000 0x5 0x0 976#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x324 0x70c 0x000 0x1 0x0
977#define MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x32c 0x714 0x000 0x1 0x0 977#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0
978#define MX6Q_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6 978#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x324 0x70c 0x000 0x5 0x0
979#define MX6Q_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0 979#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x328 0x710 0x000 0x1 0x0
980#define MX6Q_PAD_SD4_DAT4__GPIO2_IO12 0x32c 0x714 0x000 0x5 0x0 980#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x328 0x710 0x000 0x5 0x0
981#define MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x330 0x718 0x000 0x1 0x0 981#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x32c 0x714 0x000 0x1 0x0
982#define MX6Q_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4 982#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6
983#define MX6Q_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0 983#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0
984#define MX6Q_PAD_SD4_DAT5__GPIO2_IO13 0x330 0x718 0x000 0x5 0x0 984#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x32c 0x714 0x000 0x5 0x0
985#define MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x334 0x71c 0x000 0x1 0x0 985#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x330 0x718 0x000 0x1 0x0
986#define MX6Q_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0 986#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4
987#define MX6Q_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5 987#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0
988#define MX6Q_PAD_SD4_DAT6__GPIO2_IO14 0x334 0x71c 0x000 0x5 0x0 988#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x330 0x718 0x000 0x5 0x0
989#define MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x338 0x720 0x000 0x1 0x0 989#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x334 0x71c 0x000 0x1 0x0
990#define MX6Q_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0 990#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0
991#define MX6Q_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7 991#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5
992#define MX6Q_PAD_SD4_DAT7__GPIO2_IO15 0x338 0x720 0x000 0x5 0x0 992#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x334 0x71c 0x000 0x5 0x0
993#define MX6Q_PAD_SD1_DAT1__SD1_DATA1 0x33c 0x724 0x000 0x0 0x0 993#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x338 0x720 0x000 0x1 0x0
994#define MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 0x33c 0x724 0x834 0x1 0x1 994#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0
995#define MX6Q_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0 995#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7
996#define MX6Q_PAD_SD1_DAT1__GPT_CAPTURE2 0x33c 0x724 0x000 0x3 0x0 996#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x338 0x720 0x000 0x5 0x0
997#define MX6Q_PAD_SD1_DAT1__GPIO1_IO17 0x33c 0x724 0x000 0x5 0x0 997#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x33c 0x724 0x000 0x0 0x0
998#define MX6Q_PAD_SD1_DAT0__SD1_DATA0 0x340 0x728 0x000 0x0 0x0 998#define MX6QDL_PAD_SD1_DAT1__ECSPI5_SS0 0x33c 0x724 0x834 0x1 0x1
999#define MX6Q_PAD_SD1_DAT0__ECSPI5_MISO 0x340 0x728 0x82c 0x1 0x1 999#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0
1000#define MX6Q_PAD_SD1_DAT0__GPT_CAPTURE1 0x340 0x728 0x000 0x3 0x0 1000#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x33c 0x724 0x000 0x3 0x0
1001#define MX6Q_PAD_SD1_DAT0__GPIO1_IO16 0x340 0x728 0x000 0x5 0x0 1001#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x33c 0x724 0x000 0x5 0x0
1002#define MX6Q_PAD_SD1_DAT3__SD1_DATA3 0x344 0x72c 0x000 0x0 0x0 1002#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x340 0x728 0x000 0x0 0x0
1003#define MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 0x344 0x72c 0x000 0x1 0x0 1003#define MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x340 0x728 0x82c 0x1 0x1
1004#define MX6Q_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0 1004#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x340 0x728 0x000 0x3 0x0
1005#define MX6Q_PAD_SD1_DAT3__PWM1_OUT 0x344 0x72c 0x000 0x3 0x0 1005#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x340 0x728 0x000 0x5 0x0
1006#define MX6Q_PAD_SD1_DAT3__WDOG2_B 0x344 0x72c 0x000 0x4 0x0 1006#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x344 0x72c 0x000 0x0 0x0
1007#define MX6Q_PAD_SD1_DAT3__GPIO1_IO21 0x344 0x72c 0x000 0x5 0x0 1007#define MX6QDL_PAD_SD1_DAT3__ECSPI5_SS2 0x344 0x72c 0x000 0x1 0x0
1008#define MX6Q_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x344 0x72c 0x000 0x6 0x0 1008#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0
1009#define MX6Q_PAD_SD1_CMD__SD1_CMD 0x348 0x730 0x000 0x0 0x0 1009#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x344 0x72c 0x000 0x3 0x0
1010#define MX6Q_PAD_SD1_CMD__ECSPI5_MOSI 0x348 0x730 0x830 0x1 0x0 1010#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x344 0x72c 0x000 0x4 0x0
1011#define MX6Q_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 1011#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x344 0x72c 0x000 0x5 0x0
1012#define MX6Q_PAD_SD1_CMD__GPT_COMPARE1 0x348 0x730 0x000 0x3 0x0 1012#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x344 0x72c 0x000 0x6 0x0
1013#define MX6Q_PAD_SD1_CMD__GPIO1_IO18 0x348 0x730 0x000 0x5 0x0 1013#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x348 0x730 0x000 0x0 0x0
1014#define MX6Q_PAD_SD1_DAT2__SD1_DATA2 0x34c 0x734 0x000 0x0 0x0 1014#define MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x348 0x730 0x830 0x1 0x0
1015#define MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 0x34c 0x734 0x838 0x1 0x1 1015#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0
1016#define MX6Q_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0 1016#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x348 0x730 0x000 0x3 0x0
1017#define MX6Q_PAD_SD1_DAT2__PWM2_OUT 0x34c 0x734 0x000 0x3 0x0 1017#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x348 0x730 0x000 0x5 0x0
1018#define MX6Q_PAD_SD1_DAT2__WDOG1_B 0x34c 0x734 0x000 0x4 0x0 1018#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x34c 0x734 0x000 0x0 0x0
1019#define MX6Q_PAD_SD1_DAT2__GPIO1_IO19 0x34c 0x734 0x000 0x5 0x0 1019#define MX6QDL_PAD_SD1_DAT2__ECSPI5_SS1 0x34c 0x734 0x838 0x1 0x1
1020#define MX6Q_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0 1020#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0
1021#define MX6Q_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0 1021#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x34c 0x734 0x000 0x3 0x0
1022#define MX6Q_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0 1022#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x34c 0x734 0x000 0x4 0x0
1023#define MX6Q_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0 1023#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x34c 0x734 0x000 0x5 0x0
1024#define MX6Q_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0 1024#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0
1025#define MX6Q_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0 1025#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0
1026#define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK 0x354 0x73c 0x828 0x1 0x1 1026#define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0
1027#define MX6Q_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3 1027#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0
1028#define MX6Q_PAD_SD2_CLK__AUD4_RXFS 0x354 0x73c 0x7c0 0x3 0x1 1028#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0
1029#define MX6Q_PAD_SD2_CLK__GPIO1_IO10 0x354 0x73c 0x000 0x5 0x0 1029#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0
1030#define MX6Q_PAD_SD2_CMD__SD2_CMD 0x358 0x740 0x000 0x0 0x0 1030#define MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x354 0x73c 0x828 0x1 0x1
1031#define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI 0x358 0x740 0x830 0x1 0x1 1031#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3
1032#define MX6Q_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2 1032#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x354 0x73c 0x7c0 0x3 0x1
1033#define MX6Q_PAD_SD2_CMD__AUD4_RXC 0x358 0x740 0x7bc 0x3 0x1 1033#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x354 0x73c 0x000 0x5 0x0
1034#define MX6Q_PAD_SD2_CMD__GPIO1_IO11 0x358 0x740 0x000 0x5 0x0 1034#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x358 0x740 0x000 0x0 0x0
1035#define MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x35c 0x744 0x000 0x0 0x0 1035#define MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x358 0x740 0x830 0x1 0x1
1036#define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 0x35c 0x744 0x000 0x1 0x0 1036#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2
1037#define MX6Q_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2 1037#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x358 0x740 0x7bc 0x3 0x1
1038#define MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x35c 0x744 0x7c4 0x3 0x1 1038#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x358 0x740 0x000 0x5 0x0
1039#define MX6Q_PAD_SD2_DAT3__GPIO1_IO12 0x35c 0x744 0x000 0x5 0x0 1039#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x35c 0x744 0x000 0x0 0x0
1040#define MX6QDL_PAD_SD2_DAT3__ECSPI5_SS3 0x35c 0x744 0x000 0x1 0x0
1041#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2
1042#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x35c 0x744 0x7c4 0x3 0x1
1043#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x35c 0x744 0x000 0x5 0x0
1040 1044
1041#endif /* __DTS_IMX6Q_PINFUNC_H */ 1045#endif /* __DTS_IMX6Q_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
index 09a75807bc6d..334b9247e78c 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -20,24 +20,6 @@
20 compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; 20 compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
21}; 21};
22 22
23&iomuxc { 23&sata {
24 pinctrl-names = "default"; 24 status = "okay";
25 pinctrl-0 = <&pinctrl_hog>;
26
27 hog {
28 pinctrl_hog: hoggrp {
29 fsl,pins = <
30 MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
31 MX6Q_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
32 >;
33 };
34 };
35
36 ecspi1 {
37 pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
38 fsl,pins = <
39 MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000
40 >;
41 };
42 };
43}; 25};
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 6a000666c147..3530280f5150 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -65,6 +65,10 @@
65 }; 65 };
66}; 66};
67 67
68&sata {
69 status = "okay";
70};
71
68&ecspi1 { 72&ecspi1 {
69 fsl,spi-num-chipselects = <1>; 73 fsl,spi-num-chipselects = <1>;
70 cs-gpios = <&gpio3 19 0>; 74 cs-gpios = <&gpio3 19 0>;
@@ -91,14 +95,14 @@
91 hog { 95 hog {
92 pinctrl_hog: hoggrp { 96 pinctrl_hog: hoggrp {
93 fsl,pins = < 97 fsl,pins = <
94 MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x80000000 98 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000
95 MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x80000000 99 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000
96 MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000 100 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
97 MX6Q_PAD_EIM_D22__GPIO3_IO22 0x80000000 101 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
98 MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000 102 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
99 MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 103 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
100 MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 104 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
101 MX6Q_PAD_GPIO_0__CCM_CLKO1 0x80000000 105 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x80000000
102 >; 106 >;
103 }; 107 };
104 }; 108 };
@@ -163,7 +167,7 @@
163 codec: sgtl5000@0a { 167 codec: sgtl5000@0a {
164 compatible = "fsl,sgtl5000"; 168 compatible = "fsl,sgtl5000";
165 reg = <0x0a>; 169 reg = <0x0a>;
166 clocks = <&clks 169>; 170 clocks = <&clks 201>;
167 VDDA-supply = <&reg_2p5v>; 171 VDDA-supply = <&reg_2p5v>;
168 VDDIO-supply = <&reg_3p3v>; 172 VDDIO-supply = <&reg_3p3v>;
169 }; 173 };
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 0038228c508c..9cbdfe7a0931 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -20,21 +20,6 @@
20 compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; 20 compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
21}; 21};
22 22
23&iomuxc { 23&sata {
24 pinctrl-names = "default"; 24 status = "okay";
25 pinctrl-0 = <&pinctrl_hog>;
26
27 hog {
28 pinctrl_hog: hoggrp {
29 fsl,pins = <
30 MX6Q_PAD_GPIO_4__GPIO1_IO04 0x80000000
31 MX6Q_PAD_GPIO_5__GPIO1_IO05 0x80000000
32 MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x80000000
33 MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000
34 MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000
35 MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000
36 MX6Q_PAD_GPIO_0__CCM_CLKO1 0x130b0
37 >;
38 };
39 };
40}; 25};
diff --git a/arch/arm/boot/dts/imx6q-wandboard.dts b/arch/arm/boot/dts/imx6q-wandboard.dts
new file mode 100644
index 000000000000..36be17f207b1
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-wandboard.dts
@@ -0,0 +1,26 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11/dts-v1/;
12#include "imx6q.dtsi"
13#include "imx6qdl-wandboard.dtsi"
14
15/ {
16 model = "Wandboard i.MX6 Quad Board";
17 compatible = "wand,imx6q-wandboard", "fsl,imx6q";
18
19 memory {
20 reg = <0x10000000 0x80000000>;
21 };
22};
23
24&sata {
25 status = "okay";
26};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index ba09dc32324e..f024ef28b34b 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -8,8 +8,8 @@
8 * 8 *
9 */ 9 */
10 10
11#include "imx6qdl.dtsi"
12#include "imx6q-pinfunc.h" 11#include "imx6q-pinfunc.h"
12#include "imx6qdl.dtsi"
13 13
14/ { 14/ {
15 cpus { 15 cpus {
@@ -61,6 +61,12 @@
61 }; 61 };
62 62
63 soc { 63 soc {
64 ocram: sram@00900000 {
65 compatible = "mmio-sram";
66 reg = <0x00900000 0x40000>;
67 clocks = <&clks 142>;
68 };
69
64 aips-bus@02000000 { /* AIPS1 */ 70 aips-bus@02000000 { /* AIPS1 */
65 spba-bus@02000000 { 71 spba-bus@02000000 {
66 ecspi5: ecspi@02018000 { 72 ecspi5: ecspi@02018000 {
@@ -77,357 +83,54 @@
77 83
78 iomuxc: iomuxc@020e0000 { 84 iomuxc: iomuxc@020e0000 {
79 compatible = "fsl,imx6q-iomuxc"; 85 compatible = "fsl,imx6q-iomuxc";
80 reg = <0x020e0000 0x4000>;
81
82 /* shared pinctrl settings */
83 audmux {
84 pinctrl_audmux_1: audmux-1 {
85 fsl,pins = <
86 MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x80000000
87 MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x80000000
88 MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x80000000
89 MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
90 >;
91 };
92
93 pinctrl_audmux_2: audmux-2 {
94 fsl,pins = <
95 MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
96 MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
97 MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
98 MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
99 >;
100 };
101 };
102
103 ecspi1 {
104 pinctrl_ecspi1_1: ecspi1grp-1 {
105 fsl,pins = <
106 MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1
107 MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
108 MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
109 >;
110 };
111 };
112
113 ecspi3 {
114 pinctrl_ecspi3_1: ecspi3grp-1 {
115 fsl,pins = <
116 MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
117 MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
118 MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
119 >;
120 };
121 };
122
123 enet {
124 pinctrl_enet_1: enetgrp-1 {
125 fsl,pins = <
126 MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
127 MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
128 MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
129 MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
130 MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
131 MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
132 MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
133 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
134 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
135 MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
136 MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
137 MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
138 MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
139 MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
140 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
141 MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
142 >;
143 };
144
145 pinctrl_enet_2: enetgrp-2 {
146 fsl,pins = <
147 MX6Q_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
148 MX6Q_PAD_KEY_COL2__ENET_MDC 0x1b0b0
149 MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
150 MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
151 MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
152 MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
153 MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
154 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
155 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
156 MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
157 MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
158 MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
159 MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
160 MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
161 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
162 >;
163 };
164
165 pinctrl_enet_3: enetgrp-3 {
166 fsl,pins = <
167 MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
168 MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
169 MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
170 MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
171 MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
172 MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
173 MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
174 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
175 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
176 MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
177 MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
178 MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
179 MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
180 MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
181 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
182 MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
183 >;
184 };
185 };
186
187 gpmi-nand {
188 pinctrl_gpmi_nand_1: gpmi-nand-1 {
189 fsl,pins = <
190 MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1
191 MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1
192 MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
193 MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
194 MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
195 MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
196 MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
197 MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
198 MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
199 MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1
200 MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1
201 MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1
202 MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1
203 MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1
204 MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1
205 MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1
206 MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1
207 >;
208 };
209 };
210
211 i2c1 {
212 pinctrl_i2c1_1: i2c1grp-1 {
213 fsl,pins = <
214 MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
215 MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
216 >;
217 };
218 86
219 pinctrl_i2c1_2: i2c1grp-2 { 87 ipu2 {
220 fsl,pins = < 88 pinctrl_ipu2_1: ipu2grp-1 {
221 MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 89 fsl,pins = <
222 MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 90 MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
223 >; 91 MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10
224 }; 92 MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10
225 }; 93 MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10
226 94 MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000
227 i2c2 { 95 MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10
228 pinctrl_i2c2_1: i2c2grp-1 { 96 MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10
229 fsl,pins = < 97 MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10
230 MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 98 MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10
231 MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 99 MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10
100 MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10
101 MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10
102 MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10
103 MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10
104 MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10
105 MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10
106 MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10
107 MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10
108 MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10
109 MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10
110 MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10
111 MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10
112 MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10
113 MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10
114 MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10
115 MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10
116 MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10
117 MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10
118 MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10
232 >; 119 >;
233 }; 120 };
234 }; 121 };
235
236 i2c3 {
237 pinctrl_i2c3_1: i2c3grp-1 {
238 fsl,pins = <
239 MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
240 MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
241 >;
242 };
243 };
244
245 uart1 {
246 pinctrl_uart1_1: uart1grp-1 {
247 fsl,pins = <
248 MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
249 MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
250 >;
251 };
252 };
253
254 uart2 {
255 pinctrl_uart2_1: uart2grp-1 {
256 fsl,pins = <
257 MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
258 MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
259 >;
260 };
261 };
262
263 uart4 {
264 pinctrl_uart4_1: uart4grp-1 {
265 fsl,pins = <
266 MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
267 MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
268 >;
269 };
270 };
271
272 usbotg {
273 pinctrl_usbotg_1: usbotggrp-1 {
274 fsl,pins = <
275 MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059
276 >;
277 };
278
279 pinctrl_usbotg_2: usbotggrp-2 {
280 fsl,pins = <
281 MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
282 >;
283 };
284 };
285
286 usdhc2 {
287 pinctrl_usdhc2_1: usdhc2grp-1 {
288 fsl,pins = <
289 MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
290 MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
291 MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
292 MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
293 MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
294 MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
295 MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059
296 MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059
297 MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059
298 MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
299 >;
300 };
301
302 pinctrl_usdhc2_2: usdhc2grp-2 {
303 fsl,pins = <
304 MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
305 MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
306 MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
307 MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
308 MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
309 MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
310 >;
311 };
312 };
313
314 usdhc3 {
315 pinctrl_usdhc3_1: usdhc3grp-1 {
316 fsl,pins = <
317 MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
318 MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
319 MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
320 MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
321 MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
322 MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
323 MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059
324 MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059
325 MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059
326 MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059
327 >;
328 };
329
330 pinctrl_usdhc3_2: usdhc3grp-2 {
331 fsl,pins = <
332 MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
333 MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
334 MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
335 MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
336 MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
337 MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
338 >;
339 };
340 };
341
342 usdhc4 {
343 pinctrl_usdhc4_1: usdhc4grp-1 {
344 fsl,pins = <
345 MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
346 MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
347 MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
348 MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
349 MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
350 MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
351 MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059
352 MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059
353 MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059
354 MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059
355 >;
356 };
357
358 pinctrl_usdhc4_2: usdhc4grp-2 {
359 fsl,pins = <
360 MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
361 MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
362 MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
363 MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
364 MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
365 MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
366 >;
367 };
368 };
369
370 weim {
371 pinctrl_weim_cs0_1: weim_cs0grp-1 {
372 fsl,pins = <
373 MX6Q_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
374 >;
375 };
376
377 pinctrl_weim_nor_1: weimnorgrp-1 {
378 fsl,pins = <
379 MX6Q_PAD_EIM_OE__EIM_OE_B 0xb0b1
380 MX6Q_PAD_EIM_RW__EIM_RW 0xb0b1
381 MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
382 /* data */
383 MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0
384 MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0
385 MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0
386 MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0
387 MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0
388 MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0
389 MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0
390 MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0
391 MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0
392 MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0
393 MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0
394 MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0
395 MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0
396 MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0
397 MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0
398 MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0
399 /* address */
400 MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1
401 MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1
402 MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1
403 MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1
404 MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1
405 MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1
406 MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
407 MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
408 MX6Q_PAD_EIM_DA15__EIM_AD15 0xb0b1
409 MX6Q_PAD_EIM_DA14__EIM_AD14 0xb0b1
410 MX6Q_PAD_EIM_DA13__EIM_AD13 0xb0b1
411 MX6Q_PAD_EIM_DA12__EIM_AD12 0xb0b1
412 MX6Q_PAD_EIM_DA11__EIM_AD11 0xb0b1
413 MX6Q_PAD_EIM_DA10__EIM_AD10 0xb0b1
414 MX6Q_PAD_EIM_DA9__EIM_AD09 0xb0b1
415 MX6Q_PAD_EIM_DA8__EIM_AD08 0xb0b1
416 MX6Q_PAD_EIM_DA7__EIM_AD07 0xb0b1
417 MX6Q_PAD_EIM_DA6__EIM_AD06 0xb0b1
418 MX6Q_PAD_EIM_DA5__EIM_AD05 0xb0b1
419 MX6Q_PAD_EIM_DA4__EIM_AD04 0xb0b1
420 MX6Q_PAD_EIM_DA3__EIM_AD03 0xb0b1
421 MX6Q_PAD_EIM_DA2__EIM_AD02 0xb0b1
422 MX6Q_PAD_EIM_DA1__EIM_AD01 0xb0b1
423 MX6Q_PAD_EIM_DA0__EIM_AD00 0xb0b1
424 >;
425 };
426
427 };
428 }; 122 };
429 }; 123 };
430 124
125 sata: sata@02200000 {
126 compatible = "fsl,imx6q-ahci";
127 reg = <0x02200000 0x4000>;
128 interrupts = <0 39 0x04>;
129 clocks = <&clks 154>, <&clks 187>, <&clks 105>;
130 clock-names = "sata", "sata_ref", "ahb";
131 status = "disabled";
132 };
133
431 ipu2: ipu@02800000 { 134 ipu2: ipu@02800000 {
432 #crtc-cells = <1>; 135 #crtc-cells = <1>;
433 compatible = "fsl,imx6q-ipu"; 136 compatible = "fsl,imx6q-ipu";
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index e994011220e7..1cbbc5160d27 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -45,6 +45,28 @@
45 status = "okay"; 45 status = "okay";
46}; 46};
47 47
48&iomuxc {
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_hog>;
51
52 hog {
53 pinctrl_hog: hoggrp {
54 fsl,pins = <
55 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
56 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
57 >;
58 };
59 };
60
61 ecspi1 {
62 pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
63 fsl,pins = <
64 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
65 >;
66 };
67 };
68};
69
48&uart4 { 70&uart4 {
49 pinctrl-names = "default"; 71 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_uart4_1>; 72 pinctrl-0 = <&pinctrl_uart4_1>;
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 6e5dfdb32416..39eafc222a2e 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -27,6 +27,15 @@
27 enable-active-high; 27 enable-active-high;
28 }; 28 };
29 29
30 reg_usb_h1_vbus: usb_h1_vbus {
31 compatible = "regulator-fixed";
32 regulator-name = "usb_h1_vbus";
33 regulator-min-microvolt = <5000000>;
34 regulator-max-microvolt = <5000000>;
35 gpio = <&gpio1 29 0>;
36 enable-active-high;
37 };
38
30 reg_audio: wm8962_supply { 39 reg_audio: wm8962_supply {
31 compatible = "regulator-fixed"; 40 compatible = "regulator-fixed";
32 regulator-name = "wm8962-supply"; 41 regulator-name = "wm8962-supply";
@@ -41,12 +50,14 @@
41 volume-up { 50 volume-up {
42 label = "Volume Up"; 51 label = "Volume Up";
43 gpios = <&gpio1 4 0>; 52 gpios = <&gpio1 4 0>;
53 gpio-key,wakeup;
44 linux,code = <115>; /* KEY_VOLUMEUP */ 54 linux,code = <115>; /* KEY_VOLUMEUP */
45 }; 55 };
46 56
47 volume-down { 57 volume-down {
48 label = "Volume Down"; 58 label = "Volume Down";
49 gpios = <&gpio1 5 0>; 59 gpios = <&gpio1 5 0>;
60 gpio-key,wakeup;
50 linux,code = <114>; /* KEY_VOLUMEDOWN */ 61 linux,code = <114>; /* KEY_VOLUMEDOWN */
51 }; 62 };
52 }; 63 };
@@ -77,6 +88,22 @@
77 status = "okay"; 88 status = "okay";
78}; 89};
79 90
91&ecspi1 {
92 fsl,spi-num-chipselects = <1>;
93 cs-gpios = <&gpio4 9 0>;
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_ecspi1_2>;
96 status = "okay";
97
98 flash: m25p80@0 {
99 #address-cells = <1>;
100 #size-cells = <1>;
101 compatible = "st,m25p32";
102 spi-max-frequency = <20000000>;
103 reg = <0>;
104 };
105};
106
80&fec { 107&fec {
81 pinctrl-names = "default"; 108 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_enet_1>; 109 pinctrl-0 = <&pinctrl_enet_1>;
@@ -93,7 +120,7 @@
93 codec: wm8962@1a { 120 codec: wm8962@1a {
94 compatible = "wlf,wm8962"; 121 compatible = "wlf,wm8962";
95 reg = <0x1a>; 122 reg = <0x1a>;
96 clocks = <&clks 169>; 123 clocks = <&clks 201>;
97 DCVDD-supply = <&reg_audio>; 124 DCVDD-supply = <&reg_audio>;
98 DBVDD-supply = <&reg_audio>; 125 DBVDD-supply = <&reg_audio>;
99 AVDD-supply = <&reg_audio>; 126 AVDD-supply = <&reg_audio>;
@@ -113,6 +140,68 @@
113 }; 140 };
114}; 141};
115 142
143&i2c3 {
144 clock-frequency = <100000>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_i2c3_2>;
147 status = "okay";
148
149 egalax_ts@04 {
150 compatible = "eeti,egalax_ts";
151 reg = <0x04>;
152 interrupt-parent = <&gpio6>;
153 interrupts = <7 2>;
154 wakeup-gpios = <&gpio6 7 0>;
155 };
156};
157
158&iomuxc {
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_hog>;
161
162 hog {
163 pinctrl_hog: hoggrp {
164 fsl,pins = <
165 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
166 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
167 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
168 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
169 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
170 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
171 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
172 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
173 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
174 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
175 >;
176 };
177 };
178};
179
180&ldb {
181 status = "okay";
182
183 lvds-channel@1 {
184 fsl,data-mapping = "spwg";
185 fsl,data-width = <18>;
186 status = "okay";
187
188 display-timings {
189 native-mode = <&timing0>;
190 timing0: hsd100pxn1 {
191 clock-frequency = <65000000>;
192 hactive = <1024>;
193 vactive = <768>;
194 hback-porch = <220>;
195 hfront-porch = <40>;
196 vback-porch = <21>;
197 vfront-porch = <7>;
198 hsync-len = <60>;
199 vsync-len = <10>;
200 };
201 };
202 };
203};
204
116&ssi2 { 205&ssi2 {
117 fsl,mode = "i2s-slave"; 206 fsl,mode = "i2s-slave";
118 status = "okay"; 207 status = "okay";
@@ -125,6 +214,7 @@
125}; 214};
126 215
127&usbh1 { 216&usbh1 {
217 vbus-supply = <&reg_usb_h1_vbus>;
128 status = "okay"; 218 status = "okay";
129}; 219};
130 220
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
new file mode 100644
index 000000000000..a55113e65bcb
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -0,0 +1,137 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12/ {
13 regulators {
14 compatible = "simple-bus";
15
16 reg_2p5v: 2p5v {
17 compatible = "regulator-fixed";
18 regulator-name = "2P5V";
19 regulator-min-microvolt = <2500000>;
20 regulator-max-microvolt = <2500000>;
21 regulator-always-on;
22 };
23
24 reg_3p3v: 3p3v {
25 compatible = "regulator-fixed";
26 regulator-name = "3P3V";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 regulator-always-on;
30 };
31 };
32
33 sound {
34 compatible = "fsl,imx6-wandboard-sgtl5000",
35 "fsl,imx-audio-sgtl5000";
36 model = "imx6-wandboard-sgtl5000";
37 ssi-controller = <&ssi1>;
38 audio-codec = <&codec>;
39 audio-routing =
40 "MIC_IN", "Mic Jack",
41 "Mic Jack", "Mic Bias",
42 "Headphone Jack", "HP_OUT";
43 mux-int-port = <1>;
44 mux-ext-port = <3>;
45 };
46};
47
48&audmux {
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_audmux_2>;
51 status = "okay";
52};
53
54&i2c2 {
55 clock-frequency = <100000>;
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_i2c2_2>;
58 status = "okay";
59
60 codec: sgtl5000@0a {
61 compatible = "fsl,sgtl5000";
62 reg = <0x0a>;
63 clocks = <&clks 201>;
64 VDDA-supply = <&reg_2p5v>;
65 VDDIO-supply = <&reg_3p3v>;
66 };
67};
68
69&iomuxc {
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_hog>;
72
73 hog {
74 pinctrl_hog: hoggrp {
75 fsl,pins = <
76 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
77 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
78 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
79 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000 /* WL_REF_ON */
80 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 /* WL_RST_N */
81 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* WL_REG_ON */
82 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */
83 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */
84 >;
85 };
86 };
87};
88
89&fec {
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_enet_1>;
92 phy-mode = "rgmii";
93 status = "okay";
94};
95
96&ssi1 {
97 fsl,mode = "i2s-slave";
98 status = "okay";
99};
100
101&uart1 {
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_uart1_1>;
104 status = "okay";
105};
106
107&uart3 {
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_uart3_2>;
110 fsl,uart-has-rtscts;
111 status = "okay";
112};
113
114&usbh1 {
115 status = "okay";
116};
117
118&usdhc1 {
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_usdhc1_2>;
121 cd-gpios = <&gpio1 2 0>;
122 status = "okay";
123};
124
125&usdhc2 {
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_usdhc2_2>;
128 non-removable;
129 status = "okay";
130};
131
132&usdhc3 {
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_usdhc3_2>;
135 cd-gpios = <&gpio3 9 0>;
136 status = "okay";
137};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index f21d259080fd..ccd55c2fdb67 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -14,11 +14,6 @@
14 14
15/ { 15/ {
16 aliases { 16 aliases {
17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
22 gpio0 = &gpio1; 17 gpio0 = &gpio1;
23 gpio1 = &gpio2; 18 gpio1 = &gpio2;
24 gpio2 = &gpio3; 19 gpio2 = &gpio3;
@@ -26,6 +21,18 @@
26 gpio4 = &gpio5; 21 gpio4 = &gpio5;
27 gpio5 = &gpio6; 22 gpio5 = &gpio6;
28 gpio6 = &gpio7; 23 gpio6 = &gpio7;
24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 serial0 = &uart1;
28 serial1 = &uart2;
29 serial2 = &uart3;
30 serial3 = &uart4;
31 serial4 = &uart5;
32 spi0 = &ecspi1;
33 spi1 = &ecspi2;
34 spi2 = &ecspi3;
35 spi3 = &ecspi4;
29 }; 36 };
30 37
31 intc: interrupt-controller@00a01000 { 38 intc: interrupt-controller@00a01000 {
@@ -81,15 +88,14 @@
81 #size-cells = <1>; 88 #size-cells = <1>;
82 reg = <0x00112000 0x2000>, <0x00114000 0x2000>; 89 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
83 reg-names = "gpmi-nand", "bch"; 90 reg-names = "gpmi-nand", "bch";
84 interrupts = <0 13 0x04>, <0 15 0x04>; 91 interrupts = <0 15 0x04>;
85 interrupt-names = "gpmi-dma", "bch"; 92 interrupt-names = "bch";
86 clocks = <&clks 152>, <&clks 153>, <&clks 151>, 93 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
87 <&clks 150>, <&clks 149>; 94 <&clks 150>, <&clks 149>;
88 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 95 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
89 "gpmi_bch_apb", "per1_bch"; 96 "gpmi_bch_apb", "per1_bch";
90 dmas = <&dma_apbh 0>; 97 dmas = <&dma_apbh 0>;
91 dma-names = "rx-tx"; 98 dma-names = "rx-tx";
92 fsl,gpmi-dma-channel = <0>;
93 status = "disabled"; 99 status = "disabled";
94 }; 100 };
95 101
@@ -184,6 +190,8 @@
184 interrupts = <0 26 0x04>; 190 interrupts = <0 26 0x04>;
185 clocks = <&clks 160>, <&clks 161>; 191 clocks = <&clks 160>, <&clks 161>;
186 clock-names = "ipg", "per"; 192 clock-names = "ipg", "per";
193 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
194 dma-names = "rx", "tx";
187 status = "disabled"; 195 status = "disabled";
188 }; 196 };
189 197
@@ -197,6 +205,9 @@
197 reg = <0x02028000 0x4000>; 205 reg = <0x02028000 0x4000>;
198 interrupts = <0 46 0x04>; 206 interrupts = <0 46 0x04>;
199 clocks = <&clks 178>; 207 clocks = <&clks 178>;
208 dmas = <&sdma 37 1 0>,
209 <&sdma 38 1 0>;
210 dma-names = "rx", "tx";
200 fsl,fifo-depth = <15>; 211 fsl,fifo-depth = <15>;
201 fsl,ssi-dma-events = <38 37>; 212 fsl,ssi-dma-events = <38 37>;
202 status = "disabled"; 213 status = "disabled";
@@ -207,6 +218,9 @@
207 reg = <0x0202c000 0x4000>; 218 reg = <0x0202c000 0x4000>;
208 interrupts = <0 47 0x04>; 219 interrupts = <0 47 0x04>;
209 clocks = <&clks 179>; 220 clocks = <&clks 179>;
221 dmas = <&sdma 41 1 0>,
222 <&sdma 42 1 0>;
223 dma-names = "rx", "tx";
210 fsl,fifo-depth = <15>; 224 fsl,fifo-depth = <15>;
211 fsl,ssi-dma-events = <42 41>; 225 fsl,ssi-dma-events = <42 41>;
212 status = "disabled"; 226 status = "disabled";
@@ -217,6 +231,9 @@
217 reg = <0x02030000 0x4000>; 231 reg = <0x02030000 0x4000>;
218 interrupts = <0 48 0x04>; 232 interrupts = <0 48 0x04>;
219 clocks = <&clks 180>; 233 clocks = <&clks 180>;
234 dmas = <&sdma 45 1 0>,
235 <&sdma 46 1 0>;
236 dma-names = "rx", "tx";
220 fsl,fifo-depth = <15>; 237 fsl,fifo-depth = <15>;
221 fsl,ssi-dma-events = <46 45>; 238 fsl,ssi-dma-events = <46 45>;
222 status = "disabled"; 239 status = "disabled";
@@ -278,17 +295,23 @@
278 }; 295 };
279 296
280 can1: flexcan@02090000 { 297 can1: flexcan@02090000 {
298 compatible = "fsl,imx6q-flexcan";
281 reg = <0x02090000 0x4000>; 299 reg = <0x02090000 0x4000>;
282 interrupts = <0 110 0x04>; 300 interrupts = <0 110 0x04>;
301 clocks = <&clks 108>, <&clks 109>;
302 clock-names = "ipg", "per";
283 }; 303 };
284 304
285 can2: flexcan@02094000 { 305 can2: flexcan@02094000 {
306 compatible = "fsl,imx6q-flexcan";
286 reg = <0x02094000 0x4000>; 307 reg = <0x02094000 0x4000>;
287 interrupts = <0 111 0x04>; 308 interrupts = <0 111 0x04>;
309 clocks = <&clks 110>, <&clks 111>;
310 clock-names = "ipg", "per";
288 }; 311 };
289 312
290 gpt: gpt@02098000 { 313 gpt: gpt@02098000 {
291 compatible = "fsl,imx6q-gpt"; 314 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
292 reg = <0x02098000 0x4000>; 315 reg = <0x02098000 0x4000>;
293 interrupts = <0 55 0x04>; 316 interrupts = <0 55 0x04>;
294 clocks = <&clks 119>, <&clks 120>; 317 clocks = <&clks 119>, <&clks 120>;
@@ -491,6 +514,13 @@
491 }; 514 };
492 }; 515 };
493 516
517 tempmon: tempmon {
518 compatible = "fsl,imx6q-tempmon";
519 interrupts = <0 49 0x04>;
520 fsl,tempmon = <&anatop>;
521 fsl,tempmon-data = <&ocotp>;
522 };
523
494 usbphy1: usbphy@020c9000 { 524 usbphy1: usbphy@020c9000 {
495 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 525 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
496 reg = <0x020c9000 0x1000>; 526 reg = <0x020c9000 0x1000>;
@@ -546,6 +576,713 @@
546 reg = <0x020e0000 0x38>; 576 reg = <0x020e0000 0x38>;
547 }; 577 };
548 578
579 iomuxc: iomuxc@020e0000 {
580 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
581 reg = <0x020e0000 0x4000>;
582
583 audmux {
584 pinctrl_audmux_1: audmux-1 {
585 fsl,pins = <
586 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000
587 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000
588 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000
589 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
590 >;
591 };
592
593 pinctrl_audmux_2: audmux-2 {
594 fsl,pins = <
595 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
596 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
597 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
598 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
599 >;
600 };
601
602 pinctrl_audmux_3: audmux-3 {
603 fsl,pins = <
604 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000
605 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
606 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000
607 >;
608 };
609 };
610
611 ecspi1 {
612 pinctrl_ecspi1_1: ecspi1grp-1 {
613 fsl,pins = <
614 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
615 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
616 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
617 >;
618 };
619
620 pinctrl_ecspi1_2: ecspi1grp-2 {
621 fsl,pins = <
622 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
623 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
624 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
625 >;
626 };
627 };
628
629 ecspi3 {
630 pinctrl_ecspi3_1: ecspi3grp-1 {
631 fsl,pins = <
632 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
633 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
634 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
635 >;
636 };
637 };
638
639 enet {
640 pinctrl_enet_1: enetgrp-1 {
641 fsl,pins = <
642 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
643 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
644 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
645 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
646 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
647 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
648 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
649 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
650 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
651 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
652 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
653 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
654 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
655 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
656 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
657 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
658 >;
659 };
660
661 pinctrl_enet_2: enetgrp-2 {
662 fsl,pins = <
663 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
664 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
665 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
666 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
667 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
668 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
669 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
670 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
671 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
672 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
673 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
674 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
675 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
676 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
677 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
678 >;
679 };
680
681 pinctrl_enet_3: enetgrp-3 {
682 fsl,pins = <
683 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
684 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
685 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
686 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
687 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
688 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
689 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
690 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
691 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
692 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
693 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
694 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
695 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
696 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
697 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
698 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
699 >;
700 };
701 };
702
703 esai {
704 pinctrl_esai_1: esaigrp-1 {
705 fsl,pins = <
706 MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
707 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
708 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
709 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
710 MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030
711 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
712 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
713 MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030
714 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
715 >;
716 };
717
718 pinctrl_esai_2: esaigrp-2 {
719 fsl,pins = <
720 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
721 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
722 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
723 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
724 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
725 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
726 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
727 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
728 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
729 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
730 >;
731 };
732 };
733
734 flexcan1 {
735 pinctrl_flexcan1_1: flexcan1grp-1 {
736 fsl,pins = <
737 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
738 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
739 >;
740 };
741
742 pinctrl_flexcan1_2: flexcan1grp-2 {
743 fsl,pins = <
744 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
745 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
746 >;
747 };
748 };
749
750 flexcan2 {
751 pinctrl_flexcan2_1: flexcan2grp-1 {
752 fsl,pins = <
753 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
754 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
755 >;
756 };
757 };
758
759 gpmi-nand {
760 pinctrl_gpmi_nand_1: gpmi-nand-1 {
761 fsl,pins = <
762 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
763 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
764 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
765 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
766 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
767 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
768 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
769 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
770 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
771 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
772 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
773 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
774 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
775 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
776 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
777 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
778 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
779 >;
780 };
781 };
782
783 hdmi_hdcp {
784 pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
785 fsl,pins = <
786 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
787 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
788 >;
789 };
790
791 pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
792 fsl,pins = <
793 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
794 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
795 >;
796 };
797
798 pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
799 fsl,pins = <
800 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
801 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
802 >;
803 };
804 };
805
806 hdmi_cec {
807 pinctrl_hdmi_cec_1: hdmicecgrp-1 {
808 fsl,pins = <
809 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
810 >;
811 };
812
813 pinctrl_hdmi_cec_2: hdmicecgrp-2 {
814 fsl,pins = <
815 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
816 >;
817 };
818 };
819
820 i2c1 {
821 pinctrl_i2c1_1: i2c1grp-1 {
822 fsl,pins = <
823 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
824 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
825 >;
826 };
827
828 pinctrl_i2c1_2: i2c1grp-2 {
829 fsl,pins = <
830 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
831 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
832 >;
833 };
834 };
835
836 i2c2 {
837 pinctrl_i2c2_1: i2c2grp-1 {
838 fsl,pins = <
839 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
840 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
841 >;
842 };
843
844 pinctrl_i2c2_2: i2c2grp-2 {
845 fsl,pins = <
846 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
847 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
848 >;
849 };
850
851 pinctrl_i2c2_3: i2c2grp-3 {
852 fsl,pins = <
853 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
854 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
855 >;
856 };
857 };
858
859 i2c3 {
860 pinctrl_i2c3_1: i2c3grp-1 {
861 fsl,pins = <
862 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
863 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
864 >;
865 };
866
867 pinctrl_i2c3_2: i2c3grp-2 {
868 fsl,pins = <
869 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
870 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
871 >;
872 };
873
874 pinctrl_i2c3_3: i2c3grp-3 {
875 fsl,pins = <
876 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
877 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
878 >;
879 };
880
881 pinctrl_i2c3_4: i2c3grp-4 {
882 fsl,pins = <
883 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
884 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
885 >;
886 };
887 };
888
889 ipu1 {
890 pinctrl_ipu1_1: ipu1grp-1 {
891 fsl,pins = <
892 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
893 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
894 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
895 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
896 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
897 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
898 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
899 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
900 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
901 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
902 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
903 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
904 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
905 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
906 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
907 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
908 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
909 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
910 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
911 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
912 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
913 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
914 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
915 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
916 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
917 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
918 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
919 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
920 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
921 >;
922 };
923
924 pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
925 fsl,pins = <
926 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
927 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
928 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
929 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
930 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
931 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
932 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
933 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
934 MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
935 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
936 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
937 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
938 >;
939 };
940
941 pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
942 fsl,pins = <
943 MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
944 MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
945 MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
946 MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
947 MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
948 MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
949 MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
950 MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
951 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
952 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
953 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
954 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
955 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
956 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
957 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
958 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
959 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
960 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
961 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
962 >;
963 };
964 };
965
966 mlb {
967 pinctrl_mlb_1: mlbgrp-1 {
968 fsl,pins = <
969 MX6QDL_PAD_GPIO_3__MLB_CLK 0x71
970 MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
971 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
972 >;
973 };
974
975 pinctrl_mlb_2: mlbgrp-2 {
976 fsl,pins = <
977 MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71
978 MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
979 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
980 >;
981 };
982 };
983
984 pwm0 {
985 pinctrl_pwm0_1: pwm0grp-1 {
986 fsl,pins = <
987 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
988 >;
989 };
990 };
991
992 pwm3 {
993 pinctrl_pwm3_1: pwm3grp-1 {
994 fsl,pins = <
995 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
996 >;
997 };
998 };
999
1000 spdif {
1001 pinctrl_spdif_1: spdifgrp-1 {
1002 fsl,pins = <
1003 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
1004 >;
1005 };
1006
1007 pinctrl_spdif_2: spdifgrp-2 {
1008 fsl,pins = <
1009 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
1010 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
1011 >;
1012 };
1013 };
1014
1015 uart1 {
1016 pinctrl_uart1_1: uart1grp-1 {
1017 fsl,pins = <
1018 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1019 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1020 >;
1021 };
1022 };
1023
1024 uart2 {
1025 pinctrl_uart2_1: uart2grp-1 {
1026 fsl,pins = <
1027 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
1028 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
1029 >;
1030 };
1031
1032 pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
1033 fsl,pins = <
1034 MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
1035 MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
1036 MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
1037 MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
1038 >;
1039 };
1040 };
1041
1042 uart3 {
1043 pinctrl_uart3_1: uart3grp-1 {
1044 fsl,pins = <
1045 MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
1046 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
1047 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
1048 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
1049 >;
1050 };
1051
1052 pinctrl_uart3_2: uart3grp-2 {
1053 fsl,pins = <
1054 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
1055 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
1056 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
1057 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
1058 >;
1059 };
1060 };
1061
1062 uart4 {
1063 pinctrl_uart4_1: uart4grp-1 {
1064 fsl,pins = <
1065 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
1066 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
1067 >;
1068 };
1069 };
1070
1071 usbotg {
1072 pinctrl_usbotg_1: usbotggrp-1 {
1073 fsl,pins = <
1074 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
1075 >;
1076 };
1077
1078 pinctrl_usbotg_2: usbotggrp-2 {
1079 fsl,pins = <
1080 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
1081 >;
1082 };
1083 };
1084
1085 usbh2 {
1086 pinctrl_usbh2_1: usbh2grp-1 {
1087 fsl,pins = <
1088 MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030
1089 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
1090 >;
1091 };
1092
1093 pinctrl_usbh2_2: usbh2grp-2 {
1094 fsl,pins = <
1095 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
1096 >;
1097 };
1098 };
1099
1100 usbh3 {
1101 pinctrl_usbh3_1: usbh3grp-1 {
1102 fsl,pins = <
1103 MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
1104 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030
1105 >;
1106 };
1107
1108 pinctrl_usbh3_2: usbh3grp-2 {
1109 fsl,pins = <
1110 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
1111 >;
1112 };
1113 };
1114
1115 usdhc1 {
1116 pinctrl_usdhc1_1: usdhc1grp-1 {
1117 fsl,pins = <
1118 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
1119 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
1120 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1121 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1122 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1123 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1124 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
1125 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
1126 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
1127 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
1128 >;
1129 };
1130
1131 pinctrl_usdhc1_2: usdhc1grp-2 {
1132 fsl,pins = <
1133 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
1134 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
1135 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1136 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1137 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1138 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1139 >;
1140 };
1141 };
1142
1143 usdhc2 {
1144 pinctrl_usdhc2_1: usdhc2grp-1 {
1145 fsl,pins = <
1146 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
1147 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
1148 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1149 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1150 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1151 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1152 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
1153 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
1154 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
1155 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
1156 >;
1157 };
1158
1159 pinctrl_usdhc2_2: usdhc2grp-2 {
1160 fsl,pins = <
1161 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
1162 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
1163 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1164 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1165 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1166 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1167 >;
1168 };
1169 };
1170
1171 usdhc3 {
1172 pinctrl_usdhc3_1: usdhc3grp-1 {
1173 fsl,pins = <
1174 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1175 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1176 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1177 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1178 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1179 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1180 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
1181 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
1182 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
1183 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
1184 >;
1185 };
1186
1187 pinctrl_usdhc3_2: usdhc3grp-2 {
1188 fsl,pins = <
1189 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1190 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1191 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1192 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1193 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1194 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1195 >;
1196 };
1197 };
1198
1199 usdhc4 {
1200 pinctrl_usdhc4_1: usdhc4grp-1 {
1201 fsl,pins = <
1202 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1203 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1204 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1205 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1206 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1207 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1208 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
1209 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
1210 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
1211 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
1212 >;
1213 };
1214
1215 pinctrl_usdhc4_2: usdhc4grp-2 {
1216 fsl,pins = <
1217 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1218 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1219 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1220 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1221 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1222 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1223 >;
1224 };
1225 };
1226
1227 weim {
1228 pinctrl_weim_cs0_1: weim_cs0grp-1 {
1229 fsl,pins = <
1230 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
1231 >;
1232 };
1233
1234 pinctrl_weim_nor_1: weim_norgrp-1 {
1235 fsl,pins = <
1236 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
1237 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
1238 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
1239 /* data */
1240 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
1241 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
1242 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
1243 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
1244 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
1245 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
1246 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
1247 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
1248 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
1249 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
1250 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
1251 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
1252 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
1253 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
1254 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
1255 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
1256 /* address */
1257 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
1258 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
1259 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
1260 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
1261 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
1262 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
1263 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
1264 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
1265 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
1266 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
1267 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
1268 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
1269 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
1270 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
1271 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
1272 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
1273 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
1274 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
1275 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
1276 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
1277 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
1278 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
1279 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
1280 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
1281 >;
1282 };
1283 };
1284 };
1285
549 ldb: ldb@020e0008 { 1286 ldb: ldb@020e0008 {
550 #address-cells = <1>; 1287 #address-cells = <1>;
551 #size-cells = <0>; 1288 #size-cells = <0>;
@@ -555,13 +1292,11 @@
555 1292
556 lvds-channel@0 { 1293 lvds-channel@0 {
557 reg = <0>; 1294 reg = <0>;
558 crtcs = <&ipu1 0>;
559 status = "disabled"; 1295 status = "disabled";
560 }; 1296 };
561 1297
562 lvds-channel@1 { 1298 lvds-channel@1 {
563 reg = <1>; 1299 reg = <1>;
564 crtcs = <&ipu1 1>;
565 status = "disabled"; 1300 status = "disabled";
566 }; 1301 };
567 }; 1302 };
@@ -582,6 +1317,7 @@
582 interrupts = <0 2 0x04>; 1317 interrupts = <0 2 0x04>;
583 clocks = <&clks 155>, <&clks 155>; 1318 clocks = <&clks 155>, <&clks 155>;
584 clock-names = "ipg", "ahb"; 1319 clock-names = "ipg", "ahb";
1320 #dma-cells = <3>;
585 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 1321 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
586 }; 1322 };
587 }; 1323 };
@@ -751,8 +1487,8 @@
751 clocks = <&clks 196>; 1487 clocks = <&clks 196>;
752 }; 1488 };
753 1489
754 ocotp@021bc000 { 1490 ocotp: ocotp@021bc000 {
755 compatible = "fsl,imx6q-ocotp"; 1491 compatible = "fsl,imx6q-ocotp", "syscon";
756 reg = <0x021bc000 0x4000>; 1492 reg = <0x021bc000 0x4000>;
757 }; 1493 };
758 1494
@@ -791,6 +1527,8 @@
791 interrupts = <0 27 0x04>; 1527 interrupts = <0 27 0x04>;
792 clocks = <&clks 160>, <&clks 161>; 1528 clocks = <&clks 160>, <&clks 161>;
793 clock-names = "ipg", "per"; 1529 clock-names = "ipg", "per";
1530 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1531 dma-names = "rx", "tx";
794 status = "disabled"; 1532 status = "disabled";
795 }; 1533 };
796 1534
@@ -800,6 +1538,8 @@
800 interrupts = <0 28 0x04>; 1538 interrupts = <0 28 0x04>;
801 clocks = <&clks 160>, <&clks 161>; 1539 clocks = <&clks 160>, <&clks 161>;
802 clock-names = "ipg", "per"; 1540 clock-names = "ipg", "per";
1541 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1542 dma-names = "rx", "tx";
803 status = "disabled"; 1543 status = "disabled";
804 }; 1544 };
805 1545
@@ -809,6 +1549,8 @@
809 interrupts = <0 29 0x04>; 1549 interrupts = <0 29 0x04>;
810 clocks = <&clks 160>, <&clks 161>; 1550 clocks = <&clks 160>, <&clks 161>;
811 clock-names = "ipg", "per"; 1551 clock-names = "ipg", "per";
1552 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1553 dma-names = "rx", "tx";
812 status = "disabled"; 1554 status = "disabled";
813 }; 1555 };
814 1556
@@ -818,6 +1560,8 @@
818 interrupts = <0 30 0x04>; 1560 interrupts = <0 30 0x04>;
819 clocks = <&clks 160>, <&clks 161>; 1561 clocks = <&clks 160>, <&clks 161>;
820 clock-names = "ipg", "per"; 1562 clock-names = "ipg", "per";
1563 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1564 dma-names = "rx", "tx";
821 status = "disabled"; 1565 status = "disabled";
822 }; 1566 };
823 }; 1567 };
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index c5e5da02d7e3..c46651e4d966 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -152,32 +152,41 @@
152 }; 152 };
153 153
154 uart5: serial@02018000 { 154 uart5: serial@02018000 {
155 compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; 155 compatible = "fsl,imx6sl-uart",
156 "fsl,imx6q-uart", "fsl,imx21-uart";
156 reg = <0x02018000 0x4000>; 157 reg = <0x02018000 0x4000>;
157 interrupts = <0 30 0x04>; 158 interrupts = <0 30 0x04>;
158 clocks = <&clks IMX6SL_CLK_UART>, 159 clocks = <&clks IMX6SL_CLK_UART>,
159 <&clks IMX6SL_CLK_UART_SERIAL>; 160 <&clks IMX6SL_CLK_UART_SERIAL>;
160 clock-names = "ipg", "per"; 161 clock-names = "ipg", "per";
162 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
163 dma-names = "rx", "tx";
161 status = "disabled"; 164 status = "disabled";
162 }; 165 };
163 166
164 uart1: serial@02020000 { 167 uart1: serial@02020000 {
165 compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; 168 compatible = "fsl,imx6sl-uart",
169 "fsl,imx6q-uart", "fsl,imx21-uart";
166 reg = <0x02020000 0x4000>; 170 reg = <0x02020000 0x4000>;
167 interrupts = <0 26 0x04>; 171 interrupts = <0 26 0x04>;
168 clocks = <&clks IMX6SL_CLK_UART>, 172 clocks = <&clks IMX6SL_CLK_UART>,
169 <&clks IMX6SL_CLK_UART_SERIAL>; 173 <&clks IMX6SL_CLK_UART_SERIAL>;
170 clock-names = "ipg", "per"; 174 clock-names = "ipg", "per";
175 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
176 dma-names = "rx", "tx";
171 status = "disabled"; 177 status = "disabled";
172 }; 178 };
173 179
174 uart2: serial@02024000 { 180 uart2: serial@02024000 {
175 compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; 181 compatible = "fsl,imx6sl-uart",
182 "fsl,imx6q-uart", "fsl,imx21-uart";
176 reg = <0x02024000 0x4000>; 183 reg = <0x02024000 0x4000>;
177 interrupts = <0 27 0x04>; 184 interrupts = <0 27 0x04>;
178 clocks = <&clks IMX6SL_CLK_UART>, 185 clocks = <&clks IMX6SL_CLK_UART>,
179 <&clks IMX6SL_CLK_UART_SERIAL>; 186 <&clks IMX6SL_CLK_UART_SERIAL>;
180 clock-names = "ipg", "per"; 187 clock-names = "ipg", "per";
188 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
189 dma-names = "rx", "tx";
181 status = "disabled"; 190 status = "disabled";
182 }; 191 };
183 192
@@ -186,6 +195,9 @@
186 reg = <0x02028000 0x4000>; 195 reg = <0x02028000 0x4000>;
187 interrupts = <0 46 0x04>; 196 interrupts = <0 46 0x04>;
188 clocks = <&clks IMX6SL_CLK_SSI1>; 197 clocks = <&clks IMX6SL_CLK_SSI1>;
198 dmas = <&sdma 37 1 0>,
199 <&sdma 38 1 0>;
200 dma-names = "rx", "tx";
189 fsl,fifo-depth = <15>; 201 fsl,fifo-depth = <15>;
190 status = "disabled"; 202 status = "disabled";
191 }; 203 };
@@ -195,6 +207,9 @@
195 reg = <0x0202c000 0x4000>; 207 reg = <0x0202c000 0x4000>;
196 interrupts = <0 47 0x04>; 208 interrupts = <0 47 0x04>;
197 clocks = <&clks IMX6SL_CLK_SSI2>; 209 clocks = <&clks IMX6SL_CLK_SSI2>;
210 dmas = <&sdma 41 1 0>,
211 <&sdma 42 1 0>;
212 dma-names = "rx", "tx";
198 fsl,fifo-depth = <15>; 213 fsl,fifo-depth = <15>;
199 status = "disabled"; 214 status = "disabled";
200 }; 215 };
@@ -204,27 +219,36 @@
204 reg = <0x02030000 0x4000>; 219 reg = <0x02030000 0x4000>;
205 interrupts = <0 48 0x04>; 220 interrupts = <0 48 0x04>;
206 clocks = <&clks IMX6SL_CLK_SSI3>; 221 clocks = <&clks IMX6SL_CLK_SSI3>;
222 dmas = <&sdma 45 1 0>,
223 <&sdma 46 1 0>;
224 dma-names = "rx", "tx";
207 fsl,fifo-depth = <15>; 225 fsl,fifo-depth = <15>;
208 status = "disabled"; 226 status = "disabled";
209 }; 227 };
210 228
211 uart3: serial@02034000 { 229 uart3: serial@02034000 {
212 compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; 230 compatible = "fsl,imx6sl-uart",
231 "fsl,imx6q-uart", "fsl,imx21-uart";
213 reg = <0x02034000 0x4000>; 232 reg = <0x02034000 0x4000>;
214 interrupts = <0 28 0x04>; 233 interrupts = <0 28 0x04>;
215 clocks = <&clks IMX6SL_CLK_UART>, 234 clocks = <&clks IMX6SL_CLK_UART>,
216 <&clks IMX6SL_CLK_UART_SERIAL>; 235 <&clks IMX6SL_CLK_UART_SERIAL>;
217 clock-names = "ipg", "per"; 236 clock-names = "ipg", "per";
237 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
238 dma-names = "rx", "tx";
218 status = "disabled"; 239 status = "disabled";
219 }; 240 };
220 241
221 uart4: serial@02038000 { 242 uart4: serial@02038000 {
222 compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; 243 compatible = "fsl,imx6sl-uart",
244 "fsl,imx6q-uart", "fsl,imx21-uart";
223 reg = <0x02038000 0x4000>; 245 reg = <0x02038000 0x4000>;
224 interrupts = <0 29 0x04>; 246 interrupts = <0 29 0x04>;
225 clocks = <&clks IMX6SL_CLK_UART>, 247 clocks = <&clks IMX6SL_CLK_UART>,
226 <&clks IMX6SL_CLK_UART_SERIAL>; 248 <&clks IMX6SL_CLK_UART_SERIAL>;
227 clock-names = "ipg", "per"; 249 clock-names = "ipg", "per";
250 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
251 dma-names = "rx", "tx";
228 status = "disabled"; 252 status = "disabled";
229 }; 253 };
230 }; 254 };
@@ -594,6 +618,7 @@
594 clocks = <&clks IMX6SL_CLK_SDMA>, 618 clocks = <&clks IMX6SL_CLK_SDMA>,
595 <&clks IMX6SL_CLK_SDMA>; 619 <&clks IMX6SL_CLK_SDMA>;
596 clock-names = "ipg", "ahb"; 620 clock-names = "ipg", "ahb";
621 #dma-cells = <3>;
597 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin"; 622 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin";
598 }; 623 };
599 624
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
index 1e5bef0bead7..650ef30e1856 100644
--- a/arch/arm/boot/dts/kirkwood-6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
@@ -1,4 +1,39 @@
1/ { 1/ {
2 mbus {
3 pcie-controller {
4 compatible = "marvell,kirkwood-pcie";
5 status = "disabled";
6 device_type = "pci";
7
8 #address-cells = <3>;
9 #size-cells = <2>;
10
11 bus-range = <0x00 0xff>;
12
13 ranges =
14 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
15 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
16 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
17
18 pcie@1,0 {
19 device_type = "pci";
20 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
21 reg = <0x0800 0 0 0 0>;
22 #address-cells = <3>;
23 #size-cells = <2>;
24 #interrupt-cells = <1>;
25 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
26 0x81000000 0 0 0x81000000 0x1 0 1 0>;
27 interrupt-map-mask = <0 0 0 0>;
28 interrupt-map = <0 0 0 0 &intc 9>;
29 marvell,pcie-port = <0>;
30 marvell,pcie-lane = <0>;
31 clocks = <&gate_clk 2>;
32 status = "disabled";
33 };
34 };
35 };
36
2 ocp@f1000000 { 37 ocp@f1000000 {
3 pinctrl: pinctrl@10000 { 38 pinctrl: pinctrl@10000 {
4 compatible = "marvell,88f6281-pinctrl"; 39 compatible = "marvell,88f6281-pinctrl";
@@ -41,37 +76,6 @@
41 }; 76 };
42 }; 77 };
43 78
44 pcie-controller {
45 compatible = "marvell,kirkwood-pcie";
46 status = "disabled";
47 device_type = "pci";
48
49 #address-cells = <3>;
50 #size-cells = <2>;
51
52 bus-range = <0x00 0xff>;
53
54 ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */
55 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
56 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
57
58 pcie@1,0 {
59 device_type = "pci";
60 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
61 reg = <0x0800 0 0 0 0>;
62 #address-cells = <3>;
63 #size-cells = <2>;
64 #interrupt-cells = <1>;
65 ranges;
66 interrupt-map-mask = <0 0 0 0>;
67 interrupt-map = <0 0 0 0 &intc 9>;
68 marvell,pcie-port = <0>;
69 marvell,pcie-lane = <0>;
70 clocks = <&gate_clk 2>;
71 status = "disabled";
72 };
73 };
74
75 rtc@10300 { 79 rtc@10300 {
76 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; 80 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
77 reg = <0x10300 0x20>; 81 reg = <0x10300 0x20>;
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index a63a11137262..3933a331ddc2 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -1,4 +1,59 @@
1/ { 1/ {
2 mbus {
3 pcie-controller {
4 compatible = "marvell,kirkwood-pcie";
5 status = "disabled";
6 device_type = "pci";
7
8 #address-cells = <3>;
9 #size-cells = <2>;
10
11 bus-range = <0x00 0xff>;
12
13 ranges =
14 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
15 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
16 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
17 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
18 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
19 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */
20 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>;
21
22 pcie@1,0 {
23 device_type = "pci";
24 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
25 reg = <0x0800 0 0 0 0>;
26 #address-cells = <3>;
27 #size-cells = <2>;
28 #interrupt-cells = <1>;
29 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
30 0x81000000 0 0 0x81000000 0x1 0 1 0>;
31 interrupt-map-mask = <0 0 0 0>;
32 interrupt-map = <0 0 0 0 &intc 9>;
33 marvell,pcie-port = <0>;
34 marvell,pcie-lane = <0>;
35 clocks = <&gate_clk 2>;
36 status = "disabled";
37 };
38
39 pcie@2,0 {
40 device_type = "pci";
41 assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
42 reg = <0x1000 0 0 0 0>;
43 #address-cells = <3>;
44 #size-cells = <2>;
45 #interrupt-cells = <1>;
46 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
47 0x81000000 0 0 0x81000000 0x2 0 1 0>;
48 interrupt-map-mask = <0 0 0 0>;
49 interrupt-map = <0 0 0 0 &intc 10>;
50 marvell,pcie-port = <1>;
51 marvell,pcie-lane = <0>;
52 clocks = <&gate_clk 18>;
53 status = "disabled";
54 };
55 };
56 };
2 ocp@f1000000 { 57 ocp@f1000000 {
3 58
4 pinctrl: pinctrl@10000 { 59 pinctrl: pinctrl@10000 {
@@ -94,52 +149,5 @@
94 status = "disabled"; 149 status = "disabled";
95 }; 150 };
96 151
97 pcie-controller {
98 compatible = "marvell,kirkwood-pcie";
99 status = "disabled";
100 device_type = "pci";
101
102 #address-cells = <3>;
103 #size-cells = <2>;
104
105 bus-range = <0x00 0xff>;
106
107 ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */
108 0x82000000 0 0x00044000 0x00044000 0 0x00002000 /* Port 1.0 registers */
109 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
110 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
111
112 pcie@1,0 {
113 device_type = "pci";
114 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
115 reg = <0x0800 0 0 0 0>;
116 #address-cells = <3>;
117 #size-cells = <2>;
118 #interrupt-cells = <1>;
119 ranges;
120 interrupt-map-mask = <0 0 0 0>;
121 interrupt-map = <0 0 0 0 &intc 9>;
122 marvell,pcie-port = <0>;
123 marvell,pcie-lane = <0>;
124 clocks = <&gate_clk 2>;
125 status = "disabled";
126 };
127
128 pcie@2,0 {
129 device_type = "pci";
130 assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
131 reg = <0x1000 0 0 0 0>;
132 #address-cells = <3>;
133 #size-cells = <2>;
134 #interrupt-cells = <1>;
135 ranges;
136 interrupt-map-mask = <0 0 0 0>;
137 interrupt-map = <0 0 0 0 &intc 10>;
138 marvell,pcie-port = <1>;
139 marvell,pcie-lane = <0>;
140 clocks = <&gate_clk 18>;
141 status = "disabled";
142 };
143 };
144 }; 152 };
145}; 153};
diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts
index 00c48d26de68..9bf139c5a34d 100644
--- a/arch/arm/boot/dts/kirkwood-cloudbox.dts
+++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi" 4#include "kirkwood-6281.dtsi"
5 5
6/ { 6/ {
7 model = "LaCie CloudBox"; 7 model = "LaCie CloudBox";
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
index 9d777edd1f36..72c4b0a0366f 100644
--- a/arch/arm/boot/dts/kirkwood-db-88f6281.dts
+++ b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
@@ -11,14 +11,15 @@
11 11
12/dts-v1/; 12/dts-v1/;
13 13
14/include/ "kirkwood-db.dtsi" 14#include "kirkwood-db.dtsi"
15/include/ "kirkwood-6281.dtsi" 15#include "kirkwood-6281.dtsi"
16 16
17/ { 17/ {
18 model = "Marvell DB-88F6281-BP Development Board"; 18 model = "Marvell DB-88F6281-BP Development Board";
19 compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood"; 19 compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood";
20 20
21 ocp@f1000000 { 21 mbus {
22 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
22 pcie-controller { 23 pcie-controller {
23 status = "okay"; 24 status = "okay";
24 25
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
index f4c852886d23..36c411d34926 100644
--- a/arch/arm/boot/dts/kirkwood-db-88f6282.dts
+++ b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
@@ -11,14 +11,15 @@
11 11
12/dts-v1/; 12/dts-v1/;
13 13
14/include/ "kirkwood-db.dtsi" 14#include "kirkwood-db.dtsi"
15/include/ "kirkwood-6282.dtsi" 15#include "kirkwood-6282.dtsi"
16 16
17/ { 17/ {
18 model = "Marvell DB-88F6282-BP Development Board"; 18 model = "Marvell DB-88F6282-BP Development Board";
19 compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood"; 19 compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood";
20 20
21 ocp@f1000000 { 21 mbus {
22 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
22 pcie-controller { 23 pcie-controller {
23 status = "okay"; 24 status = "okay";
24 25
diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi
index c87cfb816120..45c1bf74ac00 100644
--- a/arch/arm/boot/dts/kirkwood-db.dtsi
+++ b/arch/arm/boot/dts/kirkwood-db.dtsi
@@ -12,7 +12,7 @@
12 * and 6282 variants of the Marvell Kirkwood Development Board. 12 * and 6282 variants of the Marvell Kirkwood Development Board.
13 */ 13 */
14 14
15/include/ "kirkwood.dtsi" 15#include "kirkwood.dtsi"
16 16
17/ { 17/ {
18 memory { 18 memory {
@@ -77,13 +77,5 @@
77 cd-gpios = <&gpio1 6 0>; 77 cd-gpios = <&gpio1 6 0>;
78 status = "okay"; 78 status = "okay";
79 }; 79 };
80
81 pcie-controller {
82 status = "okay";
83
84 pcie@1,0 {
85 status = "okay";
86 };
87 };
88 }; 80 };
89}; 81};
diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
index 14d4ceea3057..e112ca62d978 100644
--- a/arch/arm/boot/dts/kirkwood-dns320.dts
+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood-dnskw.dtsi" 3#include "kirkwood-dnskw.dtsi"
4 4
5/ { 5/ {
6 model = "D-Link DNS-320 NAS (Rev A1)"; 6 model = "D-Link DNS-320 NAS (Rev A1)";
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
index 63872570e6ce..5119fb8a8eb6 100644
--- a/arch/arm/boot/dts/kirkwood-dns325.dts
+++ b/arch/arm/boot/dts/kirkwood-dns325.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood-dnskw.dtsi" 3#include "kirkwood-dnskw.dtsi"
4 4
5/ { 5/ {
6 model = "D-Link DNS-325 NAS (Rev A1)"; 6 model = "D-Link DNS-325 NAS (Rev A1)";
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index 0afe1d07c803..2e04284846a0 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -1,5 +1,5 @@
1/include/ "kirkwood.dtsi" 1#include "kirkwood.dtsi"
2/include/ "kirkwood-6281.dtsi" 2#include "kirkwood-6281.dtsi"
3 3
4/ { 4/ {
5 model = "D-Link DNS NASes (kirkwood-based)"; 5 model = "D-Link DNS NASes (kirkwood-based)";
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
index 7714742bb8d8..4387ae8e93fe 100644
--- a/arch/arm/boot/dts/kirkwood-dockstar.dts
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi" 4#include "kirkwood-6281.dtsi"
5 5
6/ { 6/ {
7 model = "Seagate FreeAgent Dockstar"; 7 model = "Seagate FreeAgent Dockstar";
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 36c7ba38d500..c62837837246 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi" 4#include "kirkwood-6281.dtsi"
5 5
6/ { 6/ {
7 model = "Globalscale Technologies Dreamplug"; 7 model = "Globalscale Technologies Dreamplug";
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index 31caa6405065..e57118039277 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi" 4#include "kirkwood-6281.dtsi"
5 5
6/ { 6/ {
7 model = "Seagate GoFlex Net"; 7 model = "Seagate GoFlex Net";
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index 1e642f39b154..2c5673adb4bd 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi" 4#include "kirkwood-6281.dtsi"
5 5
6/ { 6/ {
7 model = "Globalscale Technologies Guruplug Server Plus"; 7 model = "Globalscale Technologies Guruplug Server Plus";
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
index 20c4b081f420..158161ff6826 100644
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi" 4#include "kirkwood-6281.dtsi"
5 5
6/ { 6/ {
7 model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; 7 model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)";
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 441204e8abc6..8314118b6b8a 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi" 4#include "kirkwood-6281.dtsi"
5 5
6/ { 6/ {
7 model = "Iomega Iconnect"; 7 model = "Iomega Iconnect";
@@ -18,6 +18,17 @@
18 linux,initrd-end = <0x4800000>; 18 linux,initrd-end = <0x4800000>;
19 }; 19 };
20 20
21 mbus {
22 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
23 pcie-controller {
24 status = "okay";
25
26 pcie@1,0 {
27 status = "okay";
28 };
29 };
30 };
31
21 ocp@f1000000 { 32 ocp@f1000000 {
22 pinctrl: pinctrl@10000 { 33 pinctrl: pinctrl@10000 {
23 pmx_button_reset: pmx-button-reset { 34 pmx_button_reset: pmx-button-reset {
@@ -101,14 +112,6 @@
101 reg = <0x980000 0x1f400000>; 112 reg = <0x980000 0x1f400000>;
102 }; 113 };
103 }; 114 };
104
105 pcie-controller {
106 status = "okay";
107
108 pcie@1,0 {
109 status = "okay";
110 };
111 };
112 }; 115 };
113 116
114 gpio-leds { 117 gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
index 00a7bfe5e83b..fd7f053e9c96 100644
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi" 4#include "kirkwood-6281.dtsi"
5 5
6/ { 6/ {
7 model = "Iomega StorCenter ix2-200"; 7 model = "Iomega StorCenter ix2-200";
diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/kirkwood-is2.dts
index c3f036b86cca..bd88a236f729 100644
--- a/arch/arm/boot/dts/kirkwood-is2.dts
+++ b/arch/arm/boot/dts/kirkwood-is2.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood-ns2-common.dtsi" 3#include "kirkwood-ns2-common.dtsi"
4 4
5/ { 5/ {
6 model = "LaCie Internet Space v2"; 6 model = "LaCie Internet Space v2";
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
index 5d9f5ea78700..b071d37cc291 100644
--- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-98dx4122.dtsi" 4#include "kirkwood-98dx4122.dtsi"
5 5
6/ { 6/ {
7 model = "Keymile Kirkwood Reference Design"; 7 model = "Keymile Kirkwood Reference Design";
diff --git a/arch/arm/boot/dts/kirkwood-lschlv2.dts b/arch/arm/boot/dts/kirkwood-lschlv2.dts
index 9f55d95f35f5..e2fa368aef25 100644
--- a/arch/arm/boot/dts/kirkwood-lschlv2.dts
+++ b/arch/arm/boot/dts/kirkwood-lschlv2.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood-lsxl.dtsi" 3#include "kirkwood-lsxl.dtsi"
4 4
5/ { 5/ {
6 model = "Buffalo Linkstation LS-CHLv2"; 6 model = "Buffalo Linkstation LS-CHLv2";
diff --git a/arch/arm/boot/dts/kirkwood-lsxhl.dts b/arch/arm/boot/dts/kirkwood-lsxhl.dts
index 5c84c118ed8d..8d89cdf8d6bf 100644
--- a/arch/arm/boot/dts/kirkwood-lsxhl.dts
+++ b/arch/arm/boot/dts/kirkwood-lsxhl.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood-lsxl.dtsi" 3#include "kirkwood-lsxl.dtsi"
4 4
5/ { 5/ {
6 model = "Buffalo Linkstation LS-XHL"; 6 model = "Buffalo Linkstation LS-XHL";
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
index 31b17f5b9d28..f7e247cc925a 100644
--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
@@ -1,5 +1,5 @@
1/include/ "kirkwood.dtsi" 1#include "kirkwood.dtsi"
2/include/ "kirkwood-6281.dtsi" 2#include "kirkwood-6281.dtsi"
3 3
4/ { 4/ {
5 chosen { 5 chosen {
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
index 6179333fd71f..21f1954c9e54 100644
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi" 4#include "kirkwood-6281.dtsi"
5 5
6/ { 6/ {
7 model = "MPL CEC4"; 7 model = "MPL CEC4";
@@ -16,6 +16,17 @@
16 bootargs = "console=ttyS0,115200n8 earlyprintk"; 16 bootargs = "console=ttyS0,115200n8 earlyprintk";
17 }; 17 };
18 18
19 mbus {
20 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
21 pcie-controller {
22 status = "okay";
23
24 pcie@1,0 {
25 status = "okay";
26 };
27 };
28 };
29
19 ocp@f1000000 { 30 ocp@f1000000 {
20 pinctrl: pinctrl@10000 { 31 pinctrl: pinctrl@10000 {
21 pmx_led_health: pmx-led-health { 32 pmx_led_health: pmx-led-health {
@@ -134,14 +145,6 @@
134 cd-gpios = <&gpio1 15 1>; 145 cd-gpios = <&gpio1 15 1>;
135 /* No WP GPIO */ 146 /* No WP GPIO */
136 }; 147 };
137
138 pcie-controller {
139 status = "okay";
140
141 pcie@1,0 {
142 status = "okay";
143 };
144 };
145 }; 148 };
146 149
147 gpio-leds { 150 gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
index ad6ade7d9191..cc40f19ae3fc 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6282.dtsi" 4#include "kirkwood-6282.dtsi"
5 5
6/ { 6/ {
7 model = "NETGEAR ReadyNAS Duo v2"; 7 model = "NETGEAR ReadyNAS Duo v2";
@@ -16,6 +16,17 @@
16 bootargs = "console=ttyS0,115200n8 earlyprintk"; 16 bootargs = "console=ttyS0,115200n8 earlyprintk";
17 }; 17 };
18 18
19 mbus {
20 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
21 pcie-controller {
22 status = "okay";
23
24 pcie@1,0 {
25 status = "okay";
26 };
27 };
28 };
29
19 ocp@f1000000 { 30 ocp@f1000000 {
20 pinctrl: pinctrl@10000 { 31 pinctrl: pinctrl@10000 {
21 pmx_button_power: pmx-button-power { 32 pmx_button_power: pmx-button-power {
@@ -52,6 +63,17 @@
52 }; 63 };
53 }; 64 };
54 65
66 clocks {
67 #address-cells = <1>;
68 #size-cells = <0>;
69
70 g762_clk: fixedclk {
71 compatible = "fixed-clock";
72 #clock-cells = <0>;
73 clock-frequency = <8192>;
74 };
75 };
76
55 i2c@11000 { 77 i2c@11000 {
56 status = "okay"; 78 status = "okay";
57 79
@@ -59,6 +81,15 @@
59 compatible = "ricoh,rs5c372a"; 81 compatible = "ricoh,rs5c372a";
60 reg = <0x32>; 82 reg = <0x32>;
61 }; 83 };
84
85 g762: g762@3e {
86 compatible = "gmt,g762";
87 reg = <0x3e>;
88 clocks = <&g762_clk>; /* input clock */
89 fan_gear_mode = <0>;
90 fan_startv = <1>;
91 pwm_polarity = <0>;
92 };
62 }; 93 };
63 94
64 serial@12000 { 95 serial@12000 {
@@ -101,14 +132,6 @@
101 status = "okay"; 132 status = "okay";
102 nr-ports = <2>; 133 nr-ports = <2>;
103 }; 134 };
104
105 pcie-controller {
106 status = "okay";
107
108 pcie@1,0 {
109 status = "okay";
110 };
111 };
112 }; 135 };
113 136
114 gpio-leds { 137 gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
index 2afac0405816..d0fb34dc1667 100644
--- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
@@ -1,5 +1,5 @@
1/include/ "kirkwood.dtsi" 1#include "kirkwood.dtsi"
2/include/ "kirkwood-6281.dtsi" 2#include "kirkwood-6281.dtsi"
3 3
4/ { 4/ {
5 chosen { 5 chosen {
diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/kirkwood-ns2.dts
index b50e93d7796c..0599f3cb844e 100644
--- a/arch/arm/boot/dts/kirkwood-ns2.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood-ns2-common.dtsi" 3#include "kirkwood-ns2-common.dtsi"
4 4
5/ { 5/ {
6 model = "LaCie Network Space v2"; 6 model = "LaCie Network Space v2";
diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts
index af8259fe8955..b0e17984aea0 100644
--- a/arch/arm/boot/dts/kirkwood-ns2lite.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood-ns2-common.dtsi" 3#include "kirkwood-ns2-common.dtsi"
4 4
5/ { 5/ {
6 model = "LaCie Network Space Lite v2"; 6 model = "LaCie Network Space Lite v2";
diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts
index 85f24d227e17..d4f6a586d553 100644
--- a/arch/arm/boot/dts/kirkwood-ns2max.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2max.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood-ns2-common.dtsi" 3#include "kirkwood-ns2-common.dtsi"
4 4
5/ { 5/ {
6 model = "LaCie Network Space Max v2"; 6 model = "LaCie Network Space Max v2";
diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts
index 329e530bffe7..f30e05af6473 100644
--- a/arch/arm/boot/dts/kirkwood-ns2mini.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood-ns2-common.dtsi" 3#include "kirkwood-ns2-common.dtsi"
4 4
5/ { 5/ {
6 /* This machine is embedded in the first LaCie CloudBox product. */ 6 /* This machine is embedded in the first LaCie CloudBox product. */
diff --git a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi
new file mode 100644
index 000000000000..06267a91de38
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi
@@ -0,0 +1,107 @@
1#include "kirkwood.dtsi"
2#include "kirkwood-6281.dtsi"
3
4/ {
5 model = "ZyXEL NSA310";
6
7 ocp@f1000000 {
8 pinctrl: pinctrl@10000 {
9
10 pmx_usb_power_off: pmx-usb-power-off {
11 marvell,pins = "mpp21";
12 marvell,function = "gpio";
13 };
14 pmx_pwr_off: pmx-pwr-off {
15 marvell,pins = "mpp48";
16 marvell,function = "gpio";
17 };
18
19 };
20
21 serial@12000 {
22 status = "ok";
23 };
24
25 sata@80000 {
26 status = "okay";
27 nr-ports = <2>;
28 };
29
30 nand@3000000 {
31 status = "okay";
32 chip-delay = <35>;
33
34 partition@0 {
35 label = "uboot";
36 reg = <0x0000000 0x0100000>;
37 read-only;
38 };
39 partition@100000 {
40 label = "uboot_env";
41 reg = <0x0100000 0x0080000>;
42 };
43 partition@180000 {
44 label = "key_store";
45 reg = <0x0180000 0x0080000>;
46 };
47 partition@200000 {
48 label = "info";
49 reg = <0x0200000 0x0080000>;
50 };
51 partition@280000 {
52 label = "etc";
53 reg = <0x0280000 0x0a00000>;
54 };
55 partition@c80000 {
56 label = "kernel_1";
57 reg = <0x0c80000 0x0a00000>;
58 };
59 partition@1680000 {
60 label = "rootfs1";
61 reg = <0x1680000 0x2fc0000>;
62 };
63 partition@4640000 {
64 label = "kernel_2";
65 reg = <0x4640000 0x0a00000>;
66 };
67 partition@5040000 {
68 label = "rootfs2";
69 reg = <0x5040000 0x2fc0000>;
70 };
71 };
72
73 pcie-controller {
74 status = "okay";
75
76 pcie@1,0 {
77 status = "okay";
78 };
79 };
80 };
81
82 gpio_poweroff {
83 compatible = "gpio-poweroff";
84 pinctrl-0 = <&pmx_pwr_off>;
85 pinctrl-names = "default";
86 gpios = <&gpio1 16 0>;
87 };
88
89 regulators {
90 compatible = "simple-bus";
91 #address-cells = <1>;
92 #size-cells = <0>;
93 pinctrl-0 = <&pmx_usb_power_off>;
94 pinctrl-names = "default";
95
96 usb0_power_off: regulator@1 {
97 compatible = "regulator-fixed";
98 reg = <1>;
99 regulator-name = "USB Power Off";
100 regulator-min-microvolt = <5000000>;
101 regulator-max-microvolt = <5000000>;
102 regulator-always-on;
103 regulator-boot-on;
104 gpio = <&gpio0 21 0>;
105 };
106 };
107};
diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts
index 69003598f5fa..7aeae0c2c1f4 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
@@ -1,10 +1,8 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood-nsa310-common.dtsi"
4/include/ "kirkwood-6281.dtsi"
5 4
6/ { 5/ {
7 model = "ZyXEL NSA310";
8 compatible = "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; 6 compatible = "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood";
9 7
10 memory { 8 memory {
@@ -16,6 +14,17 @@
16 bootargs = "console=ttyS0,115200"; 14 bootargs = "console=ttyS0,115200";
17 }; 15 };
18 16
17 mbus {
18 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
19 pcie-controller {
20 status = "okay";
21
22 pcie@1,0 {
23 status = "okay";
24 };
25 };
26 };
27
19 ocp@f1000000 { 28 ocp@f1000000 {
20 pinctrl: pinctrl@10000 { 29 pinctrl: pinctrl@10000 {
21 pinctrl-0 = <&pmx_unknown>; 30 pinctrl-0 = <&pmx_unknown>;
@@ -41,11 +50,6 @@
41 marvell,function = "gpio"; 50 marvell,function = "gpio";
42 }; 51 };
43 52
44 pmx_usb_power_off: pmx-usb-power-off {
45 marvell,pins = "mpp21";
46 marvell,function = "gpio";
47 };
48
49 pmx_led_sys_green: pmx-led-sys-green { 53 pmx_led_sys_green: pmx-led-sys-green {
50 marvell,pins = "mpp28"; 54 marvell,pins = "mpp28";
51 marvell,function = "gpio"; 55 marvell,function = "gpio";
@@ -95,20 +99,6 @@
95 marvell,pins = "mpp46"; 99 marvell,pins = "mpp46";
96 marvell,function = "gpio"; 100 marvell,function = "gpio";
97 }; 101 };
98
99 pmx_pwr_off: pmx-pwr-off {
100 marvell,pins = "mpp48";
101 marvell,function = "gpio";
102 };
103 };
104
105 serial@12000 {
106 status = "ok";
107 };
108
109 sata@80000 {
110 status = "okay";
111 nr-ports = <2>;
112 }; 102 };
113 103
114 i2c@11000 { 104 i2c@11000 {
@@ -119,57 +109,6 @@
119 reg = <0x2e>; 109 reg = <0x2e>;
120 }; 110 };
121 }; 111 };
122
123 nand@3000000 {
124 status = "okay";
125 chip-delay = <35>;
126
127 partition@0 {
128 label = "uboot";
129 reg = <0x0000000 0x0100000>;
130 read-only;
131 };
132 partition@100000 {
133 label = "uboot_env";
134 reg = <0x0100000 0x0080000>;
135 };
136 partition@180000 {
137 label = "key_store";
138 reg = <0x0180000 0x0080000>;
139 };
140 partition@200000 {
141 label = "info";
142 reg = <0x0200000 0x0080000>;
143 };
144 partition@280000 {
145 label = "etc";
146 reg = <0x0280000 0x0a00000>;
147 };
148 partition@c80000 {
149 label = "kernel_1";
150 reg = <0x0c80000 0x0a00000>;
151 };
152 partition@1680000 {
153 label = "rootfs1";
154 reg = <0x1680000 0x2fc0000>;
155 };
156 partition@4640000 {
157 label = "kernel_2";
158 reg = <0x4640000 0x0a00000>;
159 };
160 partition@5040000 {
161 label = "rootfs2";
162 reg = <0x5040000 0x2fc0000>;
163 };
164 };
165
166 pcie-controller {
167 status = "okay";
168
169 pcie@1,0 {
170 status = "okay";
171 };
172 };
173 }; 112 };
174 113
175 gpio_keys { 114 gpio_keys {
@@ -246,30 +185,4 @@
246 gpios = <&gpio1 8 0>; 185 gpios = <&gpio1 8 0>;
247 }; 186 };
248 }; 187 };
249
250 gpio_poweroff {
251 compatible = "gpio-poweroff";
252 pinctrl-0 = <&pmx_pwr_off>;
253 pinctrl-names = "default";
254 gpios = <&gpio1 16 0>;
255 };
256
257 regulators {
258 compatible = "simple-bus";
259 #address-cells = <1>;
260 #size-cells = <0>;
261 pinctrl-0 = <&pmx_usb_power_off>;
262 pinctrl-names = "default";
263
264 usb0_power_off: regulator@1 {
265 compatible = "regulator-fixed";
266 reg = <1>;
267 regulator-name = "USB Power Off";
268 regulator-min-microvolt = <5000000>;
269 regulator-max-microvolt = <5000000>;
270 regulator-always-on;
271 regulator-boot-on;
272 gpio = <&gpio0 21 0>;
273 };
274 };
275}; 188};
diff --git a/arch/arm/boot/dts/kirkwood-nsa310a.dts b/arch/arm/boot/dts/kirkwood-nsa310a.dts
new file mode 100644
index 000000000000..ab0212b0e6f5
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-nsa310a.dts
@@ -0,0 +1,165 @@
1/dts-v1/;
2
3#include "kirkwood-nsa310-common.dtsi"
4
5/*
6 * There are at least two different NSA310 designs. This variant does
7 * not have the red USB Led.
8 */
9
10/ {
11 compatible = "zyxel,nsa310a", "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood";
12
13 memory {
14 device_type = "memory";
15 reg = <0x00000000 0x10000000>;
16 };
17
18 chosen {
19 bootargs = "console=ttyS0,115200";
20 };
21
22 ocp@f1000000 {
23 pinctrl: pinctrl@10000 {
24 pinctrl-names = "default";
25
26 pmx_led_esata_green: pmx-led-esata-green {
27 marvell,pins = "mpp12";
28 marvell,function = "gpio";
29 };
30
31 pmx_led_esata_red: pmx-led-esata-red {
32 marvell,pins = "mpp13";
33 marvell,function = "gpio";
34 };
35
36 pmx_led_usb_green: pmx-led-usb-green {
37 marvell,pins = "mpp15";
38 marvell,function = "gpio";
39 };
40
41 pmx_usb_power_off: pmx-usb-power-off {
42 marvell,pins = "mpp21";
43 marvell,function = "gpio";
44 };
45
46 pmx_led_sys_green: pmx-led-sys-green {
47 marvell,pins = "mpp28";
48 marvell,function = "gpio";
49 };
50
51 pmx_led_sys_red: pmx-led-sys-red {
52 marvell,pins = "mpp29";
53 marvell,function = "gpio";
54 };
55
56 pmx_btn_reset: pmx-btn-reset {
57 marvell,pins = "mpp36";
58 marvell,function = "gpio";
59 };
60
61 pmx_btn_copy: pmx-btn-copy {
62 marvell,pins = "mpp37";
63 marvell,function = "gpio";
64 };
65
66 pmx_led_copy_green: pmx-led-copy-green {
67 marvell,pins = "mpp39";
68 marvell,function = "gpio";
69 };
70
71 pmx_led_copy_red: pmx-led-copy-red {
72 marvell,pins = "mpp40";
73 marvell,function = "gpio";
74 };
75
76 pmx_led_hdd_green: pmx-led-hdd-green {
77 marvell,pins = "mpp41";
78 marvell,function = "gpio";
79 };
80
81 pmx_led_hdd_red: pmx-led-hdd-red {
82 marvell,pins = "mpp42";
83 marvell,function = "gpio";
84 };
85
86 pmx_btn_power: pmx-btn-power {
87 marvell,pins = "mpp46";
88 marvell,function = "gpio";
89 };
90
91 };
92
93 i2c@11000 {
94 status = "okay";
95
96 lm85: lm85@2e {
97 compatible = "lm85";
98 reg = <0x2e>;
99 };
100 };
101 };
102
103 gpio_keys {
104 compatible = "gpio-keys";
105 #address-cells = <1>;
106 #size-cells = <0>;
107
108 button@1 {
109 label = "Power Button";
110 linux,code = <116>;
111 gpios = <&gpio1 14 0>;
112 };
113 button@2 {
114 label = "Copy Button";
115 linux,code = <133>;
116 gpios = <&gpio1 5 1>;
117 };
118 button@3 {
119 label = "Reset Button";
120 linux,code = <0x198>;
121 gpios = <&gpio1 4 1>;
122 };
123 };
124
125 gpio-leds {
126 compatible = "gpio-leds";
127
128 green-sys {
129 label = "nsa310:green:sys";
130 gpios = <&gpio0 28 0>;
131 };
132 red-sys {
133 label = "nsa310:red:sys";
134 gpios = <&gpio0 29 0>;
135 };
136 green-hdd {
137 label = "nsa310:green:hdd";
138 gpios = <&gpio1 9 0>;
139 };
140 red-hdd {
141 label = "nsa310:red:hdd";
142 gpios = <&gpio1 10 0>;
143 };
144 green-esata {
145 label = "nsa310:green:esata";
146 gpios = <&gpio0 12 0>;
147 };
148 red-esata {
149 label = "nsa310:red:esata";
150 gpios = <&gpio0 13 0>;
151 };
152 green-usb {
153 label = "nsa310:green:usb";
154 gpios = <&gpio0 15 0>;
155 };
156 green-copy {
157 label = "nsa310:green:copy";
158 gpios = <&gpio1 7 0>;
159 };
160 red-copy {
161 label = "nsa310:red:copy";
162 gpios = <&gpio1 8 0>;
163 };
164 };
165};
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
index 38dc8517d777..365b792b23a7 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6282.dtsi" 4#include "kirkwood-6282.dtsi"
5 5
6/ { 6/ {
7 model = "Plat'Home OpenBlocksA6"; 7 model = "Plat'Home OpenBlocksA6";
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
index f7143f128504..0cc5f26bbbb6 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
@@ -6,8 +6,8 @@
6 * Licensed under GPLv2 6 * Licensed under GPLv2
7 */ 7 */
8 8
9/include/ "kirkwood.dtsi" 9#include "kirkwood.dtsi"
10/include/ "kirkwood-6281.dtsi" 10#include "kirkwood-6281.dtsi"
11 11
12/ { 12/ {
13 memory { 13 memory {
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
index f620ce48de97..eac6a21f3b1f 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
@@ -8,7 +8,7 @@
8 8
9/dts-v1/; 9/dts-v1/;
10 10
11/include/ "kirkwood-sheevaplug-common.dtsi" 11#include "kirkwood-sheevaplug-common.dtsi"
12 12
13/ { 13/ {
14 model = "Globalscale Technologies eSATA SheevaPlug"; 14 model = "Globalscale Technologies eSATA SheevaPlug";
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
index bf1dff251432..bb61918313db 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug.dts
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
@@ -8,7 +8,7 @@
8 8
9/dts-v1/; 9/dts-v1/;
10 10
11/include/ "kirkwood-sheevaplug-common.dtsi" 11#include "kirkwood-sheevaplug-common.dtsi"
12 12
13/ { 13/ {
14 model = "Globalscale Technologies SheevaPlug"; 14 model = "Globalscale Technologies SheevaPlug";
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
index f2052d7bc10f..974f1e0f09b2 100644
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6282.dtsi" 4#include "kirkwood-6282.dtsi"
5 5
6/ { 6/ {
7 model = "Univeral Scientific Industrial Co. Topkick-1281P2"; 7 model = "Univeral Scientific Industrial Co. Topkick-1281P2";
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
index 6dd1038e4de4..3867ae3030be 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
@@ -1,8 +1,8 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi" 4#include "kirkwood-6281.dtsi"
5/include/ "kirkwood-ts219.dtsi" 5#include "kirkwood-ts219.dtsi"
6 6
7/ { 7/ {
8 ocp@f1000000 { 8 ocp@f1000000 {
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
index 6fdc5ffcaae5..04f6fe106bb5 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -1,10 +1,21 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6282.dtsi" 4#include "kirkwood-6282.dtsi"
5/include/ "kirkwood-ts219.dtsi" 5#include "kirkwood-ts219.dtsi"
6 6
7/ { 7/ {
8 mbus {
9 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
10 pcie-controller {
11 status = "okay";
12
13 pcie@2,0 {
14 status = "okay";
15 };
16 };
17 };
18
8 ocp@f1000000 { 19 ocp@f1000000 {
9 pinctrl: pinctrl@10000 { 20 pinctrl: pinctrl@10000 {
10 21
@@ -30,14 +41,6 @@
30 marvell,function = "gpio"; 41 marvell,function = "gpio";
31 }; 42 };
32 }; 43 };
33 pcie-controller {
34 status = "okay";
35
36 pcie@2,0 {
37 status = "okay";
38 };
39 };
40
41 }; 44 };
42 45
43 gpio_keys { 46 gpio_keys {
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
index 0c9a94cd666c..7019cf675df2 100644
--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
@@ -11,6 +11,16 @@
11 bootargs = "console=ttyS0,115200n8"; 11 bootargs = "console=ttyS0,115200n8";
12 }; 12 };
13 13
14 mbus {
15 pcie-controller {
16 status = "okay";
17
18 pcie@1,0 {
19 status = "okay";
20 };
21 };
22 };
23
14 ocp@f1000000 { 24 ocp@f1000000 {
15 i2c@11000 { 25 i2c@11000 {
16 status = "okay"; 26 status = "okay";
@@ -87,12 +97,5 @@
87 status = "okay"; 97 status = "okay";
88 nr-ports = <2>; 98 nr-ports = <2>;
89 }; 99 };
90 pcie-controller {
91 status = "okay";
92
93 pcie@1,0 {
94 status = "okay";
95 };
96 };
97 }; 100 };
98}; 101};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 9809fc1f105c..70f414d9bd9a 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -1,5 +1,7 @@
1/include/ "skeleton.dtsi" 1/include/ "skeleton.dtsi"
2 2
3#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
4
3/ { 5/ {
4 compatible = "marvell,kirkwood"; 6 compatible = "marvell,kirkwood";
5 interrupt-parent = <&intc>; 7 interrupt-parent = <&intc>;
@@ -28,15 +30,28 @@
28 <0xf1020214 0x04>; 30 <0xf1020214 0x04>;
29 }; 31 };
30 32
33 mbus {
34 compatible = "marvell,kirkwood-mbus", "simple-bus";
35 #address-cells = <2>;
36 #size-cells = <1>;
37 controller = <&mbusc>;
38 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
39 pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
40 };
41
31 ocp@f1000000 { 42 ocp@f1000000 {
32 compatible = "simple-bus"; 43 compatible = "simple-bus";
33 ranges = <0x00000000 0xf1000000 0x0100000 44 ranges = <0x00000000 0xf1000000 0x0100000
34 0xe0000000 0xe0000000 0x8100000 /* PCIE */
35 0xf4000000 0xf4000000 0x0000400 45 0xf4000000 0xf4000000 0x0000400
36 0xf5000000 0xf5000000 0x0000400>; 46 0xf5000000 0xf5000000 0x0000400>;
37 #address-cells = <1>; 47 #address-cells = <1>;
38 #size-cells = <1>; 48 #size-cells = <1>;
39 49
50 mbusc: mbus-controller@20000 {
51 compatible = "marvell,mbus-controller";
52 reg = <0x20000 0x80>, <0x1500 0x20>;
53 };
54
40 core_clk: core-clocks@10030 { 55 core_clk: core-clocks@10030 {
41 compatible = "marvell,kirkwood-core-clock"; 56 compatible = "marvell,kirkwood-core-clock";
42 reg = <0x10030 0x4>; 57 reg = <0x10030 0x4>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index d2803be4e1a8..759b0cd20013 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -125,6 +125,12 @@
125 clock-names = "apb_pclk"; 125 clock-names = "apb_pclk";
126 }; 126 };
127 127
128 scc@7fff0000 {
129 compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
130 reg = <0 0x7fff0000 0 0x1000>;
131 interrupts = <0 95 4>;
132 };
133
128 timer { 134 timer {
129 compatible = "arm,armv7-timer"; 135 compatible = "arm,armv7-timer";
130 interrupts = <1 13 0xf08>, 136 interrupts = <1 13 0xf08>,
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index b3905f5bcaf9..1a58678b93fa 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -50,6 +50,13 @@
50 status = "okay"; 50 status = "okay";
51}; 51};
52 52
53&i2c0 {
54 clock-frequency = <100000>;
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_i2c0_1>;
57 status = "okay";
58};
59
53&uart1 { 60&uart1 {
54 pinctrl-names = "default"; 61 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_uart1_1>; 62 pinctrl-0 = <&pinctrl_uart1_1>;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 01:43:34 -0500