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-rw-r--r--arch/arm/boot/dts/Makefile10
-rw-r--r--arch/arm/boot/dts/at91-cosino_mega2560.dts5
-rw-r--r--arch/arm/boot/dts/at91-sama5d3_xplained.dts8
-rw-r--r--arch/arm/boot/dts/at91sam9261.dtsi23
-rw-r--r--arch/arm/boot/dts/at91sam9261ek.dts4
-rw-r--r--arch/arm/boot/dts/at91sam9rl.dtsi46
-rw-r--r--arch/arm/boot/dts/at91sam9rlek.dts9
-rw-r--r--arch/arm/boot/dts/axm5516-amarillo.dts51
-rw-r--r--arch/arm/boot/dts/axm5516-cpus.dtsi204
-rw-r--r--arch/arm/boot/dts/axm55xx.dtsi204
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi18
-rw-r--r--arch/arm/boot/dts/exynos4210-universal_c210.dts15
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi18
-rw-r--r--arch/arm/boot/dts/exynos4412-trats2.dts79
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi18
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi18
-rw-r--r--arch/arm/boot/dts/exynos5420-peach-pit.dts147
-rw-r--r--arch/arm/boot/dts/exynos5420-pinctrl.dtsi28
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi85
-rw-r--r--arch/arm/boot/dts/omap3-evm-37xx.dts9
-rw-r--r--arch/arm/boot/dts/omap3-ldp.dts4
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts19
-rw-r--r--arch/arm/boot/dts/omap3.dtsi6
-rw-r--r--arch/arm/boot/dts/omap4-panda-common.dtsi15
-rw-r--r--arch/arm/boot/dts/omap4-sdp.dts6
-rw-r--r--arch/arm/boot/dts/omap4.dtsi6
-rw-r--r--arch/arm/boot/dts/orion5x-lacie-d2-network.dts236
-rw-r--r--arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts141
-rw-r--r--arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts178
-rw-r--r--arch/arm/boot/dts/orion5x-mv88f5182.dtsi45
-rw-r--r--arch/arm/boot/dts/orion5x-rd88f5182-nas.dts177
-rw-r--r--arch/arm/boot/dts/orion5x.dtsi289
-rw-r--r--arch/arm/boot/dts/r8a7740.dtsi1
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi2
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi2
-rw-r--r--arch/arm/boot/dts/rk3066a.dtsi1
-rw-r--r--arch/arm/boot/dts/rk3188.dtsi1
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi61
-rw-r--r--arch/arm/boot/dts/sama5d3xcm.dtsi8
-rw-r--r--arch/arm/boot/dts/twl4030_omap3.dtsi19
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi5
41 files changed, 2029 insertions, 192 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 377b7c364033..ff7a04b68d88 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -50,6 +50,7 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb
50dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb 50dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb
51 51
52dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb 52dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
53dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
53dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb 54dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
54dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb 55dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
55dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \ 56dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
@@ -73,6 +74,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
73 exynos5250-smdk5250.dtb \ 74 exynos5250-smdk5250.dtb \
74 exynos5250-snow.dtb \ 75 exynos5250-snow.dtb \
75 exynos5420-arndale-octa.dtb \ 76 exynos5420-arndale-octa.dtb \
77 exynos5420-peach-pit.dtb \
76 exynos5420-smdk5420.dtb \ 78 exynos5420-smdk5420.dtb \
77 exynos5440-sd5v1.dtb \ 79 exynos5440-sd5v1.dtb \
78 exynos5440-ssdk5440.dtb 80 exynos5440-ssdk5440.dtb
@@ -289,7 +291,10 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
289 am43x-epos-evm.dtb \ 291 am43x-epos-evm.dtb \
290 am437x-gp-evm.dtb \ 292 am437x-gp-evm.dtb \
291 dra7-evm.dtb 293 dra7-evm.dtb
292dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb 294dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \
295 orion5x-lacie-ethernet-disk-mini-v2.dtb \
296 orion5x-maxtor-shared-storage-2.dtb \
297 orion5x-rd88f5182-nas.dtb
293dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb 298dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
294dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \ 299dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
295 qcom-msm8960-cdp.dtb \ 300 qcom-msm8960-cdp.dtb \
@@ -297,8 +302,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
297dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb 302dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
298dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ 303dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
299 s3c6410-smdk6410.dtb 304 s3c6410-smdk6410.dtb
300dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \ 305dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
301 r7s72100-genmai.dtb \
302 r7s72100-genmai-reference.dtb \ 306 r7s72100-genmai-reference.dtb \
303 r8a7740-armadillo800eva.dtb \ 307 r8a7740-armadillo800eva.dtb \
304 r8a7778-bockw.dtb \ 308 r8a7778-bockw.dtb \
diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/at91-cosino_mega2560.dts
index a542d5837a17..27ebb0f722fd 100644
--- a/arch/arm/boot/dts/at91-cosino_mega2560.dts
+++ b/arch/arm/boot/dts/at91-cosino_mega2560.dts
@@ -32,11 +32,6 @@
32 status = "okay"; 32 status = "okay";
33 }; 33 };
34 34
35
36 tsadcc: tsadcc@f804c000 {
37 status = "okay";
38 };
39
40 rtc@fffffeb0 { 35 rtc@fffffeb0 {
41 status = "okay"; 36 status = "okay";
42 }; 37 };
diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
index 4537259ce529..099111bd4221 100644
--- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
@@ -21,6 +21,14 @@
21 reg = <0x20000000 0x10000000>; 21 reg = <0x20000000 0x10000000>;
22 }; 22 };
23 23
24 slow_xtal {
25 clock-frequency = <32768>;
26 };
27
28 main_xtal {
29 clock-frequency = <12000000>;
30 };
31
24 ahb { 32 ahb {
25 apb { 33 apb {
26 mmc0: mmc@f0000000 { 34 mmc0: mmc@f0000000 {
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index 3be973e9889a..80cdcecf0332 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -45,6 +45,18 @@
45 reg = <0x20000000 0x08000000>; 45 reg = <0x20000000 0x08000000>;
46 }; 46 };
47 47
48 main_xtal: main_xtal {
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
51 clock-frequency = <0>;
52 };
53
54 slow_xtal: slow_xtal {
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <0>;
58 };
59
48 ahb { 60 ahb {
49 compatible = "simple-bus"; 61 compatible = "simple-bus";
50 #address-cells = <1>; 62 #address-cells = <1>;
@@ -524,17 +536,24 @@
524 #size-cells = <0>; 536 #size-cells = <0>;
525 #interrupt-cells = <1>; 537 #interrupt-cells = <1>;
526 538
527 clk32k: slck { 539 slow_rc_osc: slow_rc_osc {
528 compatible = "fixed-clock"; 540 compatible = "fixed-clock";
529 #clock-cells = <0>; 541 #clock-cells = <0>;
530 clock-frequency = <32768>; 542 clock-frequency = <32768>;
543 clock-accuracy = <50000000>;
544 };
545
546 clk32k: slck {
547 compatible = "atmel,at91sam9260-clk-slow";
548 #clock-cells = <0>;
549 clocks = <&slow_rc_osc &slow_xtal>;
531 }; 550 };
532 551
533 main: mainck { 552 main: mainck {
534 compatible = "atmel,at91rm9200-clk-main"; 553 compatible = "atmel,at91rm9200-clk-main";
535 #clock-cells = <0>; 554 #clock-cells = <0>;
536 interrupts-extended = <&pmc AT91_PMC_MOSCS>; 555 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
537 clocks = <&clk32k>; 556 clocks = <&main_xtal>;
538 }; 557 };
539 558
540 plla: pllack { 559 plla: pllack {
diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts
index 2ce527e70c7a..c6683ea8b743 100644
--- a/arch/arm/boot/dts/at91sam9261ek.dts
+++ b/arch/arm/boot/dts/at91sam9261ek.dts
@@ -20,6 +20,10 @@
20 reg = <0x20000000 0x4000000>; 20 reg = <0x20000000 0x4000000>;
21 }; 21 };
22 22
23 main_xtal {
24 clock-frequency = <18432000>;
25 };
26
23 clocks { 27 clocks {
24 #address-cells = <1>; 28 #address-cells = <1>;
25 #size-cells = <1>; 29 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index 92a52faebef7..ae9c39a28c63 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -48,6 +48,18 @@
48 reg = <0x20000000 0x04000000>; 48 reg = <0x20000000 0x04000000>;
49 }; 49 };
50 50
51 slow_xtal: slow_xtal {
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <0>;
55 };
56
57 main_xtal: main_xtal {
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <0>;
61 };
62
51 ahb { 63 ahb {
52 compatible = "simple-bus"; 64 compatible = "simple-bus";
53 #address-cells = <1>; 65 #address-cells = <1>;
@@ -548,17 +560,11 @@
548 #size-cells = <0>; 560 #size-cells = <0>;
549 #interrupt-cells = <1>; 561 #interrupt-cells = <1>;
550 562
551 clk32k: slck {
552 compatible = "fixed-clock";
553 #clock-cells = <0>;
554 clock-frequency = <32768>;
555 };
556
557 main: mainck { 563 main: mainck {
558 compatible = "atmel,at91rm9200-clk-main"; 564 compatible = "atmel,at91rm9200-clk-main";
559 #clock-cells = <0>; 565 #clock-cells = <0>;
560 interrupts-extended = <&pmc AT91_PMC_MOSCS>; 566 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
561 clocks = <&clk32k>; 567 clocks = <&main_xtal>;
562 }; 568 };
563 569
564 plla: pllack { 570 plla: pllack {
@@ -769,6 +775,32 @@
769 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 775 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
770 status = "disabled"; 776 status = "disabled";
771 }; 777 };
778
779 sckc@fffffd50 {
780 compatible = "atmel,at91sam9x5-sckc";
781 reg = <0xfffffd50 0x4>;
782
783 slow_osc: slow_osc {
784 compatible = "atmel,at91sam9x5-clk-slow-osc";
785 #clock-cells = <0>;
786 atmel,startup-time-usec = <1200000>;
787 clocks = <&slow_xtal>;
788 };
789
790 slow_rc_osc: slow_rc_osc {
791 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
792 #clock-cells = <0>;
793 atmel,startup-time-usec = <75>;
794 clock-frequency = <32768>;
795 clock-accuracy = <50000000>;
796 };
797
798 clk32k: slck {
799 compatible = "atmel,at91sam9x5-clk-slow";
800 #clock-cells = <0>;
801 clocks = <&slow_rc_osc &slow_osc>;
802 };
803 };
772 }; 804 };
773 }; 805 };
774 806
diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts
index cddb37825fad..b3b89baf972e 100644
--- a/arch/arm/boot/dts/at91sam9rlek.dts
+++ b/arch/arm/boot/dts/at91sam9rlek.dts
@@ -20,6 +20,15 @@
20 reg = <0x20000000 0x4000000>; 20 reg = <0x20000000 0x4000000>;
21 }; 21 };
22 22
23
24 slow_xtal {
25 clock-frequency = <32768>;
26 };
27
28 main_xtal {
29 clock-frequency = <12000000>;
30 };
31
23 clocks { 32 clocks {
24 #address-cells = <1>; 33 #address-cells = <1>;
25 #size-cells = <1>; 34 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/axm5516-amarillo.dts b/arch/arm/boot/dts/axm5516-amarillo.dts
new file mode 100644
index 000000000000..a9d60471d9ff
--- /dev/null
+++ b/arch/arm/boot/dts/axm5516-amarillo.dts
@@ -0,0 +1,51 @@
1/*
2 * arch/arm/boot/dts/axm5516-amarillo.dts
3 *
4 * Copyright (C) 2013 LSI
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12/dts-v1/;
13
14/memreserve/ 0x00000000 0x00400000;
15
16#include "axm55xx.dtsi"
17#include "axm5516-cpus.dtsi"
18
19/ {
20 model = "Amarillo AXM5516";
21 compatible = "lsi,axm5516-amarillo", "lsi,axm5516";
22
23 memory {
24 device_type = "memory";
25 reg = <0 0x00000000 0x02 0x00000000>;
26 };
27};
28
29&serial0 {
30 status = "okay";
31};
32
33&serial1 {
34 status = "okay";
35};
36
37&serial2 {
38 status = "okay";
39};
40
41&serial3 {
42 status = "okay";
43};
44
45&gpio0 {
46 status = "okay";
47};
48
49&gpio1 {
50 status = "okay";
51};
diff --git a/arch/arm/boot/dts/axm5516-cpus.dtsi b/arch/arm/boot/dts/axm5516-cpus.dtsi
new file mode 100644
index 000000000000..b85f360cb125
--- /dev/null
+++ b/arch/arm/boot/dts/axm5516-cpus.dtsi
@@ -0,0 +1,204 @@
1/*
2 * arch/arm/boot/dts/axm5516-cpus.dtsi
3 *
4 * Copyright (C) 2013 LSI
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12/ {
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16
17 cpu-map {
18 cluster0 {
19 core0 {
20 cpu = <&CPU0>;
21 };
22 core1 {
23 cpu = <&CPU1>;
24 };
25 core2 {
26 cpu = <&CPU2>;
27 };
28 core3 {
29 cpu = <&CPU3>;
30 };
31 };
32 cluster1 {
33 core0 {
34 cpu = <&CPU4>;
35 };
36 core1 {
37 cpu = <&CPU5>;
38 };
39 core2 {
40 cpu = <&CPU6>;
41 };
42 core3 {
43 cpu = <&CPU7>;
44 };
45 };
46 cluster2 {
47 core0 {
48 cpu = <&CPU8>;
49 };
50 core1 {
51 cpu = <&CPU9>;
52 };
53 core2 {
54 cpu = <&CPU10>;
55 };
56 core3 {
57 cpu = <&CPU11>;
58 };
59 };
60 cluster3 {
61 core0 {
62 cpu = <&CPU12>;
63 };
64 core1 {
65 cpu = <&CPU13>;
66 };
67 core2 {
68 cpu = <&CPU14>;
69 };
70 core3 {
71 cpu = <&CPU15>;
72 };
73 };
74 };
75
76 CPU0: cpu@0 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a15";
79 reg = <0x00>;
80 clock-frequency= <1400000000>;
81 cpu-release-addr = <0>; // Fixed by the boot loader
82 };
83
84 CPU1: cpu@1 {
85 device_type = "cpu";
86 compatible = "arm,cortex-a15";
87 reg = <0x01>;
88 clock-frequency= <1400000000>;
89 cpu-release-addr = <0>; // Fixed by the boot loader
90 };
91
92 CPU2: cpu@2 {
93 device_type = "cpu";
94 compatible = "arm,cortex-a15";
95 reg = <0x02>;
96 clock-frequency= <1400000000>;
97 cpu-release-addr = <0>; // Fixed by the boot loader
98 };
99
100 CPU3: cpu@3 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a15";
103 reg = <0x03>;
104 clock-frequency= <1400000000>;
105 cpu-release-addr = <0>; // Fixed by the boot loader
106 };
107
108 CPU4: cpu@100 {
109 device_type = "cpu";
110 compatible = "arm,cortex-a15";
111 reg = <0x100>;
112 clock-frequency= <1400000000>;
113 cpu-release-addr = <0>; // Fixed by the boot loader
114 };
115
116 CPU5: cpu@101 {
117 device_type = "cpu";
118 compatible = "arm,cortex-a15";
119 reg = <0x101>;
120 clock-frequency= <1400000000>;
121 cpu-release-addr = <0>; // Fixed by the boot loader
122 };
123
124 CPU6: cpu@102 {
125 device_type = "cpu";
126 compatible = "arm,cortex-a15";
127 reg = <0x102>;
128 clock-frequency= <1400000000>;
129 cpu-release-addr = <0>; // Fixed by the boot loader
130 };
131
132 CPU7: cpu@103 {
133 device_type = "cpu";
134 compatible = "arm,cortex-a15";
135 reg = <0x103>;
136 clock-frequency= <1400000000>;
137 cpu-release-addr = <0>; // Fixed by the boot loader
138 };
139
140 CPU8: cpu@200 {
141 device_type = "cpu";
142 compatible = "arm,cortex-a15";
143 reg = <0x200>;
144 clock-frequency= <1400000000>;
145 cpu-release-addr = <0>; // Fixed by the boot loader
146 };
147
148 CPU9: cpu@201 {
149 device_type = "cpu";
150 compatible = "arm,cortex-a15";
151 reg = <0x201>;
152 clock-frequency= <1400000000>;
153 cpu-release-addr = <0>; // Fixed by the boot loader
154 };
155
156 CPU10: cpu@202 {
157 device_type = "cpu";
158 compatible = "arm,cortex-a15";
159 reg = <0x202>;
160 clock-frequency= <1400000000>;
161 cpu-release-addr = <0>; // Fixed by the boot loader
162 };
163
164 CPU11: cpu@203 {
165 device_type = "cpu";
166 compatible = "arm,cortex-a15";
167 reg = <0x203>;
168 clock-frequency= <1400000000>;
169 cpu-release-addr = <0>; // Fixed by the boot loader
170 };
171
172 CPU12: cpu@300 {
173 device_type = "cpu";
174 compatible = "arm,cortex-a15";
175 reg = <0x300>;
176 clock-frequency= <1400000000>;
177 cpu-release-addr = <0>; // Fixed by the boot loader
178 };
179
180 CPU13: cpu@301 {
181 device_type = "cpu";
182 compatible = "arm,cortex-a15";
183 reg = <0x301>;
184 clock-frequency= <1400000000>;
185 cpu-release-addr = <0>; // Fixed by the boot loader
186 };
187
188 CPU14: cpu@302 {
189 device_type = "cpu";
190 compatible = "arm,cortex-a15";
191 reg = <0x302>;
192 clock-frequency= <1400000000>;
193 cpu-release-addr = <0>; // Fixed by the boot loader
194 };
195
196 CPU15: cpu@303 {
197 device_type = "cpu";
198 compatible = "arm,cortex-a15";
199 reg = <0x303>;
200 clock-frequency= <1400000000>;
201 cpu-release-addr = <0>; // Fixed by the boot loader
202 };
203 };
204};
diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi
new file mode 100644
index 000000000000..ea288f0a1d39
--- /dev/null
+++ b/arch/arm/boot/dts/axm55xx.dtsi
@@ -0,0 +1,204 @@
1/*
2 * arch/arm/boot/dts/axm55xx.dtsi
3 *
4 * Copyright (C) 2013 LSI
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/clock/lsi,axm5516-clks.h>
14
15#include "skeleton64.dtsi"
16
17/ {
18 interrupt-parent = <&gic>;
19
20 aliases {
21 serial0 = &serial0;
22 serial1 = &serial1;
23 serial2 = &serial2;
24 serial3 = &serial3;
25 timer = &timer0;
26 };
27
28 clocks {
29 compatible = "simple-bus";
30 #address-cells = <2>;
31 #size-cells = <2>;
32 ranges;
33
34 clk_ref0: clk_ref0 {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <125000000>;
38 };
39
40 clk_ref1: clk_ref1 {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <125000000>;
44 };
45
46 clk_ref2: clk_ref2 {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <125000000>;
50 };
51
52 clks: clock-controller@2010020000 {
53 compatible = "lsi,axm5516-clks";
54 #clock-cells = <1>;
55 reg = <0x20 0x10020000 0 0x20000>;
56 };
57 };
58
59 gic: interrupt-controller@2001001000 {
60 compatible = "arm,cortex-a15-gic";
61 #interrupt-cells = <3>;
62 #address-cells = <0>;
63 interrupt-controller;
64 reg = <0x20 0x01001000 0 0x1000>,
65 <0x20 0x01002000 0 0x1000>,
66 <0x20 0x01004000 0 0x2000>,
67 <0x20 0x01006000 0 0x2000>;
68 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
69 IRQ_TYPE_LEVEL_HIGH)>;
70 };
71
72 timer {
73 compatible = "arm,armv7-timer";
74 interrupts =
75 <GIC_PPI 13
76 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
77 <GIC_PPI 14
78 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
79 <GIC_PPI 11
80 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 10
82 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
83 };
84
85
86 pmu {
87 compatible = "arm,cortex-a15-pmu";
88 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
89 };
90
91 soc {
92 compatible = "simple-bus";
93 device_type = "soc";
94 #address-cells = <2>;
95 #size-cells = <2>;
96 interrupt-parent = <&gic>;
97 ranges;
98
99 syscon: syscon@2010030000 {
100 compatible = "lsi,axxia-syscon", "syscon";
101 reg = <0x20 0x10030000 0 0x2000>;
102 };
103
104 reset: reset@2010031000 {
105 compatible = "lsi,axm55xx-reset";
106 syscon = <&syscon>;
107 };
108
109 amba {
110 compatible = "arm,amba-bus";
111 #address-cells = <2>;
112 #size-cells = <2>;
113 ranges;
114
115 serial0: uart@2010080000 {
116 compatible = "arm,pl011", "arm,primecell";
117 reg = <0x20 0x10080000 0 0x1000>;
118 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
119 clocks = <&clks AXXIA_CLK_PER>;
120 clock-names = "apb_pclk";
121 status = "disabled";
122 };
123
124 serial1: uart@2010081000 {
125 compatible = "arm,pl011", "arm,primecell";
126 reg = <0x20 0x10081000 0 0x1000>;
127 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
128 clocks = <&clks AXXIA_CLK_PER>;
129 clock-names = "apb_pclk";
130 status = "disabled";
131 };
132
133 serial2: uart@2010082000 {
134 compatible = "arm,pl011", "arm,primecell";
135 reg = <0x20 0x10082000 0 0x1000>;
136 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&clks AXXIA_CLK_PER>;
138 clock-names = "apb_pclk";
139 status = "disabled";
140 };
141
142 serial3: uart@2010083000 {
143 compatible = "arm,pl011", "arm,primecell";
144 reg = <0x20 0x10083000 0 0x1000>;
145 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&clks AXXIA_CLK_PER>;
147 clock-names = "apb_pclk";
148 status = "disabled";
149 };
150
151 timer0: timer@2010091000 {
152 compatible = "arm,sp804", "arm,primecell";
153 reg = <0x20 0x10091000 0 0x1000>;
154 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&clks AXXIA_CLK_PER>;
164 clock-names = "apb_pclk";
165 status = "okay";
166 };
167
168 gpio0: gpio@2010092000 {
169 #gpio-cells = <2>;
170 compatible = "arm,pl061", "arm,primecell";
171 gpio-controller;
172 reg = <0x20 0x10092000 0x00 0x1000>;
173 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&clks AXXIA_CLK_PER>;
182 clock-names = "apb_pclk";
183 status = "disabled";
184 };
185
186 gpio1: gpio@2010093000 {
187 #gpio-cells = <2>;
188 compatible = "arm,pl061", "arm,primecell";
189 gpio-controller;
190 reg = <0x20 0x10093000 0x00 0x1000>;
191 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
192 clocks = <&clks AXXIA_CLK_PER>;
193 clock-names = "apb_pclk";
194 status = "disabled";
195 };
196 };
197 };
198};
199
200/*
201 Local Variables:
202 mode: C
203 End:
204*/
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 2f8bcd068d17..58ff8e28c74f 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -129,12 +129,10 @@
129 status = "disabled"; 129 status = "disabled";
130 #address-cells = <1>; 130 #address-cells = <1>;
131 #size-cells = <1>; 131 #size-cells = <1>;
132 #clock-cells = <1>;
133 clock-output-names = "cam_a_clkout", "cam_b_clkout";
132 ranges; 134 ranges;
133 135
134 clock_cam: clock-controller {
135 #clock-cells = <1>;
136 };
137
138 fimc_0: fimc@11800000 { 136 fimc_0: fimc@11800000 {
139 compatible = "samsung,exynos4210-fimc"; 137 compatible = "samsung,exynos4210-fimc";
140 reg = <0x11800000 0x1000>; 138 reg = <0x11800000 0x1000>;
@@ -371,6 +369,8 @@
371 interrupts = <0 60 0>; 369 interrupts = <0 60 0>;
372 clocks = <&clock CLK_I2C2>; 370 clocks = <&clock CLK_I2C2>;
373 clock-names = "i2c"; 371 clock-names = "i2c";
372 pinctrl-names = "default";
373 pinctrl-0 = <&i2c2_bus>;
374 status = "disabled"; 374 status = "disabled";
375 }; 375 };
376 376
@@ -382,6 +382,8 @@
382 interrupts = <0 61 0>; 382 interrupts = <0 61 0>;
383 clocks = <&clock CLK_I2C3>; 383 clocks = <&clock CLK_I2C3>;
384 clock-names = "i2c"; 384 clock-names = "i2c";
385 pinctrl-names = "default";
386 pinctrl-0 = <&i2c3_bus>;
385 status = "disabled"; 387 status = "disabled";
386 }; 388 };
387 389
@@ -393,6 +395,8 @@
393 interrupts = <0 62 0>; 395 interrupts = <0 62 0>;
394 clocks = <&clock CLK_I2C4>; 396 clocks = <&clock CLK_I2C4>;
395 clock-names = "i2c"; 397 clock-names = "i2c";
398 pinctrl-names = "default";
399 pinctrl-0 = <&i2c4_bus>;
396 status = "disabled"; 400 status = "disabled";
397 }; 401 };
398 402
@@ -404,6 +408,8 @@
404 interrupts = <0 63 0>; 408 interrupts = <0 63 0>;
405 clocks = <&clock CLK_I2C5>; 409 clocks = <&clock CLK_I2C5>;
406 clock-names = "i2c"; 410 clock-names = "i2c";
411 pinctrl-names = "default";
412 pinctrl-0 = <&i2c5_bus>;
407 status = "disabled"; 413 status = "disabled";
408 }; 414 };
409 415
@@ -415,6 +421,8 @@
415 interrupts = <0 64 0>; 421 interrupts = <0 64 0>;
416 clocks = <&clock CLK_I2C6>; 422 clocks = <&clock CLK_I2C6>;
417 clock-names = "i2c"; 423 clock-names = "i2c";
424 pinctrl-names = "default";
425 pinctrl-0 = <&i2c6_bus>;
418 status = "disabled"; 426 status = "disabled";
419 }; 427 };
420 428
@@ -426,6 +434,8 @@
426 interrupts = <0 65 0>; 434 interrupts = <0 65 0>;
427 clocks = <&clock CLK_I2C7>; 435 clocks = <&clock CLK_I2C7>;
428 clock-names = "i2c"; 436 clock-names = "i2c";
437 pinctrl-names = "default";
438 pinctrl-0 = <&i2c7_bus>;
429 status = "disabled"; 439 status = "disabled";
430 }; 440 };
431 441
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 63e34b24b04f..9296dee10e26 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -28,6 +28,21 @@
28 bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; 28 bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1";
29 }; 29 };
30 30
31 sysram@02020000 {
32 smp-sysram@0 {
33 status = "disabled";
34 };
35
36 smp-sysram@5000 {
37 compatible = "samsung,exynos4210-sysram";
38 reg = <0x5000 0x1000>;
39 };
40
41 smp-sysram@1f000 {
42 status = "disabled";
43 };
44 };
45
31 mct@10050000 { 46 mct@10050000 {
32 compatible = "none"; 47 compatible = "none";
33 }; 48 };
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index cacf6140dd2f..ee3001f38821 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -31,6 +31,24 @@
31 pinctrl2 = &pinctrl_2; 31 pinctrl2 = &pinctrl_2;
32 }; 32 };
33 33
34 sysram@02020000 {
35 compatible = "mmio-sram";
36 reg = <0x02020000 0x20000>;
37 #address-cells = <1>;
38 #size-cells = <1>;
39 ranges = <0 0x02020000 0x20000>;
40
41 smp-sysram@0 {
42 compatible = "samsung,exynos4210-sysram";
43 reg = <0x0 0x1000>;
44 };
45
46 smp-sysram@1f000 {
47 compatible = "samsung,exynos4210-sysram-ns";
48 reg = <0x1f000 0x1000>;
49 };
50 };
51
34 pd_lcd1: lcd1-power-domain@10023CA0 { 52 pd_lcd1: lcd1-power-domain@10023CA0 {
35 compatible = "samsung,exynos4210-pd"; 53 compatible = "samsung,exynos4210-pd";
36 reg = <0x10023CA0 0x20>; 54 reg = <0x10023CA0 0x20>;
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 8a558b7ac999..bc08e6ef3d4f 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -20,7 +20,7 @@
20 compatible = "samsung,trats2", "samsung,exynos4412", "samsung,exynos4"; 20 compatible = "samsung,trats2", "samsung,exynos4412", "samsung,exynos4";
21 21
22 aliases { 22 aliases {
23 i2c8 = &i2c_ak8975; 23 i2c9 = &i2c_ak8975;
24 }; 24 };
25 25
26 memory { 26 memory {
@@ -80,7 +80,24 @@
80 enable-active-high; 80 enable-active-high;
81 }; 81 };
82 82
83 /* More to come */ 83 cam_af_reg: voltage-regulator-3 {
84 compatible = "regulator-fixed";
85 regulator-name = "CAM_AF";
86 regulator-min-microvolt = <2800000>;
87 regulator-max-microvolt = <2800000>;
88 gpio = <&gpm0 4 0>;
89 enable-active-high;
90 };
91
92 cam_isp_core_reg: voltage-regulator-4 {
93 compatible = "regulator-fixed";
94 regulator-name = "CAM_ISP_CORE_1.2V_EN";
95 regulator-min-microvolt = <1200000>;
96 regulator-max-microvolt = <1200000>;
97 gpio = <&gpm0 3 0>;
98 enable-active-high;
99 regulator-always-on;
100 };
84 }; 101 };
85 102
86 gpio-keys { 103 gpio-keys {
@@ -140,6 +157,38 @@
140 }; 157 };
141 }; 158 };
142 159
160 i2c_0: i2c@13860000 {
161 samsung,i2c-sda-delay = <100>;
162 samsung,i2c-slave-addr = <0x10>;
163 samsung,i2c-max-bus-freq = <400000>;
164 pinctrl-0 = <&i2c0_bus>;
165 pinctrl-names = "default";
166 status = "okay";
167
168 s5c73m3@3c {
169 compatible = "samsung,s5c73m3";
170 reg = <0x3c>;
171 standby-gpios = <&gpm0 1 1>; /* ISP_STANDBY */
172 xshutdown-gpios = <&gpf1 3 1>; /* ISP_RESET */
173 vdd-int-supply = <&buck9_reg>;
174 vddio-cis-supply = <&ldo9_reg>;
175 vdda-supply = <&ldo17_reg>;
176 vddio-host-supply = <&ldo18_reg>;
177 vdd-af-supply = <&cam_af_reg>;
178 vdd-reg-supply = <&cam_io_reg>;
179 clock-frequency = <24000000>;
180 /* CAM_A_CLKOUT */
181 clocks = <&camera 0>;
182 clock-names = "cis_extclk";
183 port {
184 s5c73m3_ep: endpoint {
185 remote-endpoint = <&csis0_ep>;
186 data-lanes = <1 2 3 4>;
187 };
188 };
189 };
190 };
191
143 i2c@138D0000 { 192 i2c@138D0000 {
144 samsung,i2c-sda-delay = <100>; 193 samsung,i2c-sda-delay = <100>;
145 samsung,i2c-slave-addr = <0x10>; 194 samsung,i2c-slave-addr = <0x10>;
@@ -586,8 +635,8 @@
586 status = "okay"; 635 status = "okay";
587 }; 636 };
588 637
589 camera { 638 camera: camera {
590 pinctrl-0 = <&cam_port_b_clk_active>; 639 pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>;
591 pinctrl-names = "default"; 640 pinctrl-names = "default";
592 status = "okay"; 641 status = "okay";
593 642
@@ -607,6 +656,23 @@
607 status = "okay"; 656 status = "okay";
608 }; 657 };
609 658
659 csis_0: csis@11880000 {
660 status = "okay";
661 vddcore-supply = <&ldo8_reg>;
662 vddio-supply = <&ldo10_reg>;
663 clock-frequency = <176000000>;
664
665 /* Camera C (3) MIPI CSI-2 (CSIS0) */
666 port@3 {
667 reg = <3>;
668 csis0_ep: endpoint {
669 remote-endpoint = <&s5c73m3_ep>;
670 data-lanes = <1 2 3 4>;
671 samsung,csis-hs-settle = <12>;
672 };
673 };
674 };
675
610 csis_1: csis@11890000 { 676 csis_1: csis@11890000 {
611 vddcore-supply = <&ldo8_reg>; 677 vddcore-supply = <&ldo8_reg>;
612 vddio-supply = <&ldo10_reg>; 678 vddio-supply = <&ldo10_reg>;
@@ -647,10 +713,11 @@
647 reg = <0x10>; 713 reg = <0x10>;
648 svdda-supply = <&cam_io_reg>; 714 svdda-supply = <&cam_io_reg>;
649 svddio-supply = <&ldo19_reg>; 715 svddio-supply = <&ldo19_reg>;
716 afvdd-supply = <&ldo19_reg>;
650 clock-frequency = <24000000>; 717 clock-frequency = <24000000>;
651 /* CAM_B_CLKOUT */ 718 /* CAM_B_CLKOUT */
652 clocks = <&clock_cam 1>; 719 clocks = <&camera 1>;
653 clock-names = "mclk"; 720 clock-names = "extclk";
654 samsung,camclk-out = <1>; 721 samsung,camclk-out = <1>;
655 gpios = <&gpm1 6 0>; 722 gpios = <&gpm1 6 0>;
656 723
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index c4a9306f8529..70e3765b51ee 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -37,6 +37,24 @@
37 interrupts = <2 2>, <3 2>, <18 2>, <19 2>; 37 interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
38 }; 38 };
39 39
40 sysram@02020000 {
41 compatible = "mmio-sram";
42 reg = <0x02020000 0x40000>;
43 #address-cells = <1>;
44 #size-cells = <1>;
45 ranges = <0 0x02020000 0x40000>;
46
47 smp-sysram@0 {
48 compatible = "samsung,exynos4210-sysram";
49 reg = <0x0 0x1000>;
50 };
51
52 smp-sysram@2f000 {
53 compatible = "samsung,exynos4210-sysram-ns";
54 reg = <0x2f000 0x1000>;
55 };
56 };
57
40 pd_isp: isp-power-domain@10023CA0 { 58 pd_isp: isp-power-domain@10023CA0 {
41 compatible = "samsung,exynos4210-pd"; 59 compatible = "samsung,exynos4210-pd";
42 reg = <0x10023CA0 0x20>; 60 reg = <0x10023CA0 0x20>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 37423314a028..e44693e2cfda 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -72,6 +72,24 @@
72 }; 72 };
73 }; 73 };
74 74
75 sysram@02020000 {
76 compatible = "mmio-sram";
77 reg = <0x02020000 0x30000>;
78 #address-cells = <1>;
79 #size-cells = <1>;
80 ranges = <0 0x02020000 0x30000>;
81
82 smp-sysram@0 {
83 compatible = "samsung,exynos4210-sysram";
84 reg = <0x0 0x1000>;
85 };
86
87 smp-sysram@2f000 {
88 compatible = "samsung,exynos4210-sysram-ns";
89 reg = <0x2f000 0x1000>;
90 };
91 };
92
75 pd_gsc: gsc-power-domain@10044000 { 93 pd_gsc: gsc-power-domain@10044000 {
76 compatible = "samsung,exynos4210-pd"; 94 compatible = "samsung,exynos4210-pd";
77 reg = <0x10044000 0x20>; 95 reg = <0x10044000 0x20>;
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
new file mode 100644
index 000000000000..fae33dddac39
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -0,0 +1,147 @@
1/*
2 * Google Peach Pit Rev 6+ board device tree source
3 *
4 * Copyright (c) 2014 Google, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/dts-v1/;
12#include <dt-bindings/input/input.h>
13#include <dt-bindings/gpio/gpio.h>
14#include "exynos5420.dtsi"
15
16/ {
17 model = "Google Peach Pit Rev 6+";
18
19 compatible = "google,pit-rev16",
20 "google,pit-rev15", "google,pit-rev14",
21 "google,pit-rev13", "google,pit-rev12",
22 "google,pit-rev11", "google,pit-rev10",
23 "google,pit-rev9", "google,pit-rev8",
24 "google,pit-rev7", "google,pit-rev6",
25 "google,pit", "google,peach","samsung,exynos5420",
26 "samsung,exynos5";
27
28 memory {
29 reg = <0x20000000 0x80000000>;
30 };
31
32 fixed-rate-clocks {
33 oscclk {
34 compatible = "samsung,exynos5420-oscclk";
35 clock-frequency = <24000000>;
36 };
37 };
38
39 gpio-keys {
40 compatible = "gpio-keys";
41
42 pinctrl-names = "default";
43 pinctrl-0 = <&power_key_irq>;
44
45 power {
46 label = "Power";
47 gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
48 linux,code = <KEY_POWER>;
49 gpio-key,wakeup;
50 };
51 };
52
53 backlight {
54 compatible = "pwm-backlight";
55 pwms = <&pwm 0 1000000 0>;
56 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
57 default-brightness-level = <7>;
58 pinctrl-0 = <&pwm0_out>;
59 pinctrl-names = "default";
60 };
61};
62
63&pinctrl_0 {
64 tpm_irq: tpm-irq {
65 samsung,pins = "gpx1-0";
66 samsung,pin-function = <0>;
67 samsung,pin-pud = <0>;
68 samsung,pin-drv = <0>;
69 };
70
71 power_key_irq: power-key-irq {
72 samsung,pins = "gpx1-2";
73 samsung,pin-function = <0>;
74 samsung,pin-pud = <0>;
75 samsung,pin-drv = <0>;
76 };
77};
78
79&rtc {
80 status = "okay";
81};
82
83&uart_3 {
84 status = "okay";
85};
86
87&mmc_0 {
88 status = "okay";
89 num-slots = <1>;
90 broken-cd;
91 caps2-mmc-hs200-1_8v;
92 supports-highspeed;
93 non-removable;
94 card-detect-delay = <200>;
95 clock-frequency = <400000000>;
96 samsung,dw-mshc-ciu-div = <3>;
97 samsung,dw-mshc-sdr-timing = <0 4>;
98 samsung,dw-mshc-ddr-timing = <0 2>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
101
102 slot@0 {
103 reg = <0>;
104 bus-width = <8>;
105 };
106};
107
108&mmc_2 {
109 status = "okay";
110 num-slots = <1>;
111 supports-highspeed;
112 card-detect-delay = <200>;
113 clock-frequency = <400000000>;
114 samsung,dw-mshc-ciu-div = <3>;
115 samsung,dw-mshc-sdr-timing = <2 3>;
116 samsung,dw-mshc-ddr-timing = <1 2>;
117 pinctrl-names = "default";
118 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
119
120 slot@0 {
121 reg = <0>;
122 bus-width = <4>;
123 };
124};
125
126&hsi2c_9 {
127 status = "okay";
128 clock-frequency = <400000>;
129
130 tpm@20 {
131 compatible = "infineon,slb9645tt";
132 reg = <0x20>;
133
134 /* Unused irq; but still need to configure the pins */
135 pinctrl-names = "default";
136 pinctrl-0 = <&tpm_irq>;
137 };
138};
139
140/*
141 * Use longest HW watchdog in SoC (32 seconds) since the hardware
142 * watchdog provides no debugging information (compared to soft/hard
143 * lockup detectors) and so should be last resort.
144 */
145&watchdog {
146 timeout-sec = <32>;
147};
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
index e62c8eb57438..ba686e40eac7 100644
--- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -624,6 +624,34 @@
624 samsung,pin-drv = <0>; 624 samsung,pin-drv = <0>;
625 }; 625 };
626 626
627 pwm0_out: pwm0-out {
628 samsung,pins = "gpb2-0";
629 samsung,pin-function = <2>;
630 samsung,pin-pud = <0>;
631 samsung,pin-drv = <0>;
632 };
633
634 pwm1_out: pwm1-out {
635 samsung,pins = "gpb2-1";
636 samsung,pin-function = <2>;
637 samsung,pin-pud = <0>;
638 samsung,pin-drv = <0>;
639 };
640
641 pwm2_out: pwm2-out {
642 samsung,pins = "gpb2-2";
643 samsung,pin-function = <2>;
644 samsung,pin-pud = <0>;
645 samsung,pin-drv = <0>;
646 };
647
648 pwm3_out: pwm3-out {
649 samsung,pins = "gpb2-3";
650 samsung,pin-function = <2>;
651 samsung,pin-pud = <0>;
652 samsung,pin-drv = <0>;
653 };
654
627 i2c7_hs_bus: i2c7-hs-bus { 655 i2c7_hs_bus: i2c7-hs-bus {
628 samsung,pins = "gpb2-2", "gpb2-3"; 656 samsung,pins = "gpb2-2", "gpb2-3";
629 samsung,pin-function = <3>; 657 samsung,pin-function = <3>;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index b69fbcb7dcb8..5e36449a831c 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -58,6 +58,7 @@
58 compatible = "arm,cortex-a15"; 58 compatible = "arm,cortex-a15";
59 reg = <0x0>; 59 reg = <0x0>;
60 clock-frequency = <1800000000>; 60 clock-frequency = <1800000000>;
61 cci-control-port = <&cci_control1>;
61 }; 62 };
62 63
63 cpu1: cpu@1 { 64 cpu1: cpu@1 {
@@ -65,6 +66,7 @@
65 compatible = "arm,cortex-a15"; 66 compatible = "arm,cortex-a15";
66 reg = <0x1>; 67 reg = <0x1>;
67 clock-frequency = <1800000000>; 68 clock-frequency = <1800000000>;
69 cci-control-port = <&cci_control1>;
68 }; 70 };
69 71
70 cpu2: cpu@2 { 72 cpu2: cpu@2 {
@@ -72,6 +74,7 @@
72 compatible = "arm,cortex-a15"; 74 compatible = "arm,cortex-a15";
73 reg = <0x2>; 75 reg = <0x2>;
74 clock-frequency = <1800000000>; 76 clock-frequency = <1800000000>;
77 cci-control-port = <&cci_control1>;
75 }; 78 };
76 79
77 cpu3: cpu@3 { 80 cpu3: cpu@3 {
@@ -79,6 +82,7 @@
79 compatible = "arm,cortex-a15"; 82 compatible = "arm,cortex-a15";
80 reg = <0x3>; 83 reg = <0x3>;
81 clock-frequency = <1800000000>; 84 clock-frequency = <1800000000>;
85 cci-control-port = <&cci_control1>;
82 }; 86 };
83 87
84 cpu4: cpu@100 { 88 cpu4: cpu@100 {
@@ -86,6 +90,7 @@
86 compatible = "arm,cortex-a7"; 90 compatible = "arm,cortex-a7";
87 reg = <0x100>; 91 reg = <0x100>;
88 clock-frequency = <1000000000>; 92 clock-frequency = <1000000000>;
93 cci-control-port = <&cci_control0>;
89 }; 94 };
90 95
91 cpu5: cpu@101 { 96 cpu5: cpu@101 {
@@ -93,6 +98,7 @@
93 compatible = "arm,cortex-a7"; 98 compatible = "arm,cortex-a7";
94 reg = <0x101>; 99 reg = <0x101>;
95 clock-frequency = <1000000000>; 100 clock-frequency = <1000000000>;
101 cci-control-port = <&cci_control0>;
96 }; 102 };
97 103
98 cpu6: cpu@102 { 104 cpu6: cpu@102 {
@@ -100,6 +106,7 @@
100 compatible = "arm,cortex-a7"; 106 compatible = "arm,cortex-a7";
101 reg = <0x102>; 107 reg = <0x102>;
102 clock-frequency = <1000000000>; 108 clock-frequency = <1000000000>;
109 cci-control-port = <&cci_control0>;
103 }; 110 };
104 111
105 cpu7: cpu@103 { 112 cpu7: cpu@103 {
@@ -107,6 +114,44 @@
107 compatible = "arm,cortex-a7"; 114 compatible = "arm,cortex-a7";
108 reg = <0x103>; 115 reg = <0x103>;
109 clock-frequency = <1000000000>; 116 clock-frequency = <1000000000>;
117 cci-control-port = <&cci_control0>;
118 };
119 };
120
121 cci@10d20000 {
122 compatible = "arm,cci-400";
123 #address-cells = <1>;
124 #size-cells = <1>;
125 reg = <0x10d20000 0x1000>;
126 ranges = <0x0 0x10d20000 0x6000>;
127
128 cci_control0: slave-if@4000 {
129 compatible = "arm,cci-400-ctrl-if";
130 interface-type = "ace";
131 reg = <0x4000 0x1000>;
132 };
133 cci_control1: slave-if@5000 {
134 compatible = "arm,cci-400-ctrl-if";
135 interface-type = "ace";
136 reg = <0x5000 0x1000>;
137 };
138 };
139
140 sysram@02020000 {
141 compatible = "mmio-sram";
142 reg = <0x02020000 0x54000>;
143 #address-cells = <1>;
144 #size-cells = <1>;
145 ranges = <0 0x02020000 0x54000>;
146
147 smp-sysram@0 {
148 compatible = "samsung,exynos4210-sysram";
149 reg = <0x0 0x1000>;
150 };
151
152 smp-sysram@53000 {
153 compatible = "samsung,exynos4210-sysram-ns";
154 reg = <0x53000 0x1000>;
110 }; 155 };
111 }; 156 };
112 157
@@ -125,7 +170,7 @@
125 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; 170 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
126 }; 171 };
127 172
128 codec@11000000 { 173 mfc: codec@11000000 {
129 compatible = "samsung,mfc-v7"; 174 compatible = "samsung,mfc-v7";
130 reg = <0x11000000 0x10000>; 175 reg = <0x11000000 0x10000>;
131 interrupts = <0 96 0>; 176 interrupts = <0 96 0>;
@@ -169,7 +214,7 @@
169 status = "disabled"; 214 status = "disabled";
170 }; 215 };
171 216
172 mct@101C0000 { 217 mct: mct@101C0000 {
173 compatible = "samsung,exynos4210-mct"; 218 compatible = "samsung,exynos4210-mct";
174 reg = <0x101C0000 0x800>; 219 reg = <0x101C0000 0x800>;
175 interrupt-controller; 220 interrupt-controller;
@@ -260,7 +305,7 @@
260 interrupts = <0 47 0>; 305 interrupts = <0 47 0>;
261 }; 306 };
262 307
263 rtc@101E0000 { 308 rtc: rtc@101E0000 {
264 clocks = <&clock CLK_RTC>; 309 clocks = <&clock CLK_RTC>;
265 clock-names = "rtc"; 310 clock-names = "rtc";
266 status = "disabled"; 311 status = "disabled";
@@ -427,22 +472,22 @@
427 status = "disabled"; 472 status = "disabled";
428 }; 473 };
429 474
430 serial@12C00000 { 475 uart_0: serial@12C00000 {
431 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 476 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
432 clock-names = "uart", "clk_uart_baud0"; 477 clock-names = "uart", "clk_uart_baud0";
433 }; 478 };
434 479
435 serial@12C10000 { 480 uart_1: serial@12C10000 {
436 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 481 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
437 clock-names = "uart", "clk_uart_baud0"; 482 clock-names = "uart", "clk_uart_baud0";
438 }; 483 };
439 484
440 serial@12C20000 { 485 uart_2: serial@12C20000 {
441 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 486 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
442 clock-names = "uart", "clk_uart_baud0"; 487 clock-names = "uart", "clk_uart_baud0";
443 }; 488 };
444 489
445 serial@12C30000 { 490 uart_3: serial@12C30000 {
446 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 491 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
447 clock-names = "uart", "clk_uart_baud0"; 492 clock-names = "uart", "clk_uart_baud0";
448 }; 493 };
@@ -462,14 +507,14 @@
462 #phy-cells = <0>; 507 #phy-cells = <0>;
463 }; 508 };
464 509
465 dp-controller@145B0000 { 510 dp: dp-controller@145B0000 {
466 clocks = <&clock CLK_DP1>; 511 clocks = <&clock CLK_DP1>;
467 clock-names = "dp"; 512 clock-names = "dp";
468 phys = <&dp_phy>; 513 phys = <&dp_phy>;
469 phy-names = "dp"; 514 phy-names = "dp";
470 }; 515 };
471 516
472 fimd@14400000 { 517 fimd: fimd@14400000 {
473 samsung,power-domain = <&disp_pd>; 518 samsung,power-domain = <&disp_pd>;
474 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 519 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
475 clock-names = "sclk_fimd", "fimd"; 520 clock-names = "sclk_fimd", "fimd";
@@ -546,7 +591,7 @@
546 #size-cells = <0>; 591 #size-cells = <0>;
547 pinctrl-names = "default"; 592 pinctrl-names = "default";
548 pinctrl-0 = <&i2c4_hs_bus>; 593 pinctrl-0 = <&i2c4_hs_bus>;
549 clocks = <&clock CLK_I2C4>; 594 clocks = <&clock CLK_USI0>;
550 clock-names = "hsi2c"; 595 clock-names = "hsi2c";
551 status = "disabled"; 596 status = "disabled";
552 }; 597 };
@@ -559,7 +604,7 @@
559 #size-cells = <0>; 604 #size-cells = <0>;
560 pinctrl-names = "default"; 605 pinctrl-names = "default";
561 pinctrl-0 = <&i2c5_hs_bus>; 606 pinctrl-0 = <&i2c5_hs_bus>;
562 clocks = <&clock CLK_I2C5>; 607 clocks = <&clock CLK_USI1>;
563 clock-names = "hsi2c"; 608 clock-names = "hsi2c";
564 status = "disabled"; 609 status = "disabled";
565 }; 610 };
@@ -572,7 +617,7 @@
572 #size-cells = <0>; 617 #size-cells = <0>;
573 pinctrl-names = "default"; 618 pinctrl-names = "default";
574 pinctrl-0 = <&i2c6_hs_bus>; 619 pinctrl-0 = <&i2c6_hs_bus>;
575 clocks = <&clock CLK_I2C6>; 620 clocks = <&clock CLK_USI2>;
576 clock-names = "hsi2c"; 621 clock-names = "hsi2c";
577 status = "disabled"; 622 status = "disabled";
578 }; 623 };
@@ -585,7 +630,7 @@
585 #size-cells = <0>; 630 #size-cells = <0>;
586 pinctrl-names = "default"; 631 pinctrl-names = "default";
587 pinctrl-0 = <&i2c7_hs_bus>; 632 pinctrl-0 = <&i2c7_hs_bus>;
588 clocks = <&clock CLK_I2C7>; 633 clocks = <&clock CLK_USI3>;
589 clock-names = "hsi2c"; 634 clock-names = "hsi2c";
590 status = "disabled"; 635 status = "disabled";
591 }; 636 };
@@ -598,7 +643,7 @@
598 #size-cells = <0>; 643 #size-cells = <0>;
599 pinctrl-names = "default"; 644 pinctrl-names = "default";
600 pinctrl-0 = <&i2c8_hs_bus>; 645 pinctrl-0 = <&i2c8_hs_bus>;
601 clocks = <&clock CLK_I2C8>; 646 clocks = <&clock CLK_USI4>;
602 clock-names = "hsi2c"; 647 clock-names = "hsi2c";
603 status = "disabled"; 648 status = "disabled";
604 }; 649 };
@@ -611,7 +656,7 @@
611 #size-cells = <0>; 656 #size-cells = <0>;
612 pinctrl-names = "default"; 657 pinctrl-names = "default";
613 pinctrl-0 = <&i2c9_hs_bus>; 658 pinctrl-0 = <&i2c9_hs_bus>;
614 clocks = <&clock CLK_I2C9>; 659 clocks = <&clock CLK_USI5>;
615 clock-names = "hsi2c"; 660 clock-names = "hsi2c";
616 status = "disabled"; 661 status = "disabled";
617 }; 662 };
@@ -624,12 +669,12 @@
624 #size-cells = <0>; 669 #size-cells = <0>;
625 pinctrl-names = "default"; 670 pinctrl-names = "default";
626 pinctrl-0 = <&i2c10_hs_bus>; 671 pinctrl-0 = <&i2c10_hs_bus>;
627 clocks = <&clock CLK_I2C10>; 672 clocks = <&clock CLK_USI6>;
628 clock-names = "hsi2c"; 673 clock-names = "hsi2c";
629 status = "disabled"; 674 status = "disabled";
630 }; 675 };
631 676
632 hdmi@14530000 { 677 hdmi: hdmi@14530000 {
633 compatible = "samsung,exynos4212-hdmi"; 678 compatible = "samsung,exynos4212-hdmi";
634 reg = <0x14530000 0x70000>; 679 reg = <0x14530000 0x70000>;
635 interrupts = <0 95 0>; 680 interrupts = <0 95 0>;
@@ -641,7 +686,7 @@
641 status = "disabled"; 686 status = "disabled";
642 }; 687 };
643 688
644 mixer@14450000 { 689 mixer: mixer@14450000 {
645 compatible = "samsung,exynos5420-mixer"; 690 compatible = "samsung,exynos5420-mixer";
646 reg = <0x14450000 0x10000>; 691 reg = <0x14450000 0x10000>;
647 interrupts = <0 94 0>; 692 interrupts = <0 94 0>;
@@ -712,7 +757,7 @@
712 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 757 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
713 }; 758 };
714 759
715 watchdog@101D0000 { 760 watchdog: watchdog@101D0000 {
716 compatible = "samsung,exynos5420-wdt"; 761 compatible = "samsung,exynos5420-wdt";
717 reg = <0x101D0000 0x100>; 762 reg = <0x101D0000 0x100>;
718 interrupts = <0 42 0>; 763 interrupts = <0 42 0>;
@@ -721,7 +766,7 @@
721 samsung,syscon-phandle = <&pmu_system_controller>; 766 samsung,syscon-phandle = <&pmu_system_controller>;
722 }; 767 };
723 768
724 sss@10830000 { 769 sss: sss@10830000 {
725 compatible = "samsung,exynos4210-secss"; 770 compatible = "samsung,exynos4210-secss";
726 reg = <0x10830000 0x10000>; 771 reg = <0x10830000 0x10000>;
727 interrupts = <0 112 0>; 772 interrupts = <0 112 0>;
diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts
index 4df68ad3736a..9cba94bed7ad 100644
--- a/arch/arm/boot/dts/omap3-evm-37xx.dts
+++ b/arch/arm/boot/dts/omap3-evm-37xx.dts
@@ -89,7 +89,16 @@
89 status = "disabled"; 89 status = "disabled";
90}; 90};
91 91
92&uart1 {
93 interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>;
94};
95
96&uart2 {
97 interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
98};
99
92&uart3 { 100&uart3 {
101 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
93 pinctrl-names = "default"; 102 pinctrl-names = "default";
94 pinctrl-0 = <&uart3_pins>; 103 pinctrl-0 = <&uart3_pins>;
95}; 104};
diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts
index 0abe986a4ecc..476ff158ddb3 100644
--- a/arch/arm/boot/dts/omap3-ldp.dts
+++ b/arch/arm/boot/dts/omap3-ldp.dts
@@ -234,6 +234,10 @@
234 }; 234 };
235}; 235};
236 236
237&uart3 {
238 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
239};
240
237&usb_otg_hs { 241&usb_otg_hs {
238 pinctrl-names = "default"; 242 pinctrl-names = "default";
239 pinctrl-0 = <&musb_pins>; 243 pinctrl-0 = <&musb_pins>;
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 1a57b61f5e24..150ca097c02d 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -21,6 +21,17 @@
21 }; 21 };
22 }; 22 };
23 23
24 leds {
25 compatible = "gpio-leds";
26 heartbeat {
27 label = "debug::sleep";
28 gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* gpio162 */
29 linux,default-trigger = "default-on";
30 pinctrl-names = "default";
31 pinctrl-0 = <&debug_leds>;
32 };
33 };
34
24 memory { 35 memory {
25 device_type = "memory"; 36 device_type = "memory";
26 reg = <0x80000000 0x10000000>; /* 256 MB */ 37 reg = <0x80000000 0x10000000>; /* 256 MB */
@@ -130,6 +141,12 @@
130 >; 141 >;
131 }; 142 };
132 143
144 debug_leds: pinmux_debug_led_pins {
145 pinctrl-single,pins = <
146 OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 */
147 >;
148 };
149
133 mmc1_pins: pinmux_mmc1_pins { 150 mmc1_pins: pinmux_mmc1_pins {
134 pinctrl-single,pins = < 151 pinctrl-single,pins = <
135 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ 152 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */
@@ -618,11 +635,13 @@
618}; 635};
619 636
620&uart2 { 637&uart2 {
638 interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
621 pinctrl-names = "default"; 639 pinctrl-names = "default";
622 pinctrl-0 = <&uart2_pins>; 640 pinctrl-0 = <&uart2_pins>;
623}; 641};
624 642
625&uart3 { 643&uart3 {
644 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
626 pinctrl-names = "default"; 645 pinctrl-names = "default";
627 pinctrl-0 = <&uart3_pins>; 646 pinctrl-0 = <&uart3_pins>;
628}; 647};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 4231191ade06..3cc092b7cce7 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -267,7 +267,7 @@
267 uart1: serial@4806a000 { 267 uart1: serial@4806a000 {
268 compatible = "ti,omap3-uart"; 268 compatible = "ti,omap3-uart";
269 reg = <0x4806a000 0x2000>; 269 reg = <0x4806a000 0x2000>;
270 interrupts = <72>; 270 interrupts-extended = <&intc 72>;
271 dmas = <&sdma 49 &sdma 50>; 271 dmas = <&sdma 49 &sdma 50>;
272 dma-names = "tx", "rx"; 272 dma-names = "tx", "rx";
273 ti,hwmods = "uart1"; 273 ti,hwmods = "uart1";
@@ -277,7 +277,7 @@
277 uart2: serial@4806c000 { 277 uart2: serial@4806c000 {
278 compatible = "ti,omap3-uart"; 278 compatible = "ti,omap3-uart";
279 reg = <0x4806c000 0x400>; 279 reg = <0x4806c000 0x400>;
280 interrupts = <73>; 280 interrupts-extended = <&intc 73>;
281 dmas = <&sdma 51 &sdma 52>; 281 dmas = <&sdma 51 &sdma 52>;
282 dma-names = "tx", "rx"; 282 dma-names = "tx", "rx";
283 ti,hwmods = "uart2"; 283 ti,hwmods = "uart2";
@@ -287,7 +287,7 @@
287 uart3: serial@49020000 { 287 uart3: serial@49020000 {
288 compatible = "ti,omap3-uart"; 288 compatible = "ti,omap3-uart";
289 reg = <0x49020000 0x400>; 289 reg = <0x49020000 0x400>;
290 interrupts = <74>; 290 interrupts-extended = <&intc 74>;
291 dmas = <&sdma 53 &sdma 54>; 291 dmas = <&sdma 53 &sdma 54>;
292 dma-names = "tx", "rx"; 292 dma-names = "tx", "rx";
293 ti,hwmods = "uart3"; 293 ti,hwmods = "uart3";
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index d2c45bfaaa2c..8cfa3c8a72b0 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -481,6 +481,21 @@
481 usb-supply = <&vusb>; 481 usb-supply = <&vusb>;
482}; 482};
483 483
484&uart2 {
485 interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
486 &omap4_pmx_core OMAP4_UART2_RX>;
487};
488
489&uart3 {
490 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
491 &omap4_pmx_core OMAP4_UART3_RX>;
492};
493
494&uart4 {
495 interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
496 &omap4_pmx_core OMAP4_UART4_RX>;
497};
498
484&usb_otg_hs { 499&usb_otg_hs {
485 interface-type = <1>; 500 interface-type = <1>;
486 mode = <3>; 501 mode = <3>;
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 48983c8d56c2..3e1da43068f6 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -570,16 +570,22 @@
570}; 570};
571 571
572&uart2 { 572&uart2 {
573 interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
574 &omap4_pmx_core OMAP4_UART2_RX>;
573 pinctrl-names = "default"; 575 pinctrl-names = "default";
574 pinctrl-0 = <&uart2_pins>; 576 pinctrl-0 = <&uart2_pins>;
575}; 577};
576 578
577&uart3 { 579&uart3 {
580 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
581 &omap4_pmx_core OMAP4_UART3_RX>;
578 pinctrl-names = "default"; 582 pinctrl-names = "default";
579 pinctrl-0 = <&uart3_pins>; 583 pinctrl-0 = <&uart3_pins>;
580}; 584};
581 585
582&uart4 { 586&uart4 {
587 interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
588 &omap4_pmx_core OMAP4_UART4_RX>;
583 pinctrl-names = "default"; 589 pinctrl-names = "default";
584 pinctrl-0 = <&uart4_pins>; 590 pinctrl-0 = <&uart4_pins>;
585}; 591};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 649b5cd38b40..b22664544a09 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -311,7 +311,7 @@
311 uart2: serial@4806c000 { 311 uart2: serial@4806c000 {
312 compatible = "ti,omap4-uart"; 312 compatible = "ti,omap4-uart";
313 reg = <0x4806c000 0x100>; 313 reg = <0x4806c000 0x100>;
314 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 314 interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
315 ti,hwmods = "uart2"; 315 ti,hwmods = "uart2";
316 clock-frequency = <48000000>; 316 clock-frequency = <48000000>;
317 }; 317 };
@@ -319,7 +319,7 @@
319 uart3: serial@48020000 { 319 uart3: serial@48020000 {
320 compatible = "ti,omap4-uart"; 320 compatible = "ti,omap4-uart";
321 reg = <0x48020000 0x100>; 321 reg = <0x48020000 0x100>;
322 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 322 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
323 ti,hwmods = "uart3"; 323 ti,hwmods = "uart3";
324 clock-frequency = <48000000>; 324 clock-frequency = <48000000>;
325 }; 325 };
@@ -327,7 +327,7 @@
327 uart4: serial@4806e000 { 327 uart4: serial@4806e000 {
328 compatible = "ti,omap4-uart"; 328 compatible = "ti,omap4-uart";
329 reg = <0x4806e000 0x100>; 329 reg = <0x4806e000 0x100>;
330 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 330 interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
331 ti,hwmods = "uart4"; 331 ti,hwmods = "uart4";
332 clock-frequency = <48000000>; 332 clock-frequency = <48000000>;
333 }; 333 };
diff --git a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts
new file mode 100644
index 000000000000..c701e8d16bbb
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts
@@ -0,0 +1,236 @@
1/*
2 * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
3 * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10/dts-v1/;
11
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/input/input.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15#include "orion5x-mv88f5182.dtsi"
16
17/ {
18 model = "LaCie d2 Network";
19 compatible = "lacie,d2-network", "marvell,orion5x-88f5182", "marvell,orion5x";
20
21 memory {
22 reg = <0x00000000 0x4000000>; /* 64 MB */
23 };
24
25 chosen {
26 bootargs = "console=ttyS0,115200n8 earlyprintk";
27 linux,stdout-path = &uart0;
28 };
29
30 soc {
31 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
32 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
33 <MBUS_ID(0x01, 0x0f) 0 0xfff80000 0x80000>;
34 };
35
36 gpio-keys {
37 compatible = "gpio-keys";
38 pinctrl-0 = <&pmx_buttons>;
39 pinctrl-names = "default";
40 #address-cells = <1>;
41 #size-cells = <0>;
42 front_button {
43 label = "Front Push Button";
44 linux,code = <KEY_POWER>;
45 gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
46 };
47
48 power_rocker_sw_on {
49 label = "Power rocker switch (on|auto)";
50 linux,input-type = <5>; /* EV_SW */
51 linux,code = <1>; /* D2NET_SWITCH_POWER_ON */
52 gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
53 };
54
55 power_rocker_sw_off {
56 label = "Power rocker switch (auto|off)";
57 linux,input-type = <5>; /* EV_SW */
58 linux,code = <2>; /* D2NET_SWITCH_POWER_OFF */
59 gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
60 };
61 };
62
63 regulators {
64 compatible = "simple-bus";
65 #address-cells = <1>;
66 #size-cells = <0>;
67 pinctrl-0 = <&pmx_sata0_power &pmx_sata1_power>;
68 pinctrl-names = "default";
69
70 sata0_power: regulator@0 {
71 compatible = "regulator-fixed";
72 reg = <0>;
73 regulator-name = "SATA0 Power";
74 regulator-min-microvolt = <5000000>;
75 regulator-max-microvolt = <5000000>;
76 enable-active-high;
77 regulator-always-on;
78 regulator-boot-on;
79 gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>;
80 };
81
82 sata1_power: regulator@1 {
83 compatible = "regulator-fixed";
84 reg = <1>;
85 regulator-name = "SATA1 Power";
86 regulator-min-microvolt = <5000000>;
87 regulator-max-microvolt = <5000000>;
88 enable-active-high;
89 regulator-always-on;
90 regulator-boot-on;
91 gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
92 };
93 };
94};
95
96&devbus_bootcs {
97 status = "okay";
98
99 devbus,keep-config;
100
101 /*
102 * Currently the MTD code does not recognize the MX29LV400CBCT
103 * as a bottom-type device. This could cause risks of
104 * accidentally erasing critical flash sectors. We thus define
105 * a single, write-protected partition covering the whole
106 * flash. TODO: once the flash part TOP/BOTTOM detection
107 * issue is sorted out in the MTD code, break this into at
108 * least three partitions: 'u-boot code', 'u-boot environment'
109 * and 'whatever is left'.
110 */
111 flash@0 {
112 compatible = "cfi-flash";
113 reg = <0 0x80000>;
114 bank-width = <1>;
115 #address-cells = <1>;
116 #size-cells = <1>;
117
118 partition@0 {
119 label = "Full512Kb";
120 reg = <0 0x80000>;
121 read-only;
122 };
123 };
124};
125
126&mdio {
127 status = "okay";
128
129 ethphy: ethernet-phy {
130 reg = <8>;
131 };
132};
133
134&ehci0 {
135 status = "okay";
136};
137
138&eth {
139 status = "okay";
140
141 ethernet-port@0 {
142 phy-handle = <&ethphy>;
143 };
144};
145
146&i2c {
147 status = "okay";
148 clock-frequency = <100000>;
149 #address-cells = <1>;
150
151 rtc@32 {
152 compatible = "ricoh,rs5c372b";
153 reg = <0x32>;
154 };
155
156 fan@3e {
157 compatible = "gmt,g762";
158 reg = <0x3e>;
159
160 /* Not enough HW info */
161 status = "disabled";
162 };
163
164 eeprom@50 {
165 compatible = "atmel,24c08";
166 reg = <0x50>;
167 };
168};
169
170&pinctrl {
171 pinctrl-0 = <&pmx_leds &pmx_board_id &pmx_fan_fail>;
172 pinctrl-names = "default";
173
174 pmx_board_id: pmx-board-id {
175 marvell,pins = "mpp0", "mpp1", "mpp2";
176 marvell,function = "gpio";
177 };
178
179 pmx_buttons: pmx-buttons {
180 marvell,pins = "mpp8", "mpp9", "mpp18";
181 marvell,function = "gpio";
182 };
183
184 pmx_fan_fail: pmx-fan-fail {
185 marvell,pins = "mpp5";
186 marvell,function = "gpio";
187 };
188
189 /*
190 * MPP6: Red front LED
191 * MPP16: Blue front LED blink control
192 */
193 pmx_leds: pmx-leds {
194 marvell,pins = "mpp6", "mpp16";
195 marvell,function = "gpio";
196 };
197
198 pmx_sata0_led_active: pmx-sata0-led-active {
199 marvell,pins = "mpp14";
200 marvell,function = "sata0";
201 };
202
203 pmx_sata0_power: pmx-sata0-power {
204 marvell,pins = "mpp3";
205 marvell,function = "gpio";
206 };
207
208 pmx_sata1_led_active: pmx-sata1-led-active {
209 marvell,pins = "mpp15";
210 marvell,function = "sata1";
211 };
212
213 pmx_sata1_power: pmx-sata1-power {
214 marvell,pins = "mpp12";
215 marvell,function = "gpio";
216 };
217
218 /*
219 * Non MPP GPIOs:
220 * GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok)
221 * GPIO 23: Blue front LED off
222 * GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled)
223 */
224};
225
226&sata {
227 pinctrl-0 = <&pmx_sata0_led_active
228 &pmx_sata1_led_active>;
229 pinctrl-names = "default";
230 status = "okay";
231 nr-ports = <2>;
232};
233
234&uart0 {
235 status = "okay";
236};
diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
index 5ed6c1376901..89ff404a528c 100644
--- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -6,8 +6,19 @@
6 * warranty of any kind, whether express or implied. 6 * warranty of any kind, whether express or implied.
7 */ 7 */
8 8
9/*
10 * TODO: add Orion USB device port init when kernel.org support is added.
11 * TODO: add flash write support: see below.
12 * TODO: add power-off support.
13 * TODO: add I2C EEPROM support.
14 */
15
9/dts-v1/; 16/dts-v1/;
10/include/ "orion5x.dtsi" 17
18#include <dt-bindings/gpio/gpio.h>
19#include <dt-bindings/input/input.h>
20#include <dt-bindings/interrupt-controller/irq.h>
21#include "orion5x-mv88f5182.dtsi"
11 22
12/ { 23/ {
13 model = "LaCie Ethernet Disk mini V2"; 24 model = "LaCie Ethernet Disk mini V2";
@@ -19,49 +30,84 @@
19 30
20 chosen { 31 chosen {
21 bootargs = "console=ttyS0,115200n8 earlyprintk"; 32 bootargs = "console=ttyS0,115200n8 earlyprintk";
33 linux,stdout-path = &uart0;
22 }; 34 };
23 35
24 ocp@f1000000 { 36 soc {
25 serial@12000 { 37 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
26 clock-frequency = <166666667>; 38 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
27 status = "okay"; 39 <MBUS_ID(0x01, 0x0f) 0 0xfff80000 0x80000>;
28 };
29
30 sata@80000 {
31 status = "okay";
32 nr-ports = <2>;
33 };
34 }; 40 };
35 41
36 gpio_keys { 42 gpio-keys {
37 compatible = "gpio-keys"; 43 compatible = "gpio-keys";
44 pinctrl-0 = <&pmx_power_button>;
45 pinctrl-names = "default";
38 #address-cells = <1>; 46 #address-cells = <1>;
39 #size-cells = <0>; 47 #size-cells = <0>;
40 button@1 { 48 button@1 {
41 label = "Power-on Switch"; 49 label = "Power-on Switch";
42 linux,code = <116>; /* KEY_POWER */ 50 linux,code = <KEY_POWER>;
43 gpios = <&gpio0 18 0>; 51 gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
44 }; 52 };
45 }; 53 };
46 54
47 gpio_leds { 55 gpio-leds {
48 compatible = "gpio-leds"; 56 compatible = "gpio-leds";
57 pinctrl-0 = <&pmx_power_led>;
58 pinctrl-names = "default";
49 59
50 led@1 { 60 led@1 {
51 label = "power:blue"; 61 label = "power:blue";
52 gpios = <&gpio0 16 1>; 62 gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
53 }; 63 };
54 }; 64 };
55}; 65};
56 66
57&mdio { 67&devbus_bootcs {
58 status = "okay"; 68 status = "okay";
59 69
60 ethphy: ethernet-phy { 70 /* Read parameters */
61 reg = <8>; 71 devbus,bus-width = <8>;
72 devbus,turn-off-ps = <90000>;
73 devbus,badr-skew-ps = <0>;
74 devbus,acc-first-ps = <186000>;
75 devbus,acc-next-ps = <186000>;
76
77 /* Write parameters */
78 devbus,wr-high-ps = <90000>;
79 devbus,wr-low-ps = <90000>;
80 devbus,ale-wr-ps = <90000>;
81
82 /*
83 * Currently the MTD code does not recognize the MX29LV400CBCT
84 * as a bottom-type device. This could cause risks of
85 * accidentally erasing critical flash sectors. We thus define
86 * a single, write-protected partition covering the whole
87 * flash. TODO: once the flash part TOP/BOTTOM detection
88 * issue is sorted out in the MTD code, break this into at
89 * least three partitions: 'u-boot code', 'u-boot environment'
90 * and 'whatever is left'.
91 */
92 flash@0 {
93 compatible = "cfi-flash";
94 reg = <0 0x80000>;
95 bank-width = <1>;
96 #address-cells = <1>;
97 #size-cells = <1>;
98
99 partition@0 {
100 label = "Full512Kb";
101 reg = <0 0x80000>;
102 read-only;
103 };
62 }; 104 };
63}; 105};
64 106
107&ehci0 {
108 status = "okay";
109};
110
65&eth { 111&eth {
66 status = "okay"; 112 status = "okay";
67 113
@@ -69,3 +115,60 @@
69 phy-handle = <&ethphy>; 115 phy-handle = <&ethphy>;
70 }; 116 };
71}; 117};
118
119&i2c {
120 status = "okay";
121 clock-frequency = <100000>;
122 #address-cells = <1>;
123
124 rtc@32 {
125 compatible = "ricoh,rs5c372a";
126 reg = <0x32>;
127 interrupt-parent = <&gpio0>;
128 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
129 };
130};
131
132&mdio {
133 status = "okay";
134
135 ethphy: ethernet-phy {
136 reg = <8>;
137 };
138};
139
140&pinctrl {
141 pinctrl-0 = <&pmx_rtc &pmx_power_led_ctrl>;
142 pinctrl-names = "default";
143
144 pmx_power_button: pmx-power-button {
145 marvell,pins = "mpp18";
146 marvell,function = "gpio";
147 };
148
149 pmx_power_led: pmx-power-led {
150 marvell,pins = "mpp16";
151 marvell,function = "gpio";
152 };
153
154 pmx_power_led_ctrl: pmx-power-led-ctrl {
155 marvell,pins = "mpp17";
156 marvell,function = "gpio";
157 };
158
159 pmx_rtc: pmx-rtc {
160 marvell,pins = "mpp3";
161 marvell,function = "gpio";
162 };
163};
164
165&sata {
166 pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
167 pinctrl-names = "default";
168 status = "okay";
169 nr-ports = <2>;
170};
171
172&uart0 {
173 status = "okay";
174};
diff --git a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts
new file mode 100644
index 000000000000..ff3484904294
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts
@@ -0,0 +1,178 @@
1/*
2 * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
3 * Copyright (C) Sylver Bruneau <sylver.bruneau@googlemail.com>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10/dts-v1/;
11
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/input/input.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15#include "orion5x-mv88f5182.dtsi"
16
17/ {
18 model = "Maxtor Shared Storage II";
19 compatible = "maxtor,shared-storage-2", "marvell,orion5x-88f5182", "marvell,orion5x";
20
21 memory {
22 reg = <0x00000000 0x4000000>; /* 64 MB */
23 };
24
25 chosen {
26 bootargs = "console=ttyS0,115200n8 earlyprintk";
27 linux,stdout-path = &uart0;
28 };
29
30 soc {
31 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
32 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
33 <MBUS_ID(0x01, 0x0f) 0 0xff800000 0x40000>;
34 };
35
36 gpio-keys {
37 compatible = "gpio-keys";
38 pinctrl-0 = <&pmx_buttons>;
39 pinctrl-names = "default";
40 #address-cells = <1>;
41 #size-cells = <0>;
42 power {
43 label = "Power";
44 linux,code = <KEY_POWER>;
45 gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
46 };
47
48 reset {
49 label = "Reset";
50 linux,code = <KEY_RESTART>;
51 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
52 };
53 };
54};
55
56&devbus_bootcs {
57 status = "okay";
58
59 devbus,keep-config;
60
61 /*
62 * Currently the MTD code does not recognize the MX29LV400CBCT
63 * as a bottom-type device. This could cause risks of
64 * accidentally erasing critical flash sectors. We thus define
65 * a single, write-protected partition covering the whole
66 * flash. TODO: once the flash part TOP/BOTTOM detection
67 * issue is sorted out in the MTD code, break this into at
68 * least three partitions: 'u-boot code', 'u-boot environment'
69 * and 'whatever is left'.
70 */
71 flash@0 {
72 compatible = "cfi-flash";
73 reg = <0 0x40000>;
74 bank-width = <1>;
75 #address-cells = <1>;
76 #size-cells = <1>;
77 };
78};
79
80&mdio {
81 status = "okay";
82
83 ethphy: ethernet-phy {
84 reg = <8>;
85 };
86};
87
88&ehci0 {
89 status = "okay";
90};
91
92&eth {
93 status = "okay";
94
95 ethernet-port@0 {
96 phy-handle = <&ethphy>;
97 };
98};
99
100&i2c {
101 status = "okay";
102 clock-frequency = <100000>;
103 #address-cells = <1>;
104
105 rtc@68 {
106 compatible = "st,m41t81";
107 reg = <0x68>;
108 pinctrl-0 = <&pmx_rtc>;
109 pinctrl-names = "default";
110 interrupt-parent = <&gpio0>;
111 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
112 };
113};
114
115&pinctrl {
116 pinctrl-0 = <&pmx_leds &pmx_misc>;
117 pinctrl-names = "default";
118
119 pmx_buttons: pmx-buttons {
120 marvell,pins = "mpp11", "mpp12";
121 marvell,function = "gpio";
122 };
123
124 /*
125 * MPP0: Power LED
126 * MPP1: Error LED
127 */
128 pmx_leds: pmx-leds {
129 marvell,pins = "mpp0", "mpp1";
130 marvell,function = "gpio";
131 };
132
133 /*
134 * MPP4: HDD ind. (Single/Dual)
135 * MPP5: HD0 5V control
136 * MPP6: HD0 12V control
137 * MPP7: HD1 5V control
138 * MPP8: HD1 12V control
139 */
140 pmx_misc: pmx-misc {
141 marvell,pins = "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", "mpp10";
142 marvell,function = "gpio";
143 };
144
145 pmx_rtc: pmx-rtc {
146 marvell,pins = "mpp3";
147 marvell,function = "gpio";
148 };
149
150 pmx_sata0_led_active: pmx-sata0-led-active {
151 marvell,pins = "mpp14";
152 marvell,function = "sata0";
153 };
154
155 pmx_sata1_led_active: pmx-sata1-led-active {
156 marvell,pins = "mpp15";
157 marvell,function = "sata1";
158 };
159
160 /*
161 * Non MPP GPIOs:
162 * GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok)
163 * GPIO 23: Blue front LED off
164 * GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled)
165 */
166};
167
168&sata {
169 pinctrl-0 = <&pmx_sata0_led_active
170 &pmx_sata1_led_active>;
171 pinctrl-names = "default";
172 status = "okay";
173 nr-ports = <2>;
174};
175
176&uart0 {
177 status = "okay";
178};
diff --git a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
new file mode 100644
index 000000000000..d1ed71c60209
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
@@ -0,0 +1,45 @@
1/*
2 * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#include "orion5x.dtsi"
10
11/ {
12 compatible = "marvell,orion5x-88f5182", "marvell,orion5x";
13
14 soc {
15 compatible = "marvell,orion5x-88f5182-mbus", "simple-bus";
16
17 internal-regs {
18 pinctrl: pinctrl@10000 {
19 compatible = "marvell,88f5182-pinctrl";
20 reg = <0x10000 0x8>, <0x10050 0x4>;
21
22 pmx_sata0: pmx-sata0 {
23 marvell,pins = "mpp12", "mpp14";
24 marvell,function = "sata0";
25 };
26
27 pmx_sata1: pmx-sata1 {
28 marvell,pins = "mpp13", "mpp15";
29 marvell,function = "sata1";
30 };
31 };
32
33 core_clk: core-clocks@10030 {
34 compatible = "marvell,mv88f5182-core-clock";
35 reg = <0x10010 0x4>;
36 #clock-cells = <1>;
37 };
38
39 mbusc: mbus-controller@20000 {
40 compatible = "marvell,mbus-controller";
41 reg = <0x20000 0x100>, <0x1500 0x20>;
42 };
43 };
44 };
45};
diff --git a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
new file mode 100644
index 000000000000..6fb052507b36
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
@@ -0,0 +1,177 @@
1/*
2 * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/gpio/gpio.h>
12#include "orion5x-mv88f5182.dtsi"
13
14/ {
15 model = "Marvell Reference Design 88F5182 NAS";
16 compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x";
17
18 memory {
19 reg = <0x00000000 0x4000000>; /* 64 MB */
20 };
21
22 chosen {
23 bootargs = "console=ttyS0,115200n8 earlyprintk";
24 linux,stdout-path = &uart0;
25 };
26
27 soc {
28 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
29 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
30 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x80000>,
31 <MBUS_ID(0x01, 0x1d) 0 0xfc000000 0x1000000>;
32 };
33
34 gpio-leds {
35 compatible = "gpio-leds";
36 pinctrl-0 = <&pmx_debug_led>;
37 pinctrl-names = "default";
38
39 led@0 {
40 label = "rd88f5182:cpu";
41 linux,default-trigger = "heartbeat";
42 gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
43 };
44 };
45};
46
47&devbus_bootcs {
48 status = "okay";
49
50 /* Read parameters */
51 devbus,bus-width = <8>;
52 devbus,turn-off-ps = <90000>;
53 devbus,badr-skew-ps = <0>;
54 devbus,acc-first-ps = <186000>;
55 devbus,acc-next-ps = <186000>;
56
57 /* Write parameters */
58 devbus,wr-high-ps = <90000>;
59 devbus,wr-low-ps = <90000>;
60 devbus,ale-wr-ps = <90000>;
61
62 flash@0 {
63 compatible = "cfi-flash";
64 reg = <0 0x80000>;
65 bank-width = <1>;
66 };
67};
68
69&devbus_cs1 {
70 status = "okay";
71
72 /* Read parameters */
73 devbus,bus-width = <8>;
74 devbus,turn-off-ps = <90000>;
75 devbus,badr-skew-ps = <0>;
76 devbus,acc-first-ps = <186000>;
77 devbus,acc-next-ps = <186000>;
78
79 /* Write parameters */
80 devbus,wr-high-ps = <90000>;
81 devbus,wr-low-ps = <90000>;
82 devbus,ale-wr-ps = <90000>;
83
84 flash@0 {
85 compatible = "cfi-flash";
86 reg = <0 0x1000000>;
87 bank-width = <1>;
88 };
89};
90
91&ehci0 {
92 status = "okay";
93};
94
95&ehci1 {
96 status = "okay";
97};
98
99&eth {
100 status = "okay";
101
102 ethernet-port@0 {
103 phy-handle = <&ethphy>;
104 };
105};
106
107&i2c {
108 status = "okay";
109 clock-frequency = <100000>;
110 #address-cells = <1>;
111
112 rtc@68 {
113 pinctrl-0 = <&pmx_rtc>;
114 pinctrl-names = "default";
115 compatible = "dallas,ds1338";
116 reg = <0x68>;
117 };
118};
119
120&mdio {
121 status = "okay";
122
123 ethphy: ethernet-phy {
124 reg = <8>;
125 };
126};
127
128&pinctrl {
129 pinctrl-0 = <&pmx_reset_switch &pmx_misc_gpios
130 &pmx_pci_gpios>;
131 pinctrl-names = "default";
132
133 /*
134 * MPP[20] PCI Clock to MV88F5182
135 * MPP[21] PCI Clock to mini PCI CON11
136 * MPP[22] USB 0 over current indication
137 * MPP[23] USB 1 over current indication
138 * MPP[24] USB 1 over current enable
139 * MPP[25] USB 0 over current enable
140 */
141
142 pmx_debug_led: pmx-debug_led {
143 marvell,pins = "mpp0";
144 marvell,function = "gpio";
145 };
146
147 pmx_reset_switch: pmx-reset-switch {
148 marvell,pins = "mpp1";
149 marvell,function = "gpio";
150 };
151
152 pmx_rtc: pmx-rtc {
153 marvell,pins = "mpp3";
154 marvell,function = "gpio";
155 };
156
157 pmx_misc_gpios: pmx-misc-gpios {
158 marvell,pins = "mpp4", "mpp5";
159 marvell,function = "gpio";
160 };
161
162 pmx_pci_gpios: pmx-pci-gpios {
163 marvell,pins = "mpp6", "mpp7";
164 marvell,function = "gpio";
165 };
166};
167
168&sata {
169 pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
170 pinctrl-names = "default";
171 status = "okay";
172 nr-ports = <2>;
173};
174
175&uart0 {
176 status = "okay";
177};
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index 174d89241f70..75cd01bd6024 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -6,7 +6,9 @@
6 * warranty of any kind, whether express or implied. 6 * warranty of any kind, whether express or implied.
7 */ 7 */
8 8
9/include/ "skeleton.dtsi" 9#include "skeleton.dtsi"
10
11#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
10 12
11/ { 13/ {
12 model = "Marvell Orion5x SoC"; 14 model = "Marvell Orion5x SoC";
@@ -17,149 +19,214 @@
17 gpio0 = &gpio0; 19 gpio0 = &gpio0;
18 }; 20 };
19 21
20 intc: interrupt-controller { 22 soc {
21 compatible = "marvell,orion-intc"; 23 #address-cells = <2>;
22 interrupt-controller;
23 #interrupt-cells = <1>;
24 reg = <0xf1020200 0x08>;
25 };
26
27 ocp@f1000000 {
28 compatible = "simple-bus";
29 ranges = <0x00000000 0xf1000000 0x4000000
30 0xf2200000 0xf2200000 0x0000800>;
31 #address-cells = <1>;
32 #size-cells = <1>; 24 #size-cells = <1>;
25 controller = <&mbusc>;
33 26
34 gpio0: gpio@10100 { 27 devbus_bootcs: devbus-bootcs {
35 compatible = "marvell,orion-gpio"; 28 compatible = "marvell,orion-devbus";
36 #gpio-cells = <2>; 29 reg = <MBUS_ID(0xf0, 0x01) 0x1046C 0x4>;
37 gpio-controller; 30 ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>;
38 reg = <0x10100 0x40>;
39 ngpios = <32>;
40 interrupt-controller;
41 #interrupt-cells = <2>;
42 interrupts = <6>, <7>, <8>, <9>;
43 };
44
45 spi@10600 {
46 compatible = "marvell,orion-spi";
47 #address-cells = <1>; 31 #address-cells = <1>;
48 #size-cells = <0>; 32 #size-cells = <1>;
49 cell-index = <0>; 33 clocks = <&core_clk 0>;
50 reg = <0x10600 0x28>;
51 status = "disabled"; 34 status = "disabled";
52 }; 35 };
53 36
54 i2c@11000 { 37 devbus_cs0: devbus-cs0 {
55 compatible = "marvell,mv64xxx-i2c"; 38 compatible = "marvell,orion-devbus";
56 reg = <0x11000 0x20>; 39 reg = <MBUS_ID(0xf0, 0x01) 0x1045C 0x4>;
40 ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>;
57 #address-cells = <1>; 41 #address-cells = <1>;
58 #size-cells = <0>; 42 #size-cells = <1>;
59 interrupts = <5>; 43 clocks = <&core_clk 0>;
60 clock-frequency = <100000>;
61 status = "disabled"; 44 status = "disabled";
62 }; 45 };
63 46
64 serial@12000 { 47 devbus_cs1: devbus-cs1 {
65 compatible = "ns16550a"; 48 compatible = "marvell,orion-devbus";
66 reg = <0x12000 0x100>; 49 reg = <MBUS_ID(0xf0, 0x01) 0x10460 0x4>;
67 reg-shift = <2>; 50 ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>;
68 interrupts = <3>; 51 #address-cells = <1>;
69 /* set clock-frequency in board dts */ 52 #size-cells = <1>;
53 clocks = <&core_clk 0>;
70 status = "disabled"; 54 status = "disabled";
71 }; 55 };
72 56
73 serial@12100 { 57 devbus_cs2: devbus-cs2 {
74 compatible = "ns16550a"; 58 compatible = "marvell,orion-devbus";
75 reg = <0x12100 0x100>; 59 reg = <MBUS_ID(0xf0, 0x01) 0x10464 0x4>;
76 reg-shift = <2>; 60 ranges = <0 MBUS_ID(0x01, 0x1b) 0 0xffffffff>;
77 interrupts = <4>; 61 #address-cells = <1>;
78 /* set clock-frequency in board dts */ 62 #size-cells = <1>;
63 clocks = <&core_clk 0>;
79 status = "disabled"; 64 status = "disabled";
80 }; 65 };
81 66
82 wdt@20300 { 67 internal-regs {
83 compatible = "marvell,orion-wdt"; 68 compatible = "simple-bus";
84 reg = <0x20300 0x28>; 69 #address-cells = <1>;
85 status = "okay"; 70 #size-cells = <1>;
86 }; 71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
72
73 gpio0: gpio@10100 {
74 compatible = "marvell,orion-gpio";
75 #gpio-cells = <2>;
76 gpio-controller;
77 reg = <0x10100 0x40>;
78 ngpios = <32>;
79 interrupt-controller;
80 #interrupt-cells = <2>;
81 interrupts = <6>, <7>, <8>, <9>;
82 };
87 83
88 ehci@50000 { 84 spi: spi@10600 {
89 compatible = "marvell,orion-ehci"; 85 compatible = "marvell,orion-spi";
90 reg = <0x50000 0x1000>; 86 #address-cells = <1>;
91 interrupts = <17>; 87 #size-cells = <0>;
92 status = "disabled"; 88 cell-index = <0>;
93 }; 89 reg = <0x10600 0x28>;
90 status = "disabled";
91 };
94 92
95 xor@60900 { 93 i2c: i2c@11000 {
96 compatible = "marvell,orion-xor"; 94 compatible = "marvell,mv64xxx-i2c";
97 reg = <0x60900 0x100 95 reg = <0x11000 0x20>;
98 0x60b00 0x100>; 96 #address-cells = <1>;
99 status = "okay"; 97 #size-cells = <0>;
98 interrupts = <5>;
99 clocks = <&core_clk 0>;
100 status = "disabled";
101 };
100 102
101 xor00 { 103 uart0: serial@12000 {
102 interrupts = <30>; 104 compatible = "ns16550a";
103 dmacap,memcpy; 105 reg = <0x12000 0x100>;
104 dmacap,xor; 106 reg-shift = <2>;
107 interrupts = <3>;
108 clocks = <&core_clk 0>;
109 status = "disabled";
105 }; 110 };
106 xor01 { 111
107 interrupts = <31>; 112 uart1: serial@12100 {
108 dmacap,memcpy; 113 compatible = "ns16550a";
109 dmacap,xor; 114 reg = <0x12100 0x100>;
110 dmacap,memset; 115 reg-shift = <2>;
116 interrupts = <4>;
117 clocks = <&core_clk 0>;
118 status = "disabled";
111 }; 119 };
112 };
113 120
114 eth: ethernet-controller@72000 { 121 bridge_intc: bridge-interrupt-ctrl@20110 {
115 compatible = "marvell,orion-eth"; 122 compatible = "marvell,orion-bridge-intc";
116 #address-cells = <1>; 123 interrupt-controller;
117 #size-cells = <0>; 124 #interrupt-cells = <1>;
118 reg = <0x72000 0x4000>; 125 reg = <0x20110 0x8>;
119 marvell,tx-checksum-limit = <1600>; 126 interrupts = <0>;
120 status = "disabled"; 127 marvell,#interrupts = <4>;
128 };
121 129
122 ethernet-port@0 { 130 intc: interrupt-controller@20200 {
123 compatible = "marvell,orion-eth-port"; 131 compatible = "marvell,orion-intc";
124 reg = <0>; 132 interrupt-controller;
125 /* overwrite MAC address in bootloader */ 133 #interrupt-cells = <1>;
126 local-mac-address = [00 00 00 00 00 00]; 134 reg = <0x20200 0x08>;
127 /* set phy-handle property in board file */
128 }; 135 };
129 };
130 136
131 mdio: mdio-bus@72004 { 137 timer: timer@20300 {
132 compatible = "marvell,orion-mdio"; 138 compatible = "marvell,orion-timer";
133 #address-cells = <1>; 139 reg = <0x20300 0x20>;
134 #size-cells = <0>; 140 interrupt-parent = <&bridge_intc>;
135 reg = <0x72004 0x84>; 141 interrupts = <1>, <2>;
136 interrupts = <22>; 142 clocks = <&core_clk 0>;
137 status = "disabled"; 143 };
138 144
139 /* add phy nodes in board file */ 145 wdt: wdt@20300 {
140 }; 146 compatible = "marvell,orion-wdt";
147 reg = <0x20300 0x28>;
148 interrupt-parent = <&bridge_intc>;
149 interrupts = <3>;
150 status = "okay";
151 };
141 152
142 sata@80000 { 153 ehci0: ehci@50000 {
143 compatible = "marvell,orion-sata"; 154 compatible = "marvell,orion-ehci";
144 reg = <0x80000 0x5000>; 155 reg = <0x50000 0x1000>;
145 interrupts = <29>; 156 interrupts = <17>;
146 status = "disabled"; 157 status = "disabled";
158 };
159
160 xor: dma-controller@60900 {
161 compatible = "marvell,orion-xor";
162 reg = <0x60900 0x100
163 0x60b00 0x100>;
164 status = "okay";
165
166 xor00 {
167 interrupts = <30>;
168 dmacap,memcpy;
169 dmacap,xor;
170 };
171 xor01 {
172 interrupts = <31>;
173 dmacap,memcpy;
174 dmacap,xor;
175 dmacap,memset;
176 };
177 };
178
179 eth: ethernet-controller@72000 {
180 compatible = "marvell,orion-eth";
181 #address-cells = <1>;
182 #size-cells = <0>;
183 reg = <0x72000 0x4000>;
184 marvell,tx-checksum-limit = <1600>;
185 status = "disabled";
186
187 ethport: ethernet-port@0 {
188 compatible = "marvell,orion-eth-port";
189 reg = <0>;
190 interrupts = <21>;
191 /* overwrite MAC address in bootloader */
192 local-mac-address = [00 00 00 00 00 00];
193 /* set phy-handle property in board file */
194 };
195 };
196
197 mdio: mdio-bus@72004 {
198 compatible = "marvell,orion-mdio";
199 #address-cells = <1>;
200 #size-cells = <0>;
201 reg = <0x72004 0x84>;
202 interrupts = <22>;
203 status = "disabled";
204
205 /* add phy nodes in board file */
206 };
207
208 sata: sata@80000 {
209 compatible = "marvell,orion-sata";
210 reg = <0x80000 0x5000>;
211 interrupts = <29>;
212 status = "disabled";
213 };
214
215 ehci1: ehci@a0000 {
216 compatible = "marvell,orion-ehci";
217 reg = <0xa0000 0x1000>;
218 interrupts = <12>;
219 status = "disabled";
220 };
147 }; 221 };
148 222
149 crypto@90000 { 223 cesa: crypto@90000 {
150 compatible = "marvell,orion-crypto"; 224 compatible = "marvell,orion-crypto";
151 reg = <0x90000 0x10000>, 225 reg = <MBUS_ID(0xf0, 0x01) 0x90000 0x10000>,
152 <0xf2200000 0x800>; 226 <MBUS_ID(0x09, 0x00) 0x0 0x800>;
153 reg-names = "regs", "sram"; 227 reg-names = "regs", "sram";
154 interrupts = <28>; 228 interrupts = <28>;
155 status = "okay"; 229 status = "okay";
156 }; 230 };
157
158 ehci@a0000 {
159 compatible = "marvell,orion-ehci";
160 reg = <0xa0000 0x1000>;
161 interrupts = <12>;
162 status = "disabled";
163 };
164 }; 231 };
165}; 232};
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 2551e9438d35..97a9545f5232 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -22,6 +22,7 @@
22 compatible = "arm,cortex-a9"; 22 compatible = "arm,cortex-a9";
23 device_type = "cpu"; 23 device_type = "cpu";
24 reg = <0x0>; 24 reg = <0x0>;
25 clock-frequency = <800000000>;
25 }; 26 };
26 }; 27 };
27 28
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 618e5b537eaf..10b326bdf831 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -673,7 +673,7 @@
673 renesas,clock-indices = < 673 renesas,clock-indices = <
674 R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 674 R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
675 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 675 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
676 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY 676 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
677 >; 677 >;
678 clock-output-names = 678 clock-output-names =
679 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", 679 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 46181708e59c..aa1cba94196c 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -688,7 +688,7 @@
688 renesas,clock-indices = < 688 renesas,clock-indices = <
689 R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 689 R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
690 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 690 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
691 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_SY 691 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
692 >; 692 >;
693 clock-output-names = 693 clock-output-names =
694 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", 694 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 4d4dfbb59f4b..90b354db16a0 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -24,6 +24,7 @@
24 cpus { 24 cpus {
25 #address-cells = <1>; 25 #address-cells = <1>;
26 #size-cells = <0>; 26 #size-cells = <0>;
27 enable-method = "rockchip,rk3066-smp";
27 28
28 cpu@0 { 29 cpu@0 {
29 device_type = "cpu"; 30 device_type = "cpu";
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index ed9a70af3e3f..2b494ceef6fc 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -24,6 +24,7 @@
24 cpus { 24 cpus {
25 #address-cells = <1>; 25 #address-cells = <1>;
26 #size-cells = <0>; 26 #size-cells = <0>;
27 enable-method = "rockchip,rk3066-smp";
27 28
28 cpu@0 { 29 cpu@0 {
29 device_type = "cpu"; 30 device_type = "cpu";
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index a106b0872910..3f260b9cd51f 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -58,6 +58,18 @@
58 reg = <0x20000000 0x8000000>; 58 reg = <0x20000000 0x8000000>;
59 }; 59 };
60 60
61 slow_xtal: slow_xtal {
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <0>;
65 };
66
67 main_xtal: main_xtal {
68 compatible = "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <0>;
71 };
72
61 clocks { 73 clocks {
62 adc_op_clk: adc_op_clk{ 74 adc_op_clk: adc_op_clk{
63 compatible = "fixed-clock"; 75 compatible = "fixed-clock";
@@ -749,18 +761,29 @@
749 #size-cells = <0>; 761 #size-cells = <0>;
750 #interrupt-cells = <1>; 762 #interrupt-cells = <1>;
751 763
752 clk32k: slck { 764 main_rc_osc: main_rc_osc {
753 compatible = "fixed-clock"; 765 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
754 #clock-cells = <0>; 766 #clock-cells = <0>;
755 clock-frequency = <32768>; 767 interrupt-parent = <&pmc>;
768 interrupts = <AT91_PMC_MOSCRCS>;
769 clock-frequency = <12000000>;
770 clock-accuracy = <50000000>;
756 }; 771 };
757 772
758 main: mainck { 773 main_osc: main_osc {
759 compatible = "atmel,at91rm9200-clk-main"; 774 compatible = "atmel,at91rm9200-clk-main-osc";
760 #clock-cells = <0>; 775 #clock-cells = <0>;
761 interrupt-parent = <&pmc>; 776 interrupt-parent = <&pmc>;
762 interrupts = <AT91_PMC_MOSCS>; 777 interrupts = <AT91_PMC_MOSCS>;
763 clocks = <&clk32k>; 778 clocks = <&main_xtal>;
779 };
780
781 main: mainck {
782 compatible = "atmel,at91sam9x5-clk-main";
783 #clock-cells = <0>;
784 interrupt-parent = <&pmc>;
785 interrupts = <AT91_PMC_MOSCSELS>;
786 clocks = <&main_rc_osc &main_osc>;
764 }; 787 };
765 788
766 plla: pllack { 789 plla: pllack {
@@ -1089,6 +1112,32 @@
1089 status = "disabled"; 1112 status = "disabled";
1090 }; 1113 };
1091 1114
1115 sckc@fffffe50 {
1116 compatible = "atmel,at91sam9x5-sckc";
1117 reg = <0xfffffe50 0x4>;
1118
1119 slow_rc_osc: slow_rc_osc {
1120 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1121 #clock-cells = <0>;
1122 clock-frequency = <32768>;
1123 clock-accuracy = <50000000>;
1124 atmel,startup-time-usec = <75>;
1125 };
1126
1127 slow_osc: slow_osc {
1128 compatible = "atmel,at91sam9x5-clk-slow-osc";
1129 #clock-cells = <0>;
1130 clocks = <&slow_xtal>;
1131 atmel,startup-time-usec = <1200000>;
1132 };
1133
1134 clk32k: slowck {
1135 compatible = "atmel,at91sam9x5-clk-slow";
1136 #clock-cells = <0>;
1137 clocks = <&slow_rc_osc &slow_osc>;
1138 };
1139 };
1140
1092 rtc@fffffeb0 { 1141 rtc@fffffeb0 {
1093 compatible = "atmel,at91rm9200-rtc"; 1142 compatible = "atmel,at91rm9200-rtc";
1094 reg = <0xfffffeb0 0x30>; 1143 reg = <0xfffffeb0 0x30>;
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index f55ed072c8e6..b0b1331c1974 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -18,6 +18,14 @@
18 reg = <0x20000000 0x20000000>; 18 reg = <0x20000000 0x20000000>;
19 }; 19 };
20 20
21 slow_xtal {
22 clock-frequency = <32768>;
23 };
24
25 main_xtal {
26 clock-frequency = <12000000>;
27 };
28
21 ahb { 29 ahb {
22 apb { 30 apb {
23 spi0: spi@f0004000 { 31 spi0: spi@f0004000 {
diff --git a/arch/arm/boot/dts/twl4030_omap3.dtsi b/arch/arm/boot/dts/twl4030_omap3.dtsi
index c353ef0a6ac7..3537ae5b2146 100644
--- a/arch/arm/boot/dts/twl4030_omap3.dtsi
+++ b/arch/arm/boot/dts/twl4030_omap3.dtsi
@@ -8,7 +8,7 @@
8 8
9&twl { 9&twl {
10 pinctrl-names = "default"; 10 pinctrl-names = "default";
11 pinctrl-0 = <&twl4030_pins>; 11 pinctrl-0 = <&twl4030_pins &twl4030_vpins>;
12}; 12};
13 13
14&omap3_pmx_core { 14&omap3_pmx_core {
@@ -23,3 +23,20 @@
23 >; 23 >;
24 }; 24 };
25}; 25};
26
27/*
28 * If your board is not using the I2C4 pins with twl4030, then don't include
29 * this file. For proper idle mode signaling with sys_clkreq and sys_off_mode
30 * pins we need to configure I2C4, or else use the legacy sys_nvmode1 and
31 * sys_nvmode2 signaling.
32 */
33&omap3_pmx_wkup {
34 twl4030_vpins: pinmux_twl4030_vpins {
35 pinctrl-single,pins = <
36 OMAP3_WKUP_IOPAD(0x2a00, PIN_INPUT | MUX_MODE0) /* i2c4_scl.i2c4_scl */
37 OMAP3_WKUP_IOPAD(0x2a02, PIN_INPUT | MUX_MODE0) /* i2c4_sda.i2c4_sda */
38 OMAP3_WKUP_IOPAD(0x2a06, PIN_OUTPUT | MUX_MODE0) /* sys_clkreq.sys_clkreq */
39 OMAP3_WKUP_IOPAD(0x2a18, PIN_OUTPUT | MUX_MODE0) /* sys_off_mode.sys_off_mode */
40 >;
41 };
42};
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index c1176abc34d9..80d8e4f3f626 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -177,6 +177,11 @@
177 }; 177 };
178 }; 178 };
179 179
180 devcfg: devcfg@f8007000 {
181 compatible = "xlnx,zynq-devcfg-1.0";
182 reg = <0xf8007000 0x100>;
183 } ;
184
180 global_timer: timer@f8f00200 { 185 global_timer: timer@f8f00200 {
181 compatible = "arm,cortex-a9-global-timer"; 186 compatible = "arm,cortex-a9-global-timer";
182 reg = <0xf8f00200 0x20>; 187 reg = <0xf8f00200 0x20>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 13:30:57 -0500