1 files changed, 133 insertions, 3 deletions

diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index 3f0c736d31d6..1420bb14d95c 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -12,6 +12,7 @@
 / {
         model = "V2P-CA9";
         arm,hbi = <0x191>;
+        arm,vexpress,site = <0xf>;
         compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
         interrupt-parent = <&gic>;
         #address-cells = <1>;
@@ -70,11 +71,15 @@
                 compatible = "arm,pl111", "arm,primecell";
                 reg = <0x10020000 0x1000>;
                 interrupts = <0 44 4>;
+                clocks = <&oscclk1>, <&oscclk2>;
+                clock-names = "clcdclk", "apb_pclk";
         };
 
         memory-controller@100e0000 {
                 compatible = "arm,pl341", "arm,primecell";
                 reg = <0x100e0000 0x1000>;
+                clocks = <&oscclk2>;
+                clock-names = "apb_pclk";
         };
 
         memory-controller@100e1000 {
@@ -82,6 +87,8 @@
                 reg = <0x100e1000 0x1000>;
                 interrupts = <0 45 4>,
                              <0 46 4>;
+                clocks = <&oscclk2>;
+                clock-names = "apb_pclk";
         };
 
         timer@100e4000 {
@@ -89,12 +96,16 @@
                 reg = <0x100e4000 0x1000>;
                 interrupts = <0 48 4>,
                              <0 49 4>;
+                clocks = <&oscclk2>, <&oscclk2>;
+                clock-names = "timclk", "apb_pclk";
         };
 
         watchdog@100e5000 {
                 compatible = "arm,sp805", "arm,primecell";
                 reg = <0x100e5000 0x1000>;
                 interrupts = <0 51 4>;
+                clocks = <&oscclk2>, <&oscclk2>;
+                clock-names = "wdogclk", "apb_pclk";
         };
 
         scu@1e000000 {
@@ -140,13 +151,132 @@
                              <0 63 4>;
         };
 
-        motherboard {
+        dcc {
+                compatible = "arm,vexpress,config-bus";
+                arm,vexpress,config-bridge = <&v2m_sysreg>;
+
+                osc@0 {
+                        /* ACLK clock to the AXI master port on the test chip */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 0>;
+                        freq-range = <30000000 50000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "extsaxiclk";
+                };
+
+                oscclk1: osc@1 {
+                        /* Reference clock for the CLCD */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 1>;
+                        freq-range = <10000000 80000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "clcdclk";
+                };
+
+                smbclk: oscclk2: osc@2 {
+                        /* Reference clock for the test chip internal PLLs */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 2>;
+                        freq-range = <33000000 100000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "tcrefclk";
+                };
+
+                volt@0 {
+                        /* Test Chip internal logic voltage */
+                        compatible = "arm,vexpress-volt";
+                        arm,vexpress-sysreg,func = <2 0>;
+                        regulator-name = "VD10";
+                        regulator-always-on;
+                        label = "VD10";
+                };
+
+                volt@1 {
+                        /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
+                        compatible = "arm,vexpress-volt";
+                        arm,vexpress-sysreg,func = <2 1>;
+                        regulator-name = "VD10_S2";
+                        regulator-always-on;
+                        label = "VD10_S2";
+                };
+
+                volt@2 {
+                        /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
+                        compatible = "arm,vexpress-volt";
+                        arm,vexpress-sysreg,func = <2 2>;
+                        regulator-name = "VD10_S3";
+                        regulator-always-on;
+                        label = "VD10_S3";
+                };
+
+                volt@3 {
+                        /* DDR2 SDRAM and Test Chip DDR2 I/O supply */
+                        compatible = "arm,vexpress-volt";
+                        arm,vexpress-sysreg,func = <2 3>;
+                        regulator-name = "VCC1V8";
+                        regulator-always-on;
+                        label = "VCC1V8";
+                };
+
+                volt@4 {
+                        /* DDR2 SDRAM VTT termination voltage */
+                        compatible = "arm,vexpress-volt";
+                        arm,vexpress-sysreg,func = <2 4>;
+                        regulator-name = "DDR2VTT";
+                        regulator-always-on;
+                        label = "DDR2VTT";
+                };
+
+                volt@5 {
+                        /* Local board supply for miscellaneous logic external to the Test Chip */
+                        arm,vexpress-sysreg,func = <2 5>;
+                        compatible = "arm,vexpress-volt";
+                        regulator-name = "VCC3V3";
+                        regulator-always-on;
+                        label = "VCC3V3";
+                };
+
+                amp@0 {
+                        /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
+                        compatible = "arm,vexpress-amp";
+                        arm,vexpress-sysreg,func = <3 0>;
+                        label = "VD10_S2";
+                };
+
+                amp@1 {
+                        /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
+                        compatible = "arm,vexpress-amp";
+                        arm,vexpress-sysreg,func = <3 1>;
+                        label = "VD10_S3";
+                };
+
+                power@0 {
+                        /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
+                        compatible = "arm,vexpress-power";
+                        arm,vexpress-sysreg,func = <12 0>;
+                        label = "PVD10_S2";
+                };
+
+                power@1 {
+                        /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
+                        compatible = "arm,vexpress-power";
+                        arm,vexpress-sysreg,func = <12 1>;
+                        label = "PVD10_S3";
+                };
+        };
+
+        smb {
+                compatible = "simple-bus";
+
+                #address-cells = <2>;
+                #size-cells = <1>;
                 ranges = <0 0 0x40000000 0x04000000>,
                          <1 0 0x44000000 0x04000000>,
                          <2 0 0x48000000 0x04000000>,
                          <3 0 0x4c000000 0x04000000>,
                          <7 0 0x10000000 0x00020000>;
 
+                #interrupt-cells = <1>;
                 interrupt-map-mask = <0 0 63>;
                 interrupt-map = <0 0  0 &gic 0  0 4>,
                                 <0 0  1 &gic 0  1 4>,
@@ -191,7 +321,7 @@
                                 <0 0 40 &gic 0 40 4>,
                                 <0 0 41 &gic 0 41 4>,
                                 <0 0 42 &gic 0 42 4>;
+
+                /include/ "vexpress-v2m.dtsi"
         };
 };
-
-/include/ "vexpress-v2m.dtsi"