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Diffstat (limited to 'arch/arm/boot/dts/tegra30.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi156
1 files changed, 156 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index d8783f0fae63..0022c127e1d9 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -16,6 +16,76 @@
16 serial4 = &uarte; 16 serial4 = &uarte;
17 }; 17 };
18 18
19 pcie-controller {
20 compatible = "nvidia,tegra30-pcie";
21 device_type = "pci";
22 reg = <0x00003000 0x00000800 /* PADS registers */
23 0x00003800 0x00000200 /* AFI registers */
24 0x10000000 0x10000000>; /* configuration space */
25 reg-names = "pads", "afi", "cs";
26 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
27 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
28 interrupt-names = "intr", "msi";
29
30 bus-range = <0x00 0xff>;
31 #address-cells = <3>;
32 #size-cells = <2>;
33
34 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
35 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
36 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
37 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
38 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
39 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
40
41 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
42 <&tegra_car TEGRA30_CLK_AFI>,
43 <&tegra_car TEGRA30_CLK_PCIEX>,
44 <&tegra_car TEGRA30_CLK_PLL_E>,
45 <&tegra_car TEGRA30_CLK_CML0>;
46 clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
47 status = "disabled";
48
49 pci@1,0 {
50 device_type = "pci";
51 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
52 reg = <0x000800 0 0 0 0>;
53 status = "disabled";
54
55 #address-cells = <3>;
56 #size-cells = <2>;
57 ranges;
58
59 nvidia,num-lanes = <2>;
60 };
61
62 pci@2,0 {
63 device_type = "pci";
64 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
65 reg = <0x001000 0 0 0 0>;
66 status = "disabled";
67
68 #address-cells = <3>;
69 #size-cells = <2>;
70 ranges;
71
72 nvidia,num-lanes = <2>;
73 };
74
75 pci@3,0 {
76 device_type = "pci";
77 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
78 reg = <0x001800 0 0 0 0>;
79 status = "disabled";
80
81 #address-cells = <3>;
82 #size-cells = <2>;
83 ranges;
84
85 nvidia,num-lanes = <2>;
86 };
87 };
88
19 host1x { 89 host1x {
20 compatible = "nvidia,tegra30-host1x", "simple-bus"; 90 compatible = "nvidia,tegra30-host1x", "simple-bus";
21 reg = <0x50000000 0x00024000>; 91 reg = <0x50000000 0x00024000>;
@@ -561,6 +631,92 @@
561 status = "disabled"; 631 status = "disabled";
562 }; 632 };
563 633
634 usb@7d000000 {
635 compatible = "nvidia,tegra30-ehci", "usb-ehci";
636 reg = <0x7d000000 0x4000>;
637 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
638 phy_type = "utmi";
639 clocks = <&tegra_car TEGRA30_CLK_USBD>;
640 nvidia,needs-double-reset;
641 nvidia,phy = <&phy1>;
642 status = "disabled";
643 };
644
645 phy1: usb-phy@7d000000 {
646 compatible = "nvidia,tegra30-usb-phy";
647 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
648 phy_type = "utmi";
649 clocks = <&tegra_car TEGRA30_CLK_USBD>,
650 <&tegra_car TEGRA30_CLK_PLL_U>,
651 <&tegra_car TEGRA30_CLK_USBD>;
652 clock-names = "reg", "pll_u", "utmi-pads";
653 nvidia,hssync-start-delay = <9>;
654 nvidia,idle-wait-delay = <17>;
655 nvidia,elastic-limit = <16>;
656 nvidia,term-range-adj = <6>;
657 nvidia,xcvr-setup = <51>;
658 nvidia.xcvr-setup-use-fuses;
659 nvidia,xcvr-lsfslew = <1>;
660 nvidia,xcvr-lsrslew = <1>;
661 nvidia,xcvr-hsslew = <32>;
662 nvidia,hssquelch-level = <2>;
663 nvidia,hsdiscon-level = <5>;
664 status = "disabled";
665 };
666
667 usb@7d004000 {
668 compatible = "nvidia,tegra30-ehci", "usb-ehci";
669 reg = <0x7d004000 0x4000>;
670 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
671 phy_type = "ulpi";
672 clocks = <&tegra_car TEGRA30_CLK_USB2>;
673 nvidia,phy = <&phy2>;
674 status = "disabled";
675 };
676
677 phy2: usb-phy@7d004000 {
678 compatible = "nvidia,tegra30-usb-phy";
679 reg = <0x7d004000 0x4000>;
680 phy_type = "ulpi";
681 clocks = <&tegra_car TEGRA30_CLK_USB2>,
682 <&tegra_car TEGRA30_CLK_PLL_U>,
683 <&tegra_car TEGRA30_CLK_CDEV2>;
684 clock-names = "reg", "pll_u", "ulpi-link";
685 status = "disabled";
686 };
687
688 usb@7d008000 {
689 compatible = "nvidia,tegra30-ehci", "usb-ehci";
690 reg = <0x7d008000 0x4000>;
691 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
692 phy_type = "utmi";
693 clocks = <&tegra_car TEGRA30_CLK_USB3>;
694 nvidia,phy = <&phy3>;
695 status = "disabled";
696 };
697
698 phy3: usb-phy@7d008000 {
699 compatible = "nvidia,tegra30-usb-phy";
700 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
701 phy_type = "utmi";
702 clocks = <&tegra_car TEGRA30_CLK_USB3>,
703 <&tegra_car TEGRA30_CLK_PLL_U>,
704 <&tegra_car TEGRA30_CLK_USBD>;
705 clock-names = "reg", "pll_u", "utmi-pads";
706 nvidia,hssync-start-delay = <0>;
707 nvidia,idle-wait-delay = <17>;
708 nvidia,elastic-limit = <16>;
709 nvidia,term-range-adj = <6>;
710 nvidia,xcvr-setup = <51>;
711 nvidia.xcvr-setup-use-fuses;
712 nvidia,xcvr-lsfslew = <2>;
713 nvidia,xcvr-lsrslew = <2>;
714 nvidia,xcvr-hsslew = <32>;
715 nvidia,hssquelch-level = <2>;
716 nvidia,hsdiscon-level = <5>;
717 status = "disabled";
718 };
719
564 cpus { 720 cpus {
565 #address-cells = <1>; 721 #address-cells = <1>;
566 #size-cells = <0>; 722 #size-cells = <0>;