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Diffstat (limited to 'arch/arm/boot/dts/tegra20-colibri-512.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra20-colibri-512.dtsi491
1 files changed, 491 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
new file mode 100644
index 000000000000..444162090042
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -0,0 +1,491 @@
1/include/ "tegra20.dtsi"
2
3/ {
4 model = "Toradex Colibri T20 512MB";
5 compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
6
7 memory {
8 reg = <0x00000000 0x20000000>;
9 };
10
11 host1x {
12 hdmi {
13 vdd-supply = <&hdmi_vdd_reg>;
14 pll-supply = <&hdmi_pll_reg>;
15
16 nvidia,ddc-i2c-bus = <&i2c_ddc>;
17 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
18 };
19 };
20
21 pinmux {
22 pinctrl-names = "default";
23 pinctrl-0 = <&state_default>;
24
25 state_default: pinmux {
26 audio_refclk {
27 nvidia,pins = "cdev1";
28 nvidia,function = "plla_out";
29 nvidia,pull = <0>;
30 nvidia,tristate = <0>;
31 };
32 crt {
33 nvidia,pins = "crtp";
34 nvidia,function = "crt";
35 nvidia,pull = <0>;
36 nvidia,tristate = <1>;
37 };
38 dap3 {
39 nvidia,pins = "dap3";
40 nvidia,function = "dap3";
41 nvidia,pull = <0>;
42 nvidia,tristate = <0>;
43 };
44 displaya {
45 nvidia,pins = "ld0", "ld1", "ld2", "ld3",
46 "ld4", "ld5", "ld6", "ld7", "ld8",
47 "ld9", "ld10", "ld11", "ld12", "ld13",
48 "ld14", "ld15", "ld16", "ld17",
49 "lhs", "lpw0", "lpw2", "lsc0",
50 "lsc1", "lsck", "lsda", "lspi", "lvs";
51 nvidia,function = "displaya";
52 nvidia,tristate = <1>;
53 };
54 gpio_dte {
55 nvidia,pins = "dte";
56 nvidia,function = "rsvd1";
57 nvidia,pull = <0>;
58 nvidia,tristate = <0>;
59 };
60 gpio_gmi {
61 nvidia,pins = "ata", "atc", "atd", "ate",
62 "dap1", "dap2", "dap4", "gpu", "irrx",
63 "irtx", "spia", "spib", "spic";
64 nvidia,function = "gmi";
65 nvidia,pull = <0>;
66 nvidia,tristate = <0>;
67 };
68 gpio_pta {
69 nvidia,pins = "pta";
70 nvidia,function = "rsvd4";
71 nvidia,pull = <0>;
72 nvidia,tristate = <0>;
73 };
74 gpio_uac {
75 nvidia,pins = "uac";
76 nvidia,function = "rsvd2";
77 nvidia,pull = <0>;
78 nvidia,tristate = <0>;
79 };
80 hdint {
81 nvidia,pins = "hdint";
82 nvidia,function = "hdmi";
83 nvidia,tristate = <1>;
84 };
85 i2c1 {
86 nvidia,pins = "rm";
87 nvidia,function = "i2c1";
88 nvidia,pull = <0>;
89 nvidia,tristate = <1>;
90 };
91 i2c3 {
92 nvidia,pins = "dtf";
93 nvidia,function = "i2c3";
94 nvidia,pull = <0>;
95 nvidia,tristate = <1>;
96 };
97 i2cddc {
98 nvidia,pins = "ddc";
99 nvidia,function = "i2c2";
100 nvidia,pull = <2>;
101 nvidia,tristate = <1>;
102 };
103 i2cp {
104 nvidia,pins = "i2cp";
105 nvidia,function = "i2cp";
106 nvidia,pull = <0>;
107 nvidia,tristate = <0>;
108 };
109 irda {
110 nvidia,pins = "uad";
111 nvidia,function = "irda";
112 nvidia,pull = <0>;
113 nvidia,tristate = <1>;
114 };
115 nand {
116 nvidia,pins = "kbca", "kbcc", "kbcd",
117 "kbce", "kbcf";
118 nvidia,function = "nand";
119 nvidia,pull = <0>;
120 nvidia,tristate = <0>;
121 };
122 owc {
123 nvidia,pins = "owc";
124 nvidia,function = "owr";
125 nvidia,pull = <0>;
126 nvidia,tristate = <1>;
127 };
128 pmc {
129 nvidia,pins = "pmc";
130 nvidia,function = "pwr_on";
131 nvidia,tristate = <0>;
132 };
133 pwm {
134 nvidia,pins = "sdb", "sdc", "sdd";
135 nvidia,function = "pwm";
136 nvidia,tristate = <1>;
137 };
138 sdio4 {
139 nvidia,pins = "atb", "gma", "gme";
140 nvidia,function = "sdio4";
141 nvidia,pull = <0>;
142 nvidia,tristate = <1>;
143 };
144 spi1 {
145 nvidia,pins = "spid", "spie", "spif";
146 nvidia,function = "spi1";
147 nvidia,pull = <0>;
148 nvidia,tristate = <1>;
149 };
150 spi4 {
151 nvidia,pins = "slxa", "slxc", "slxd", "slxk";
152 nvidia,function = "spi4";
153 nvidia,pull = <0>;
154 nvidia,tristate = <1>;
155 };
156 uarta {
157 nvidia,pins = "sdio1";
158 nvidia,function = "uarta";
159 nvidia,pull = <0>;
160 nvidia,tristate = <1>;
161 };
162 uartd {
163 nvidia,pins = "gmc";
164 nvidia,function = "uartd";
165 nvidia,pull = <0>;
166 nvidia,tristate = <1>;
167 };
168 ulpi {
169 nvidia,pins = "uaa", "uab", "uda";
170 nvidia,function = "ulpi";
171 nvidia,pull = <0>;
172 nvidia,tristate = <0>;
173 };
174 ulpi_refclk {
175 nvidia,pins = "cdev2";
176 nvidia,function = "pllp_out4";
177 nvidia,pull = <0>;
178 nvidia,tristate = <0>;
179 };
180 usb_gpio {
181 nvidia,pins = "spig", "spih";
182 nvidia,function = "spi2_alt";
183 nvidia,pull = <0>;
184 nvidia,tristate = <0>;
185 };
186 vi {
187 nvidia,pins = "dta", "dtb", "dtc", "dtd";
188 nvidia,function = "vi";
189 nvidia,pull = <0>;
190 nvidia,tristate = <1>;
191 };
192 vi_sc {
193 nvidia,pins = "csus";
194 nvidia,function = "vi_sensor_clk";
195 nvidia,pull = <0>;
196 nvidia,tristate = <1>;
197 };
198 };
199 };
200
201 i2c@7000c000 {
202 clock-frequency = <400000>;
203 };
204
205 i2c_ddc: i2c@7000c400 {
206 clock-frequency = <100000>;
207 };
208
209 i2c@7000c500 {
210 clock-frequency = <400000>;
211 };
212
213 i2c@7000d000 {
214 status = "okay";
215 clock-frequency = <400000>;
216
217 pmic: tps6586x@34 {
218 compatible = "ti,tps6586x";
219 reg = <0x34>;
220 interrupts = <0 86 0x4>;
221
222 ti,system-power-controller;
223
224 #gpio-cells = <2>;
225 gpio-controller;
226
227 sys-supply = <&vdd_5v0_reg>;
228 vin-sm0-supply = <&sys_reg>;
229 vin-sm1-supply = <&sys_reg>;
230 vin-sm2-supply = <&sys_reg>;
231 vinldo01-supply = <&sm2_reg>;
232 vinldo23-supply = <&sm2_reg>;
233 vinldo4-supply = <&sm2_reg>;
234 vinldo678-supply = <&sm2_reg>;
235 vinldo9-supply = <&sm2_reg>;
236
237 regulators {
238 #address-cells = <1>;
239 #size-cells = <0>;
240
241 sys_reg: regulator@0 {
242 reg = <0>;
243 regulator-compatible = "sys";
244 regulator-name = "vdd_sys";
245 regulator-always-on;
246 };
247
248 regulator@1 {
249 reg = <1>;
250 regulator-compatible = "sm0";
251 regulator-name = "vdd_sm0,vdd_core";
252 regulator-min-microvolt = <1275000>;
253 regulator-max-microvolt = <1275000>;
254 regulator-always-on;
255 };
256
257 regulator@2 {
258 reg = <2>;
259 regulator-compatible = "sm1";
260 regulator-name = "vdd_sm1,vdd_cpu";
261 regulator-min-microvolt = <1100000>;
262 regulator-max-microvolt = <1100000>;
263 regulator-always-on;
264 };
265
266 sm2_reg: regulator@3 {
267 reg = <3>;
268 regulator-compatible = "sm2";
269 regulator-name = "vdd_sm2,vin_ldo*";
270 regulator-min-microvolt = <3700000>;
271 regulator-max-microvolt = <3700000>;
272 regulator-always-on;
273 };
274
275 /* LDO0 is not connected to anything */
276
277 regulator@5 {
278 reg = <5>;
279 regulator-compatible = "ldo1";
280 regulator-name = "vdd_ldo1,avdd_pll*";
281 regulator-min-microvolt = <1100000>;
282 regulator-max-microvolt = <1100000>;
283 regulator-always-on;
284 };
285
286 regulator@6 {
287 reg = <6>;
288 regulator-compatible = "ldo2";
289 regulator-name = "vdd_ldo2,vdd_rtc";
290 regulator-min-microvolt = <1200000>;
291 regulator-max-microvolt = <1200000>;
292 };
293
294 /* LDO3 is not connected to anything */
295
296 regulator@8 {
297 reg = <8>;
298 regulator-compatible = "ldo4";
299 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
300 regulator-min-microvolt = <1800000>;
301 regulator-max-microvolt = <1800000>;
302 regulator-always-on;
303 };
304
305 ldo5_reg: regulator@9 {
306 reg = <9>;
307 regulator-compatible = "ldo5";
308 regulator-name = "vdd_ldo5,vdd_fuse";
309 regulator-min-microvolt = <3300000>;
310 regulator-max-microvolt = <3300000>;
311 regulator-always-on;
312 };
313
314 regulator@10 {
315 reg = <10>;
316 regulator-compatible = "ldo6";
317 regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
318 regulator-min-microvolt = <1800000>;
319 regulator-max-microvolt = <1800000>;
320 };
321
322 hdmi_vdd_reg: regulator@11 {
323 reg = <11>;
324 regulator-compatible = "ldo7";
325 regulator-name = "vdd_ldo7,avdd_hdmi";
326 regulator-min-microvolt = <3300000>;
327 regulator-max-microvolt = <3300000>;
328 };
329
330 hdmi_pll_reg: regulator@12 {
331 reg = <12>;
332 regulator-compatible = "ldo8";
333 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
334 regulator-min-microvolt = <1800000>;
335 regulator-max-microvolt = <1800000>;
336 };
337
338 regulator@13 {
339 reg = <13>;
340 regulator-compatible = "ldo9";
341 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
342 regulator-min-microvolt = <2850000>;
343 regulator-max-microvolt = <2850000>;
344 regulator-always-on;
345 };
346
347 regulator@14 {
348 reg = <14>;
349 regulator-compatible = "ldo_rtc";
350 regulator-name = "vdd_rtc_out,vdd_cell";
351 regulator-min-microvolt = <3300000>;
352 regulator-max-microvolt = <3300000>;
353 regulator-always-on;
354 };
355 };
356 };
357
358 temperature-sensor@4c {
359 compatible = "national,lm95245";
360 reg = <0x4c>;
361 };
362 };
363
364 memory-controller@7000f400 {
365 emc-table@83250 {
366 reg = <83250>;
367 compatible = "nvidia,tegra20-emc-table";
368 clock-frequency = <83250>;
369 nvidia,emc-registers = <0x00000005 0x00000011
370 0x00000004 0x00000002 0x00000004 0x00000004
371 0x00000001 0x0000000a 0x00000002 0x00000002
372 0x00000001 0x00000001 0x00000003 0x00000004
373 0x00000003 0x00000009 0x0000000c 0x0000025f
374 0x00000000 0x00000003 0x00000003 0x00000002
375 0x00000002 0x00000001 0x00000008 0x000000c8
376 0x00000003 0x00000005 0x00000003 0x0000000c
377 0x00000002 0x00000000 0x00000000 0x00000002
378 0x00000000 0x00000000 0x00000083 0x00520006
379 0x00000010 0x00000008 0x00000000 0x00000000
380 0x00000000 0x00000000 0x00000000 0x00000000>;
381 };
382 emc-table@133200 {
383 reg = <133200>;
384 compatible = "nvidia,tegra20-emc-table";
385 clock-frequency = <133200>;
386 nvidia,emc-registers = <0x00000008 0x00000019
387 0x00000006 0x00000002 0x00000004 0x00000004
388 0x00000001 0x0000000a 0x00000002 0x00000002
389 0x00000002 0x00000001 0x00000003 0x00000004
390 0x00000003 0x00000009 0x0000000c 0x0000039f
391 0x00000000 0x00000003 0x00000003 0x00000002
392 0x00000002 0x00000001 0x00000008 0x000000c8
393 0x00000003 0x00000007 0x00000003 0x0000000c
394 0x00000002 0x00000000 0x00000000 0x00000002
395 0x00000000 0x00000000 0x00000083 0x00510006
396 0x00000010 0x00000008 0x00000000 0x00000000
397 0x00000000 0x00000000 0x00000000 0x00000000>;
398 };
399 emc-table@166500 {
400 reg = <166500>;
401 compatible = "nvidia,tegra20-emc-table";
402 clock-frequency = <166500>;
403 nvidia,emc-registers = <0x0000000a 0x00000021
404 0x00000008 0x00000003 0x00000004 0x00000004
405 0x00000002 0x0000000a 0x00000003 0x00000003
406 0x00000002 0x00000001 0x00000003 0x00000004
407 0x00000003 0x00000009 0x0000000c 0x000004df
408 0x00000000 0x00000003 0x00000003 0x00000003
409 0x00000003 0x00000001 0x00000009 0x000000c8
410 0x00000003 0x00000009 0x00000004 0x0000000c
411 0x00000002 0x00000000 0x00000000 0x00000002
412 0x00000000 0x00000000 0x00000083 0x004f0006
413 0x00000010 0x00000008 0x00000000 0x00000000
414 0x00000000 0x00000000 0x00000000 0x00000000>;
415 };
416 emc-table@333000 {
417 reg = <333000>;
418 compatible = "nvidia,tegra20-emc-table";
419 clock-frequency = <333000>;
420 nvidia,emc-registers = <0x00000014 0x00000041
421 0x0000000f 0x00000005 0x00000004 0x00000005
422 0x00000003 0x0000000a 0x00000005 0x00000005
423 0x00000004 0x00000001 0x00000003 0x00000004
424 0x00000003 0x00000009 0x0000000c 0x000009ff
425 0x00000000 0x00000003 0x00000003 0x00000005
426 0x00000005 0x00000001 0x0000000e 0x000000c8
427 0x00000003 0x00000011 0x00000006 0x0000000c
428 0x00000002 0x00000000 0x00000000 0x00000002
429 0x00000000 0x00000000 0x00000083 0x00380006
430 0x00000010 0x00000008 0x00000000 0x00000000
431 0x00000000 0x00000000 0x00000000 0x00000000>;
432 };
433 };
434
435 ac97: ac97 {
436 status = "okay";
437 nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
438 nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */
439 };
440
441 usb@c5004000 {
442 status = "okay";
443 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
444 };
445
446 sdhci@c8000600 {
447 cd-gpios = <&gpio 23 0>; /* gpio PC7 */
448 };
449
450 sound {
451 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
452 "nvidia,tegra-audio-wm9712";
453 nvidia,model = "Colibri T20 AC97 Audio";
454
455 nvidia,audio-routing =
456 "Headphone", "HPOUTL",
457 "Headphone", "HPOUTR",
458 "LineIn", "LINEINL",
459 "LineIn", "LINEINR",
460 "Mic", "MIC1";
461
462 nvidia,ac97-controller = <&ac97>;
463 };
464
465 regulators {
466 compatible = "simple-bus";
467 #address-cells = <1>;
468 #size-cells = <0>;
469
470 vdd_5v0_reg: regulator@100 {
471 compatible = "regulator-fixed";
472 reg = <100>;
473 regulator-name = "vdd_5v0";
474 regulator-min-microvolt = <5000000>;
475 regulator-max-microvolt = <5000000>;
476 regulator-always-on;
477 };
478
479 regulator@101 {
480 compatible = "regulator-fixed";
481 reg = <101>;
482 regulator-name = "internal_usb";
483 regulator-min-microvolt = <5000000>;
484 regulator-max-microvolt = <5000000>;
485 enable-active-high;
486 regulator-boot-on;
487 regulator-always-on;
488 gpio = <&gpio 217 0>;
489 };
490 };
491};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-16 21:01:11 -0500