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-rw-r--r--arch/arm/boot/dts/socfpga.dtsi22
1 files changed, 10 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 19aec421bb26..936d2306e7e1 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -25,6 +25,10 @@
25 ethernet0 = &gmac0; 25 ethernet0 = &gmac0;
26 serial0 = &uart0; 26 serial0 = &uart0;
27 serial1 = &uart1; 27 serial1 = &uart1;
28 timer0 = &timer0;
29 timer1 = &timer1;
30 timer2 = &timer2;
31 timer3 = &timer3;
28 }; 32 };
29 33
30 cpus { 34 cpus {
@@ -98,47 +102,41 @@
98 interrupts = <1 13 0xf04>; 102 interrupts = <1 13 0xf04>;
99 }; 103 };
100 104
101 timer0: timer@ffc08000 { 105 timer0: timer0@ffc08000 {
102 compatible = "snps,dw-apb-timer-sp"; 106 compatible = "snps,dw-apb-timer-sp";
103 interrupts = <0 167 4>; 107 interrupts = <0 167 4>;
104 clock-frequency = <200000000>;
105 reg = <0xffc08000 0x1000>; 108 reg = <0xffc08000 0x1000>;
106 }; 109 };
107 110
108 timer1: timer@ffc09000 { 111 timer1: timer1@ffc09000 {
109 compatible = "snps,dw-apb-timer-sp"; 112 compatible = "snps,dw-apb-timer-sp";
110 interrupts = <0 168 4>; 113 interrupts = <0 168 4>;
111 clock-frequency = <200000000>;
112 reg = <0xffc09000 0x1000>; 114 reg = <0xffc09000 0x1000>;
113 }; 115 };
114 116
115 timer2: timer@ffd00000 { 117 timer2: timer2@ffd00000 {
116 compatible = "snps,dw-apb-timer-osc"; 118 compatible = "snps,dw-apb-timer-osc";
117 interrupts = <0 169 4>; 119 interrupts = <0 169 4>;
118 clock-frequency = <200000000>;
119 reg = <0xffd00000 0x1000>; 120 reg = <0xffd00000 0x1000>;
120 }; 121 };
121 122
122 timer3: timer@ffd01000 { 123 timer3: timer3@ffd01000 {
123 compatible = "snps,dw-apb-timer-osc"; 124 compatible = "snps,dw-apb-timer-osc";
124 interrupts = <0 170 4>; 125 interrupts = <0 170 4>;
125 clock-frequency = <200000000>;
126 reg = <0xffd01000 0x1000>; 126 reg = <0xffd01000 0x1000>;
127 }; 127 };
128 128
129 uart0: uart@ffc02000 { 129 uart0: serial0@ffc02000 {
130 compatible = "snps,dw-apb-uart"; 130 compatible = "snps,dw-apb-uart";
131 reg = <0xffc02000 0x1000>; 131 reg = <0xffc02000 0x1000>;
132 clock-frequency = <7372800>;
133 interrupts = <0 162 4>; 132 interrupts = <0 162 4>;
134 reg-shift = <2>; 133 reg-shift = <2>;
135 reg-io-width = <4>; 134 reg-io-width = <4>;
136 }; 135 };
137 136
138 uart1: uart@ffc03000 { 137 uart1: serial1@ffc03000 {
139 compatible = "snps,dw-apb-uart"; 138 compatible = "snps,dw-apb-uart";
140 reg = <0xffc03000 0x1000>; 139 reg = <0xffc03000 0x1000>;
141 clock-frequency = <7372800>;
142 interrupts = <0 163 4>; 140 interrupts = <0 163 4>;
143 reg-shift = <2>; 141 reg-shift = <2>;
144 reg-io-width = <4>; 142 reg-io-width = <4>;