diff options
Diffstat (limited to 'arch/arm/boot/dts/omap3-n900.dts')
-rw-r--r-- | arch/arm/boot/dts/omap3-n900.dts | 35 |
1 files changed, 31 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index bc82a12d4c2c..08ef71fe5273 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts | |||
@@ -142,6 +142,33 @@ | |||
142 | >; | 142 | >; |
143 | }; | 143 | }; |
144 | 144 | ||
145 | gpmc_pins: pinmux_gpmc_pins { | ||
146 | pinctrl-single,pins = < | ||
147 | |||
148 | /* address lines */ | ||
149 | OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */ | ||
150 | OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */ | ||
151 | OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */ | ||
152 | |||
153 | /* data lines, gpmc_d0..d7 not muxable according to TRM */ | ||
154 | OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */ | ||
155 | OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */ | ||
156 | OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */ | ||
157 | OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */ | ||
158 | OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */ | ||
159 | OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */ | ||
160 | OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */ | ||
161 | OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */ | ||
162 | |||
163 | /* | ||
164 | * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable | ||
165 | * according to TRM. OneNAND seems to require PIN_INPUT on clock. | ||
166 | */ | ||
167 | OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */ | ||
168 | OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ | ||
169 | >; | ||
170 | }; | ||
171 | |||
145 | i2c1_pins: pinmux_i2c1_pins { | 172 | i2c1_pins: pinmux_i2c1_pins { |
146 | pinctrl-single,pins = < | 173 | pinctrl-single,pins = < |
147 | 0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl */ | 174 | 0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl */ |
@@ -585,16 +612,16 @@ | |||
585 | }; | 612 | }; |
586 | 613 | ||
587 | &gpmc { | 614 | &gpmc { |
588 | ranges = <0 0 0x04000000 0x10000000>; /* 256MB */ | ||
589 | ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */ | 615 | ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */ |
590 | <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */ | 616 | <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */ |
617 | pinctrl-names = "default"; | ||
618 | pinctrl-0 = <&gpmc_pins>; | ||
591 | 619 | ||
592 | /* gpio-irq for dma: 65 */ | 620 | /* sys_ndmareq1 could be used by the driver, not as gpio65 though */ |
593 | |||
594 | onenand@0,0 { | 621 | onenand@0,0 { |
595 | #address-cells = <1>; | 622 | #address-cells = <1>; |
596 | #size-cells = <1>; | 623 | #size-cells = <1>; |
597 | reg = <0 0 0x10000000>; | 624 | reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ |
598 | 625 | ||
599 | gpmc,sync-read; | 626 | gpmc,sync-read; |
600 | gpmc,sync-write; | 627 | gpmc,sync-write; |