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Diffstat (limited to 'arch/arm/boot/dts/imx53-m53evk.dts')
-rw-r--r--arch/arm/boot/dts/imx53-m53evk.dts232
1 files changed, 213 insertions, 19 deletions
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
index 0298adc73bb7..f6d3ac3e5587 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -25,7 +25,7 @@
25 compatible = "fsl,imx-parallel-display"; 25 compatible = "fsl,imx-parallel-display";
26 interface-pix-fmt = "bgr666"; 26 interface-pix-fmt = "bgr666";
27 pinctrl-names = "default"; 27 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_ipu_disp2_1>; 28 pinctrl-0 = <&pinctrl_ipu_disp1>;
29 29
30 display-timings { 30 display-timings {
31 800x480p60 { 31 800x480p60 {
@@ -56,6 +56,7 @@
56 pwms = <&pwm1 0 3000>; 56 pwms = <&pwm1 0 3000>;
57 brightness-levels = <0 4 8 16 32 64 128 255>; 57 brightness-levels = <0 4 8 16 32 64 128 255>;
58 default-brightness-level = <6>; 58 default-brightness-level = <6>;
59 power-supply = <&reg_backlight>;
59 }; 60 };
60 61
61 leds { 62 leds {
@@ -78,14 +79,36 @@
78 79
79 regulators { 80 regulators {
80 compatible = "simple-bus"; 81 compatible = "simple-bus";
82 #address-cells = <1>;
83 #size-cells = <0>;
81 84
82 reg_3p2v: 3p2v { 85 reg_3p2v: regulator@0 {
83 compatible = "regulator-fixed"; 86 compatible = "regulator-fixed";
87 reg = <0>;
84 regulator-name = "3P2V"; 88 regulator-name = "3P2V";
85 regulator-min-microvolt = <3200000>; 89 regulator-min-microvolt = <3200000>;
86 regulator-max-microvolt = <3200000>; 90 regulator-max-microvolt = <3200000>;
87 regulator-always-on; 91 regulator-always-on;
88 }; 92 };
93
94
95 reg_backlight: regulator@1 {
96 compatible = "regulator-fixed";
97 reg = <1>;
98 regulator-name = "lcd-supply";
99 regulator-min-microvolt = <3200000>;
100 regulator-max-microvolt = <3200000>;
101 regulator-always-on;
102 };
103
104 reg_usbh1_vbus: regulator@3 {
105 compatible = "regulator-fixed";
106 reg = <3>;
107 regulator-name = "vbus";
108 regulator-min-microvolt = <5000000>;
109 regulator-max-microvolt = <5000000>;
110 gpio = <&gpio1 2 0>;
111 };
89 }; 112 };
90 113
91 sound { 114 sound {
@@ -107,25 +130,25 @@
107 130
108&audmux { 131&audmux {
109 pinctrl-names = "default"; 132 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_audmux_2>; 133 pinctrl-0 = <&pinctrl_audmux>;
111 status = "okay"; 134 status = "okay";
112}; 135};
113 136
114&can1 { 137&can1 {
115 pinctrl-names = "default"; 138 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_can1_3>; 139 pinctrl-0 = <&pinctrl_can1>;
117 status = "okay"; 140 status = "okay";
118}; 141};
119 142
120&can2 { 143&can2 {
121 pinctrl-names = "default"; 144 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_can2_1>; 145 pinctrl-0 = <&pinctrl_can2>;
123 status = "okay"; 146 status = "okay";
124}; 147};
125 148
126&esdhc1 { 149&esdhc1 {
127 pinctrl-names = "default"; 150 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_esdhc1_1>; 151 pinctrl-0 = <&pinctrl_esdhc1>;
129 cd-gpios = <&gpio1 1 0>; 152 cd-gpios = <&gpio1 1 0>;
130 wp-gpios = <&gpio1 9 0>; 153 wp-gpios = <&gpio1 9 0>;
131 status = "okay"; 154 status = "okay";
@@ -133,14 +156,14 @@
133 156
134&fec { 157&fec {
135 pinctrl-names = "default"; 158 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_fec_1>; 159 pinctrl-0 = <&pinctrl_fec>;
137 phy-mode = "rmii"; 160 phy-mode = "rmii";
138 status = "okay"; 161 status = "okay";
139}; 162};
140 163
141&i2c1 { 164&i2c1 {
142 pinctrl-names = "default"; 165 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_i2c1_2>; 166 pinctrl-0 = <&pinctrl_i2c1>;
144 status = "okay"; 167 status = "okay";
145 168
146 sgtl5000: codec@0a { 169 sgtl5000: codec@0a {
@@ -148,13 +171,13 @@
148 reg = <0x0a>; 171 reg = <0x0a>;
149 VDDA-supply = <&reg_3p2v>; 172 VDDA-supply = <&reg_3p2v>;
150 VDDIO-supply = <&reg_3p2v>; 173 VDDIO-supply = <&reg_3p2v>;
151 clocks = <&clks 150>; 174 clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
152 }; 175 };
153}; 176};
154 177
155&i2c2 { 178&i2c2 {
156 pinctrl-names = "default"; 179 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_i2c2_2>; 180 pinctrl-0 = <&pinctrl_i2c2>;
158 clock-frequency = <400000>; 181 clock-frequency = <400000>;
159 status = "okay"; 182 status = "okay";
160 183
@@ -198,7 +221,7 @@
198 221
199&i2c3 { 222&i2c3 {
200 pinctrl-names = "default"; 223 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_i2c3_1>; 224 pinctrl-0 = <&pinctrl_i2c3>;
202 status = "okay"; 225 status = "okay";
203}; 226};
204 227
@@ -206,14 +229,14 @@
206 pinctrl-names = "default"; 229 pinctrl-names = "default";
207 pinctrl-0 = <&pinctrl_hog>; 230 pinctrl-0 = <&pinctrl_hog>;
208 231
209 hog { 232 imx53-m53evk {
210 pinctrl_hog: hoggrp { 233 pinctrl_hog: hoggrp {
211 fsl,pins = < 234 fsl,pins = <
212 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 235 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
213 MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 236 MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
214 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 237 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
215 MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 238 MX53_PAD_GPIO_2__GPIO1_2 0x80000000
216 239 MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000
217 >; 240 >;
218 }; 241 };
219 242
@@ -223,6 +246,162 @@
223 MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000 246 MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000
224 >; 247 >;
225 }; 248 };
249
250 pinctrl_audmux: audmuxgrp {
251 fsl,pins = <
252 MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
253 MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
254 MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
255 MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
256 >;
257 };
258
259 pinctrl_can1: can1grp {
260 fsl,pins = <
261 MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
262 MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
263 >;
264 };
265
266 pinctrl_can2: can2grp {
267 fsl,pins = <
268 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
269 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
270 >;
271 };
272
273 pinctrl_esdhc1: esdhc1grp {
274 fsl,pins = <
275 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
276 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
277 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
278 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
279 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
280 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
281 >;
282 };
283
284 pinctrl_fec: fecgrp {
285 fsl,pins = <
286 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
287 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
288 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
289 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
290 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
291 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
292 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
293 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
294 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
295 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
296 >;
297 };
298
299 pinctrl_i2c1: i2c1grp {
300 fsl,pins = <
301 MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
302 MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
303 >;
304 };
305
306 pinctrl_i2c2: i2c2grp {
307 fsl,pins = <
308 MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
309 MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
310 >;
311 };
312
313 pinctrl_i2c3: i2c3grp {
314 fsl,pins = <
315 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
316 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
317 >;
318 };
319
320 pinctrl_ipu_disp1: ipudisp1grp {
321 fsl,pins = <
322 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5
323 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5
324 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5
325 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5
326 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5
327 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5
328 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5
329 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5
330 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5
331 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5
332 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5
333 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5
334 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5
335 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5
336 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5
337 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5
338 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5
339 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5
340 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5
341 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5
342 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5
343 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5
344 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5
345 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5
346 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5
347 MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5
348 MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5
349 MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5
350 MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5
351 MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5
352 MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5
353 MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
354 >;
355 };
356
357 pinctrl_nand: nandgrp {
358 fsl,pins = <
359 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
360 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
361 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
362 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
363 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
364 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
365 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
366 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
367 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
368 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
369 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
370 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
371 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
372 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
373 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
374 >;
375 };
376
377 pinctrl_pwm1: pwm1grp {
378 fsl,pins = <
379 MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
380 >;
381 };
382
383 pinctrl_uart1: uart1grp {
384 fsl,pins = <
385 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
386 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
387 >;
388 };
389
390 pinctrl_uart2: uart2grp {
391 fsl,pins = <
392 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
393 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
394 >;
395 };
396
397 pinctrl_uart3: uart3grp {
398 fsl,pins = <
399 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
400 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
401 MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
402 MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
403 >;
404 };
226 }; 405 };
227}; 406};
228 407
@@ -232,7 +411,7 @@
232 411
233&nfc { 412&nfc {
234 pinctrl-names = "default"; 413 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_nand_1>; 414 pinctrl-0 = <&pinctrl_nand>;
236 nand-bus-width = <8>; 415 nand-bus-width = <8>;
237 nand-ecc-mode = "hw"; 416 nand-ecc-mode = "hw";
238 status = "okay"; 417 status = "okay";
@@ -240,7 +419,11 @@
240 419
241&pwm1 { 420&pwm1 {
242 pinctrl-names = "default"; 421 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_pwm1_1>; 422 pinctrl-0 = <&pinctrl_pwm1>;
423 status = "okay";
424};
425
426&sata {
244 status = "okay"; 427 status = "okay";
245}; 428};
246 429
@@ -251,18 +434,29 @@
251 434
252&uart1 { 435&uart1 {
253 pinctrl-names = "default"; 436 pinctrl-names = "default";
254 pinctrl-0 = <&pinctrl_uart1_2>; 437 pinctrl-0 = <&pinctrl_uart1>;
255 status = "okay"; 438 status = "okay";
256}; 439};
257 440
258&uart2 { 441&uart2 {
259 pinctrl-names = "default"; 442 pinctrl-names = "default";
260 pinctrl-0 = <&pinctrl_uart2_1>; 443 pinctrl-0 = <&pinctrl_uart2>;
261 status = "okay"; 444 status = "okay";
262}; 445};
263 446
264&uart3 { 447&uart3 {
265 pinctrl-names = "default"; 448 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_uart3_1>; 449 pinctrl-0 = <&pinctrl_uart3>;
450 status = "okay";
451};
452
453&usbh1 {
454 vbus-supply = <&reg_usbh1_vbus>;
455 phy_type = "utmi";
456 status = "okay";
457};
458
459&usbotg {
460 dr_mode = "peripheral";
267 status = "okay"; 461 status = "okay";
268}; 462};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 01:00:23 -0500