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Diffstat (limited to 'arch/arm/boot/dts/imx51.dtsi')
-rw-r--r--arch/arm/boot/dts/imx51.dtsi146
1 files changed, 145 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index aba28dc87fc8..2f71a91ca98e 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -130,6 +130,34 @@
130 }; 130 };
131 }; 131 };
132 132
133 usb@73f80000 {
134 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
135 reg = <0x73f80000 0x0200>;
136 interrupts = <18>;
137 status = "disabled";
138 };
139
140 usb@73f80200 {
141 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
142 reg = <0x73f80200 0x0200>;
143 interrupts = <14>;
144 status = "disabled";
145 };
146
147 usb@73f80400 {
148 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
149 reg = <0x73f80400 0x0200>;
150 interrupts = <16>;
151 status = "disabled";
152 };
153
154 usb@73f80600 {
155 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
156 reg = <0x73f80600 0x0200>;
157 interrupts = <17>;
158 status = "disabled";
159 };
160
133 gpio1: gpio@73f84000 { 161 gpio1: gpio@73f84000 {
134 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; 162 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
135 reg = <0x73f84000 0x4000>; 163 reg = <0x73f84000 0x4000>;
@@ -174,7 +202,6 @@
174 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 202 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
175 reg = <0x73f98000 0x4000>; 203 reg = <0x73f98000 0x4000>;
176 interrupts = <58>; 204 interrupts = <58>;
177 status = "disabled";
178 }; 205 };
179 206
180 wdog@73f9c000 { /* WDOG2 */ 207 wdog@73f9c000 { /* WDOG2 */
@@ -184,6 +211,122 @@
184 status = "disabled"; 211 status = "disabled";
185 }; 212 };
186 213
214 iomuxc@73fa8000 {
215 compatible = "fsl,imx51-iomuxc";
216 reg = <0x73fa8000 0x4000>;
217
218 audmux {
219 pinctrl_audmux_1: audmuxgrp-1 {
220 fsl,pins = <
221 384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
222 386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
223 389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
224 391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
225 >;
226 };
227 };
228
229 fec {
230 pinctrl_fec_1: fecgrp-1 {
231 fsl,pins = <
232 128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */
233 134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
234 146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
235 152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
236 158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */
237 165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */
238 206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */
239 213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
240 293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
241 298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
242 225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
243 231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */
244 237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
245 243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
246 250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
247 255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
248 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
249 >;
250 };
251 };
252
253 ecspi1 {
254 pinctrl_ecspi1_1: ecspi1grp-1 {
255 fsl,pins = <
256 398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
257 394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
258 409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
259 >;
260 };
261 };
262
263 esdhc1 {
264 pinctrl_esdhc1_1: esdhc1grp-1 {
265 fsl,pins = <
266 666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */
267 669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */
268 672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
269 678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
270 684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
271 691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
272 >;
273 };
274 };
275
276 esdhc2 {
277 pinctrl_esdhc2_1: esdhc2grp-1 {
278 fsl,pins = <
279 704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */
280 707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */
281 710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
282 712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
283 715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
284 719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
285 >;
286 };
287 };
288
289 i2c2 {
290 pinctrl_i2c2_1: i2c2grp-1 {
291 fsl,pins = <
292 449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */
293 454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */
294 >;
295 };
296 };
297
298 uart1 {
299 pinctrl_uart1_1: uart1grp-1 {
300 fsl,pins = <
301 413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */
302 416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */
303 418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */
304 420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */
305 >;
306 };
307 };
308
309 uart2 {
310 pinctrl_uart2_1: uart2grp-1 {
311 fsl,pins = <
312 423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */
313 426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */
314 >;
315 };
316 };
317
318 uart3 {
319 pinctrl_uart3_1: uart3grp-1 {
320 fsl,pins = <
321 54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */
322 59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */
323 65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */
324 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
325 >;
326 };
327 };
328 };
329
187 uart1: serial@73fbc000 { 330 uart1: serial@73fbc000 {
188 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 331 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
189 reg = <0x73fbc000 0x4000>; 332 reg = <0x73fbc000 0x4000>;
@@ -219,6 +362,7 @@
219 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; 362 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
220 reg = <0x83fb0000 0x4000>; 363 reg = <0x83fb0000 0x4000>;
221 interrupts = <6>; 364 interrupts = <6>;
365 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
222 }; 366 };
223 367
224 cspi@83fc0000 { 368 cspi@83fc0000 {