1 files changed, 81 insertions, 9 deletions

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 4bdcbd61ce47..99b09a44e269 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -243,10 +243,18 @@
                 ti,invert-autoidle-bit;
         };
 
+        dpll_core_byp_mux: dpll_core_byp_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+                ti,bit-shift = <23>;
+                reg = <0x012c>;
+        };
+
         dpll_core_ck: dpll_core_ck {
                 #clock-cells = <0>;
                 compatible = "ti,omap4-dpll-core-clock";
-                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+                clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
                 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
         };
 
@@ -309,10 +317,18 @@
                 clock-div = <1>;
         };
 
+        dpll_dsp_byp_mux: dpll_dsp_byp_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
+                ti,bit-shift = <23>;
+                reg = <0x0240>;
+        };
+
         dpll_dsp_ck: dpll_dsp_ck {
                 #clock-cells = <0>;
                 compatible = "ti,omap4-dpll-clock";
-                clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
+                clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
                 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
         };
 
@@ -335,10 +351,18 @@
                 clock-div = <1>;
         };
 
+        dpll_iva_byp_mux: dpll_iva_byp_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
+                ti,bit-shift = <23>;
+                reg = <0x01ac>;
+        };
+
         dpll_iva_ck: dpll_iva_ck {
                 #clock-cells = <0>;
                 compatible = "ti,omap4-dpll-clock";
-                clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
+                clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
                 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
         };
 
@@ -361,10 +385,18 @@
                 clock-div = <1>;
         };
 
+        dpll_gpu_byp_mux: dpll_gpu_byp_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+                ti,bit-shift = <23>;
+                reg = <0x02e4>;
+        };
+
         dpll_gpu_ck: dpll_gpu_ck {
                 #clock-cells = <0>;
                 compatible = "ti,omap4-dpll-clock";
-                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+                clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
                 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
         };
 
@@ -398,10 +430,18 @@
                 clock-div = <1>;
         };
 
+        dpll_ddr_byp_mux: dpll_ddr_byp_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+                ti,bit-shift = <23>;
+                reg = <0x021c>;
+        };
+
         dpll_ddr_ck: dpll_ddr_ck {
                 #clock-cells = <0>;
                 compatible = "ti,omap4-dpll-clock";
-                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+                clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
                 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
         };
 
@@ -416,10 +456,18 @@
                 ti,invert-autoidle-bit;
         };
 
+        dpll_gmac_byp_mux: dpll_gmac_byp_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+                ti,bit-shift = <23>;
+                reg = <0x02b4>;
+        };
+
         dpll_gmac_ck: dpll_gmac_ck {
                 #clock-cells = <0>;
                 compatible = "ti,omap4-dpll-clock";
-                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+                clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
                 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
         };
 
@@ -482,10 +530,18 @@
                 clock-div = <1>;
         };
 
+        dpll_eve_byp_mux: dpll_eve_byp_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
+                ti,bit-shift = <23>;
+                reg = <0x0290>;
+        };
+
         dpll_eve_ck: dpll_eve_ck {
                 #clock-cells = <0>;
                 compatible = "ti,omap4-dpll-clock";
-                clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
+                clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
                 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
         };
 
@@ -1249,10 +1305,18 @@
                 clock-div = <1>;
         };
 
+        dpll_per_byp_mux: dpll_per_byp_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
+                ti,bit-shift = <23>;
+                reg = <0x014c>;
+        };
+
         dpll_per_ck: dpll_per_ck {
                 #clock-cells = <0>;
                 compatible = "ti,omap4-dpll-clock";
-                clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
+                clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
                 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
         };
 
@@ -1275,10 +1339,18 @@
                 clock-div = <1>;
         };
 
+        dpll_usb_byp_mux: dpll_usb_byp_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
+                ti,bit-shift = <23>;
+                reg = <0x018c>;
+        };
+
         dpll_usb_ck: dpll_usb_ck {
                 #clock-cells = <0>;
                 compatible = "ti,omap4-dpll-j-type-clock";
-                clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
+                clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
                 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
         };