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-rw-r--r--arch/arm/boot/dts/am43x-epos-evm.dts183
1 files changed, 183 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index fbf9c4c7a94f..167dbc8494de 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -13,6 +13,7 @@
13#include "am4372.dtsi" 13#include "am4372.dtsi"
14#include <dt-bindings/pinctrl/am43xx.h> 14#include <dt-bindings/pinctrl/am43xx.h>
15#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/pwm/pwm.h>
16 17
17/ { 18/ {
18 model = "TI AM43x EPOS EVM"; 19 model = "TI AM43x EPOS EVM";
@@ -79,6 +80,64 @@
79 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 80 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
80 >; 81 >;
81 }; 82 };
83
84 nand_flash_x8: nand_flash_x8 {
85 pinctrl-single,pins = <
86 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */
87 0x0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
88 0x4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
89 0x8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
90 0xc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
91 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
92 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
93 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
94 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
95 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
96 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
97 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
98 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
99 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
100 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
101 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
102 >;
103 };
104
105 ecap0_pins: backlight_pins {
106 pinctrl-single,pins = <
107 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
108 >;
109 };
110
111 i2c2_pins: pinmux_i2c2_pins {
112 pinctrl-single,pins = <
113 0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */
114 0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */
115 >;
116 };
117
118 spi0_pins: pinmux_spi0_pins {
119 pinctrl-single,pins = <
120 0x150 (PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */
121 0x154 (PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */
122 0x158 (PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */
123 0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
124 >;
125 };
126
127 spi1_pins: pinmux_spi1_pins {
128 pinctrl-single,pins = <
129 0x190 (PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */
130 0x194 (PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
131 0x198 (PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
132 0x19c (PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
133 >;
134 };
135
136 mmc1_pins: pinmux_mmc1_pins {
137 pinctrl-single,pins = <
138 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
139 >;
140 };
82 }; 141 };
83 142
84 matrix_keypad: matrix_keypad@0 { 143 matrix_keypad: matrix_keypad@0 {
@@ -113,12 +172,22 @@
113 0x0203006c /* DOWN */ 172 0x0203006c /* DOWN */
114 0x03030069>; /* LEFT */ 173 0x03030069>; /* LEFT */
115 }; 174 };
175
176 backlight {
177 compatible = "pwm-backlight";
178 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
179 brightness-levels = <0 51 53 56 62 75 101 152 255>;
180 default-brightness-level = <8>;
181 };
116}; 182};
117 183
118&mmc1 { 184&mmc1 {
119 status = "okay"; 185 status = "okay";
120 vmmc-supply = <&vmmcsd_fixed>; 186 vmmc-supply = <&vmmcsd_fixed>;
121 bus-width = <4>; 187 bus-width = <4>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&mmc1_pins>;
190 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
122}; 191};
123 192
124&mac { 193&mac {
@@ -169,6 +238,12 @@
169 }; 238 };
170}; 239};
171 240
241&i2c2 {
242 pinctrl-names = "default";
243 pinctrl-0 = <&i2c2_pins>;
244 status = "okay";
245};
246
172&gpio0 { 247&gpio0 {
173 status = "okay"; 248 status = "okay";
174}; 249};
@@ -184,3 +259,111 @@
184&gpio3 { 259&gpio3 {
185 status = "okay"; 260 status = "okay";
186}; 261};
262
263&elm {
264 status = "okay";
265};
266
267&gpmc {
268 status = "okay";
269 pinctrl-names = "default";
270 pinctrl-0 = <&nand_flash_x8>;
271 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
272 nand@0,0 {
273 reg = <0 0 0>; /* CS0, offset 0 */
274 ti,nand-ecc-opt = "bch8";
275 ti,elm-id = <&elm>;
276 nand-bus-width = <8>;
277 gpmc,device-width = <1>;
278 gpmc,sync-clk-ps = <0>;
279 gpmc,cs-on-ns = <0>;
280 gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
281 gpmc,cs-wr-off-ns = <40>;
282 gpmc,adv-on-ns = <0>; /* cs-on-ns */
283 gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
284 gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
285 gpmc,we-on-ns = <0>; /* cs-on-ns */
286 gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
287 gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */
288 gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
289 gpmc,access-ns = <30>; /* tCEA + 4*/
290 gpmc,rd-cycle-ns = <40>;
291 gpmc,wr-cycle-ns = <40>;
292 gpmc,wait-on-read = "true";
293 gpmc,wait-on-write = "true";
294 gpmc,bus-turnaround-ns = <0>;
295 gpmc,cycle2cycle-delay-ns = <0>;
296 gpmc,clk-activation-ns = <0>;
297 gpmc,wait-monitoring-ns = <0>;
298 gpmc,wr-access-ns = <40>;
299 gpmc,wr-data-mux-bus-ns = <0>;
300 /* MTD partition table */
301 /* All SPL-* partitions are sized to minimal length
302 * which can be independently programmable. For
303 * NAND flash this is equal to size of erase-block */
304 #address-cells = <1>;
305 #size-cells = <1>;
306 partition@0 {
307 label = "NAND.SPL";
308 reg = <0x00000000 0x00040000>;
309 };
310 partition@1 {
311 label = "NAND.SPL.backup1";
312 reg = <0x00040000 0x00040000>;
313 };
314 partition@2 {
315 label = "NAND.SPL.backup2";
316 reg = <0x00080000 0x00040000>;
317 };
318 partition@3 {
319 label = "NAND.SPL.backup3";
320 reg = <0x000C0000 0x00040000>;
321 };
322 partition@4 {
323 label = "NAND.u-boot-spl-os";
324 reg = <0x00100000 0x00080000>;
325 };
326 partition@5 {
327 label = "NAND.u-boot";
328 reg = <0x00180000 0x00100000>;
329 };
330 partition@6 {
331 label = "NAND.u-boot-env";
332 reg = <0x00280000 0x00040000>;
333 };
334 partition@7 {
335 label = "NAND.u-boot-env.backup1";
336 reg = <0x002C0000 0x00040000>;
337 };
338 partition@8 {
339 label = "NAND.kernel";
340 reg = <0x00300000 0x00700000>;
341 };
342 partition@9 {
343 label = "NAND.file-system";
344 reg = <0x00800000 0x1F600000>;
345 };
346 };
347};
348
349&epwmss0 {
350 status = "okay";
351};
352
353&ecap0 {
354 status = "okay";
355 pinctrl-names = "default";
356 pinctrl-0 = <&ecap0_pins>;
357};
358
359&spi0 {
360 pinctrl-names = "default";
361 pinctrl-0 = <&spi0_pins>;
362 status = "okay";
363};
364
365&spi1 {
366 pinctrl-names = "default";
367 pinctrl-0 = <&spi1_pins>;
368 status = "okay";
369};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 01:07:51 -0500