diff options
Diffstat (limited to 'arch/arm/Kconfig')
-rw-r--r-- | arch/arm/Kconfig | 117 |
1 files changed, 26 insertions, 91 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a7ed21f0136a..88c97bc7a6f5 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -271,7 +271,6 @@ config ARCH_AT91 | |||
271 | bool "Atmel AT91" | 271 | bool "Atmel AT91" |
272 | select ARCH_REQUIRE_GPIOLIB | 272 | select ARCH_REQUIRE_GPIOLIB |
273 | select HAVE_CLK | 273 | select HAVE_CLK |
274 | select ARCH_USES_GETTIMEOFFSET | ||
275 | help | 274 | help |
276 | This enables support for systems based on the Atmel AT91RM9200, | 275 | This enables support for systems based on the Atmel AT91RM9200, |
277 | AT91SAM9 and AT91CAP9 processors. | 276 | AT91SAM9 and AT91CAP9 processors. |
@@ -1051,6 +1050,32 @@ config ARM_ERRATA_460075 | |||
1051 | ACTLR register. Note that setting specific bits in the ACTLR register | 1050 | ACTLR register. Note that setting specific bits in the ACTLR register |
1052 | may not be available in non-secure mode. | 1051 | may not be available in non-secure mode. |
1053 | 1052 | ||
1053 | config ARM_ERRATA_742230 | ||
1054 | bool "ARM errata: DMB operation may be faulty" | ||
1055 | depends on CPU_V7 && SMP | ||
1056 | help | ||
1057 | This option enables the workaround for the 742230 Cortex-A9 | ||
1058 | (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction | ||
1059 | between two write operations may not ensure the correct visibility | ||
1060 | ordering of the two writes. This workaround sets a specific bit in | ||
1061 | the diagnostic register of the Cortex-A9 which causes the DMB | ||
1062 | instruction to behave as a DSB, ensuring the correct behaviour of | ||
1063 | the two writes. | ||
1064 | |||
1065 | config ARM_ERRATA_742231 | ||
1066 | bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" | ||
1067 | depends on CPU_V7 && SMP | ||
1068 | help | ||
1069 | This option enables the workaround for the 742231 Cortex-A9 | ||
1070 | (r2p0..r2p2) erratum. Under certain conditions, specific to the | ||
1071 | Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, | ||
1072 | accessing some data located in the same cache line, may get corrupted | ||
1073 | data due to bad handling of the address hazard when the line gets | ||
1074 | replaced from one of the CPUs at the same time as another CPU is | ||
1075 | accessing it. This workaround sets specific bits in the diagnostic | ||
1076 | register of the Cortex-A9 which reduces the linefill issuing | ||
1077 | capabilities of the processor. | ||
1078 | |||
1054 | config PL310_ERRATA_588369 | 1079 | config PL310_ERRATA_588369 |
1055 | bool "Clean & Invalidate maintenance operations do not invalidate clean lines" | 1080 | bool "Clean & Invalidate maintenance operations do not invalidate clean lines" |
1056 | depends on CACHE_L2X0 && ARCH_OMAP4 | 1081 | depends on CACHE_L2X0 && ARCH_OMAP4 |
@@ -1576,96 +1601,6 @@ config AUTO_ZRELADDR | |||
1576 | 0xf8000000. This assumes the zImage being placed in the first 128MB | 1601 | 0xf8000000. This assumes the zImage being placed in the first 128MB |
1577 | from start of memory. | 1602 | from start of memory. |
1578 | 1603 | ||
1579 | config ZRELADDR | ||
1580 | hex "Physical address of the decompressed kernel image" | ||
1581 | depends on !AUTO_ZRELADDR | ||
1582 | default 0x00008000 if ARCH_BCMRING ||\ | ||
1583 | ARCH_CNS3XXX ||\ | ||
1584 | ARCH_DOVE ||\ | ||
1585 | ARCH_EBSA110 ||\ | ||
1586 | ARCH_FOOTBRIDGE ||\ | ||
1587 | ARCH_INTEGRATOR ||\ | ||
1588 | ARCH_IOP13XX ||\ | ||
1589 | ARCH_IOP33X ||\ | ||
1590 | ARCH_IXP2000 ||\ | ||
1591 | ARCH_IXP23XX ||\ | ||
1592 | ARCH_IXP4XX ||\ | ||
1593 | ARCH_KIRKWOOD ||\ | ||
1594 | ARCH_KS8695 ||\ | ||
1595 | ARCH_LOKI ||\ | ||
1596 | ARCH_MMP ||\ | ||
1597 | ARCH_MV78XX0 ||\ | ||
1598 | ARCH_NOMADIK ||\ | ||
1599 | ARCH_NUC93X ||\ | ||
1600 | ARCH_NS9XXX ||\ | ||
1601 | ARCH_ORION5X ||\ | ||
1602 | ARCH_SPEAR3XX ||\ | ||
1603 | ARCH_SPEAR6XX ||\ | ||
1604 | ARCH_U8500 ||\ | ||
1605 | ARCH_VERSATILE ||\ | ||
1606 | ARCH_W90X900 | ||
1607 | default 0x08008000 if ARCH_MX1 ||\ | ||
1608 | ARCH_SHARK | ||
1609 | default 0x10008000 if ARCH_MSM ||\ | ||
1610 | ARCH_OMAP1 ||\ | ||
1611 | ARCH_RPC | ||
1612 | default 0x20008000 if ARCH_S5P6440 ||\ | ||
1613 | ARCH_S5P6442 ||\ | ||
1614 | ARCH_S5PC100 ||\ | ||
1615 | ARCH_S5PV210 | ||
1616 | default 0x30008000 if ARCH_S3C2410 ||\ | ||
1617 | ARCH_S3C2400 ||\ | ||
1618 | ARCH_S3C2412 ||\ | ||
1619 | ARCH_S3C2416 ||\ | ||
1620 | ARCH_S3C2440 ||\ | ||
1621 | ARCH_S3C2443 | ||
1622 | default 0x40008000 if ARCH_STMP378X ||\ | ||
1623 | ARCH_STMP37XX ||\ | ||
1624 | ARCH_SH7372 ||\ | ||
1625 | ARCH_SH7377 ||\ | ||
1626 | ARCH_S5PV310 | ||
1627 | default 0x50008000 if ARCH_S3C64XX ||\ | ||
1628 | ARCH_SH7367 | ||
1629 | default 0x60008000 if ARCH_VEXPRESS | ||
1630 | default 0x80008000 if ARCH_MX25 ||\ | ||
1631 | ARCH_MX3 ||\ | ||
1632 | ARCH_NETX ||\ | ||
1633 | ARCH_OMAP2PLUS ||\ | ||
1634 | ARCH_PNX4008 | ||
1635 | default 0x90008000 if ARCH_MX5 ||\ | ||
1636 | ARCH_MX91231 | ||
1637 | default 0xa0008000 if ARCH_IOP32X ||\ | ||
1638 | ARCH_PXA ||\ | ||
1639 | MACH_MX27 | ||
1640 | default 0xc0008000 if ARCH_LH7A40X ||\ | ||
1641 | MACH_MX21 | ||
1642 | default 0xf0008000 if ARCH_AAEC2000 ||\ | ||
1643 | ARCH_L7200 | ||
1644 | default 0xc0028000 if ARCH_CLPS711X | ||
1645 | default 0x70008000 if ARCH_AT91 && (ARCH_AT91CAP9 || ARCH_AT91SAM9G45) | ||
1646 | default 0x20008000 if ARCH_AT91 && !(ARCH_AT91CAP9 || ARCH_AT91SAM9G45) | ||
1647 | default 0xc0008000 if ARCH_DAVINCI && ARCH_DAVINCI_DA8XX | ||
1648 | default 0x80008000 if ARCH_DAVINCI && !ARCH_DAVINCI_DA8XX | ||
1649 | default 0x00008000 if ARCH_EP93XX && EP93XX_SDCE3_SYNC_PHYS_OFFSET | ||
1650 | default 0xc0008000 if ARCH_EP93XX && EP93XX_SDCE0_PHYS_OFFSET | ||
1651 | default 0xd0008000 if ARCH_EP93XX && EP93XX_SDCE1_PHYS_OFFSET | ||
1652 | default 0xe0008000 if ARCH_EP93XX && EP93XX_SDCE2_PHYS_OFFSET | ||
1653 | default 0xf0008000 if ARCH_EP93XX && EP93XX_SDCE3_ASYNC_PHYS_OFFSET | ||
1654 | default 0x00008000 if ARCH_GEMINI && GEMINI_MEM_SWAP | ||
1655 | default 0x10008000 if ARCH_GEMINI && !GEMINI_MEM_SWAP | ||
1656 | default 0x70008000 if ARCH_REALVIEW && REALVIEW_HIGH_PHYS_OFFSET | ||
1657 | default 0x00008000 if ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET | ||
1658 | default 0xc0208000 if ARCH_SA1100 && SA1111 | ||
1659 | default 0xc0008000 if ARCH_SA1100 && !SA1111 | ||
1660 | default 0x30108000 if ARCH_S3C2410 && PM_H1940 | ||
1661 | default 0x28E08000 if ARCH_U300 && MACH_U300_SINGLE_RAM | ||
1662 | default 0x48008000 if ARCH_U300 && !MACH_U300_SINGLE_RAM | ||
1663 | help | ||
1664 | ZRELADDR is the physical address where the decompressed kernel | ||
1665 | image will be placed. ZRELADDR has to be specified when the | ||
1666 | assumption of AUTO_ZRELADDR is not valid, or when ZBOOT_ROM is | ||
1667 | selected. | ||
1668 | |||
1669 | endmenu | 1604 | endmenu |
1670 | 1605 | ||
1671 | menu "CPU Power Management" | 1606 | menu "CPU Power Management" |