4 files changed, 65 insertions, 2 deletions

diff --git a/Documentation/devicetree/bindings/mips/cpu_irq.txt b/Documentation/devicetree/bindings/mips/cpu_irq.txt
new file mode 100644
index 000000000000..13aa4b62c62a
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/cpu_irq.txt
@@ -0,0 +1,47 @@
+MIPS CPU interrupt controller
+
+On MIPS the mips_cpu_intc_init() helper can be used to initialize the 8 CPU
+IRQs from a devicetree file and create a irq_domain for IRQ controller.
+
+With the irq_domain in place we can describe how the 8 IRQs are wired to the
+platforms internal interrupt controller cascade.
+
+Below is an example of a platform describing the cascade inside the devicetree
+and the code used to load it inside arch_init_irq().
+
+Required properties:
+- compatible : Should be "mti,cpu-interrupt-controller"
+
+Example devicetree:
+        cpu-irq: cpu-irq@0 {
+                #address-cells = <0>;
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+
+                compatible = "mti,cpu-interrupt-controller";
+        };
+
+        intc: intc@200 {
+                compatible = "ralink,rt2880-intc";
+                reg = <0x200 0x100>;
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+
+                interrupt-parent = <&cpu-irq>;
+                interrupts = <2>;
+        };
+
+
+Example platform irq.c:
+static struct of_device_id __initdata of_irq_ids[] = {
+        { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
+        { .compatible = "ralink,rt2880-intc", .data = intc_of_init },
+        {},
+};
+
+void __init arch_init_irq(void)
+{
+        of_irq_init(of_irq_ids);
+}
diff --git a/Documentation/devicetree/bindings/serial/lantiq_asc.txt b/Documentation/devicetree/bindings/serial/lantiq_asc.txt
new file mode 100644
index 000000000000..5b78591aaa46
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/lantiq_asc.txt
@@ -0,0 +1,16 @@
+Lantiq SoC ASC serial controller
+
+Required properties:
+- compatible : Should be "lantiq,asc"
+- reg : Address and length of the register set for the device
+- interrupts: the 3 (tx rx err) interrupt numbers. The interrupt specifier
+  depends on the interrupt-parent interrupt controller.
+
+Example:
+
+asc1: serial@E100C00 {
+        compatible = "lantiq,asc";
+        reg = <0xE100C00 0x400>;
+        interrupt-parent = <&icu0>;
+        interrupts = <112 113 114>;
+};
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 363e348bff9b..6c723811c0a0 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -2438,7 +2438,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
                         real-time workloads.  It can also improve energy
                         efficiency for asymmetric multiprocessors.
 
-        rcu_nocbs_poll  [KNL,BOOT]
+        rcu_nocb_poll   [KNL,BOOT]
                         Rather than requiring that offloaded CPUs
                         (specified by rcu_nocbs= above) explicitly
                         awaken the corresponding "rcuoN" kthreads,
diff --git a/Documentation/x86/boot.txt b/Documentation/x86/boot.txt
index 3edb4c2887a1..e540fd67f767 100644
--- a/Documentation/x86/boot.txt
+++ b/Documentation/x86/boot.txt
@@ -57,7 +57,7 @@ Protocol 2.10:	(Kernel 2.6.31) Added a protocol for relaxed alignment
 Protocol 2.11:  (Kernel 3.6) Added a field for offset of EFI handover
                 protocol entry point.
 
-Protocol 2.12:  (Kernel 3.9) Added the xloadflags field and extension fields
+Protocol 2.12:  (Kernel 3.8) Added the xloadflags field and extension fields
                 to struct boot_params for for loading bzImage and ramdisk
                 above 4G in 64bit.