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Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/powerpc/00-INDEX | 2 | ||||
-rw-r--r-- | Documentation/powerpc/pmu-ebb.txt | 137 |
2 files changed, 139 insertions, 0 deletions
diff --git a/Documentation/powerpc/00-INDEX b/Documentation/powerpc/00-INDEX index dd9e92802ec0..05026ce1875e 100644 --- a/Documentation/powerpc/00-INDEX +++ b/Documentation/powerpc/00-INDEX | |||
@@ -14,6 +14,8 @@ hvcs.txt | |||
14 | - IBM "Hypervisor Virtual Console Server" Installation Guide | 14 | - IBM "Hypervisor Virtual Console Server" Installation Guide |
15 | mpc52xx.txt | 15 | mpc52xx.txt |
16 | - Linux 2.6.x on MPC52xx family | 16 | - Linux 2.6.x on MPC52xx family |
17 | pmu-ebb.txt | ||
18 | - Description of the API for using the PMU with Event Based Branches. | ||
17 | qe_firmware.txt | 19 | qe_firmware.txt |
18 | - describes the layout of firmware binaries for the Freescale QUICC | 20 | - describes the layout of firmware binaries for the Freescale QUICC |
19 | Engine and the code that parses and uploads the microcode therein. | 21 | Engine and the code that parses and uploads the microcode therein. |
diff --git a/Documentation/powerpc/pmu-ebb.txt b/Documentation/powerpc/pmu-ebb.txt new file mode 100644 index 000000000000..73cd163dbfb8 --- /dev/null +++ b/Documentation/powerpc/pmu-ebb.txt | |||
@@ -0,0 +1,137 @@ | |||
1 | PMU Event Based Branches | ||
2 | ======================== | ||
3 | |||
4 | Event Based Branches (EBBs) are a feature which allows the hardware to | ||
5 | branch directly to a specified user space address when certain events occur. | ||
6 | |||
7 | The full specification is available in Power ISA v2.07: | ||
8 | |||
9 | https://www.power.org/documentation/power-isa-version-2-07/ | ||
10 | |||
11 | One type of event for which EBBs can be configured is PMU exceptions. This | ||
12 | document describes the API for configuring the Power PMU to generate EBBs, | ||
13 | using the Linux perf_events API. | ||
14 | |||
15 | |||
16 | Terminology | ||
17 | ----------- | ||
18 | |||
19 | Throughout this document we will refer to an "EBB event" or "EBB events". This | ||
20 | just refers to a struct perf_event which has set the "EBB" flag in its | ||
21 | attr.config. All events which can be configured on the hardware PMU are | ||
22 | possible "EBB events". | ||
23 | |||
24 | |||
25 | Background | ||
26 | ---------- | ||
27 | |||
28 | When a PMU EBB occurs it is delivered to the currently running process. As such | ||
29 | EBBs can only sensibly be used by programs for self-monitoring. | ||
30 | |||
31 | It is a feature of the perf_events API that events can be created on other | ||
32 | processes, subject to standard permission checks. This is also true of EBB | ||
33 | events, however unless the target process enables EBBs (via mtspr(BESCR)) no | ||
34 | EBBs will ever be delivered. | ||
35 | |||
36 | This makes it possible for a process to enable EBBs for itself, but not | ||
37 | actually configure any events. At a later time another process can come along | ||
38 | and attach an EBB event to the process, which will then cause EBBs to be | ||
39 | delivered to the first process. It's not clear if this is actually useful. | ||
40 | |||
41 | |||
42 | When the PMU is configured for EBBs, all PMU interrupts are delivered to the | ||
43 | user process. This means once an EBB event is scheduled on the PMU, no non-EBB | ||
44 | events can be configured. This means that EBB events can not be run | ||
45 | concurrently with regular 'perf' commands, or any other perf events. | ||
46 | |||
47 | It is however safe to run 'perf' commands on a process which is using EBBs. The | ||
48 | kernel will in general schedule the EBB event, and perf will be notified that | ||
49 | its events could not run. | ||
50 | |||
51 | The exclusion between EBB events and regular events is implemented using the | ||
52 | existing "pinned" and "exclusive" attributes of perf_events. This means EBB | ||
53 | events will be given priority over other events, unless they are also pinned. | ||
54 | If an EBB event and a regular event are both pinned, then whichever is enabled | ||
55 | first will be scheduled and the other will be put in error state. See the | ||
56 | section below titled "Enabling an EBB event" for more information. | ||
57 | |||
58 | |||
59 | Creating an EBB event | ||
60 | --------------------- | ||
61 | |||
62 | To request that an event is counted using EBB, the event code should have bit | ||
63 | 63 set. | ||
64 | |||
65 | EBB events must be created with a particular, and restrictive, set of | ||
66 | attributes - this is so that they interoperate correctly with the rest of the | ||
67 | perf_events subsystem. | ||
68 | |||
69 | An EBB event must be created with the "pinned" and "exclusive" attributes set. | ||
70 | Note that if you are creating a group of EBB events, only the leader can have | ||
71 | these attributes set. | ||
72 | |||
73 | An EBB event must NOT set any of the "inherit", "sample_period", "freq" or | ||
74 | "enable_on_exec" attributes. | ||
75 | |||
76 | An EBB event must be attached to a task. This is specified to perf_event_open() | ||
77 | by passing a pid value, typically 0 indicating the current task. | ||
78 | |||
79 | All events in a group must agree on whether they want EBB. That is all events | ||
80 | must request EBB, or none may request EBB. | ||
81 | |||
82 | EBB events must specify the PMC they are to be counted on. This ensures | ||
83 | userspace is able to reliably determine which PMC the event is scheduled on. | ||
84 | |||
85 | |||
86 | Enabling an EBB event | ||
87 | --------------------- | ||
88 | |||
89 | Once an EBB event has been successfully opened, it must be enabled with the | ||
90 | perf_events API. This can be achieved either via the ioctl() interface, or the | ||
91 | prctl() interface. | ||
92 | |||
93 | However, due to the design of the perf_events API, enabling an event does not | ||
94 | guarantee that it has been scheduled on the PMU. To ensure that the EBB event | ||
95 | has been scheduled on the PMU, you must perform a read() on the event. If the | ||
96 | read() returns EOF, then the event has not been scheduled and EBBs are not | ||
97 | enabled. | ||
98 | |||
99 | This behaviour occurs because the EBB event is pinned and exclusive. When the | ||
100 | EBB event is enabled it will force all other non-pinned events off the PMU. In | ||
101 | this case the enable will be successful. However if there is already an event | ||
102 | pinned on the PMU then the enable will not be successful. | ||
103 | |||
104 | |||
105 | Reading an EBB event | ||
106 | -------------------- | ||
107 | |||
108 | It is possible to read() from an EBB event. However the results are | ||
109 | meaningless. Because interrupts are being delivered to the user process the | ||
110 | kernel is not able to count the event, and so will return a junk value. | ||
111 | |||
112 | |||
113 | Closing an EBB event | ||
114 | -------------------- | ||
115 | |||
116 | When an EBB event is finished with, you can close it using close() as for any | ||
117 | regular event. If this is the last EBB event the PMU will be deconfigured and | ||
118 | no further PMU EBBs will be delivered. | ||
119 | |||
120 | |||
121 | EBB Handler | ||
122 | ----------- | ||
123 | |||
124 | The EBB handler is just regular userspace code, however it must be written in | ||
125 | the style of an interrupt handler. When the handler is entered all registers | ||
126 | are live (possibly) and so must be saved somehow before the handler can invoke | ||
127 | other code. | ||
128 | |||
129 | It's up to the program how to handle this. For C programs a relatively simple | ||
130 | option is to create an interrupt frame on the stack and save registers there. | ||
131 | |||
132 | Fork | ||
133 | ---- | ||
134 | |||
135 | EBB events are not inherited across fork. If the child process wishes to use | ||
136 | EBBs it should open a new event for itself. Similarly the EBB state in | ||
137 | BESCR/EBBHR/EBBRR is cleared across fork(). | ||