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-rw-r--r--Documentation/powerpc/dts-bindings/4xx/ppc440spe-adma.txt93
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/board.txt4
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/can.txt53
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt54
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/dma.txt8
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/i2c.txt30
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/mpc5121-psc.txt70
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/mpc5200.txt20
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/mpic.txt42
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/spi.txt7
-rw-r--r--Documentation/powerpc/dts-bindings/nintendo/gamecube.txt109
-rw-r--r--Documentation/powerpc/dts-bindings/nintendo/wii.txt184
-rw-r--r--Documentation/powerpc/dts-bindings/xilinx.txt11
-rw-r--r--Documentation/powerpc/ptrace.txt134
14 files changed, 810 insertions, 9 deletions
diff --git a/Documentation/powerpc/dts-bindings/4xx/ppc440spe-adma.txt b/Documentation/powerpc/dts-bindings/4xx/ppc440spe-adma.txt
new file mode 100644
index 000000000000..515ebcf1b97d
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/4xx/ppc440spe-adma.txt
@@ -0,0 +1,93 @@
1PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator)
2
3Device nodes needed for operation of the ppc440spe-adma driver
4are specified hereby. These are I2O/DMA, DMA and XOR nodes
5for DMA engines and Memory Queue Module node. The latter is used
6by ADMA driver for configuration of RAID-6 H/W capabilities of
7the PPC440SPe. In addition to the nodes and properties described
8below, the ranges property of PLB node must specify ranges for
9DMA devices.
10
11 i) The I2O node
12
13 Required properties:
14
15 - compatible : "ibm,i2o-440spe";
16 - reg : <registers mapping>
17 - dcr-reg : <DCR registers range>
18
19 Example:
20
21 I2O: i2o@400100000 {
22 compatible = "ibm,i2o-440spe";
23 reg = <0x00000004 0x00100000 0x100>;
24 dcr-reg = <0x060 0x020>;
25 };
26
27
28 ii) The DMA node
29
30 Required properties:
31
32 - compatible : "ibm,dma-440spe";
33 - cell-index : 1 cell, hardware index of the DMA engine
34 (typically 0x0 and 0x1 for DMA0 and DMA1)
35 - reg : <registers mapping>
36 - dcr-reg : <DCR registers range>
37 - interrupts : <interrupt mapping for DMA0/1 interrupts sources:
38 2 sources: DMAx CS FIFO Needs Service IRQ (on UIC0)
39 and DMA Error IRQ (on UIC1). The latter is common
40 for both DMA engines>.
41 - interrupt-parent : needed for interrupt mapping
42
43 Example:
44
45 DMA0: dma0@400100100 {
46 compatible = "ibm,dma-440spe";
47 cell-index = <0>;
48 reg = <0x00000004 0x00100100 0x100>;
49 dcr-reg = <0x060 0x020>;
50 interrupt-parent = <&DMA0>;
51 interrupts = <0 1>;
52 #interrupt-cells = <1>;
53 #address-cells = <0>;
54 #size-cells = <0>;
55 interrupt-map = <
56 0 &UIC0 0x14 4
57 1 &UIC1 0x16 4>;
58 };
59
60
61 iii) XOR Accelerator node
62
63 Required properties:
64
65 - compatible : "amcc,xor-accelerator";
66 - reg : <registers mapping>
67 - interrupts : <interrupt mapping for XOR interrupt source>
68 - interrupt-parent : for interrupt mapping
69
70 Example:
71
72 xor-accel@400200000 {
73 compatible = "amcc,xor-accelerator";
74 reg = <0x00000004 0x00200000 0x400>;
75 interrupt-parent = <&UIC1>;
76 interrupts = <0x1f 4>;
77 };
78
79
80 iv) Memory Queue Module node
81
82 Required properties:
83
84 - compatible : "ibm,mq-440spe";
85 - dcr-reg : <DCR registers range>
86
87 Example:
88
89 MQ0: mq {
90 compatible = "ibm,mq-440spe";
91 dcr-reg = <0x040 0x020>;
92 };
93
diff --git a/Documentation/powerpc/dts-bindings/fsl/board.txt b/Documentation/powerpc/dts-bindings/fsl/board.txt
index e8b5bc24d0ac..39e941515a36 100644
--- a/Documentation/powerpc/dts-bindings/fsl/board.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/board.txt
@@ -20,12 +20,16 @@ Required properities:
20- compatible : should be "fsl,fpga-pixis". 20- compatible : should be "fsl,fpga-pixis".
21- reg : should contain the address and the length of the FPPGA register 21- reg : should contain the address and the length of the FPPGA register
22 set. 22 set.
23- interrupt-parent: should specify phandle for the interrupt controller.
24- interrupts : should specify event (wakeup) IRQ.
23 25
24Example (MPC8610HPCD): 26Example (MPC8610HPCD):
25 27
26 board-control@e8000000 { 28 board-control@e8000000 {
27 compatible = "fsl,fpga-pixis"; 29 compatible = "fsl,fpga-pixis";
28 reg = <0xe8000000 32>; 30 reg = <0xe8000000 32>;
31 interrupt-parent = <&mpic>;
32 interrupts = <8 8>;
29 }; 33 };
30 34
31* Freescale BCSR GPIO banks 35* Freescale BCSR GPIO banks
diff --git a/Documentation/powerpc/dts-bindings/fsl/can.txt b/Documentation/powerpc/dts-bindings/fsl/can.txt
new file mode 100644
index 000000000000..2fa4fcd38fd6
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/can.txt
@@ -0,0 +1,53 @@
1CAN Device Tree Bindings
2------------------------
3
4(c) 2006-2009 Secret Lab Technologies Ltd
5Grant Likely <grant.likely@secretlab.ca>
6
7fsl,mpc5200-mscan nodes
8-----------------------
9In addition to the required compatible-, reg- and interrupt-properties, you can
10also specify which clock source shall be used for the controller:
11
12- fsl,mscan-clock-source : a string describing the clock source. Valid values
13 are: "ip" for ip bus clock
14 "ref" for reference clock (XTAL)
15 "ref" is default in case this property is not
16 present.
17
18fsl,mpc5121-mscan nodes
19-----------------------
20In addition to the required compatible-, reg- and interrupt-properties, you can
21also specify which clock source and divider shall be used for the controller:
22
23- fsl,mscan-clock-source : a string describing the clock source. Valid values
24 are: "ip" for ip bus clock
25 "ref" for reference clock
26 "sys" for system clock
27 If this property is not present, an optimal CAN
28 clock source and frequency based on the system
29 clock will be selected. If this is not possible,
30 the reference clock will be used.
31
32- fsl,mscan-clock-divider: for the reference and system clock, an additional
33 clock divider can be specified. By default, a
34 value of 1 is used.
35
36Note that the MPC5121 Rev. 1 processor is not supported.
37
38Examples:
39 can@1300 {
40 compatible = "fsl,mpc5121-mscan";
41 interrupts = <12 0x8>;
42 interrupt-parent = <&ipic>;
43 reg = <0x1300 0x80>;
44 };
45
46 can@1380 {
47 compatible = "fsl,mpc5121-mscan";
48 interrupts = <13 0x8>;
49 interrupt-parent = <&ipic>;
50 reg = <0x1380 0x80>;
51 fsl,mscan-clock-source = "ref";
52 fsl,mscan-clock-divider = <3>;
53 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
index 6e37be1eeb2d..4f8930263dd9 100644
--- a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
@@ -21,6 +21,15 @@ Required properties:
21- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use for the 21- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use for the
22 threads. 22 threads.
23 23
24Optional properties:
25- fsl,firmware-phandle:
26 Usage: required only if there is no fsl,qe-firmware child node
27 Value type: <phandle>
28 Definition: Points to a firmware node (see "QE Firmware Node" below)
29 that contains the firmware that should be uploaded for this QE.
30 The compatible property for the firmware node should say,
31 "fsl,qe-firmware".
32
24Recommended properties 33Recommended properties
25- brg-frequency : the internal clock source frequency for baud-rate 34- brg-frequency : the internal clock source frequency for baud-rate
26 generators in Hz. 35 generators in Hz.
@@ -59,3 +68,48 @@ Example:
59 reg = <0 c000>; 68 reg = <0 c000>;
60 }; 69 };
61 }; 70 };
71
72* QE Firmware Node
73
74This node defines a firmware binary that is embedded in the device tree, for
75the purpose of passing the firmware from bootloader to the kernel, or from
76the hypervisor to the guest.
77
78The firmware node itself contains the firmware binary contents, a compatible
79property, and any firmware-specific properties. The node should be placed
80inside a QE node that needs it. Doing so eliminates the need for a
81fsl,firmware-phandle property. Other QE nodes that need the same firmware
82should define an fsl,firmware-phandle property that points to the firmware node
83in the first QE node.
84
85The fsl,firmware property can be specified in the DTS (possibly using incbin)
86or can be inserted by the boot loader at boot time.
87
88Required properties:
89 - compatible
90 Usage: required
91 Value type: <string>
92 Definition: A standard property. Specify a string that indicates what
93 kind of firmware it is. For QE, this should be "fsl,qe-firmware".
94
95 - fsl,firmware
96 Usage: required
97 Value type: <prop-encoded-array>, encoded as an array of bytes
98 Definition: A standard property. This property contains the firmware
99 binary "blob".
100
101Example:
102 qe1@e0080000 {
103 compatible = "fsl,qe";
104 qe_firmware:qe-firmware {
105 compatible = "fsl,qe-firmware";
106 fsl,firmware = [0x70 0xcd 0x00 0x00 0x01 0x46 0x45 ...];
107 };
108 ...
109 };
110
111 qe2@e0090000 {
112 compatible = "fsl,qe";
113 fsl,firmware-phandle = <&qe_firmware>;
114 ...
115 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/dma.txt b/Documentation/powerpc/dts-bindings/fsl/dma.txt
index 0732cdd05ba1..2a4b4bce6110 100644
--- a/Documentation/powerpc/dts-bindings/fsl/dma.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/dma.txt
@@ -44,21 +44,29 @@ Example:
44 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 44 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
45 cell-index = <0>; 45 cell-index = <0>;
46 reg = <0 0x80>; 46 reg = <0 0x80>;
47 interrupt-parent = <&ipic>;
48 interrupts = <71 8>;
47 }; 49 };
48 dma-channel@80 { 50 dma-channel@80 {
49 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 51 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
50 cell-index = <1>; 52 cell-index = <1>;
51 reg = <0x80 0x80>; 53 reg = <0x80 0x80>;
54 interrupt-parent = <&ipic>;
55 interrupts = <71 8>;
52 }; 56 };
53 dma-channel@100 { 57 dma-channel@100 {
54 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 58 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
55 cell-index = <2>; 59 cell-index = <2>;
56 reg = <0x100 0x80>; 60 reg = <0x100 0x80>;
61 interrupt-parent = <&ipic>;
62 interrupts = <71 8>;
57 }; 63 };
58 dma-channel@180 { 64 dma-channel@180 {
59 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 65 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
60 cell-index = <3>; 66 cell-index = <3>;
61 reg = <0x180 0x80>; 67 reg = <0x180 0x80>;
68 interrupt-parent = <&ipic>;
69 interrupts = <71 8>;
62 }; 70 };
63 }; 71 };
64 72
diff --git a/Documentation/powerpc/dts-bindings/fsl/i2c.txt b/Documentation/powerpc/dts-bindings/fsl/i2c.txt
index b6d2e21474f9..50da20310585 100644
--- a/Documentation/powerpc/dts-bindings/fsl/i2c.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/i2c.txt
@@ -2,15 +2,14 @@
2 2
3Required properties : 3Required properties :
4 4
5 - device_type : Should be "i2c"
6 - reg : Offset and length of the register set for the device 5 - reg : Offset and length of the register set for the device
6 - compatible : should be "fsl,CHIP-i2c" where CHIP is the name of a
7 compatible processor, e.g. mpc8313, mpc8543, mpc8544, mpc5121,
8 mpc5200 or mpc5200b. For the mpc5121, an additional node
9 "fsl,mpc5121-i2c-ctrl" is required as shown in the example below.
7 10
8Recommended properties : 11Recommended properties :
9 12
10 - compatible : compatibility list with 2 entries, the first should
11 be "fsl,CHIP-i2c" where CHIP is the name of a compatible processor,
12 e.g. mpc8313, mpc8543, mpc8544, mpc5200 or mpc5200b. The second one
13 should be "fsl-i2c".
14 - interrupts : <a b> where a is the interrupt number and b is a 13 - interrupts : <a b> where a is the interrupt number and b is a
15 field that represents an encoding of the sense and level 14 field that represents an encoding of the sense and level
16 information for the interrupt. This should be encoded based on 15 information for the interrupt. This should be encoded based on
@@ -24,25 +23,40 @@ Recommended properties :
24 23
25Examples : 24Examples :
26 25
26 /* MPC5121 based board */
27 i2c@1740 {
28 #address-cells = <1>;
29 #size-cells = <0>;
30 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
31 reg = <0x1740 0x20>;
32 interrupts = <11 0x8>;
33 interrupt-parent = <&ipic>;
34 clock-frequency = <100000>;
35 };
36
37 i2ccontrol@1760 {
38 compatible = "fsl,mpc5121-i2c-ctrl";
39 reg = <0x1760 0x8>;
40 };
41
42 /* MPC5200B based board */
27 i2c@3d00 { 43 i2c@3d00 {
28 #address-cells = <1>; 44 #address-cells = <1>;
29 #size-cells = <0>; 45 #size-cells = <0>;
30 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 46 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
31 cell-index = <0>;
32 reg = <0x3d00 0x40>; 47 reg = <0x3d00 0x40>;
33 interrupts = <2 15 0>; 48 interrupts = <2 15 0>;
34 interrupt-parent = <&mpc5200_pic>; 49 interrupt-parent = <&mpc5200_pic>;
35 fsl,preserve-clocking; 50 fsl,preserve-clocking;
36 }; 51 };
37 52
53 /* MPC8544 base board */
38 i2c@3100 { 54 i2c@3100 {
39 #address-cells = <1>; 55 #address-cells = <1>;
40 #size-cells = <0>; 56 #size-cells = <0>;
41 cell-index = <1>;
42 compatible = "fsl,mpc8544-i2c", "fsl-i2c"; 57 compatible = "fsl,mpc8544-i2c", "fsl-i2c";
43 reg = <0x3100 0x100>; 58 reg = <0x3100 0x100>;
44 interrupts = <43 2>; 59 interrupts = <43 2>;
45 interrupt-parent = <&mpic>; 60 interrupt-parent = <&mpic>;
46 clock-frequency = <400000>; 61 clock-frequency = <400000>;
47 }; 62 };
48
diff --git a/Documentation/powerpc/dts-bindings/fsl/mpc5121-psc.txt b/Documentation/powerpc/dts-bindings/fsl/mpc5121-psc.txt
new file mode 100644
index 000000000000..8832e8798912
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/mpc5121-psc.txt
@@ -0,0 +1,70 @@
1MPC5121 PSC Device Tree Bindings
2
3PSC in UART mode
4----------------
5
6For PSC in UART mode the needed PSC serial devices
7are specified by fsl,mpc5121-psc-uart nodes in the
8fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9Controller node fsl,mpc5121-psc-fifo is requered there:
10
11fsl,mpc5121-psc-uart nodes
12--------------------------
13
14Required properties :
15 - compatible : Should contain "fsl,mpc5121-psc-uart" and "fsl,mpc5121-psc"
16 - cell-index : Index of the PSC in hardware
17 - reg : Offset and length of the register set for the PSC device
18 - interrupts : <a b> where a is the interrupt number of the
19 PSC FIFO Controller and b is a field that represents an
20 encoding of the sense and level information for the interrupt.
21 - interrupt-parent : the phandle for the interrupt controller that
22 services interrupts for this device.
23
24Recommended properties :
25 - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4)
26 - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4)
27
28
29fsl,mpc5121-psc-fifo node
30-------------------------
31
32Required properties :
33 - compatible : Should be "fsl,mpc5121-psc-fifo"
34 - reg : Offset and length of the register set for the PSC
35 FIFO Controller
36 - interrupts : <a b> where a is the interrupt number of the
37 PSC FIFO Controller and b is a field that represents an
38 encoding of the sense and level information for the interrupt.
39 - interrupt-parent : the phandle for the interrupt controller that
40 services interrupts for this device.
41
42
43Example for a board using PSC0 and PSC1 devices in serial mode:
44
45serial@11000 {
46 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
47 cell-index = <0>;
48 reg = <0x11000 0x100>;
49 interrupts = <40 0x8>;
50 interrupt-parent = < &ipic >;
51 fsl,rx-fifo-size = <16>;
52 fsl,tx-fifo-size = <16>;
53};
54
55serial@11100 {
56 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
57 cell-index = <1>;
58 reg = <0x11100 0x100>;
59 interrupts = <40 0x8>;
60 interrupt-parent = < &ipic >;
61 fsl,rx-fifo-size = <16>;
62 fsl,tx-fifo-size = <16>;
63};
64
65pscfifo@11f00 {
66 compatible = "fsl,mpc5121-psc-fifo";
67 reg = <0x11f00 0x100>;
68 interrupts = <40 0x8>;
69 interrupt-parent = < &ipic >;
70};
diff --git a/Documentation/powerpc/dts-bindings/fsl/mpc5200.txt b/Documentation/powerpc/dts-bindings/fsl/mpc5200.txt
index 8447fd7090d0..4ccb2cd5df94 100644
--- a/Documentation/powerpc/dts-bindings/fsl/mpc5200.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/mpc5200.txt
@@ -103,7 +103,22 @@ fsl,mpc5200-gpt nodes
103--------------------- 103---------------------
104On the mpc5200 and 5200b, GPT0 has a watchdog timer function. If the board 104On the mpc5200 and 5200b, GPT0 has a watchdog timer function. If the board
105design supports the internal wdt, then the device node for GPT0 should 105design supports the internal wdt, then the device node for GPT0 should
106include the empty property 'fsl,has-wdt'. 106include the empty property 'fsl,has-wdt'. Note that this does not activate
107the watchdog. The timer will function as a GPT if the timer api is used, and
108it will function as watchdog if the watchdog device is used. The watchdog
109mode has priority over the gpt mode, i.e. if the watchdog is activated, any
110gpt api call to this timer will fail with -EBUSY.
111
112If you add the property
113 fsl,wdt-on-boot = <n>;
114GPT0 will be marked as in-use watchdog, i.e. blocking every gpt access to it.
115If n>0, the watchdog is started with a timeout of n seconds. If n=0, the
116configuration of the watchdog is not touched. This is useful in two cases:
117- just mark GPT0 as watchdog, blocking gpt accesses, and configure it later;
118- do not touch a configuration assigned by the boot loader which supervises
119 the boot process itself.
120
121The watchdog will respect the CONFIG_WATCHDOG_NOWAYOUT option.
107 122
108An mpc5200-gpt can be used as a single line GPIO controller. To do so, 123An mpc5200-gpt can be used as a single line GPIO controller. To do so,
109add the following properties to the gpt node: 124add the following properties to the gpt node:
@@ -178,3 +193,6 @@ External interrupts:
178 external irq3: interrupts = <1 3 n>; 193 external irq3: interrupts = <1 3 n>;
179'n' is sense (0: level high, 1: edge rising, 2: edge falling 3: level low) 194'n' is sense (0: level high, 1: edge rising, 2: edge falling 3: level low)
180 195
196fsl,mpc5200-mscan nodes
197-----------------------
198See file can.txt in this directory.
diff --git a/Documentation/powerpc/dts-bindings/fsl/mpic.txt b/Documentation/powerpc/dts-bindings/fsl/mpic.txt
new file mode 100644
index 000000000000..71e39cf3215b
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/mpic.txt
@@ -0,0 +1,42 @@
1* OpenPIC and its interrupt numbers on Freescale's e500/e600 cores
2
3The OpenPIC specification does not specify which interrupt source has to
4become which interrupt number. This is up to the software implementation
5of the interrupt controller. The only requirement is that every
6interrupt source has to have an unique interrupt number / vector number.
7To accomplish this the current implementation assigns the number zero to
8the first source, the number one to the second source and so on until
9all interrupt sources have their unique number.
10Usually the assigned vector number equals the interrupt number mentioned
11in the documentation for a given core / CPU. This is however not true
12for the e500 cores (MPC85XX CPUs) where the documentation distinguishes
13between internal and external interrupt sources and starts counting at
14zero for both of them.
15
16So what to write for external interrupt source X or internal interrupt
17source Y into the device tree? Here is an example:
18
19The memory map for the interrupt controller in the MPC8544[0] shows,
20that the first interrupt source starts at 0x5_0000 (PIC Register Address
21Map-Interrupt Source Configuration Registers). This source becomes the
22number zero therefore:
23 External interrupt 0 = interrupt number 0
24 External interrupt 1 = interrupt number 1
25 External interrupt 2 = interrupt number 2
26 ...
27Every interrupt number allocates 0x20 bytes register space. So to get
28its number it is sufficient to shift the lower 16bits to right by five.
29So for the external interrupt 10 we have:
30 0x0140 >> 5 = 10
31
32After the external sources, the internal sources follow. The in core I2C
33controller on the MPC8544 for instance has the internal source number
3427. Oo obtain its interrupt number we take the lower 16bits of its memory
35address (0x5_0560) and shift it right:
36 0x0560 >> 5 = 43
37
38Therefore the I2C device node for the MPC8544 CPU has to have the
39interrupt number 43 specified in the device tree.
40
41[0] MPC8544E PowerQUICCTM III, Integrated Host Processor Family Reference Manual
42 MPC8544ERM Rev. 1 10/2007
diff --git a/Documentation/powerpc/dts-bindings/fsl/spi.txt b/Documentation/powerpc/dts-bindings/fsl/spi.txt
index e7d9a344c4f4..80510c018eea 100644
--- a/Documentation/powerpc/dts-bindings/fsl/spi.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/spi.txt
@@ -13,6 +13,11 @@ Required properties:
13- interrupt-parent : the phandle for the interrupt controller that 13- interrupt-parent : the phandle for the interrupt controller that
14 services interrupts for this device. 14 services interrupts for this device.
15 15
16Optional properties:
17- gpios : specifies the gpio pins to be used for chipselects.
18 The gpios will be referred to as reg = <index> in the SPI child nodes.
19 If unspecified, a single SPI device without a chip select can be used.
20
16Example: 21Example:
17 spi@4c0 { 22 spi@4c0 {
18 cell-index = <0>; 23 cell-index = <0>;
@@ -21,4 +26,6 @@ Example:
21 interrupts = <82 0>; 26 interrupts = <82 0>;
22 interrupt-parent = <700>; 27 interrupt-parent = <700>;
23 mode = "cpu"; 28 mode = "cpu";
29 gpios = <&gpio 18 1 // device reg=<0>
30 &gpio 19 1>; // device reg=<1>
24 }; 31 };
diff --git a/Documentation/powerpc/dts-bindings/nintendo/gamecube.txt b/Documentation/powerpc/dts-bindings/nintendo/gamecube.txt
new file mode 100644
index 000000000000..b558585b1aaf
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/nintendo/gamecube.txt
@@ -0,0 +1,109 @@
1
2Nintendo GameCube device tree
3=============================
4
51) The "flipper" node
6
7 This node represents the multi-function "Flipper" chip, which packages
8 many of the devices found in the Nintendo GameCube.
9
10 Required properties:
11
12 - compatible : Should be "nintendo,flipper"
13
141.a) The Video Interface (VI) node
15
16 Represents the interface between the graphics processor and a external
17 video encoder.
18
19 Required properties:
20
21 - compatible : should be "nintendo,flipper-vi"
22 - reg : should contain the VI registers location and length
23 - interrupts : should contain the VI interrupt
24
251.b) The Processor Interface (PI) node
26
27 Represents the data and control interface between the main processor
28 and graphics and audio processor.
29
30 Required properties:
31
32 - compatible : should be "nintendo,flipper-pi"
33 - reg : should contain the PI registers location and length
34
351.b.i) The "Flipper" interrupt controller node
36
37 Represents the interrupt controller within the "Flipper" chip.
38 The node for the "Flipper" interrupt controller must be placed under
39 the PI node.
40
41 Required properties:
42
43 - compatible : should be "nintendo,flipper-pic"
44
451.c) The Digital Signal Procesor (DSP) node
46
47 Represents the digital signal processor interface, designed to offload
48 audio related tasks.
49
50 Required properties:
51
52 - compatible : should be "nintendo,flipper-dsp"
53 - reg : should contain the DSP registers location and length
54 - interrupts : should contain the DSP interrupt
55
561.c.i) The Auxiliary RAM (ARAM) node
57
58 Represents the non cpu-addressable ram designed mainly to store audio
59 related information.
60 The ARAM node must be placed under the DSP node.
61
62 Required properties:
63
64 - compatible : should be "nintendo,flipper-aram"
65 - reg : should contain the ARAM start (zero-based) and length
66
671.d) The Disk Interface (DI) node
68
69 Represents the interface used to communicate with mass storage devices.
70
71 Required properties:
72
73 - compatible : should be "nintendo,flipper-di"
74 - reg : should contain the DI registers location and length
75 - interrupts : should contain the DI interrupt
76
771.e) The Audio Interface (AI) node
78
79 Represents the interface to the external 16-bit stereo digital-to-analog
80 converter.
81
82 Required properties:
83
84 - compatible : should be "nintendo,flipper-ai"
85 - reg : should contain the AI registers location and length
86 - interrupts : should contain the AI interrupt
87
881.f) The Serial Interface (SI) node
89
90 Represents the interface to the four single bit serial interfaces.
91 The SI is a proprietary serial interface used normally to control gamepads.
92 It's NOT a RS232-type interface.
93
94 Required properties:
95
96 - compatible : should be "nintendo,flipper-si"
97 - reg : should contain the SI registers location and length
98 - interrupts : should contain the SI interrupt
99
1001.g) The External Interface (EXI) node
101
102 Represents the multi-channel SPI-like interface.
103
104 Required properties:
105
106 - compatible : should be "nintendo,flipper-exi"
107 - reg : should contain the EXI registers location and length
108 - interrupts : should contain the EXI interrupt
109
diff --git a/Documentation/powerpc/dts-bindings/nintendo/wii.txt b/Documentation/powerpc/dts-bindings/nintendo/wii.txt
new file mode 100644
index 000000000000..a7e155a023b8
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/nintendo/wii.txt
@@ -0,0 +1,184 @@
1
2Nintendo Wii device tree
3========================
4
50) The root node
6
7 This node represents the Nintendo Wii video game console.
8
9 Required properties:
10
11 - model : Should be "nintendo,wii"
12 - compatible : Should be "nintendo,wii"
13
141) The "hollywood" node
15
16 This node represents the multi-function "Hollywood" chip, which packages
17 many of the devices found in the Nintendo Wii.
18
19 Required properties:
20
21 - compatible : Should be "nintendo,hollywood"
22
231.a) The Video Interface (VI) node
24
25 Represents the interface between the graphics processor and a external
26 video encoder.
27
28 Required properties:
29
30 - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi"
31 - reg : should contain the VI registers location and length
32 - interrupts : should contain the VI interrupt
33
341.b) The Processor Interface (PI) node
35
36 Represents the data and control interface between the main processor
37 and graphics and audio processor.
38
39 Required properties:
40
41 - compatible : should be "nintendo,hollywood-pi","nintendo,flipper-pi"
42 - reg : should contain the PI registers location and length
43
441.b.i) The "Flipper" interrupt controller node
45
46 Represents the "Flipper" interrupt controller within the "Hollywood" chip.
47 The node for the "Flipper" interrupt controller must be placed under
48 the PI node.
49
50 Required properties:
51
52 - #interrupt-cells : <1>
53 - compatible : should be "nintendo,flipper-pic"
54 - interrupt-controller
55
561.c) The Digital Signal Procesor (DSP) node
57
58 Represents the digital signal processor interface, designed to offload
59 audio related tasks.
60
61 Required properties:
62
63 - compatible : should be "nintendo,hollywood-dsp","nintendo,flipper-dsp"
64 - reg : should contain the DSP registers location and length
65 - interrupts : should contain the DSP interrupt
66
671.d) The Serial Interface (SI) node
68
69 Represents the interface to the four single bit serial interfaces.
70 The SI is a proprietary serial interface used normally to control gamepads.
71 It's NOT a RS232-type interface.
72
73 Required properties:
74
75 - compatible : should be "nintendo,hollywood-si","nintendo,flipper-si"
76 - reg : should contain the SI registers location and length
77 - interrupts : should contain the SI interrupt
78
791.e) The Audio Interface (AI) node
80
81 Represents the interface to the external 16-bit stereo digital-to-analog
82 converter.
83
84 Required properties:
85
86 - compatible : should be "nintendo,hollywood-ai","nintendo,flipper-ai"
87 - reg : should contain the AI registers location and length
88 - interrupts : should contain the AI interrupt
89
901.f) The External Interface (EXI) node
91
92 Represents the multi-channel SPI-like interface.
93
94 Required properties:
95
96 - compatible : should be "nintendo,hollywood-exi","nintendo,flipper-exi"
97 - reg : should contain the EXI registers location and length
98 - interrupts : should contain the EXI interrupt
99
1001.g) The Open Host Controller Interface (OHCI) nodes
101
102 Represent the USB 1.x Open Host Controller Interfaces.
103
104 Required properties:
105
106 - compatible : should be "nintendo,hollywood-usb-ohci","usb-ohci"
107 - reg : should contain the OHCI registers location and length
108 - interrupts : should contain the OHCI interrupt
109
1101.h) The Enhanced Host Controller Interface (EHCI) node
111
112 Represents the USB 2.0 Enhanced Host Controller Interface.
113
114 Required properties:
115
116 - compatible : should be "nintendo,hollywood-usb-ehci","usb-ehci"
117 - reg : should contain the EHCI registers location and length
118 - interrupts : should contain the EHCI interrupt
119
1201.i) The Secure Digital Host Controller Interface (SDHCI) nodes
121
122 Represent the Secure Digital Host Controller Interfaces.
123
124 Required properties:
125
126 - compatible : should be "nintendo,hollywood-sdhci","sdhci"
127 - reg : should contain the SDHCI registers location and length
128 - interrupts : should contain the SDHCI interrupt
129
1301.j) The Inter-Processsor Communication (IPC) node
131
132 Represent the Inter-Processor Communication interface. This interface
133 enables communications between the Broadway and the Starlet processors.
134
135 - compatible : should be "nintendo,hollywood-ipc"
136 - reg : should contain the IPC registers location and length
137 - interrupts : should contain the IPC interrupt
138
1391.k) The "Hollywood" interrupt controller node
140
141 Represents the "Hollywood" interrupt controller within the
142 "Hollywood" chip.
143
144 Required properties:
145
146 - #interrupt-cells : <1>
147 - compatible : should be "nintendo,hollywood-pic"
148 - reg : should contain the controller registers location and length
149 - interrupt-controller
150 - interrupts : should contain the cascade interrupt of the "flipper" pic
151 - interrupt-parent: should contain the phandle of the "flipper" pic
152
1531.l) The General Purpose I/O (GPIO) controller node
154
155 Represents the dual access 32 GPIO controller interface.
156
157 Required properties:
158
159 - #gpio-cells : <2>
160 - compatible : should be "nintendo,hollywood-gpio"
161 - reg : should contain the IPC registers location and length
162 - gpio-controller
163
1641.m) The control node
165
166 Represents the control interface used to setup several miscellaneous
167 settings of the "Hollywood" chip like boot memory mappings, resets,
168 disk interface mode, etc.
169
170 Required properties:
171
172 - compatible : should be "nintendo,hollywood-control"
173 - reg : should contain the control registers location and length
174
1751.n) The Disk Interface (DI) node
176
177 Represents the interface used to communicate with mass storage devices.
178
179 Required properties:
180
181 - compatible : should be "nintendo,hollywood-di"
182 - reg : should contain the DI registers location and length
183 - interrupts : should contain the DI interrupt
184
diff --git a/Documentation/powerpc/dts-bindings/xilinx.txt b/Documentation/powerpc/dts-bindings/xilinx.txt
index 80339fe4300b..ea68046bb9cb 100644
--- a/Documentation/powerpc/dts-bindings/xilinx.txt
+++ b/Documentation/powerpc/dts-bindings/xilinx.txt
@@ -292,4 +292,15 @@
292 - reg-offset : A value of 3 is required 292 - reg-offset : A value of 3 is required
293 - reg-shift : A value of 2 is required 293 - reg-shift : A value of 2 is required
294 294
295 vii) Xilinx USB Host controller
296
297 The Xilinx USB host controller is EHCI compatible but with a different
298 base address for the EHCI registers, and it is always a big-endian
299 USB Host controller. The hardware can be configured as high speed only,
300 or high speed/full speed hybrid.
301
302 Required properties:
303 - xlnx,support-usb-fs: A value 0 means the core is built as high speed
304 only. A value 1 means the core also supports
305 full speed devices.
295 306
diff --git a/Documentation/powerpc/ptrace.txt b/Documentation/powerpc/ptrace.txt
new file mode 100644
index 000000000000..f4a5499b7bc6
--- /dev/null
+++ b/Documentation/powerpc/ptrace.txt
@@ -0,0 +1,134 @@
1GDB intends to support the following hardware debug features of BookE
2processors:
3
44 hardware breakpoints (IAC)
52 hardware watchpoints (read, write and read-write) (DAC)
62 value conditions for the hardware watchpoints (DVC)
7
8For that, we need to extend ptrace so that GDB can query and set these
9resources. Since we're extending, we're trying to create an interface
10that's extendable and that covers both BookE and server processors, so
11that GDB doesn't need to special-case each of them. We added the
12following 3 new ptrace requests.
13
141. PTRACE_PPC_GETHWDEBUGINFO
15
16Query for GDB to discover the hardware debug features. The main info to
17be returned here is the minimum alignment for the hardware watchpoints.
18BookE processors don't have restrictions here, but server processors have
19an 8-byte alignment restriction for hardware watchpoints. We'd like to avoid
20adding special cases to GDB based on what it sees in AUXV.
21
22Since we're at it, we added other useful info that the kernel can return to
23GDB: this query will return the number of hardware breakpoints, hardware
24watchpoints and whether it supports a range of addresses and a condition.
25The query will fill the following structure provided by the requesting process:
26
27struct ppc_debug_info {
28 unit32_t version;
29 unit32_t num_instruction_bps;
30 unit32_t num_data_bps;
31 unit32_t num_condition_regs;
32 unit32_t data_bp_alignment;
33 unit32_t sizeof_condition; /* size of the DVC register */
34 uint64_t features; /* bitmask of the individual flags */
35};
36
37features will have bits indicating whether there is support for:
38
39#define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
40#define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
41#define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
42#define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
43
442. PTRACE_SETHWDEBUG
45
46Sets a hardware breakpoint or watchpoint, according to the provided structure:
47
48struct ppc_hw_breakpoint {
49 uint32_t version;
50#define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
51#define PPC_BREAKPOINT_TRIGGER_READ 0x2
52#define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
53 uint32_t trigger_type; /* only some combinations allowed */
54#define PPC_BREAKPOINT_MODE_EXACT 0x0
55#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
56#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
57#define PPC_BREAKPOINT_MODE_MASK 0x3
58 uint32_t addr_mode; /* address match mode */
59
60#define PPC_BREAKPOINT_CONDITION_MODE 0x3
61#define PPC_BREAKPOINT_CONDITION_NONE 0x0
62#define PPC_BREAKPOINT_CONDITION_AND 0x1
63#define PPC_BREAKPOINT_CONDITION_EXACT 0x1 /* different name for the same thing as above */
64#define PPC_BREAKPOINT_CONDITION_OR 0x2
65#define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
66#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 /* byte enable bits */
67#define PPC_BREAKPOINT_CONDITION_BE(n) (1<<((n)+16))
68 uint32_t condition_mode; /* break/watchpoint condition flags */
69
70 uint64_t addr;
71 uint64_t addr2;
72 uint64_t condition_value;
73};
74
75A request specifies one event, not necessarily just one register to be set.
76For instance, if the request is for a watchpoint with a condition, both the
77DAC and DVC registers will be set in the same request.
78
79With this GDB can ask for all kinds of hardware breakpoints and watchpoints
80that the BookE supports. COMEFROM breakpoints available in server processors
81are not contemplated, but that is out of the scope of this work.
82
83ptrace will return an integer (handle) uniquely identifying the breakpoint or
84watchpoint just created. This integer will be used in the PTRACE_DELHWDEBUG
85request to ask for its removal. Return -ENOSPC if the requested breakpoint
86can't be allocated on the registers.
87
88Some examples of using the structure to:
89
90- set a breakpoint in the first breakpoint register
91
92 p.version = PPC_DEBUG_CURRENT_VERSION;
93 p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
94 p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
95 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
96 p.addr = (uint64_t) address;
97 p.addr2 = 0;
98 p.condition_value = 0;
99
100- set a watchpoint which triggers on reads in the second watchpoint register
101
102 p.version = PPC_DEBUG_CURRENT_VERSION;
103 p.trigger_type = PPC_BREAKPOINT_TRIGGER_READ;
104 p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
105 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
106 p.addr = (uint64_t) address;
107 p.addr2 = 0;
108 p.condition_value = 0;
109
110- set a watchpoint which triggers only with a specific value
111
112 p.version = PPC_DEBUG_CURRENT_VERSION;
113 p.trigger_type = PPC_BREAKPOINT_TRIGGER_READ;
114 p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
115 p.condition_mode = PPC_BREAKPOINT_CONDITION_AND | PPC_BREAKPOINT_CONDITION_BE_ALL;
116 p.addr = (uint64_t) address;
117 p.addr2 = 0;
118 p.condition_value = (uint64_t) condition;
119
120- set a ranged hardware breakpoint
121
122 p.version = PPC_DEBUG_CURRENT_VERSION;
123 p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
124 p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
125 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
126 p.addr = (uint64_t) begin_range;
127 p.addr2 = (uint64_t) end_range;
128 p.condition_value = 0;
129
1303. PTRACE_DELHWDEBUG
131
132Takes an integer which identifies an existing breakpoint or watchpoint
133(i.e., the value returned from PTRACE_SETHWDEBUG), and deletes the
134corresponding breakpoint or watchpoint..
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-18 17:20:54 -0400