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-rw-r--r--Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt32
-rw-r--r--Documentation/devicetree/bindings/arm/marvell,berlin.txt24
-rw-r--r--Documentation/devicetree/bindings/clock/imx35-clock.txt113
-rw-r--r--Documentation/devicetree/bindings/clock/imx5-clock.txt195
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt2
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt32
6 files changed, 205 insertions, 193 deletions
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
new file mode 100644
index 000000000000..8c7a4653508d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -0,0 +1,32 @@
1Hisilicon Platforms Device Tree Bindings
2----------------------------------------------------
3
4Hi4511 Board
5Required root node properties:
6 - compatible = "hisilicon,hi3620-hi4511";
7
8Hisilicon system controller
9
10Required properties:
11- compatible : "hisilicon,sysctrl"
12- reg : Register address and size
13
14Optional properties:
15- smp-offset : offset in sysctrl for notifying slave cpu booting
16 cpu 1, reg;
17 cpu 2, reg + 0x4;
18 cpu 3, reg + 0x8;
19 If reg value is not zero, cpun exit wfi and go
20- resume-offset : offset in sysctrl for notifying cpu0 when resume
21- reboot-offset : offset in sysctrl for system reboot
22
23Example:
24
25 /* for Hi3620 */
26 sysctrl: system-controller@fc802000 {
27 compatible = "hisilicon,sysctrl";
28 reg = <0xfc802000 0x1000>;
29 smp-offset = <0x31c>;
30 resume-offset = <0x308>;
31 reboot-offset = <0x4>;
32 };
diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
new file mode 100644
index 000000000000..737afa5f8148
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
@@ -0,0 +1,24 @@
1Marvell Berlin SoC Family Device Tree Bindings
2---------------------------------------------------------------
3
4Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
5shall have the following properties:
6
7* Required root node properties:
8compatible: must contain "marvell,berlin"
9
10In addition, the above compatible shall be extended with the specific
11SoC and board used. Currently known SoC compatibles are:
12 "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
13 "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
14 "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
15 "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
16
17* Example:
18
19/ {
20 model = "Sony NSZ-GS7";
21 compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
22
23 ...
24}
diff --git a/Documentation/devicetree/bindings/clock/imx35-clock.txt b/Documentation/devicetree/bindings/clock/imx35-clock.txt
new file mode 100644
index 000000000000..a70356452a82
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx35-clock.txt
@@ -0,0 +1,113 @@
1* Clock bindings for Freescale i.MX35
2
3Required properties:
4- compatible: Should be "fsl,imx35-ccm"
5- reg: Address and length of the register set
6- interrupts: Should contain CCM interrupt
7- #clock-cells: Should be <1>
8
9The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell. The following is a full list of i.MX35
11clocks and IDs.
12
13 Clock ID
14 ---------------------------
15 ckih 0
16 mpll 1
17 ppll 2
18 mpll_075 3
19 arm 4
20 hsp 5
21 hsp_div 6
22 hsp_sel 7
23 ahb 8
24 ipg 9
25 arm_per_div 10
26 ahb_per_div 11
27 ipg_per 12
28 uart_sel 13
29 uart_div 14
30 esdhc_sel 15
31 esdhc1_div 16
32 esdhc2_div 17
33 esdhc3_div 18
34 spdif_sel 19
35 spdif_div_pre 20
36 spdif_div_post 21
37 ssi_sel 22
38 ssi1_div_pre 23
39 ssi1_div_post 24
40 ssi2_div_pre 25
41 ssi2_div_post 26
42 usb_sel 27
43 usb_div 28
44 nfc_div 29
45 asrc_gate 30
46 pata_gate 31
47 audmux_gate 32
48 can1_gate 33
49 can2_gate 34
50 cspi1_gate 35
51 cspi2_gate 36
52 ect_gate 37
53 edio_gate 38
54 emi_gate 39
55 epit1_gate 40
56 epit2_gate 41
57 esai_gate 42
58 esdhc1_gate 43
59 esdhc2_gate 44
60 esdhc3_gate 45
61 fec_gate 46
62 gpio1_gate 47
63 gpio2_gate 48
64 gpio3_gate 49
65 gpt_gate 50
66 i2c1_gate 51
67 i2c2_gate 52
68 i2c3_gate 53
69 iomuxc_gate 54
70 ipu_gate 55
71 kpp_gate 56
72 mlb_gate 57
73 mshc_gate 58
74 owire_gate 59
75 pwm_gate 60
76 rngc_gate 61
77 rtc_gate 62
78 rtic_gate 63
79 scc_gate 64
80 sdma_gate 65
81 spba_gate 66
82 spdif_gate 67
83 ssi1_gate 68
84 ssi2_gate 69
85 uart1_gate 70
86 uart2_gate 71
87 uart3_gate 72
88 usbotg_gate 73
89 wdog_gate 74
90 max_gate 75
91 admux_gate 76
92 csi_gate 77
93 csi_div 78
94 csi_sel 79
95 iim_gate 80
96 gpu2d_gate 81
97
98Examples:
99
100clks: ccm@53f80000 {
101 compatible = "fsl,imx35-ccm";
102 reg = <0x53f80000 0x4000>;
103 interrupts = <31>;
104 #clock-cells = <1>;
105};
106
107esdhc1: esdhc@53fb4000 {
108 compatible = "fsl,imx35-esdhc";
109 reg = <0x53fb4000 0x4000>;
110 interrupts = <7>;
111 clocks = <&clks 9>, <&clks 8>, <&clks 43>;
112 clock-names = "ipg", "ahb", "per";
113};
diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
index 4c029a8739d3..cadc4d29ada6 100644
--- a/Documentation/devicetree/bindings/clock/imx5-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -7,197 +7,8 @@ Required properties:
7- #clock-cells: Should be <1> 7- #clock-cells: Should be <1>
8 8
9The clock consumer should specify the desired clock by having the clock 9The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell. The following is a full list of i.MX5 10ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx5-clock.h
11clocks and IDs. 11for the full list of i.MX5 clock IDs.
12
13 Clock ID
14 ---------------------------
15 dummy 0
16 ckil 1
17 osc 2
18 ckih1 3
19 ckih2 4
20 ahb 5
21 ipg 6
22 axi_a 7
23 axi_b 8
24 uart_pred 9
25 uart_root 10
26 esdhc_a_pred 11
27 esdhc_b_pred 12
28 esdhc_c_s 13
29 esdhc_d_s 14
30 emi_sel 15
31 emi_slow_podf 16
32 nfc_podf 17
33 ecspi_pred 18
34 ecspi_podf 19
35 usboh3_pred 20
36 usboh3_podf 21
37 usb_phy_pred 22
38 usb_phy_podf 23
39 cpu_podf 24
40 di_pred 25
41 tve_s 27
42 uart1_ipg_gate 28
43 uart1_per_gate 29
44 uart2_ipg_gate 30
45 uart2_per_gate 31
46 uart3_ipg_gate 32
47 uart3_per_gate 33
48 i2c1_gate 34
49 i2c2_gate 35
50 gpt_ipg_gate 36
51 pwm1_ipg_gate 37
52 pwm1_hf_gate 38
53 pwm2_ipg_gate 39
54 pwm2_hf_gate 40
55 gpt_hf_gate 41
56 fec_gate 42
57 usboh3_per_gate 43
58 esdhc1_ipg_gate 44
59 esdhc2_ipg_gate 45
60 esdhc3_ipg_gate 46
61 esdhc4_ipg_gate 47
62 ssi1_ipg_gate 48
63 ssi2_ipg_gate 49
64 ssi3_ipg_gate 50
65 ecspi1_ipg_gate 51
66 ecspi1_per_gate 52
67 ecspi2_ipg_gate 53
68 ecspi2_per_gate 54
69 cspi_ipg_gate 55
70 sdma_gate 56
71 emi_slow_gate 57
72 ipu_s 58
73 ipu_gate 59
74 nfc_gate 60
75 ipu_di1_gate 61
76 vpu_s 62
77 vpu_gate 63
78 vpu_reference_gate 64
79 uart4_ipg_gate 65
80 uart4_per_gate 66
81 uart5_ipg_gate 67
82 uart5_per_gate 68
83 tve_gate 69
84 tve_pred 70
85 esdhc1_per_gate 71
86 esdhc2_per_gate 72
87 esdhc3_per_gate 73
88 esdhc4_per_gate 74
89 usb_phy_gate 75
90 hsi2c_gate 76
91 mipi_hsc1_gate 77
92 mipi_hsc2_gate 78
93 mipi_esc_gate 79
94 mipi_hsp_gate 80
95 ldb_di1_div_3_5 81
96 ldb_di1_div 82
97 ldb_di0_div_3_5 83
98 ldb_di0_div 84
99 ldb_di1_gate 85
100 can2_serial_gate 86
101 can2_ipg_gate 87
102 i2c3_gate 88
103 lp_apm 89
104 periph_apm 90
105 main_bus 91
106 ahb_max 92
107 aips_tz1 93
108 aips_tz2 94
109 tmax1 95
110 tmax2 96
111 tmax3 97
112 spba 98
113 uart_sel 99
114 esdhc_a_sel 100
115 esdhc_b_sel 101
116 esdhc_a_podf 102
117 esdhc_b_podf 103
118 ecspi_sel 104
119 usboh3_sel 105
120 usb_phy_sel 106
121 iim_gate 107
122 usboh3_gate 108
123 emi_fast_gate 109
124 ipu_di0_gate 110
125 gpc_dvfs 111
126 pll1_sw 112
127 pll2_sw 113
128 pll3_sw 114
129 ipu_di0_sel 115
130 ipu_di1_sel 116
131 tve_ext_sel 117
132 mx51_mipi 118
133 pll4_sw 119
134 ldb_di1_sel 120
135 di_pll4_podf 121
136 ldb_di0_sel 122
137 ldb_di0_gate 123
138 usb_phy1_gate 124
139 usb_phy2_gate 125
140 per_lp_apm 126
141 per_pred1 127
142 per_pred2 128
143 per_podf 129
144 per_root 130
145 ssi_apm 131
146 ssi1_root_sel 132
147 ssi2_root_sel 133
148 ssi3_root_sel 134
149 ssi_ext1_sel 135
150 ssi_ext2_sel 136
151 ssi_ext1_com_sel 137
152 ssi_ext2_com_sel 138
153 ssi1_root_pred 139
154 ssi1_root_podf 140
155 ssi2_root_pred 141
156 ssi2_root_podf 142
157 ssi_ext1_pred 143
158 ssi_ext1_podf 144
159 ssi_ext2_pred 145
160 ssi_ext2_podf 146
161 ssi1_root_gate 147
162 ssi2_root_gate 148
163 ssi3_root_gate 149
164 ssi_ext1_gate 150
165 ssi_ext2_gate 151
166 epit1_ipg_gate 152
167 epit1_hf_gate 153
168 epit2_ipg_gate 154
169 epit2_hf_gate 155
170 can_sel 156
171 can1_serial_gate 157
172 can1_ipg_gate 158
173 owire_gate 159
174 gpu3d_s 160
175 gpu2d_s 161
176 gpu3d_gate 162
177 gpu2d_gate 163
178 garb_gate 164
179 cko1_sel 165
180 cko1_podf 166
181 cko1 167
182 cko2_sel 168
183 cko2_podf 169
184 cko2 170
185 srtc_gate 171
186 pata_gate 172
187 sata_gate 173
188 spdif_xtal_sel 174
189 spdif0_sel 175
190 spdif1_sel 176
191 spdif0_pred 177
192 spdif0_podf 178
193 spdif1_pred 179
194 spdif1_podf 180
195 spdif0_com_sel 181
196 spdif1_com_sel 182
197 spdif0_gate 183
198 spdif1_gate 184
199 spdif_ipg_gate 185
200 ocram 186
201 12
202Examples (for mx53): 13Examples (for mx53):
203 14
@@ -212,7 +23,7 @@ can1: can@53fc8000 {
212 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; 23 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
213 reg = <0x53fc8000 0x4000>; 24 reg = <0x53fc8000 0x4000>;
214 interrupts = <82>; 25 interrupts = <82>;
215 clocks = <&clks 158>, <&clks 157>; 26 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
216 clock-names = "ipg", "per"; 27 clock-names = "ipg", "per";
217 status = "disabled"; 28 status = "disabled";
218}; 29};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
index 3d3b2b91e333..32cec4b26cd0 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
@@ -14,5 +14,5 @@ intc: interrupt-controller {
14 compatible = "allwinner,sun4i-ic"; 14 compatible = "allwinner,sun4i-ic";
15 reg = <0x01c20400 0x400>; 15 reg = <0x01c20400 0x400>;
16 interrupt-controller; 16 interrupt-controller;
17 #interrupt-cells = <2>; 17 #interrupt-cells = <1>;
18}; 18};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
new file mode 100644
index 000000000000..492911744ca3
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
@@ -0,0 +1,32 @@
1Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
2
3Synopsys DesignWare provides interrupt controller IP for APB known as
4dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
5APB bus, e.g. Marvell Armada 1500.
6
7Required properties:
8- compatible: shall be "snps,dw-apb-ictl"
9- reg: physical base address of the controller and length of memory mapped
10 region starting with ENABLE_LOW register
11- interrupt-controller: identifies the node as an interrupt controller
12- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
13- interrupts: interrupt reference to primary interrupt controller
14- interrupt-parent: (optional) reference specific primary interrupt controller
15
16The interrupt sources map to the corresponding bits in the interrupt
17registers, i.e.
18- 0 maps to bit 0 of low interrupts,
19- 1 maps to bit 1 of low interrupts,
20- 32 maps to bit 0 of high interrupts,
21- 33 maps to bit 1 of high interrupts,
22- (optional) fast interrupts start at 64.
23
24Example:
25 aic: interrupt-controller@3000 {
26 compatible = "snps,dw-apb-ictl";
27 reg = <0x3000 0xc00>;
28 interrupt-controller;
29 #interrupt-cells = <1>;
30 interrupt-parent = <&gic>;
31 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
32 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-23 09:25:27 -0500