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-rw-r--r--Documentation/devicetree/bindings/arm/omap/mpu.txt8
-rw-r--r--Documentation/devicetree/bindings/arm/pmu.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt2
-rw-r--r--Documentation/devicetree/bindings/clock/exynos4-clock.txt2
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5250-clock.txt2
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5420-clock.txt2
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5440-clock.txt2
-rw-r--r--Documentation/devicetree/bindings/dma/atmel-dma.txt2
-rw-r--r--Documentation/devicetree/bindings/gpio/8xxx_gpio.txt66
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-omap.txt3
-rw-r--r--Documentation/devicetree/bindings/i2c/trivial-devices.txt4
-rw-r--r--Documentation/devicetree/bindings/mmc/ti-omap.txt54
-rw-r--r--Documentation/devicetree/bindings/net/davinci_emac.txt2
-rw-r--r--Documentation/devicetree/bindings/net/fsl-fec.txt2
-rw-r--r--Documentation/devicetree/bindings/net/smsc-lan91c111.txt4
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/dma.txt138
-rw-r--r--Documentation/devicetree/bindings/rng/qcom,prng.txt17
-rw-r--r--Documentation/devicetree/bindings/spi/nvidia,tegra20-spi.txt5
-rw-r--r--Documentation/devicetree/bindings/vendor-prefixes.txt2
19 files changed, 242 insertions, 76 deletions
diff --git a/Documentation/devicetree/bindings/arm/omap/mpu.txt b/Documentation/devicetree/bindings/arm/omap/mpu.txt
index 1a5a42ce21bb..83f405bde138 100644
--- a/Documentation/devicetree/bindings/arm/omap/mpu.txt
+++ b/Documentation/devicetree/bindings/arm/omap/mpu.txt
@@ -7,10 +7,18 @@ The MPU contain CPUs, GIC, L2 cache and a local PRCM.
7Required properties: 7Required properties:
8- compatible : Should be "ti,omap3-mpu" for OMAP3 8- compatible : Should be "ti,omap3-mpu" for OMAP3
9 Should be "ti,omap4-mpu" for OMAP4 9 Should be "ti,omap4-mpu" for OMAP4
10 Should be "ti,omap5-mpu" for OMAP5
10- ti,hwmods: "mpu" 11- ti,hwmods: "mpu"
11 12
12Examples: 13Examples:
13 14
15- For an OMAP5 SMP system:
16
17mpu {
18 compatible = "ti,omap5-mpu";
19 ti,hwmods = "mpu"
20};
21
14- For an OMAP4 SMP system: 22- For an OMAP4 SMP system:
15 23
16mpu { 24mpu {
diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt
index 343781b9f246..3e1e498fea96 100644
--- a/Documentation/devicetree/bindings/arm/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/pmu.txt
@@ -7,6 +7,7 @@ representation in the device tree should be done as under:-
7Required properties: 7Required properties:
8 8
9- compatible : should be one of 9- compatible : should be one of
10 "arm,armv8-pmuv3"
10 "arm,cortex-a15-pmu" 11 "arm,cortex-a15-pmu"
11 "arm,cortex-a9-pmu" 12 "arm,cortex-a9-pmu"
12 "arm,cortex-a8-pmu" 13 "arm,cortex-a8-pmu"
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
index 47ada1dff216..5d49f2b37f68 100644
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
@@ -49,7 +49,7 @@ adc@12D10000 {
49 /* NTC thermistor is a hwmon device */ 49 /* NTC thermistor is a hwmon device */
50 ncp15wb473@0 { 50 ncp15wb473@0 {
51 compatible = "ntc,ncp15wb473"; 51 compatible = "ntc,ncp15wb473";
52 pullup-uV = <1800000>; 52 pullup-uv = <1800000>;
53 pullup-ohm = <47000>; 53 pullup-ohm = <47000>;
54 pulldown-ohm = <0>; 54 pulldown-ohm = <0>;
55 io-channels = <&adc 4>; 55 io-channels = <&adc 4>;
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index c6bf8a6c8f52..a2ac2d9ac71a 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -6,7 +6,7 @@ SoC's in the Exynos4 family.
6 6
7Required Properties: 7Required Properties:
8 8
9- comptible: should be one of the following. 9- compatible: should be one of the following.
10 - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC. 10 - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
11 - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC. 11 - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
12 12
diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 24765c146e31..46f5c791ea0d 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -5,7 +5,7 @@ controllers within the Exynos5250 SoC.
5 5
6Required Properties: 6Required Properties:
7 7
8- comptible: should be one of the following. 8- compatible: should be one of the following.
9 - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC. 9 - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
10 10
11- reg: physical base address of the controller and length of memory mapped 11- reg: physical base address of the controller and length of memory mapped
diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
index 32aa34ecad36..458f34789e5d 100644
--- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -5,7 +5,7 @@ controllers within the Exynos5420 SoC.
5 5
6Required Properties: 6Required Properties:
7 7
8- comptible: should be one of the following. 8- compatible: should be one of the following.
9 - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC. 9 - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
10 10
11- reg: physical base address of the controller and length of memory mapped 11- reg: physical base address of the controller and length of memory mapped
diff --git a/Documentation/devicetree/bindings/clock/exynos5440-clock.txt b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
index 4499e9966bc9..9955dc9c7d96 100644
--- a/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
@@ -5,7 +5,7 @@ controllers within the Exynos5440 SoC.
5 5
6Required Properties: 6Required Properties:
7 7
8- comptible: should be "samsung,exynos5440-clock". 8- compatible: should be "samsung,exynos5440-clock".
9 9
10- reg: physical base address of the controller and length of memory mapped 10- reg: physical base address of the controller and length of memory mapped
11 region. 11 region.
diff --git a/Documentation/devicetree/bindings/dma/atmel-dma.txt b/Documentation/devicetree/bindings/dma/atmel-dma.txt
index e1f343c7a34b..f69bcf5a6343 100644
--- a/Documentation/devicetree/bindings/dma/atmel-dma.txt
+++ b/Documentation/devicetree/bindings/dma/atmel-dma.txt
@@ -28,7 +28,7 @@ The three cells in order are:
28dependent: 28dependent:
29 - bit 7-0: peripheral identifier for the hardware handshaking interface. The 29 - bit 7-0: peripheral identifier for the hardware handshaking interface. The
30 identifier can be different for tx and rx. 30 identifier can be different for tx and rx.
31 - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 1 for ASAP. 31 - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP.
32 32
33Example: 33Example:
34 34
diff --git a/Documentation/devicetree/bindings/gpio/8xxx_gpio.txt b/Documentation/devicetree/bindings/gpio/8xxx_gpio.txt
index b0019eb5330e..798cfc9d3839 100644
--- a/Documentation/devicetree/bindings/gpio/8xxx_gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/8xxx_gpio.txt
@@ -5,16 +5,42 @@ This is for the non-QE/CPM/GUTs GPIO controllers as found on
5 5
6Every GPIO controller node must have #gpio-cells property defined, 6Every GPIO controller node must have #gpio-cells property defined,
7this information will be used to translate gpio-specifiers. 7this information will be used to translate gpio-specifiers.
8See bindings/gpio/gpio.txt for details of how to specify GPIO
9information for devices.
10
11The GPIO module usually is connected to the SoC's internal interrupt
12controller, see bindings/interrupt-controller/interrupts.txt (the
13interrupt client nodes section) for details how to specify this GPIO
14module's interrupt.
15
16The GPIO module may serve as another interrupt controller (cascaded to
17the SoC's internal interrupt controller). See the interrupt controller
18nodes section in bindings/interrupt-controller/interrupts.txt for
19details.
8 20
9Required properties: 21Required properties:
10- compatible : "fsl,<CHIP>-gpio" followed by "fsl,mpc8349-gpio" for 22- compatible: "fsl,<chip>-gpio" followed by "fsl,mpc8349-gpio"
11 83xx, "fsl,mpc8572-gpio" for 85xx and "fsl,mpc8610-gpio" for 86xx. 23 for 83xx, "fsl,mpc8572-gpio" for 85xx, or
12- #gpio-cells : Should be two. The first cell is the pin number and the 24 "fsl,mpc8610-gpio" for 86xx.
13 second cell is used to specify optional parameters (currently unused). 25- #gpio-cells: Should be two. The first cell is the pin number
14 - interrupts : Interrupt mapping for GPIO IRQ. 26 and the second cell is used to specify optional
15 - interrupt-parent : Phandle for the interrupt controller that 27 parameters (currently unused).
16 services interrupts for this device. 28- interrupt-parent: Phandle for the interrupt controller that
17- gpio-controller : Marks the port as GPIO controller. 29 services interrupts for this device.
30- interrupts: Interrupt mapping for GPIO IRQ.
31- gpio-controller: Marks the port as GPIO controller.
32
33Optional properties:
34- interrupt-controller: Empty boolean property which marks the GPIO
35 module as an IRQ controller.
36- #interrupt-cells: Should be two. Defines the number of integer
37 cells required to specify an interrupt within
38 this interrupt controller. The first cell
39 defines the pin number, the second cell
40 defines additional flags (trigger type,
41 trigger polarity). Note that the available
42 set of trigger conditions supported by the
43 GPIO module depends on the actual SoC.
18 44
19Example of gpio-controller nodes for a MPC8347 SoC: 45Example of gpio-controller nodes for a MPC8347 SoC:
20 46
@@ -22,39 +48,27 @@ Example of gpio-controller nodes for a MPC8347 SoC:
22 #gpio-cells = <2>; 48 #gpio-cells = <2>;
23 compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio"; 49 compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
24 reg = <0xc00 0x100>; 50 reg = <0xc00 0x100>;
25 interrupts = <74 0x8>;
26 interrupt-parent = <&ipic>; 51 interrupt-parent = <&ipic>;
52 interrupts = <74 0x8>;
27 gpio-controller; 53 gpio-controller;
54 interrupt-controller;
55 #interrupt-cells = <2>;
28 }; 56 };
29 57
30 gpio2: gpio-controller@d00 { 58 gpio2: gpio-controller@d00 {
31 #gpio-cells = <2>; 59 #gpio-cells = <2>;
32 compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio"; 60 compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
33 reg = <0xd00 0x100>; 61 reg = <0xd00 0x100>;
34 interrupts = <75 0x8>;
35 interrupt-parent = <&ipic>; 62 interrupt-parent = <&ipic>;
63 interrupts = <75 0x8>;
36 gpio-controller; 64 gpio-controller;
37 }; 65 };
38 66
39See booting-without-of.txt for details of how to specify GPIO 67Example of a peripheral using the GPIO module as an IRQ controller:
40information for devices.
41
42To use GPIO pins as interrupt sources for peripherals, specify the
43GPIO controller as the interrupt parent and define GPIO number +
44trigger mode using the interrupts property, which is defined like
45this:
46
47interrupts = <number trigger>, where:
48 - number: GPIO pin (0..31)
49 - trigger: trigger mode:
50 2 = trigger on falling edge
51 3 = trigger on both edges
52
53Example of device using this is:
54 68
55 funkyfpga@0 { 69 funkyfpga@0 {
56 compatible = "funky-fpga"; 70 compatible = "funky-fpga";
57 ... 71 ...
58 interrupts = <4 3>;
59 interrupt-parent = <&gpio1>; 72 interrupt-parent = <&gpio1>;
73 interrupts = <4 3>;
60 }; 74 };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-omap.txt b/Documentation/devicetree/bindings/i2c/i2c-omap.txt
index 56564aa4b444..7e49839d4124 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-omap.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-omap.txt
@@ -1,7 +1,8 @@
1I2C for OMAP platforms 1I2C for OMAP platforms
2 2
3Required properties : 3Required properties :
4- compatible : Must be "ti,omap3-i2c" or "ti,omap4-i2c" 4- compatible : Must be "ti,omap2420-i2c", "ti,omap2430-i2c", "ti,omap3-i2c"
5 or "ti,omap4-i2c"
5- ti,hwmods : Must be "i2c<n>", n being the instance number (1-based) 6- ti,hwmods : Must be "i2c<n>", n being the instance number (1-based)
6- #address-cells = <1>; 7- #address-cells = <1>;
7- #size-cells = <0>; 8- #size-cells = <0>;
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
index ad6a73852f08..b1cb3415e6f1 100644
--- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt
+++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
@@ -15,6 +15,7 @@ adi,adt7461 +/-1C TDM Extended Temp Range I.C
15adt7461 +/-1C TDM Extended Temp Range I.C 15adt7461 +/-1C TDM Extended Temp Range I.C
16at,24c08 i2c serial eeprom (24cxx) 16at,24c08 i2c serial eeprom (24cxx)
17atmel,24c02 i2c serial eeprom (24cxx) 17atmel,24c02 i2c serial eeprom (24cxx)
18atmel,at97sc3204t i2c trusted platform module (TPM)
18catalyst,24c32 i2c serial eeprom 19catalyst,24c32 i2c serial eeprom
19dallas,ds1307 64 x 8, Serial, I2C Real-Time Clock 20dallas,ds1307 64 x 8, Serial, I2C Real-Time Clock
20dallas,ds1338 I2C RTC with 56-Byte NV RAM 21dallas,ds1338 I2C RTC with 56-Byte NV RAM
@@ -35,6 +36,7 @@ fsl,mc13892 MC13892: Power Management Integrated Circuit (PMIC) for i.MX35/51
35fsl,mma8450 MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer 36fsl,mma8450 MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer
36fsl,mpr121 MPR121: Proximity Capacitive Touch Sensor Controller 37fsl,mpr121 MPR121: Proximity Capacitive Touch Sensor Controller
37fsl,sgtl5000 SGTL5000: Ultra Low-Power Audio Codec 38fsl,sgtl5000 SGTL5000: Ultra Low-Power Audio Codec
39gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface
38infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) 40infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz)
39infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz) 41infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz)
40maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator 42maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator
@@ -44,6 +46,7 @@ mc,rv3029c2 Real Time Clock Module with I2C-Bus
44national,lm75 I2C TEMP SENSOR 46national,lm75 I2C TEMP SENSOR
45national,lm80 Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor 47national,lm80 Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor
46national,lm92 ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator with Two-Wire Interface 48national,lm92 ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator with Two-Wire Interface
49nuvoton,npct501 i2c trusted platform module (TPM)
47nxp,pca9556 Octal SMBus and I2C registered interface 50nxp,pca9556 Octal SMBus and I2C registered interface
48nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset 51nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset
49nxp,pcf8563 Real-time clock/calendar 52nxp,pcf8563 Real-time clock/calendar
@@ -61,3 +64,4 @@ taos,tsl2550 Ambient Light Sensor with SMBUS/Two Wire Serial Interface
61ti,tsc2003 I2C Touch-Screen Controller 64ti,tsc2003 I2C Touch-Screen Controller
62ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface 65ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
63ti,tmp275 Digital Temperature Sensor 66ti,tmp275 Digital Temperature Sensor
67winbond,wpct301 i2c trusted platform module (TPM)
diff --git a/Documentation/devicetree/bindings/mmc/ti-omap.txt b/Documentation/devicetree/bindings/mmc/ti-omap.txt
new file mode 100644
index 000000000000..8de579969763
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/ti-omap.txt
@@ -0,0 +1,54 @@
1* TI MMC host controller for OMAP1 and 2420
2
3The MMC Host Controller on TI OMAP1 and 2420 family provides
4an interface for MMC, SD, and SDIO types of memory cards.
5
6This file documents differences between the core properties described
7by mmc.txt and the properties used by the omap mmc driver.
8
9Note that this driver will not work with omap2430 or later omaps,
10please see the omap hsmmc driver for the current omaps.
11
12Required properties:
13- compatible: Must be "ti,omap2420-mmc", for OMAP2420 controllers
14- ti,hwmods: For 2420, must be "msdi<n>", where n is controller
15 instance starting 1
16
17Examples:
18
19 msdi1: mmc@4809c000 {
20 compatible = "ti,omap2420-mmc";
21 ti,hwmods = "msdi1";
22 reg = <0x4809c000 0x80>;
23 interrupts = <83>;
24 dmas = <&sdma 61 &sdma 62>;
25 dma-names = "tx", "rx";
26 };
27
28* TI MMC host controller for OMAP1 and 2420
29
30The MMC Host Controller on TI OMAP1 and 2420 family provides
31an interface for MMC, SD, and SDIO types of memory cards.
32
33This file documents differences between the core properties described
34by mmc.txt and the properties used by the omap mmc driver.
35
36Note that this driver will not work with omap2430 or later omaps,
37please see the omap hsmmc driver for the current omaps.
38
39Required properties:
40- compatible: Must be "ti,omap2420-mmc", for OMAP2420 controllers
41- ti,hwmods: For 2420, must be "msdi<n>", where n is controller
42 instance starting 1
43
44Examples:
45
46 msdi1: mmc@4809c000 {
47 compatible = "ti,omap2420-mmc";
48 ti,hwmods = "msdi1";
49 reg = <0x4809c000 0x80>;
50 interrupts = <83>;
51 dmas = <&sdma 61 &sdma 62>;
52 dma-names = "tx", "rx";
53 };
54
diff --git a/Documentation/devicetree/bindings/net/davinci_emac.txt b/Documentation/devicetree/bindings/net/davinci_emac.txt
index 48b259e29e87..bad381faf036 100644
--- a/Documentation/devicetree/bindings/net/davinci_emac.txt
+++ b/Documentation/devicetree/bindings/net/davinci_emac.txt
@@ -4,7 +4,7 @@ This file provides information, what the device node
4for the davinci_emac interface contains. 4for the davinci_emac interface contains.
5 5
6Required properties: 6Required properties:
7- compatible: "ti,davinci-dm6467-emac"; 7- compatible: "ti,davinci-dm6467-emac" or "ti,am3517-emac"
8- reg: Offset and length of the register set for the device 8- reg: Offset and length of the register set for the device
9- ti,davinci-ctrl-reg-offset: offset to control register 9- ti,davinci-ctrl-reg-offset: offset to control register
10- ti,davinci-ctrl-mod-reg-offset: offset to control module register 10- ti,davinci-ctrl-mod-reg-offset: offset to control module register
diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt
index d53639221403..845ff848d895 100644
--- a/Documentation/devicetree/bindings/net/fsl-fec.txt
+++ b/Documentation/devicetree/bindings/net/fsl-fec.txt
@@ -15,6 +15,7 @@ Optional properties:
15 only if property "phy-reset-gpios" is available. Missing the property 15 only if property "phy-reset-gpios" is available. Missing the property
16 will have the duration be 1 millisecond. Numbers greater than 1000 are 16 will have the duration be 1 millisecond. Numbers greater than 1000 are
17 invalid and 1 millisecond will be used instead. 17 invalid and 1 millisecond will be used instead.
18- phy-supply: regulator that powers the Ethernet PHY.
18 19
19Example: 20Example:
20 21
@@ -25,4 +26,5 @@ ethernet@83fec000 {
25 phy-mode = "mii"; 26 phy-mode = "mii";
26 phy-reset-gpios = <&gpio2 14 0>; /* GPIO2_14 */ 27 phy-reset-gpios = <&gpio2 14 0>; /* GPIO2_14 */
27 local-mac-address = [00 04 9F 01 1B B9]; 28 local-mac-address = [00 04 9F 01 1B B9];
29 phy-supply = <&reg_fec_supply>;
28}; 30};
diff --git a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt b/Documentation/devicetree/bindings/net/smsc-lan91c111.txt
index 953049b4248a..5a41a8658daa 100644
--- a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt
+++ b/Documentation/devicetree/bindings/net/smsc-lan91c111.txt
@@ -8,3 +8,7 @@ Required properties:
8Optional properties: 8Optional properties:
9- phy-device : phandle to Ethernet phy 9- phy-device : phandle to Ethernet phy
10- local-mac-address : Ethernet mac address to use 10- local-mac-address : Ethernet mac address to use
11- reg-io-width : Mask of sizes (in bytes) of the IO accesses that
12 are supported on the device. Valid value for SMSC LAN91c111 are
13 1, 2 or 4. If it's omitted or invalid, the size would be 2 meaning
14 16-bit access only.
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
index 2a4b4bce6110..7fc1b010fa75 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
@@ -1,33 +1,30 @@
1* Freescale 83xx DMA Controller 1* Freescale DMA Controllers
2 2
3Freescale PowerPC 83xx have on chip general purpose DMA controllers. 3** Freescale Elo DMA Controller
4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
5 series chips such as mpc8315, mpc8349, mpc8379 etc.
4 6
5Required properties: 7Required properties:
6 8
7- compatible : compatible list, contains 2 entries, first is 9- compatible : must include "fsl,elo-dma"
8 "fsl,CHIP-dma", where CHIP is the processor 10- reg : DMA General Status Register, i.e. DGSR which contains
9 (mpc8349, mpc8360, etc.) and the second is 11 status for all the 4 DMA channels
10 "fsl,elo-dma" 12- ranges : describes the mapping between the address space of the
11- reg : <registers mapping for DMA general status reg> 13 DMA channels and the address space of the DMA controller
12- ranges : Should be defined as specified in 1) to describe the
13 DMA controller channels.
14- cell-index : controller index. 0 for controller @ 0x8100 14- cell-index : controller index. 0 for controller @ 0x8100
15- interrupts : <interrupt mapping for DMA IRQ> 15- interrupts : interrupt specifier for DMA IRQ
16- interrupt-parent : optional, if needed for interrupt mapping 16- interrupt-parent : optional, if needed for interrupt mapping
17 17
18
19- DMA channel nodes: 18- DMA channel nodes:
20 - compatible : compatible list, contains 2 entries, first is 19 - compatible : must include "fsl,elo-dma-channel"
21 "fsl,CHIP-dma-channel", where CHIP is the processor 20 However, see note below.
22 (mpc8349, mpc8350, etc.) and the second is 21 - reg : DMA channel specific registers
23 "fsl,elo-dma-channel". However, see note below. 22 - cell-index : DMA channel index starts at 0.
24 - reg : <registers mapping for channel>
25 - cell-index : dma channel index starts at 0.
26 23
27Optional properties: 24Optional properties:
28 - interrupts : <interrupt mapping for DMA channel IRQ> 25 - interrupts : interrupt specifier for DMA channel IRQ
29 (on 83xx this is expected to be identical to 26 (on 83xx this is expected to be identical to
30 the interrupts property of the parent node) 27 the interrupts property of the parent node)
31 - interrupt-parent : optional, if needed for interrupt mapping 28 - interrupt-parent : optional, if needed for interrupt mapping
32 29
33Example: 30Example:
@@ -70,30 +67,27 @@ Example:
70 }; 67 };
71 }; 68 };
72 69
73* Freescale 85xx/86xx DMA Controller 70** Freescale EloPlus DMA Controller
74 71 This is a 4-channel DMA controller with extended addresses and chaining,
75Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers. 72 mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as
73 mpc8540, mpc8641 p4080, bsc9131 etc.
76 74
77Required properties: 75Required properties:
78 76
79- compatible : compatible list, contains 2 entries, first is 77- compatible : must include "fsl,eloplus-dma"
80 "fsl,CHIP-dma", where CHIP is the processor 78- reg : DMA General Status Register, i.e. DGSR which contains
81 (mpc8540, mpc8540, etc.) and the second is 79 status for all the 4 DMA channels
82 "fsl,eloplus-dma"
83- reg : <registers mapping for DMA general status reg>
84- cell-index : controller index. 0 for controller @ 0x21000, 80- cell-index : controller index. 0 for controller @ 0x21000,
85 1 for controller @ 0xc000 81 1 for controller @ 0xc000
86- ranges : Should be defined as specified in 1) to describe the 82- ranges : describes the mapping between the address space of the
87 DMA controller channels. 83 DMA channels and the address space of the DMA controller
88 84
89- DMA channel nodes: 85- DMA channel nodes:
90 - compatible : compatible list, contains 2 entries, first is 86 - compatible : must include "fsl,eloplus-dma-channel"
91 "fsl,CHIP-dma-channel", where CHIP is the processor 87 However, see note below.
92 (mpc8540, mpc8560, etc.) and the second is 88 - cell-index : DMA channel index starts at 0.
93 "fsl,eloplus-dma-channel". However, see note below. 89 - reg : DMA channel specific registers
94 - cell-index : dma channel index starts at 0. 90 - interrupts : interrupt specifier for DMA channel IRQ
95 - reg : <registers mapping for channel>
96 - interrupts : <interrupt mapping for DMA channel IRQ>
97 - interrupt-parent : optional, if needed for interrupt mapping 91 - interrupt-parent : optional, if needed for interrupt mapping
98 92
99Example: 93Example:
@@ -134,6 +128,76 @@ Example:
134 }; 128 };
135 }; 129 };
136 130
131** Freescale Elo3 DMA Controller
132 DMA controller which has same function as EloPlus except that Elo3 has 8
133 channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx
134 series chips, such as t1040, t4240, b4860.
135
136Required properties:
137
138- compatible : must include "fsl,elo3-dma"
139- reg : contains two entries for DMA General Status Registers,
140 i.e. DGSR0 which includes status for channel 1~4, and
141 DGSR1 for channel 5~8
142- ranges : describes the mapping between the address space of the
143 DMA channels and the address space of the DMA controller
144
145- DMA channel nodes:
146 - compatible : must include "fsl,eloplus-dma-channel"
147 - reg : DMA channel specific registers
148 - interrupts : interrupt specifier for DMA channel IRQ
149 - interrupt-parent : optional, if needed for interrupt mapping
150
151Example:
152dma@100300 {
153 #address-cells = <1>;
154 #size-cells = <1>;
155 compatible = "fsl,elo3-dma";
156 reg = <0x100300 0x4>,
157 <0x100600 0x4>;
158 ranges = <0x0 0x100100 0x500>;
159 dma-channel@0 {
160 compatible = "fsl,eloplus-dma-channel";
161 reg = <0x0 0x80>;
162 interrupts = <28 2 0 0>;
163 };
164 dma-channel@80 {
165 compatible = "fsl,eloplus-dma-channel";
166 reg = <0x80 0x80>;
167 interrupts = <29 2 0 0>;
168 };
169 dma-channel@100 {
170 compatible = "fsl,eloplus-dma-channel";
171 reg = <0x100 0x80>;
172 interrupts = <30 2 0 0>;
173 };
174 dma-channel@180 {
175 compatible = "fsl,eloplus-dma-channel";
176 reg = <0x180 0x80>;
177 interrupts = <31 2 0 0>;
178 };
179 dma-channel@300 {
180 compatible = "fsl,eloplus-dma-channel";
181 reg = <0x300 0x80>;
182 interrupts = <76 2 0 0>;
183 };
184 dma-channel@380 {
185 compatible = "fsl,eloplus-dma-channel";
186 reg = <0x380 0x80>;
187 interrupts = <77 2 0 0>;
188 };
189 dma-channel@400 {
190 compatible = "fsl,eloplus-dma-channel";
191 reg = <0x400 0x80>;
192 interrupts = <78 2 0 0>;
193 };
194 dma-channel@480 {
195 compatible = "fsl,eloplus-dma-channel";
196 reg = <0x480 0x80>;
197 interrupts = <79 2 0 0>;
198 };
199};
200
137Note on DMA channel compatible properties: The compatible property must say 201Note on DMA channel compatible properties: The compatible property must say
138"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA 202"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA
139driver (fsldma). Any DMA channel used by fsldma cannot be used by another 203driver (fsldma). Any DMA channel used by fsldma cannot be used by another
diff --git a/Documentation/devicetree/bindings/rng/qcom,prng.txt b/Documentation/devicetree/bindings/rng/qcom,prng.txt
new file mode 100644
index 000000000000..8e5853c2879b
--- /dev/null
+++ b/Documentation/devicetree/bindings/rng/qcom,prng.txt
@@ -0,0 +1,17 @@
1Qualcomm MSM pseudo random number generator.
2
3Required properties:
4
5- compatible : should be "qcom,prng"
6- reg : specifies base physical address and size of the registers map
7- clocks : phandle to clock-controller plus clock-specifier pair
8- clock-names : "core" clocks all registers, FIFO and circuits in PRNG IP block
9
10Example:
11
12 rng@f9bff000 {
13 compatible = "qcom,prng";
14 reg = <0xf9bff000 0x200>;
15 clocks = <&clock GCC_PRNG_AHB_CLK>;
16 clock-names = "core";
17 };
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-spi.txt
deleted file mode 100644
index 6b9e51896693..000000000000
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-spi.txt
+++ /dev/null
@@ -1,5 +0,0 @@
1NVIDIA Tegra 2 SPI device
2
3Required properties:
4- compatible : should be "nvidia,tegra20-spi".
5- gpios : should specify GPIOs used for chipselect.
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index ce95ed1c6d3e..edbb8d88c85e 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -32,12 +32,14 @@ est ESTeem Wireless Modems
32fsl Freescale Semiconductor 32fsl Freescale Semiconductor
33GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc. 33GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
34gef GE Fanuc Intelligent Platforms Embedded Systems, Inc. 34gef GE Fanuc Intelligent Platforms Embedded Systems, Inc.
35gmt Global Mixed-mode Technology, Inc.
35hisilicon Hisilicon Limited. 36hisilicon Hisilicon Limited.
36hp Hewlett Packard 37hp Hewlett Packard
37ibm International Business Machines (IBM) 38ibm International Business Machines (IBM)
38idt Integrated Device Technologies, Inc. 39idt Integrated Device Technologies, Inc.
39img Imagination Technologies Ltd. 40img Imagination Technologies Ltd.
40intercontrol Inter Control Group 41intercontrol Inter Control Group
42lg LG Corporation
41linux Linux-specific binding 43linux Linux-specific binding
42lsi LSI Corp. (LSI Logic) 44lsi LSI Corp. (LSI Logic)
43marvell Marvell Technology Group Ltd. 45marvell Marvell Technology Group Ltd.
generated by cgit v1.2.2 (git 2.25.0) at 2026-07-08 08:23:50 -0400