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-rw-r--r--Documentation/devicetree/bindings/drm/armada/marvell,dove-lcd.txt30
-rw-r--r--Documentation/devicetree/bindings/drm/i2c/tda998x.txt2
-rw-r--r--Documentation/devicetree/bindings/drm/msm/gpu.txt52
-rw-r--r--Documentation/devicetree/bindings/drm/msm/hdmi.txt46
-rw-r--r--Documentation/devicetree/bindings/drm/msm/mdp.txt48
-rw-r--r--Documentation/devicetree/bindings/gpu/st,stih4xx.txt189
-rw-r--r--Documentation/devicetree/bindings/panel/auo,b133htn01.txt7
-rw-r--r--Documentation/devicetree/bindings/panel/foxlink,fl500wvr00-a0t.txt7
-rw-r--r--Documentation/devicetree/bindings/panel/innolux,n116bge.txt7
-rw-r--r--Documentation/devicetree/bindings/panel/innolux,n156bge-l21.txt7
-rw-r--r--Documentation/devicetree/bindings/video/exynos_dsim.txt4
-rw-r--r--Documentation/devicetree/bindings/video/exynos_mixer.txt5
-rw-r--r--Documentation/devicetree/bindings/video/samsung-fimd.txt28
13 files changed, 429 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/drm/armada/marvell,dove-lcd.txt b/Documentation/devicetree/bindings/drm/armada/marvell,dove-lcd.txt
new file mode 100644
index 000000000000..46525ea3e646
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/armada/marvell,dove-lcd.txt
@@ -0,0 +1,30 @@
1Device Tree bindings for Armada DRM CRTC driver
2
3Required properties:
4 - compatible: value should be "marvell,dove-lcd".
5 - reg: base address and size of the LCD controller
6 - interrupts: single interrupt number for the LCD controller
7 - port: video output port with endpoints, as described by graph.txt
8
9Optional properties:
10
11 - clocks: as described by clock-bindings.txt
12 - clock-names: as described by clock-bindings.txt
13 "axiclk" - axi bus clock for pixel clock
14 "plldivider" - pll divider clock for pixel clock
15 "ext_ref_clk0" - external clock 0 for pixel clock
16 "ext_ref_clk1" - external clock 1 for pixel clock
17
18Note: all clocks are optional but at least one must be specified.
19Further clocks may be added in the future according to requirements of
20different SoCs.
21
22Example:
23
24 lcd0: lcd-controller@820000 {
25 compatible = "marvell,dove-lcd";
26 reg = <0x820000 0x1000>;
27 interrupts = <47>;
28 clocks = <&si5351 0>;
29 clock-names = "ext_ref_clk_1";
30 };
diff --git a/Documentation/devicetree/bindings/drm/i2c/tda998x.txt b/Documentation/devicetree/bindings/drm/i2c/tda998x.txt
index d7df01c5bb3a..e9e4bce40760 100644
--- a/Documentation/devicetree/bindings/drm/i2c/tda998x.txt
+++ b/Documentation/devicetree/bindings/drm/i2c/tda998x.txt
@@ -3,6 +3,8 @@ Device-Tree bindings for the NXP TDA998x HDMI transmitter
3Required properties; 3Required properties;
4 - compatible: must be "nxp,tda998x" 4 - compatible: must be "nxp,tda998x"
5 5
6 - reg: I2C address
7
6Optional properties: 8Optional properties:
7 - interrupts: interrupt number and trigger type 9 - interrupts: interrupt number and trigger type
8 default: polling 10 default: polling
diff --git a/Documentation/devicetree/bindings/drm/msm/gpu.txt b/Documentation/devicetree/bindings/drm/msm/gpu.txt
new file mode 100644
index 000000000000..67d0a58dbb77
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/msm/gpu.txt
@@ -0,0 +1,52 @@
1Qualcomm adreno/snapdragon GPU
2
3Required properties:
4- compatible: "qcom,adreno-3xx"
5- reg: Physical base address and length of the controller's registers.
6- interrupts: The interrupt signal from the gpu.
7- clocks: device clocks
8 See ../clocks/clock-bindings.txt for details.
9- clock-names: the following clocks are required:
10 * "core_clk"
11 * "iface_clk"
12 * "mem_iface_clk"
13- qcom,chipid: gpu chip-id. Note this may become optional for future
14 devices if we can reliably read the chipid from hw
15- qcom,gpu-pwrlevels: list of operating points
16 - compatible: "qcom,gpu-pwrlevels"
17 - for each qcom,gpu-pwrlevel:
18 - qcom,gpu-freq: requested gpu clock speed
19 - NOTE: downstream android driver defines additional parameters to
20 configure memory bandwidth scaling per OPP.
21
22Example:
23
24/ {
25 ...
26
27 gpu: qcom,kgsl-3d0@4300000 {
28 compatible = "qcom,adreno-3xx";
29 reg = <0x04300000 0x20000>;
30 reg-names = "kgsl_3d0_reg_memory";
31 interrupts = <GIC_SPI 80 0>;
32 interrupt-names = "kgsl_3d0_irq";
33 clock-names =
34 "core_clk",
35 "iface_clk",
36 "mem_iface_clk";
37 clocks =
38 <&mmcc GFX3D_CLK>,
39 <&mmcc GFX3D_AHB_CLK>,
40 <&mmcc MMSS_IMEM_AHB_CLK>;
41 qcom,chipid = <0x03020100>;
42 qcom,gpu-pwrlevels {
43 compatible = "qcom,gpu-pwrlevels";
44 qcom,gpu-pwrlevel@0 {
45 qcom,gpu-freq = <450000000>;
46 };
47 qcom,gpu-pwrlevel@1 {
48 qcom,gpu-freq = <27000000>;
49 };
50 };
51 };
52};
diff --git a/Documentation/devicetree/bindings/drm/msm/hdmi.txt b/Documentation/devicetree/bindings/drm/msm/hdmi.txt
new file mode 100644
index 000000000000..aca917fe2ba7
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/msm/hdmi.txt
@@ -0,0 +1,46 @@
1Qualcomm adreno/snapdragon hdmi output
2
3Required properties:
4- compatible: one of the following
5 * "qcom,hdmi-tx-8660"
6 * "qcom,hdmi-tx-8960"
7- reg: Physical base address and length of the controller's registers
8- reg-names: "core_physical"
9- interrupts: The interrupt signal from the hdmi block.
10- clocks: device clocks
11 See ../clocks/clock-bindings.txt for details.
12- qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin
13- qcom,hdmi-tx-ddc-data-gpio: ddc data pin
14- qcom,hdmi-tx-hpd-gpio: hpd pin
15- core-vdda-supply: phandle to supply regulator
16- hdmi-mux-supply: phandle to mux regulator
17
18Optional properties:
19- qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin
20- qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin
21
22Example:
23
24/ {
25 ...
26
27 hdmi: qcom,hdmi-tx-8960@4a00000 {
28 compatible = "qcom,hdmi-tx-8960";
29 reg-names = "core_physical";
30 reg = <0x04a00000 0x1000>;
31 interrupts = <GIC_SPI 79 0>;
32 clock-names =
33 "core_clk",
34 "master_iface_clk",
35 "slave_iface_clk";
36 clocks =
37 <&mmcc HDMI_APP_CLK>,
38 <&mmcc HDMI_M_AHB_CLK>,
39 <&mmcc HDMI_S_AHB_CLK>;
40 qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>;
41 qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>;
42 qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>;
43 core-vdda-supply = <&pm8921_hdmi_mvs>;
44 hdmi-mux-supply = <&ext_3p3v>;
45 };
46};
diff --git a/Documentation/devicetree/bindings/drm/msm/mdp.txt b/Documentation/devicetree/bindings/drm/msm/mdp.txt
new file mode 100644
index 000000000000..1a0598e5279d
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/msm/mdp.txt
@@ -0,0 +1,48 @@
1Qualcomm adreno/snapdragon display controller
2
3Required properties:
4- compatible:
5 * "qcom,mdp" - mdp4
6- reg: Physical base address and length of the controller's registers.
7- interrupts: The interrupt signal from the display controller.
8- connectors: array of phandles for output device(s)
9- clocks: device clocks
10 See ../clocks/clock-bindings.txt for details.
11- clock-names: the following clocks are required:
12 * "core_clk"
13 * "iface_clk"
14 * "lut_clk"
15 * "src_clk"
16 * "hdmi_clk"
17 * "mpd_clk"
18
19Optional properties:
20- gpus: phandle for gpu device
21
22Example:
23
24/ {
25 ...
26
27 mdp: qcom,mdp@5100000 {
28 compatible = "qcom,mdp";
29 reg = <0x05100000 0xf0000>;
30 interrupts = <GIC_SPI 75 0>;
31 connectors = <&hdmi>;
32 gpus = <&gpu>;
33 clock-names =
34 "core_clk",
35 "iface_clk",
36 "lut_clk",
37 "src_clk",
38 "hdmi_clk",
39 "mdp_clk";
40 clocks =
41 <&mmcc MDP_SRC>,
42 <&mmcc MDP_AHB_CLK>,
43 <&mmcc MDP_LUT_CLK>,
44 <&mmcc TV_SRC>,
45 <&mmcc HDMI_TV_CLK>,
46 <&mmcc MDP_TV_CLK>;
47 };
48};
diff --git a/Documentation/devicetree/bindings/gpu/st,stih4xx.txt b/Documentation/devicetree/bindings/gpu/st,stih4xx.txt
new file mode 100644
index 000000000000..2d150c311a05
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/st,stih4xx.txt
@@ -0,0 +1,189 @@
1STMicroelectronics stih4xx platforms
2
3- sti-vtg: video timing generator
4 Required properties:
5 - compatible: "st,vtg"
6 - reg: Physical base address of the IP registers and length of memory mapped region.
7 Optional properties:
8 - interrupts : VTG interrupt number to the CPU.
9 - st,slave: phandle on a slave vtg
10
11- sti-vtac: video timing advanced inter dye communication Rx and TX
12 Required properties:
13 - compatible: "st,vtac-main" or "st,vtac-aux"
14 - reg: Physical base address of the IP registers and length of memory mapped region.
15 - clocks: from common clock binding: handle hardware IP needed clocks, the
16 number of clocks may depend of the SoC type.
17 See ../clocks/clock-bindings.txt for details.
18 - clock-names: names of the clocks listed in clocks property in the same
19 order.
20
21- sti-display-subsystem: Master device for DRM sub-components
22 This device must be the parent of all the sub-components and is responsible
23 of bind them.
24 Required properties:
25 - compatible: "st,sti-display-subsystem"
26 - ranges: to allow probing of subdevices
27
28- sti-compositor: frame compositor engine
29 must be a child of sti-display-subsystem
30 Required properties:
31 - compatible: "st,stih<chip>-compositor"
32 - reg: Physical base address of the IP registers and length of memory mapped region.
33 - clocks: from common clock binding: handle hardware IP needed clocks, the
34 number of clocks may depend of the SoC type.
35 See ../clocks/clock-bindings.txt for details.
36 - clock-names: names of the clocks listed in clocks property in the same
37 order.
38 - resets: resets to be used by the device
39 See ../reset/reset.txt for details.
40 - reset-names: names of the resets listed in resets property in the same
41 order.
42 - st,vtg: phandle(s) on vtg device (main and aux) nodes.
43
44- sti-tvout: video out hardware block
45 must be a child of sti-display-subsystem
46 Required properties:
47 - compatible: "st,stih<chip>-tvout"
48 - reg: Physical base address of the IP registers and length of memory mapped region.
49 - reg-names: names of the mapped memory regions listed in regs property in
50 the same order.
51 - resets: resets to be used by the device
52 See ../reset/reset.txt for details.
53 - reset-names: names of the resets listed in resets property in the same
54 order.
55 - ranges: to allow probing of subdevices
56
57- sti-hdmi: hdmi output block
58 must be a child of sti-tvout
59 Required properties:
60 - compatible: "st,stih<chip>-hdmi";
61 - reg: Physical base address of the IP registers and length of memory mapped region.
62 - reg-names: names of the mapped memory regions listed in regs property in
63 the same order.
64 - interrupts : HDMI interrupt number to the CPU.
65 - interrupt-names: name of the interrupts listed in interrupts property in
66 the same order
67 - clocks: from common clock binding: handle hardware IP needed clocks, the
68 number of clocks may depend of the SoC type.
69 - clock-names: names of the clocks listed in clocks property in the same
70 order.
71 - hdmi,hpd-gpio: gpio id to detect if an hdmi cable is plugged or not.
72
73sti-hda:
74 Required properties:
75 must be a child of sti-tvout
76 - compatible: "st,stih<chip>-hda"
77 - reg: Physical base address of the IP registers and length of memory mapped region.
78 - reg-names: names of the mapped memory regions listed in regs property in
79 the same order.
80 - clocks: from common clock binding: handle hardware IP needed clocks, the
81 number of clocks may depend of the SoC type.
82 See ../clocks/clock-bindings.txt for details.
83 - clock-names: names of the clocks listed in clocks property in the same
84 order.
85
86Example:
87
88/ {
89 ...
90
91 vtg_main_slave: sti-vtg-main-slave@fe85A800 {
92 compatible = "st,vtg";
93 reg = <0xfe85A800 0x300>;
94 interrupts = <GIC_SPI 175 IRQ_TYPE_NONE>;
95 };
96
97 vtg_main: sti-vtg-main-master@fd348000 {
98 compatible = "st,vtg";
99 reg = <0xfd348000 0x400>;
100 st,slave = <&vtg_main_slave>;
101 };
102
103 vtg_aux_slave: sti-vtg-aux-slave@fd348400 {
104 compatible = "st,vtg";
105 reg = <0xfe858200 0x300>;
106 interrupts = <GIC_SPI 176 IRQ_TYPE_NONE>;
107 };
108
109 vtg_aux: sti-vtg-aux-master@fd348400 {
110 compatible = "st,vtg";
111 reg = <0xfd348400 0x400>;
112 st,slave = <&vtg_aux_slave>;
113 };
114
115
116 sti-vtac-rx-main@fee82800 {
117 compatible = "st,vtac-main";
118 reg = <0xfee82800 0x200>;
119 clock-names = "vtac";
120 clocks = <&clk_m_a2_div0 CLK_M_VTAC_MAIN_PHY>;
121 };
122
123 sti-vtac-rx-aux@fee82a00 {
124 compatible = "st,vtac-aux";
125 reg = <0xfee82a00 0x200>;
126 clock-names = "vtac";
127 clocks = <&clk_m_a2_div0 CLK_M_VTAC_AUX_PHY>;
128 };
129
130 sti-vtac-tx-main@fd349000 {
131 compatible = "st,vtac-main";
132 reg = <0xfd349000 0x200>, <0xfd320000 0x10000>;
133 clock-names = "vtac";
134 clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
135 };
136
137 sti-vtac-tx-aux@fd349200 {
138 compatible = "st,vtac-aux";
139 reg = <0xfd349200 0x200>, <0xfd320000 0x10000>;
140 clock-names = "vtac";
141 clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
142 };
143
144 sti-display-subsystem {
145 compatible = "st,sti-display-subsystem";
146 ranges;
147
148 sti-compositor@fd340000 {
149 compatible = "st,stih416-compositor";
150 reg = <0xfd340000 0x1000>;
151 clock-names = "compo_main", "compo_aux",
152 "pix_main", "pix_aux";
153 clocks = <&clk_m_a2_div1 CLK_M_COMPO_MAIN>, <&clk_m_a2_div1 CLK_M_COMPO_AUX>,
154 <&clockgen_c_vcc CLK_S_PIX_MAIN>, <&clockgen_c_vcc CLK_S_PIX_AUX>;
155 reset-names = "compo-main", "compo-aux";
156 resets = <&softreset STIH416_COMPO_M_SOFTRESET>, <&softreset STIH416_COMPO_A_SOFTRESET>;
157 st,vtg = <&vtg_main>, <&vtg_aux>;
158 };
159
160 sti-tvout@fe000000 {
161 compatible = "st,stih416-tvout";
162 reg = <0xfe000000 0x1000>, <0xfe85a000 0x400>, <0xfe830000 0x10000>;
163 reg-names = "tvout-reg", "hda-reg", "syscfg";
164 reset-names = "tvout";
165 resets = <&softreset STIH416_HDTVOUT_SOFTRESET>;
166 ranges;
167
168 sti-hdmi@fe85c000 {
169 compatible = "st,stih416-hdmi";
170 reg = <0xfe85c000 0x1000>, <0xfe830000 0x10000>;
171 reg-names = "hdmi-reg", "syscfg";
172 interrupts = <GIC_SPI 173 IRQ_TYPE_NONE>;
173 interrupt-names = "irq";
174 clock-names = "pix", "tmds", "phy", "audio";
175 clocks = <&clockgen_c_vcc CLK_S_PIX_HDMI>, <&clockgen_c_vcc CLK_S_TMDS_HDMI>, <&clockgen_c_vcc CLK_S_HDMI_REJECT_PLL>, <&clockgen_b1 CLK_S_PCM_0>;
176 hdmi,hpd-gpio = <&PIO2 5>;
177 };
178
179 sti-hda@fe85a000 {
180 compatible = "st,stih416-hda";
181 reg = <0xfe85a000 0x400>, <0xfe83085c 0x4>;
182 reg-names = "hda-reg", "video-dacs-ctrl";
183 clock-names = "pix", "hddac";
184 clocks = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>;
185 };
186 };
187 };
188 ...
189};
diff --git a/Documentation/devicetree/bindings/panel/auo,b133htn01.txt b/Documentation/devicetree/bindings/panel/auo,b133htn01.txt
new file mode 100644
index 000000000000..302226b5bb55
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/auo,b133htn01.txt
@@ -0,0 +1,7 @@
1AU Optronics Corporation 13.3" FHD (1920x1080) color TFT-LCD panel
2
3Required properties:
4- compatible: should be "auo,b133htn01"
5
6This binding is compatible with the simple-panel binding, which is specified
7in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/panel/foxlink,fl500wvr00-a0t.txt b/Documentation/devicetree/bindings/panel/foxlink,fl500wvr00-a0t.txt
new file mode 100644
index 000000000000..b47f9d87bc19
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/foxlink,fl500wvr00-a0t.txt
@@ -0,0 +1,7 @@
1Foxlink Group 5" WVGA TFT LCD panel
2
3Required properties:
4- compatible: should be "foxlink,fl500wvr00-a0t"
5
6This binding is compatible with the simple-panel binding, which is specified
7in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/panel/innolux,n116bge.txt b/Documentation/devicetree/bindings/panel/innolux,n116bge.txt
new file mode 100644
index 000000000000..081bb939ed31
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/innolux,n116bge.txt
@@ -0,0 +1,7 @@
1Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel
2
3Required properties:
4- compatible: should be "innolux,n116bge"
5
6This binding is compatible with the simple-panel binding, which is specified
7in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/panel/innolux,n156bge-l21.txt b/Documentation/devicetree/bindings/panel/innolux,n156bge-l21.txt
new file mode 100644
index 000000000000..7825844aafdf
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/innolux,n156bge-l21.txt
@@ -0,0 +1,7 @@
1InnoLux 15.6" WXGA TFT LCD panel
2
3Required properties:
4- compatible: should be "innolux,n156bge-l21"
5
6This binding is compatible with the simple-panel binding, which is specified
7in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt b/Documentation/devicetree/bindings/video/exynos_dsim.txt
index 33b5730d07ba..31036c667d54 100644
--- a/Documentation/devicetree/bindings/video/exynos_dsim.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt
@@ -1,7 +1,9 @@
1Exynos MIPI DSI Master 1Exynos MIPI DSI Master
2 2
3Required properties: 3Required properties:
4 - compatible: "samsung,exynos4210-mipi-dsi" 4 - compatible: value should be one of the following
5 "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
6 "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
5 - reg: physical base address and length of the registers set for the device 7 - reg: physical base address and length of the registers set for the device
6 - interrupts: should contain DSI interrupt 8 - interrupts: should contain DSI interrupt
7 - clocks: list of clock specifiers, must contain an entry for each required 9 - clocks: list of clock specifiers, must contain an entry for each required
diff --git a/Documentation/devicetree/bindings/video/exynos_mixer.txt b/Documentation/devicetree/bindings/video/exynos_mixer.txt
index 7bfde9c9d658..08b394b1edbf 100644
--- a/Documentation/devicetree/bindings/video/exynos_mixer.txt
+++ b/Documentation/devicetree/bindings/video/exynos_mixer.txt
@@ -4,8 +4,9 @@ Required properties:
4- compatible: value should be one of the following: 4- compatible: value should be one of the following:
5 1) "samsung,exynos5-mixer" <DEPRECATED> 5 1) "samsung,exynos5-mixer" <DEPRECATED>
6 2) "samsung,exynos4210-mixer" 6 2) "samsung,exynos4210-mixer"
7 3) "samsung,exynos5250-mixer" 7 3) "samsung,exynos4212-mixer"
8 4) "samsung,exynos5420-mixer" 8 4) "samsung,exynos5250-mixer"
9 5) "samsung,exynos5420-mixer"
9 10
10- reg: physical base address of the mixer and length of memory mapped 11- reg: physical base address of the mixer and length of memory mapped
11 region. 12 region.
diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt b/Documentation/devicetree/bindings/video/samsung-fimd.txt
index 2dad41b689af..8428fcff8037 100644
--- a/Documentation/devicetree/bindings/video/samsung-fimd.txt
+++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt
@@ -44,6 +44,34 @@ Optional Properties:
44- display-timings: timing settings for FIMD, as described in document [1]. 44- display-timings: timing settings for FIMD, as described in document [1].
45 Can be used in case timings cannot be provided otherwise 45 Can be used in case timings cannot be provided otherwise
46 or to override timings provided by the panel. 46 or to override timings provided by the panel.
47- samsung,sysreg: handle to syscon used to control the system registers
48- i80-if-timings: timing configuration for lcd i80 interface support.
49 - cs-setup: clock cycles for the active period of address signal is enabled
50 until chip select is enabled.
51 If not specified, the default value(0) will be used.
52 - wr-setup: clock cycles for the active period of CS signal is enabled until
53 write signal is enabled.
54 If not specified, the default value(0) will be used.
55 - wr-active: clock cycles for the active period of CS is enabled.
56 If not specified, the default value(1) will be used.
57 - wr-hold: clock cycles for the active period of CS is disabled until write
58 signal is disabled.
59 If not specified, the default value(0) will be used.
60
61 The parameters are defined as:
62
63 VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|??
64 : : : : :
65 Address Output --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX
66 | cs-setup+1 | : : :
67 |<---------->| : : :
68 Chip Select ???????????????|____________:____________:____________|??
69 | wr-setup+1 | | wr-hold+1 |
70 |<---------->| |<---------->|
71 Write Enable ????????????????????????????|____________|???????????????
72 | wr-active+1|
73 |<---------->|
74 Video Data ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>--
47 75
48The device node can contain 'port' child nodes according to the bindings defined 76The device node can contain 'port' child nodes according to the bindings defined
49in [2]. The following are properties specific to those nodes: 77in [2]. The following are properties specific to those nodes:
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 12:50:29 -0500