aboutsummaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree
diff options
context:
space:
mode:
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/arm/davinci.txt17
-rw-r--r--Documentation/devicetree/bindings/arm/exynos/power_domain.txt15
-rw-r--r--Documentation/devicetree/bindings/arm/fsl.txt4
-rw-r--r--Documentation/devicetree/bindings/ata/exynos-sata-phy.txt14
-rw-r--r--Documentation/devicetree/bindings/ata/exynos-sata.txt17
-rw-r--r--Documentation/devicetree/bindings/clock/imx25-clock.txt162
-rw-r--r--Documentation/devicetree/bindings/clock/zynq-7000.txt55
-rw-r--r--Documentation/devicetree/bindings/drm/exynos/hdmi.txt22
-rw-r--r--Documentation/devicetree/bindings/drm/exynos/hdmiddc.txt12
-rw-r--r--Documentation/devicetree/bindings/drm/exynos/hdmiphy.txt12
-rw-r--r--Documentation/devicetree/bindings/drm/exynos/mixer.txt15
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-poweroff.txt22
-rw-r--r--Documentation/devicetree/bindings/gpio/leds-ns2.txt26
-rw-r--r--Documentation/devicetree/bindings/input/touchscreen/bu21013.txt28
-rw-r--r--Documentation/devicetree/bindings/media/s5p-mfc.txt23
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt39
-rw-r--r--Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt119
-rw-r--r--Documentation/devicetree/bindings/usb/ehci-orion.txt15
-rw-r--r--Documentation/devicetree/bindings/vendor-prefixes.txt1
-rw-r--r--Documentation/devicetree/bindings/watchdog/atmel-wdt.txt15
20 files changed, 604 insertions, 29 deletions
diff --git a/Documentation/devicetree/bindings/arm/davinci.txt b/Documentation/devicetree/bindings/arm/davinci.txt
new file mode 100644
index 000000000000..cfaeda4274e6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/davinci.txt
@@ -0,0 +1,17 @@
1Texas Instruments DaVinci Platforms Device Tree Bindings
2--------------------------------------------------------
3
4DA850/OMAP-L138/AM18x Evaluation Module (EVM) board
5Required root node properties:
6 - compatible = "ti,da850-evm", "ti,da850";
7
8EnBW AM1808 based CMC board
9Required root node properties:
10 - compatible = "enbw,cmc", "ti,da850;
11
12Generic DaVinci Boards
13----------------------
14
15DA850/OMAP-L138/AM18x generic board
16Required root node properties:
17 - compatible = "ti,da850";
diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index 6528e215c5fe..5216b419016a 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -4,14 +4,13 @@ Exynos processors include support for multiple power domains which are used
4to gate power to one or more peripherals on the processor. 4to gate power to one or more peripherals on the processor.
5 5
6Required Properties: 6Required Properties:
7- compatiable: should be one of the following. 7- compatible: should be one of the following.
8 * samsung,exynos4210-pd - for exynos4210 type power domain. 8 * samsung,exynos4210-pd - for exynos4210 type power domain.
9- reg: physical base address of the controller and length of memory mapped 9- reg: physical base address of the controller and length of memory mapped
10 region. 10 region.
11 11
12Optional Properties: 12Node of a device using power domains must have a samsung,power-domain property
13- samsung,exynos4210-pd-off: Specifies that the power domain is in turned-off 13defined with a phandle to respective power domain.
14 state during boot and remains to be turned-off until explicitly turned-on.
15 14
16Example: 15Example:
17 16
@@ -19,3 +18,11 @@ Example:
19 compatible = "samsung,exynos4210-pd"; 18 compatible = "samsung,exynos4210-pd";
20 reg = <0x10023C00 0x10>; 19 reg = <0x10023C00 0x10>;
21 }; 20 };
21
22Example of the node using power domain:
23
24 node {
25 /* ... */
26 samsung,power-domain = <&lcd0>;
27 /* ... */
28 };
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index ac9e7516756e..f79818711e83 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -41,6 +41,10 @@ i.MX6 Quad SABRE Smart Device Board
41Required root node properties: 41Required root node properties:
42 - compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; 42 - compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
43 43
44i.MX6 Quad SABRE Automotive Board
45Required root node properties:
46 - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
47
44Generic i.MX boards 48Generic i.MX boards
45------------------- 49-------------------
46 50
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
new file mode 100644
index 000000000000..37824fac688e
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
@@ -0,0 +1,14 @@
1* Samsung SATA PHY Controller
2
3SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
4Each SATA PHY controller should have its own node.
5
6Required properties:
7- compatible : compatible list, contains "samsung,exynos5-sata-phy"
8- reg : <registers mapping>
9
10Example:
11 sata@ffe07000 {
12 compatible = "samsung,exynos5-sata-phy";
13 reg = <0xffe07000 0x1000>;
14 };
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata.txt b/Documentation/devicetree/bindings/ata/exynos-sata.txt
new file mode 100644
index 000000000000..0849f1025e34
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/exynos-sata.txt
@@ -0,0 +1,17 @@
1* Samsung AHCI SATA Controller
2
3SATA nodes are defined to describe on-chip Serial ATA controllers.
4Each SATA controller should have its own node.
5
6Required properties:
7- compatible : compatible list, contains "samsung,exynos5-sata"
8- interrupts : <interrupt mapping for SATA IRQ>
9- reg : <registers mapping>
10- samsung,sata-freq : <frequency in MHz>
11
12Example:
13 sata@ffe08000 {
14 compatible = "samsung,exynos5-sata";
15 reg = <0xffe08000 0x1000>;
16 interrupts = <115>;
17 };
diff --git a/Documentation/devicetree/bindings/clock/imx25-clock.txt b/Documentation/devicetree/bindings/clock/imx25-clock.txt
new file mode 100644
index 000000000000..c2a3525ecb4e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx25-clock.txt
@@ -0,0 +1,162 @@
1* Clock bindings for Freescale i.MX25
2
3Required properties:
4- compatible: Should be "fsl,imx25-ccm"
5- reg: Address and length of the register set
6- interrupts: Should contain CCM interrupt
7- #clock-cells: Should be <1>
8
9The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell. The following is a full list of i.MX25
11clocks and IDs.
12
13 Clock ID
14 ---------------------------
15 dummy 0
16 osc 1
17 mpll 2
18 upll 3
19 mpll_cpu_3_4 4
20 cpu_sel 5
21 cpu 6
22 ahb 7
23 usb_div 8
24 ipg 9
25 per0_sel 10
26 per1_sel 11
27 per2_sel 12
28 per3_sel 13
29 per4_sel 14
30 per5_sel 15
31 per6_sel 16
32 per7_sel 17
33 per8_sel 18
34 per9_sel 19
35 per10_sel 20
36 per11_sel 21
37 per12_sel 22
38 per13_sel 23
39 per14_sel 24
40 per15_sel 25
41 per0 26
42 per1 27
43 per2 28
44 per3 29
45 per4 30
46 per5 31
47 per6 32
48 per7 33
49 per8 34
50 per9 35
51 per10 36
52 per11 37
53 per12 38
54 per13 39
55 per14 40
56 per15 41
57 csi_ipg_per 42
58 epit_ipg_per 43
59 esai_ipg_per 44
60 esdhc1_ipg_per 45
61 esdhc2_ipg_per 46
62 gpt_ipg_per 47
63 i2c_ipg_per 48
64 lcdc_ipg_per 49
65 nfc_ipg_per 50
66 owire_ipg_per 51
67 pwm_ipg_per 52
68 sim1_ipg_per 53
69 sim2_ipg_per 54
70 ssi1_ipg_per 55
71 ssi2_ipg_per 56
72 uart_ipg_per 57
73 ata_ahb 58
74 reserved 59
75 csi_ahb 60
76 emi_ahb 61
77 esai_ahb 62
78 esdhc1_ahb 63
79 esdhc2_ahb 64
80 fec_ahb 65
81 lcdc_ahb 66
82 rtic_ahb 67
83 sdma_ahb 68
84 slcdc_ahb 69
85 usbotg_ahb 70
86 reserved 71
87 reserved 72
88 reserved 73
89 reserved 74
90 can1_ipg 75
91 can2_ipg 76
92 csi_ipg 77
93 cspi1_ipg 78
94 cspi2_ipg 79
95 cspi3_ipg 80
96 dryice_ipg 81
97 ect_ipg 82
98 epit1_ipg 83
99 epit2_ipg 84
100 reserved 85
101 esdhc1_ipg 86
102 esdhc2_ipg 87
103 fec_ipg 88
104 reserved 89
105 reserved 90
106 reserved 91
107 gpt1_ipg 92
108 gpt2_ipg 93
109 gpt3_ipg 94
110 gpt4_ipg 95
111 reserved 96
112 reserved 97
113 reserved 98
114 iim_ipg 99
115 reserved 100
116 reserved 101
117 kpp_ipg 102
118 lcdc_ipg 103
119 reserved 104
120 pwm1_ipg 105
121 pwm2_ipg 106
122 pwm3_ipg 107
123 pwm4_ipg 108
124 rngb_ipg 109
125 reserved 110
126 scc_ipg 111
127 sdma_ipg 112
128 sim1_ipg 113
129 sim2_ipg 114
130 slcdc_ipg 115
131 spba_ipg 116
132 ssi1_ipg 117
133 ssi2_ipg 118
134 tsc_ipg 119
135 uart1_ipg 120
136 uart2_ipg 121
137 uart3_ipg 122
138 uart4_ipg 123
139 uart5_ipg 124
140 reserved 125
141 wdt_ipg 126
142
143Examples:
144
145clks: ccm@53f80000 {
146 compatible = "fsl,imx25-ccm";
147 reg = <0x53f80000 0x4000>;
148 interrupts = <31>;
149 clock-output-names = ...
150 "uart_ipg",
151 "uart_serial",
152 ...;
153};
154
155uart1: serial@43f90000 {
156 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
157 reg = <0x43f90000 0x4000>;
158 interrupts = <45>;
159 clocks = <&clks 79>, <&clks 50>;
160 clock-names = "ipg", "per";
161 status = "disabled";
162};
diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt
new file mode 100644
index 000000000000..23ae1db1bc13
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/zynq-7000.txt
@@ -0,0 +1,55 @@
1Device Tree Clock bindings for the Zynq 7000 EPP
2
3The Zynq EPP has several different clk providers, each with there own bindings.
4The purpose of this document is to document their usage.
5
6See clock_bindings.txt for more information on the generic clock bindings.
7See Chapter 25 of Zynq TRM for more information about Zynq clocks.
8
9== PLLs ==
10
11Used to describe the ARM_PLL, DDR_PLL, and IO_PLL.
12
13Required properties:
14- #clock-cells : shall be 0 (only one clock is output from this node)
15- compatible : "xlnx,zynq-pll"
16- reg : pair of u32 values, which are the address offsets within the SLCR
17 of the relevant PLL_CTRL register and PLL_CFG register respectively
18- clocks : phandle for parent clock. should be the phandle for ps_clk
19
20Optional properties:
21- clock-output-names : name of the output clock
22
23Example:
24 armpll: armpll {
25 #clock-cells = <0>;
26 compatible = "xlnx,zynq-pll";
27 clocks = <&ps_clk>;
28 reg = <0x100 0x110>;
29 clock-output-names = "armpll";
30 };
31
32== Peripheral clocks ==
33
34Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks.
35
36Required properties:
37- #clock-cells : shall be 1
38- compatible : "xlnx,zynq-periph-clock"
39- reg : a single u32 value, describing the offset within the SLCR where
40 the CLK_CTRL register is found for this peripheral
41- clocks : phandle for parent clocks. should hold phandles for
42 the IO_PLL, ARM_PLL, and DDR_PLL in order
43- clock-output-names : names of the output clock(s). For peripherals that have
44 two output clocks (for example, the UART), two clocks
45 should be listed.
46
47Example:
48 uart_clk: uart_clk {
49 #clock-cells = <1>;
50 compatible = "xlnx,zynq-periph-clock";
51 clocks = <&iopll &armpll &ddrpll>;
52 reg = <0x154>;
53 clock-output-names = "uart0_ref_clk",
54 "uart1_ref_clk";
55 };
diff --git a/Documentation/devicetree/bindings/drm/exynos/hdmi.txt b/Documentation/devicetree/bindings/drm/exynos/hdmi.txt
new file mode 100644
index 000000000000..589edee37394
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/exynos/hdmi.txt
@@ -0,0 +1,22 @@
1Device-Tree bindings for drm hdmi driver
2
3Required properties:
4- compatible: value should be "samsung,exynos5-hdmi".
5- reg: physical base address of the hdmi and length of memory mapped
6 region.
7- interrupts: interrupt number to the cpu.
8- hpd-gpio: following information about the hotplug gpio pin.
9 a) phandle of the gpio controller node.
10 b) pin number within the gpio controller.
11 c) pin function mode.
12 d) optional flags and pull up/down.
13 e) drive strength.
14
15Example:
16
17 hdmi {
18 compatible = "samsung,exynos5-hdmi";
19 reg = <0x14530000 0x100000>;
20 interrupts = <0 95 0>;
21 hpd-gpio = <&gpx3 7 0xf 1 3>;
22 };
diff --git a/Documentation/devicetree/bindings/drm/exynos/hdmiddc.txt b/Documentation/devicetree/bindings/drm/exynos/hdmiddc.txt
new file mode 100644
index 000000000000..fa166d945809
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/exynos/hdmiddc.txt
@@ -0,0 +1,12 @@
1Device-Tree bindings for hdmiddc driver
2
3Required properties:
4- compatible: value should be "samsung,exynos5-hdmiddc".
5- reg: I2C address of the hdmiddc device.
6
7Example:
8
9 hdmiddc {
10 compatible = "samsung,exynos5-hdmiddc";
11 reg = <0x50>;
12 };
diff --git a/Documentation/devicetree/bindings/drm/exynos/hdmiphy.txt b/Documentation/devicetree/bindings/drm/exynos/hdmiphy.txt
new file mode 100644
index 000000000000..858f4f9b902f
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/exynos/hdmiphy.txt
@@ -0,0 +1,12 @@
1Device-Tree bindings for hdmiphy driver
2
3Required properties:
4- compatible: value should be "samsung,exynos5-hdmiphy".
5- reg: I2C address of the hdmiphy device.
6
7Example:
8
9 hdmiphy {
10 compatible = "samsung,exynos5-hdmiphy";
11 reg = <0x38>;
12 };
diff --git a/Documentation/devicetree/bindings/drm/exynos/mixer.txt b/Documentation/devicetree/bindings/drm/exynos/mixer.txt
new file mode 100644
index 000000000000..9b2ea0343566
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/exynos/mixer.txt
@@ -0,0 +1,15 @@
1Device-Tree bindings for mixer driver
2
3Required properties:
4- compatible: value should be "samsung,exynos5-mixer".
5- reg: physical base address of the mixer and length of memory mapped
6 region.
7- interrupts: interrupt number to the cpu.
8
9Example:
10
11 mixer {
12 compatible = "samsung,exynos5-mixer";
13 reg = <0x14450000 0x10000>;
14 interrupts = <0 94 0>;
15 };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-poweroff.txt b/Documentation/devicetree/bindings/gpio/gpio-poweroff.txt
new file mode 100644
index 000000000000..558cdf3c9abc
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-poweroff.txt
@@ -0,0 +1,22 @@
1GPIO line that should be set high/low to power off a device
2
3Required properties:
4- compatible : should be "gpio-poweroff".
5- gpios : The GPIO to set high/low, see "gpios property" in
6 Documentation/devicetree/bindings/gpio/gpio.txt. If the pin should be
7 low to power down the board set it to "Active Low", otherwise set
8 gpio to "Active High".
9
10Optional properties:
11- input : Initially configure the GPIO line as an input. Only reconfigure
12 it to an output when the pm_power_off function is called. If this optional
13 property is not specified, the GPIO is initialized as an output in its
14 inactive state.
15
16
17Examples:
18
19gpio-poweroff {
20 compatible = "gpio-poweroff";
21 gpios = <&gpio 4 0>; /* GPIO 4 Active Low */
22};
diff --git a/Documentation/devicetree/bindings/gpio/leds-ns2.txt b/Documentation/devicetree/bindings/gpio/leds-ns2.txt
new file mode 100644
index 000000000000..aef3aca34d2d
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/leds-ns2.txt
@@ -0,0 +1,26 @@
1Binding for dual-GPIO LED found on Network Space v2 (and parents).
2
3Required properties:
4- compatible: "lacie,ns2-leds".
5
6Each LED is represented as a sub-node of the ns2-leds device.
7
8Required sub-node properties:
9- cmd-gpio: Command LED GPIO. See OF device-tree GPIO specification.
10- slow-gpio: Slow LED GPIO. See OF device-tree GPIO specification.
11
12Optional sub-node properties:
13- label: Name for this LED. If omitted, the label is taken from the node name.
14- linux,default-trigger: Trigger assigned to the LED.
15
16Example:
17
18ns2-leds {
19 compatible = "lacie,ns2-leds";
20
21 blue-sata {
22 label = "ns2:blue:sata";
23 slow-gpio = <&gpio0 29 0>;
24 cmd-gpio = <&gpio0 30 0>;
25 };
26};
diff --git a/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt b/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt
new file mode 100644
index 000000000000..ca5a2c86480c
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt
@@ -0,0 +1,28 @@
1* Rohm BU21013 Touch Screen
2
3Required properties:
4 - compatible : "rohm,bu21013_tp"
5 - reg : I2C device address
6
7Optional properties:
8 - touch-gpio : GPIO pin registering a touch event
9 - <supply_name>-supply : Phandle to a regulator supply
10 - rohm,touch-max-x : Maximum outward permitted limit in the X axis
11 - rohm,touch-max-y : Maximum outward permitted limit in the Y axis
12 - rohm,flip-x : Flip touch coordinates on the X axis
13 - rohm,flip-y : Flip touch coordinates on the Y axis
14
15Example:
16
17 i2c@80110000 {
18 bu21013_tp@0x5c {
19 compatible = "rohm,bu21013_tp";
20 reg = <0x5c>;
21 touch-gpio = <&gpio2 20 0x4>;
22 avdd-supply = <&ab8500_ldo_aux1_reg>;
23
24 rohm,touch-max-x = <384>;
25 rohm,touch-max-y = <704>;
26 rohm,flip-y;
27 };
28 };
diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt
new file mode 100644
index 000000000000..67ec3d4ccc7f
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -0,0 +1,23 @@
1* Samsung Multi Format Codec (MFC)
2
3Multi Format Codec (MFC) is the IP present in Samsung SoCs which
4supports high resolution decoding and encoding functionalities.
5The MFC device driver is a v4l2 driver which can encode/decode
6video raw/elementary streams and has support for all popular
7video codecs.
8
9Required properties:
10 - compatible : value should be either one among the following
11 (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
12 (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
13
14 - reg : Physical base address of the IP registers and length of memory
15 mapped region.
16
17 - interrupts : MFC interrupt number to the CPU.
18
19 - samsung,mfc-r : Base address of the first memory bank used by MFC
20 for DMA contiguous memory allocation and its size.
21
22 - samsung,mfc-l : Base address of the second memory bank used by MFC
23 for DMA contiguous memory allocation and its size.
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
index 361bccb7ec89..95daf6335c37 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
@@ -7,8 +7,10 @@ Required properties:
7- compatible: "marvell,88f6180-pinctrl", 7- compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl", 8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl" 9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
10 "marvell,98dx4122-pinctrl"
10 11
11This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x. 12This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
13It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
12 14
13Available mpp pins/groups and functions: 15Available mpp pins/groups and functions:
14Note: brackets (x) are not part of the mpp name for marvell,function and given 16Note: brackets (x) are not part of the mpp name for marvell,function and given
@@ -277,3 +279,40 @@ mpp46 46 gpio, ts(mp10), tdm(fs), lcd(hsync)
277mpp47 47 gpio, ts(mp11), tdm(drx), lcd(vsync) 279mpp47 47 gpio, ts(mp11), tdm(drx), lcd(vsync)
278mpp48 48 gpio, ts(mp12), tdm(dtx), lcd(d16) 280mpp48 48 gpio, ts(mp12), tdm(dtx), lcd(d16)
279mpp49 49 gpo, tdm(rx0ql), pex(clkreq), lcd(d17) 281mpp49 49 gpo, tdm(rx0ql), pex(clkreq), lcd(d17)
282
283* Marvell Bobcat 98dx4122
284
285name pins functions
286================================================================================
287mpp0 0 gpio, nand(io2), spi(cs)
288mpp1 1 gpo, nand(io3), spi(mosi)
289mpp2 2 gpo, nand(io4), spi(sck)
290mpp3 3 gpo, nand(io5), spi(miso)
291mpp4 4 gpio, nand(io6), uart0(rxd)
292mpp5 5 gpo, nand(io7), uart0(txd)
293mpp6 6 sysrst(out), spi(mosi)
294mpp7 7 gpo, pex(rsto), spi(cs)
295mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts)
296mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts)
297mpp10 10 gpo, spi(sck), uart0(txd)
298mpp11 11 gpio, spi(miso), uart0(rxd)
299mpp13 13 gpio, uart1(txd)
300mpp14 14 gpio, uart1(rxd)
301mpp15 15 gpio, uart0(rts)
302mpp16 16 gpio, uart0(cts)
303mpp18 18 gpo, nand(io0)
304mpp19 19 gpo, nand(io1)
305mpp34 34 gpio
306mpp35 35 gpio
307mpp36 36 gpio
308mpp37 37 gpio
309mpp38 38 gpio
310mpp39 39 gpio
311mpp40 40 gpio
312mpp41 41 gpio
313mpp42 42 gpio
314mpp43 43 gpio
315mpp44 44 gpio
316mpp45 45 gpio
317mpp49 49 gpio
318
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index 03dee50532f5..e97a27856b21 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -8,13 +8,20 @@ on-chip controllers onto these pads.
8Required Properties: 8Required Properties:
9- compatible: should be one of the following. 9- compatible: should be one of the following.
10 - "samsung,pinctrl-exynos4210": for Exynos4210 compatible pin-controller. 10 - "samsung,pinctrl-exynos4210": for Exynos4210 compatible pin-controller.
11 - "samsung,pinctrl-exynos4x12": for Exynos4x12 compatible pin-controller.
11 - "samsung,pinctrl-exynos5250": for Exynos5250 compatible pin-controller. 12 - "samsung,pinctrl-exynos5250": for Exynos5250 compatible pin-controller.
12 13
13- reg: Base address of the pin controller hardware module and length of 14- reg: Base address of the pin controller hardware module and length of
14 the address space it occupies. 15 the address space it occupies.
15 16
16- interrupts: interrupt specifier for the controller. The format and value of 17- Pin banks as child nodes: Pin banks of the controller are represented by child
17 the interrupt specifier depends on the interrupt parent for the controller. 18 nodes of the controller node. Bank name is taken from name of the node. Each
19 bank node must contain following properties:
20
21 - gpio-controller: identifies the node as a gpio controller and pin bank.
22 - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
23 binding is used, the amount of cells must be specified as 2. See generic
24 GPIO binding documentation for description of particular cells.
18 25
19- Pin mux/config groups as child nodes: The pin mux (selecting pin function 26- Pin mux/config groups as child nodes: The pin mux (selecting pin function
20 mode) and pin config (pull up/down, driver strength) settings are represented 27 mode) and pin config (pull up/down, driver strength) settings are represented
@@ -72,16 +79,24 @@ used as system wakeup events.
72A. External GPIO Interrupts: For supporting external gpio interrupts, the 79A. External GPIO Interrupts: For supporting external gpio interrupts, the
73 following properties should be specified in the pin-controller device node. 80 following properties should be specified in the pin-controller device node.
74 81
75- interrupt-controller: identifies the controller node as interrupt-parent. 82 - interrupt-parent: phandle of the interrupt parent to which the external
76- #interrupt-cells: the value of this property should be 2. 83 GPIO interrupts are forwarded to.
77 - First Cell: represents the external gpio interrupt number local to the 84 - interrupts: interrupt specifier for the controller. The format and value of
78 external gpio interrupt space of the controller. 85 the interrupt specifier depends on the interrupt parent for the controller.
79 - Second Cell: flags to identify the type of the interrupt 86
80 - 1 = rising edge triggered 87 In addition, following properties must be present in node of every bank
81 - 2 = falling edge triggered 88 of pins supporting GPIO interrupts:
82 - 3 = rising and falling edge triggered 89
83 - 4 = high level triggered 90 - interrupt-controller: identifies the controller node as interrupt-parent.
84 - 8 = low level triggered 91 - #interrupt-cells: the value of this property should be 2.
92 - First Cell: represents the external gpio interrupt number local to the
93 external gpio interrupt space of the controller.
94 - Second Cell: flags to identify the type of the interrupt
95 - 1 = rising edge triggered
96 - 2 = falling edge triggered
97 - 3 = rising and falling edge triggered
98 - 4 = high level triggered
99 - 8 = low level triggered
85 100
86B. External Wakeup Interrupts: For supporting external wakeup interrupts, a 101B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
87 child node representing the external wakeup interrupt controller should be 102 child node representing the external wakeup interrupt controller should be
@@ -94,6 +109,11 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
94 found on Samsung Exynos4210 SoC. 109 found on Samsung Exynos4210 SoC.
95 - interrupt-parent: phandle of the interrupt parent to which the external 110 - interrupt-parent: phandle of the interrupt parent to which the external
96 wakeup interrupts are forwarded to. 111 wakeup interrupts are forwarded to.
112 - interrupts: interrupt used by multiplexed wakeup interrupts.
113
114 In addition, following properties must be present in node of every bank
115 of pins supporting wake-up interrupts:
116
97 - interrupt-controller: identifies the node as interrupt-parent. 117 - interrupt-controller: identifies the node as interrupt-parent.
98 - #interrupt-cells: the value of this property should be 2 118 - #interrupt-cells: the value of this property should be 2
99 - First Cell: represents the external wakeup interrupt number local to 119 - First Cell: represents the external wakeup interrupt number local to
@@ -105,11 +125,63 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
105 - 4 = high level triggered 125 - 4 = high level triggered
106 - 8 = low level triggered 126 - 8 = low level triggered
107 127
128 Node of every bank of pins supporting direct wake-up interrupts (without
129 multiplexing) must contain following properties:
130
131 - interrupt-parent: phandle of the interrupt parent to which the external
132 wakeup interrupts are forwarded to.
133 - interrupts: interrupts of the interrupt parent which are used for external
134 wakeup interrupts from pins of the bank, must contain interrupts for all
135 pins of the bank.
136
108Aliases: 137Aliases:
109 138
110All the pin controller nodes should be represented in the aliases node using 139All the pin controller nodes should be represented in the aliases node using
111the following format 'pinctrl{n}' where n is a unique number for the alias. 140the following format 'pinctrl{n}' where n is a unique number for the alias.
112 141
142Example: A pin-controller node with pin banks:
143
144 pinctrl_0: pinctrl@11400000 {
145 compatible = "samsung,pinctrl-exynos4210";
146 reg = <0x11400000 0x1000>;
147 interrupts = <0 47 0>;
148
149 /* ... */
150
151 /* Pin bank without external interrupts */
152 gpy0: gpy0 {
153 gpio-controller;
154 #gpio-cells = <2>;
155 };
156
157 /* ... */
158
159 /* Pin bank with external GPIO or muxed wake-up interrupts */
160 gpj0: gpj0 {
161 gpio-controller;
162 #gpio-cells = <2>;
163
164 interrupt-controller;
165 #interrupt-cells = <2>;
166 };
167
168 /* ... */
169
170 /* Pin bank with external direct wake-up interrupts */
171 gpx0: gpx0 {
172 gpio-controller;
173 #gpio-cells = <2>;
174
175 interrupt-controller;
176 interrupt-parent = <&gic>;
177 interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
178 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
179 #interrupt-cells = <2>;
180 };
181
182 /* ... */
183 };
184
113Example 1: A pin-controller node with pin groups. 185Example 1: A pin-controller node with pin groups.
114 186
115 pinctrl_0: pinctrl@11400000 { 187 pinctrl_0: pinctrl@11400000 {
@@ -117,6 +189,8 @@ Example 1: A pin-controller node with pin groups.
117 reg = <0x11400000 0x1000>; 189 reg = <0x11400000 0x1000>;
118 interrupts = <0 47 0>; 190 interrupts = <0 47 0>;
119 191
192 /* ... */
193
120 uart0_data: uart0-data { 194 uart0_data: uart0-data {
121 samsung,pins = "gpa0-0", "gpa0-1"; 195 samsung,pins = "gpa0-0", "gpa0-1";
122 samsung,pin-function = <2>; 196 samsung,pin-function = <2>;
@@ -158,20 +232,14 @@ Example 2: A pin-controller node with external wakeup interrupt controller node.
158 pinctrl_1: pinctrl@11000000 { 232 pinctrl_1: pinctrl@11000000 {
159 compatible = "samsung,pinctrl-exynos4210"; 233 compatible = "samsung,pinctrl-exynos4210";
160 reg = <0x11000000 0x1000>; 234 reg = <0x11000000 0x1000>;
161 interrupts = <0 46 0>; 235 interrupts = <0 46 0>
162 interrupt-controller;
163 #interrupt-cells = <2>;
164 236
165 wakup_eint: wakeup-interrupt-controller { 237 /* ... */
238
239 wakeup-interrupt-controller {
166 compatible = "samsung,exynos4210-wakeup-eint"; 240 compatible = "samsung,exynos4210-wakeup-eint";
167 interrupt-parent = <&gic>; 241 interrupt-parent = <&gic>;
168 interrupt-controller; 242 interrupts = <0 32 0>;
169 #interrupt-cells = <2>;
170 interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
171 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
172 <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
173 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
174 <0 32 0>;
175 }; 243 };
176 }; 244 };
177 245
@@ -190,7 +258,8 @@ Example 4: Set up the default pin state for uart controller.
190 258
191 static int s3c24xx_serial_probe(struct platform_device *pdev) { 259 static int s3c24xx_serial_probe(struct platform_device *pdev) {
192 struct pinctrl *pinctrl; 260 struct pinctrl *pinctrl;
193 ... 261
194 ... 262 /* ... */
263
195 pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 264 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
196 } 265 }
diff --git a/Documentation/devicetree/bindings/usb/ehci-orion.txt b/Documentation/devicetree/bindings/usb/ehci-orion.txt
new file mode 100644
index 000000000000..6bc09ec14c4d
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/ehci-orion.txt
@@ -0,0 +1,15 @@
1* EHCI controller, Orion Marvell variants
2
3Required properties:
4- compatible: must be "marvell,orion-ehci"
5- reg: physical base address of the controller and length of memory mapped
6 region.
7- interrupts: The EHCI interrupt
8
9Example:
10
11 ehci@50000 {
12 compatible = "marvell,orion-ehci";
13 reg = <0x50000 0x1000>;
14 interrupts = <19>;
15 };
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 9de2b9ff9d6e..ac2c2c416a14 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -51,4 +51,5 @@ ti Texas Instruments
51via VIA Technologies, Inc. 51via VIA Technologies, Inc.
52wlf Wolfson Microelectronics 52wlf Wolfson Microelectronics
53wm Wondermedia Technologies, Inc. 53wm Wondermedia Technologies, Inc.
54winbond Winbond Electronics corp.
54xlnx Xilinx 55xlnx Xilinx
diff --git a/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt b/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
new file mode 100644
index 000000000000..2957ebb5aa71
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
@@ -0,0 +1,15 @@
1* Atmel Watchdog Timers
2
3** at91sam9-wdt
4
5Required properties:
6- compatible: must be "atmel,at91sam9260-wdt".
7- reg: physical base address of the controller and length of memory mapped
8 region.
9
10Example:
11
12 watchdog@fffffd40 {
13 compatible = "atmel,at91sam9260-wdt";
14 reg = <0xfffffd40 0x10>;
15 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-12 14:43:19 -0400