diff options
Diffstat (limited to 'Documentation/devicetree/bindings')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/l2cc.txt | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt index cbef09b5c8a7..69ddf9fad2dc 100644 --- a/Documentation/devicetree/bindings/arm/l2cc.txt +++ b/Documentation/devicetree/bindings/arm/l2cc.txt | |||
| @@ -16,6 +16,9 @@ Required properties: | |||
| 16 | performs the same operation). | 16 | performs the same operation). |
| 17 | "marvell,"aurora-outer-cache: Marvell Controller designed to be | 17 | "marvell,"aurora-outer-cache: Marvell Controller designed to be |
| 18 | compatible with the ARM one with outer cache mode. | 18 | compatible with the ARM one with outer cache mode. |
| 19 | "bcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an | ||
| 20 | offset needs to be added to the address before passing down to the L2 | ||
| 21 | cache controller | ||
| 19 | - cache-unified : Specifies the cache is a unified cache. | 22 | - cache-unified : Specifies the cache is a unified cache. |
| 20 | - cache-level : Should be set to 2 for a level 2 cache. | 23 | - cache-level : Should be set to 2 for a level 2 cache. |
| 21 | - reg : Physical base address and size of cache controller's memory mapped | 24 | - reg : Physical base address and size of cache controller's memory mapped |