3 files changed, 86 insertions, 2 deletions

diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index 34dc40cffdfd..af9b4a0d902b 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -91,7 +91,7 @@ Boards:
   compatible = "ti,omap3-beagle", "ti,omap3"
 
 - OMAP3 Tobi with Overo : Commercial expansion board with daughter board
-  compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3"
+  compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3"
 
 - OMAP4 SDP : Software Development Board
   compatible = "ti,omap4-sdp", "ti,omap4430"
diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt
index 0fd76c405208..6630d842c7a3 100644
--- a/Documentation/devicetree/bindings/bus/imx-weim.txt
+++ b/Documentation/devicetree/bindings/bus/imx-weim.txt
@@ -8,7 +8,12 @@ The actual devices are instantiated from the child nodes of a WEIM node.
 
 Required properties:
 
- - compatible:          Should be set to "fsl,<soc>-weim"
+ - compatible:          Should contain one of the following:
+                          "fsl,imx1-weim"
+                          "fsl,imx27-weim"
+                          "fsl,imx51-weim"
+                          "fsl,imx50-weim"
+                          "fsl,imx6q-weim"
  - reg:                 A resource specifier for the register space
                         (see the example below)
  - clocks:              the clock, see the example below.
@@ -19,6 +24,26 @@ Required properties:
 
                            <cs-number> 0 <physical address of mapping> <size>
 
+Optional properties:
+
+ - fsl,weim-cs-gpr:     For "fsl,imx50-weim" and "fsl,imx6q-weim" type of
+                        devices, it should be the phandle to the system General
+                        Purpose Register controller that contains WEIM CS GPR
+                        register, e.g. IOMUXC_GPR1 on i.MX6Q.  IOMUXC_GPR1[11:0]
+                        should be set up as one of the following 4 possible
+                        values depending on the CS space configuration.
+
+                        IOMUXC_GPR1[11:0]    CS0    CS1    CS2    CS3
+                        ---------------------------------------------
+                                05          128M     0M     0M     0M
+                                033          64M    64M     0M     0M
+                                0113         64M    32M    32M     0M
+                                01111        32M    32M    32M    32M
+
+                        In case that the property is absent, the reset value or
+                        what bootloader sets up in IOMUXC_GPR1[11:0] will be
+                        used.
+
 Timing property for child nodes. It is mandatory, not optional.
 
  - fsl,weim-cs-timing:  The timing array, contains timing values for the
@@ -43,6 +68,7 @@ Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
                 #address-cells = <2>;
                 #size-cells = <1>;
                 ranges = <0 0 0x08000000 0x08000000>;
+                fsl,weim-cs-gpr = <&gpr>;
 
                 nor@0,0 {
                         compatible = "cfi-flash";
diff --git a/Documentation/devicetree/bindings/net/sti-dwmac.txt b/Documentation/devicetree/bindings/net/sti-dwmac.txt
new file mode 100644
index 000000000000..3dd3d0bf112f
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/sti-dwmac.txt
@@ -0,0 +1,58 @@
+STMicroelectronics SoC DWMAC glue layer controller
+
+The device node has following properties.
+
+Required properties:
+ - compatible   : Can be "st,stih415-dwmac", "st,stih416-dwmac" or
+   "st,stid127-dwmac".
+ - reg          : Offset of the glue configuration register map in system
+   configuration regmap pointed by st,syscon property and size.
+
+ - reg-names    : Should be "sti-ethconf".
+
+ - st,syscon    : Should be phandle to system configuration node which
+   encompases this glue registers.
+
+ - st,tx-retime-src: On STi Parts for Giga bit speeds, 125Mhz clocks can be
+   wired up in from different sources. One via TXCLK pin and other via CLK_125
+   pin. This wiring is totally board dependent. However the retiming glue
+   logic should be configured accordingly. Possible values for this property
+
+           "txclk" - if 125Mhz clock is wired up via txclk line.
+           "clk_125" - if 125Mhz clock is wired up via clk_125 line.
+
+   This property is only valid for Giga bit setup( GMII, RGMII), and it is
+   un-used for non-giga bit (MII and RMII) setups. Also note that internal
+   clockgen can not generate stable 125Mhz clock.
+
+ - st,ext-phyclk: This boolean property indicates who is generating the clock
+  for tx and rx. This property is only valid for RMII case where the clock can
+  be generated from the MAC or PHY.
+
+ - clock-names: should be "sti-ethclk".
+ - clocks: Should point to ethernet clockgen which can generate phyclk.
+
+
+Example:
+
+ethernet0: dwmac@fe810000 {
+        device_type     = "network";
+        compatible      = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
+        reg             = <0xfe810000 0x8000>, <0x8bc 0x4>;
+        reg-names       = "stmmaceth", "sti-ethconf";
+        interrupts      = <0 133 0>, <0 134 0>, <0 135 0>;
+        interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+        phy-mode        = "mii";
+
+        st,syscon       = <&syscfg_rear>;
+
+        snps,pbl        = <32>;
+        snps,mixed-burst;
+
+        resets          = <&softreset STIH416_ETH0_SOFTRESET>;
+        reset-names     = "stmmaceth";
+        pinctrl-0       = <&pinctrl_mii0>;
+        pinctrl-names   = "default";
+        clocks          = <&CLK_S_GMAC0_PHY>;
+        clock-names     = "stmmaceth";
+};