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-rw-r--r--Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt3
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
index 906109d4c593..b5082a1cf461 100644
--- a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
@@ -10,6 +10,8 @@ Required properties:
10- reg : Specifies base physical address and size of the registers. 10- reg : Specifies base physical address and size of the registers.
11- interrupts : A list of 6 interrupts; one per each of timer channels 1 11- interrupts : A list of 6 interrupts; one per each of timer channels 1
12 through 5, and one for the shared interrupt for the remaining channels. 12 through 5, and one for the shared interrupt for the remaining channels.
13- clocks : Must contain one entry, for the module clock.
14 See ../clocks/clock-bindings.txt for details.
13 15
14timer { 16timer {
15 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; 17 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
@@ -20,4 +22,5 @@ timer {
20 0 42 0x04 22 0 42 0x04
21 0 121 0x04 23 0 121 0x04
22 0 122 0x04>; 24 0 122 0x04>;
25 clocks = <&tegra_car 214>;
23}; 26};