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-rw-r--r--Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt9
1 files changed, 9 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
index c3fc57af8772..c7ea9d4a988b 100644
--- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
@@ -7,6 +7,12 @@ Required properties:
7- reg: physical base address and length of the controller's registers 7- reg: physical base address and length of the controller's registers
8- #pwm-cells: should be 2. See pwm.txt in this directory for a description of 8- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
9 the cells format. 9 the cells format.
10- clocks: Must contain one entry, for the module clock.
11 See ../clocks/clock-bindings.txt for details.
12- resets: Must contain an entry for each entry in reset-names.
13 See ../reset/reset.txt for details.
14- reset-names: Must include the following entries:
15 - pwm
10 16
11Example: 17Example:
12 18
@@ -14,4 +20,7 @@ Example:
14 compatible = "nvidia,tegra20-pwm"; 20 compatible = "nvidia,tegra20-pwm";
15 reg = <0x7000a000 0x100>; 21 reg = <0x7000a000 0x100>;
16 #pwm-cells = <2>; 22 #pwm-cells = <2>;
23 clocks = <&tegra_car 17>;
24 resets = <&tegra_car 17>;
25 reset-names = "pwm";
17 }; 26 };