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-rw-r--r--Documentation/devicetree/bindings/powerpc/4xx/cpm.txt52
-rw-r--r--Documentation/devicetree/bindings/powerpc/4xx/emac.txt148
-rw-r--r--Documentation/devicetree/bindings/powerpc/4xx/ndfc.txt39
-rw-r--r--Documentation/devicetree/bindings/powerpc/4xx/ppc440spe-adma.txt93
-rw-r--r--Documentation/devicetree/bindings/powerpc/4xx/reboot.txt18
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/board.txt63
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm.txt67
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/brg.txt21
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/i2c.txt41
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/pic.txt18
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/usb.txt15
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/gpio.txt38
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt45
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt115
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/firmware.txt24
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/par_io.txt51
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/pincfg.txt60
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/ucc.txt70
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/usb.txt37
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/serial.txt32
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/diu.txt34
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/dma.txt144
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/ecm.txt64
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/gtm.txt31
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/guts.txt25
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/lbc.txt35
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/mcm.txt64
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/mcu-mpc8349emitx.txt17
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/mpc5121-psc.txt70
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/mpc5200.txt198
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/mpic.txt42
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt36
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/pmc.txt63
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/sec.txt68
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/ssi.txt73
-rw-r--r--Documentation/devicetree/bindings/powerpc/nintendo/gamecube.txt109
-rw-r--r--Documentation/devicetree/bindings/powerpc/nintendo/wii.txt184
37 files changed, 2304 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/powerpc/4xx/cpm.txt b/Documentation/devicetree/bindings/powerpc/4xx/cpm.txt
new file mode 100644
index 000000000000..ee459806d35e
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/4xx/cpm.txt
@@ -0,0 +1,52 @@
1PPC4xx Clock Power Management (CPM) node
2
3Required properties:
4 - compatible : compatible list, currently only "ibm,cpm"
5 - dcr-access-method : "native"
6 - dcr-reg : < DCR register range >
7
8Optional properties:
9 - er-offset : All 4xx SoCs with a CPM controller have
10 one of two different order for the CPM
11 registers. Some have the CPM registers
12 in the following order (ER,FR,SR). The
13 others have them in the following order
14 (SR,ER,FR). For the second case set
15 er-offset = <1>.
16 - unused-units : specifier consist of one cell. For each
17 bit in the cell, the corresponding bit
18 in CPM will be set to turn off unused
19 devices.
20 - idle-doze : specifier consist of one cell. For each
21 bit in the cell, the corresponding bit
22 in CPM will be set to turn off unused
23 devices. This is usually just CPM[CPU].
24 - standby : specifier consist of one cell. For each
25 bit in the cell, the corresponding bit
26 in CPM will be set on standby and
27 restored on resume.
28 - suspend : specifier consist of one cell. For each
29 bit in the cell, the corresponding bit
30 in CPM will be set on suspend (mem) and
31 restored on resume. Note, for standby
32 and suspend the corresponding bits can
33 be different or the same. Usually for
34 standby only class 2 and 3 units are set.
35 However, the interface does not care.
36 If they are the same, the additional
37 power saving will be seeing if support
38 is available to put the DDR in self
39 refresh mode and any additional power
40 saving techniques for the specific SoC.
41
42Example:
43 CPM0: cpm {
44 compatible = "ibm,cpm";
45 dcr-access-method = "native";
46 dcr-reg = <0x160 0x003>;
47 er-offset = <0>;
48 unused-units = <0x00000100>;
49 idle-doze = <0x02000000>;
50 standby = <0xfeff0000>;
51 suspend = <0xfeff791d>;
52};
diff --git a/Documentation/devicetree/bindings/powerpc/4xx/emac.txt b/Documentation/devicetree/bindings/powerpc/4xx/emac.txt
new file mode 100644
index 000000000000..2161334a7ca5
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/4xx/emac.txt
@@ -0,0 +1,148 @@
1 4xx/Axon EMAC ethernet nodes
2
3 The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
4 the Axon bridge. To operate this needs to interact with a ths
5 special McMAL DMA controller, and sometimes an RGMII or ZMII
6 interface. In addition to the nodes and properties described
7 below, the node for the OPB bus on which the EMAC sits must have a
8 correct clock-frequency property.
9
10 i) The EMAC node itself
11
12 Required properties:
13 - device_type : "network"
14
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
17 405gp, Axon) and second is either "ibm,emac" or
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
19 "ibm,emac4"
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - interrupt-parent : optional, if needed for interrupt mapping
22 - reg : <registers mapping>
23 - local-mac-address : 6 bytes, MAC address
24 - mal-device : phandle of the associated McMAL node
25 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
26 with this EMAC
27 - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated
28 with this EMAC
29 - cell-index : 1 cell, hardware index of the EMAC cell on a given
30 ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on
31 each Axon chip)
32 - max-frame-size : 1 cell, maximum frame size supported in bytes
33 - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
34 operations.
35 For Axon, 2048
36 - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec
37 operations.
38 For Axon, 2048.
39 - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate
40 thresholds).
41 For Axon, 0x00000010
42 - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds)
43 in bytes.
44 For Axon, 0x00000100 (I think ...)
45 - phy-mode : string, mode of operations of the PHY interface.
46 Supported values are: "mii", "rmii", "smii", "rgmii",
47 "tbi", "gmii", rtbi", "sgmii".
48 For Axon on CAB, it is "rgmii"
49 - mdio-device : 1 cell, required iff using shared MDIO registers
50 (440EP). phandle of the EMAC to use to drive the
51 MDIO lines for the PHY used by this EMAC.
52 - zmii-device : 1 cell, required iff connected to a ZMII. phandle of
53 the ZMII device node
54 - zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII
55 channel or 0xffffffff if ZMII is only used for MDIO.
56 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
57 of the RGMII device node.
58 For Axon: phandle of plb5/plb4/opb/rgmii
59 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
60 RGMII channel is used by this EMAC.
61 Fox Axon: present, whatever value is appropriate for each
62 EMAC, that is the content of the current (bogus) "phy-port"
63 property.
64
65 Optional properties:
66 - phy-address : 1 cell, optional, MDIO address of the PHY. If absent,
67 a search is performed.
68 - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY
69 for, used if phy-address is absent. bit 0x00000001 is
70 MDIO address 0.
71 For Axon it can be absent, though my current driver
72 doesn't handle phy-address yet so for now, keep
73 0x00ffffff in it.
74 - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
75 operations (if absent the value is the same as
76 rx-fifo-size). For Axon, either absent or 2048.
77 - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec
78 operations (if absent the value is the same as
79 tx-fifo-size). For Axon, either absent or 2048.
80 - tah-device : 1 cell, optional. If connected to a TAH engine for
81 offload, phandle of the TAH device node.
82 - tah-channel : 1 cell, optional. If appropriate, channel used on the
83 TAH engine.
84
85 Example:
86
87 EMAC0: ethernet@40000800 {
88 device_type = "network";
89 compatible = "ibm,emac-440gp", "ibm,emac";
90 interrupt-parent = <&UIC1>;
91 interrupts = <1c 4 1d 4>;
92 reg = <40000800 70>;
93 local-mac-address = [00 04 AC E3 1B 1E];
94 mal-device = <&MAL0>;
95 mal-tx-channel = <0 1>;
96 mal-rx-channel = <0>;
97 cell-index = <0>;
98 max-frame-size = <5dc>;
99 rx-fifo-size = <1000>;
100 tx-fifo-size = <800>;
101 phy-mode = "rmii";
102 phy-map = <00000001>;
103 zmii-device = <&ZMII0>;
104 zmii-channel = <0>;
105 };
106
107 ii) McMAL node
108
109 Required properties:
110 - device_type : "dma-controller"
111 - compatible : compatible list, containing 2 entries, first is
112 "ibm,mcmal-CHIP" where CHIP is the host ASIC (like
113 emac) and the second is either "ibm,mcmal" or
114 "ibm,mcmal2".
115 For Axon, "ibm,mcmal-axon","ibm,mcmal2"
116 - interrupts : <interrupt mapping for the MAL interrupts sources:
117 5 sources: tx_eob, rx_eob, serr, txde, rxde>.
118 For Axon: This is _different_ from the current
119 firmware. We use the "delayed" interrupts for txeob
120 and rxeob. Thus we end up with mapping those 5 MPIC
121 interrupts, all level positive sensitive: 10, 11, 32,
122 33, 34 (in decimal)
123 - dcr-reg : < DCR registers range >
124 - dcr-parent : if needed for dcr-reg
125 - num-tx-chans : 1 cell, number of Tx channels
126 - num-rx-chans : 1 cell, number of Rx channels
127
128 iii) ZMII node
129
130 Required properties:
131 - compatible : compatible list, containing 2 entries, first is
132 "ibm,zmii-CHIP" where CHIP is the host ASIC (like
133 EMAC) and the second is "ibm,zmii".
134 For Axon, there is no ZMII node.
135 - reg : <registers mapping>
136
137 iv) RGMII node
138
139 Required properties:
140 - compatible : compatible list, containing 2 entries, first is
141 "ibm,rgmii-CHIP" where CHIP is the host ASIC (like
142 EMAC) and the second is "ibm,rgmii".
143 For Axon, "ibm,rgmii-axon","ibm,rgmii"
144 - reg : <registers mapping>
145 - revision : as provided by the RGMII new version register if
146 available.
147 For Axon: 0x0000012a
148
diff --git a/Documentation/devicetree/bindings/powerpc/4xx/ndfc.txt b/Documentation/devicetree/bindings/powerpc/4xx/ndfc.txt
new file mode 100644
index 000000000000..869f0b5f16e8
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/4xx/ndfc.txt
@@ -0,0 +1,39 @@
1AMCC NDFC (NanD Flash Controller)
2
3Required properties:
4- compatible : "ibm,ndfc".
5- reg : should specify chip select and size used for the chip (0x2000).
6
7Optional properties:
8- ccr : NDFC config and control register value (default 0).
9- bank-settings : NDFC bank configuration register value (default 0).
10
11Notes:
12- partition(s) - follows the OF MTD standard for partitions
13
14Example:
15
16ndfc@1,0 {
17 compatible = "ibm,ndfc";
18 reg = <0x00000001 0x00000000 0x00002000>;
19 ccr = <0x00001000>;
20 bank-settings = <0x80002222>;
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 nand {
25 #address-cells = <1>;
26 #size-cells = <1>;
27
28 partition@0 {
29 label = "kernel";
30 reg = <0x00000000 0x00200000>;
31 };
32 partition@200000 {
33 label = "root";
34 reg = <0x00200000 0x03E00000>;
35 };
36 };
37};
38
39
diff --git a/Documentation/devicetree/bindings/powerpc/4xx/ppc440spe-adma.txt b/Documentation/devicetree/bindings/powerpc/4xx/ppc440spe-adma.txt
new file mode 100644
index 000000000000..515ebcf1b97d
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/4xx/ppc440spe-adma.txt
@@ -0,0 +1,93 @@
1PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator)
2
3Device nodes needed for operation of the ppc440spe-adma driver
4are specified hereby. These are I2O/DMA, DMA and XOR nodes
5for DMA engines and Memory Queue Module node. The latter is used
6by ADMA driver for configuration of RAID-6 H/W capabilities of
7the PPC440SPe. In addition to the nodes and properties described
8below, the ranges property of PLB node must specify ranges for
9DMA devices.
10
11 i) The I2O node
12
13 Required properties:
14
15 - compatible : "ibm,i2o-440spe";
16 - reg : <registers mapping>
17 - dcr-reg : <DCR registers range>
18
19 Example:
20
21 I2O: i2o@400100000 {
22 compatible = "ibm,i2o-440spe";
23 reg = <0x00000004 0x00100000 0x100>;
24 dcr-reg = <0x060 0x020>;
25 };
26
27
28 ii) The DMA node
29
30 Required properties:
31
32 - compatible : "ibm,dma-440spe";
33 - cell-index : 1 cell, hardware index of the DMA engine
34 (typically 0x0 and 0x1 for DMA0 and DMA1)
35 - reg : <registers mapping>
36 - dcr-reg : <DCR registers range>
37 - interrupts : <interrupt mapping for DMA0/1 interrupts sources:
38 2 sources: DMAx CS FIFO Needs Service IRQ (on UIC0)
39 and DMA Error IRQ (on UIC1). The latter is common
40 for both DMA engines>.
41 - interrupt-parent : needed for interrupt mapping
42
43 Example:
44
45 DMA0: dma0@400100100 {
46 compatible = "ibm,dma-440spe";
47 cell-index = <0>;
48 reg = <0x00000004 0x00100100 0x100>;
49 dcr-reg = <0x060 0x020>;
50 interrupt-parent = <&DMA0>;
51 interrupts = <0 1>;
52 #interrupt-cells = <1>;
53 #address-cells = <0>;
54 #size-cells = <0>;
55 interrupt-map = <
56 0 &UIC0 0x14 4
57 1 &UIC1 0x16 4>;
58 };
59
60
61 iii) XOR Accelerator node
62
63 Required properties:
64
65 - compatible : "amcc,xor-accelerator";
66 - reg : <registers mapping>
67 - interrupts : <interrupt mapping for XOR interrupt source>
68 - interrupt-parent : for interrupt mapping
69
70 Example:
71
72 xor-accel@400200000 {
73 compatible = "amcc,xor-accelerator";
74 reg = <0x00000004 0x00200000 0x400>;
75 interrupt-parent = <&UIC1>;
76 interrupts = <0x1f 4>;
77 };
78
79
80 iv) Memory Queue Module node
81
82 Required properties:
83
84 - compatible : "ibm,mq-440spe";
85 - dcr-reg : <DCR registers range>
86
87 Example:
88
89 MQ0: mq {
90 compatible = "ibm,mq-440spe";
91 dcr-reg = <0x040 0x020>;
92 };
93
diff --git a/Documentation/devicetree/bindings/powerpc/4xx/reboot.txt b/Documentation/devicetree/bindings/powerpc/4xx/reboot.txt
new file mode 100644
index 000000000000..d7217260589c
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/4xx/reboot.txt
@@ -0,0 +1,18 @@
1Reboot property to control system reboot on PPC4xx systems:
2
3By setting "reset_type" to one of the following values, the default
4software reset mechanism may be overidden. Here the possible values of
5"reset_type":
6
7 1 - PPC4xx core reset
8 2 - PPC4xx chip reset
9 3 - PPC4xx system reset (default)
10
11Example:
12
13 cpu@0 {
14 device_type = "cpu";
15 model = "PowerPC,440SPe";
16 ...
17 reset-type = <2>; /* Use chip-reset */
18 };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/board.txt b/Documentation/devicetree/bindings/powerpc/fsl/board.txt
new file mode 100644
index 000000000000..39e941515a36
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/board.txt
@@ -0,0 +1,63 @@
1* Board Control and Status (BCSR)
2
3Required properties:
4
5 - compatible : Should be "fsl,<board>-bcsr"
6 - reg : Offset and length of the register set for the device
7
8Example:
9
10 bcsr@f8000000 {
11 compatible = "fsl,mpc8360mds-bcsr";
12 reg = <f8000000 8000>;
13 };
14
15* Freescale on board FPGA
16
17This is the memory-mapped registers for on board FPGA.
18
19Required properities:
20- compatible : should be "fsl,fpga-pixis".
21- reg : should contain the address and the length of the FPPGA register
22 set.
23- interrupt-parent: should specify phandle for the interrupt controller.
24- interrupts : should specify event (wakeup) IRQ.
25
26Example (MPC8610HPCD):
27
28 board-control@e8000000 {
29 compatible = "fsl,fpga-pixis";
30 reg = <0xe8000000 32>;
31 interrupt-parent = <&mpic>;
32 interrupts = <8 8>;
33 };
34
35* Freescale BCSR GPIO banks
36
37Some BCSR registers act as simple GPIO controllers, each such
38register can be represented by the gpio-controller node.
39
40Required properities:
41- compatible : Should be "fsl,<board>-bcsr-gpio".
42- reg : Should contain the address and the length of the GPIO bank
43 register.
44- #gpio-cells : Should be two. The first cell is the pin number and the
45 second cell is used to specify optional parameters (currently unused).
46- gpio-controller : Marks the port as GPIO controller.
47
48Example:
49
50 bcsr@1,0 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "fsl,mpc8360mds-bcsr";
54 reg = <1 0 0x8000>;
55 ranges = <0 1 0 0x8000>;
56
57 bcsr13: gpio-controller@d {
58 #gpio-cells = <2>;
59 compatible = "fsl,mpc8360mds-bcsr-gpio";
60 reg = <0xd 1>;
61 gpio-controller;
62 };
63 };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm.txt
new file mode 100644
index 000000000000..160c752484b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm.txt
@@ -0,0 +1,67 @@
1* Freescale Communications Processor Module
2
3NOTE: This is an interim binding, and will likely change slightly,
4as more devices are supported. The QE bindings especially are
5incomplete.
6
7* Root CPM node
8
9Properties:
10- compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
11- reg : A 48-byte region beginning with CPCR.
12
13Example:
14 cpm@119c0 {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 #interrupt-cells = <2>;
18 compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
19 reg = <119c0 30>;
20 }
21
22* Properties common to multiple CPM/QE devices
23
24- fsl,cpm-command : This value is ORed with the opcode and command flag
25 to specify the device on which a CPM command operates.
26
27- fsl,cpm-brg : Indicates which baud rate generator the device
28 is associated with. If absent, an unused BRG
29 should be dynamically allocated. If zero, the
30 device uses an external clock rather than a BRG.
31
32- reg : Unless otherwise specified, the first resource represents the
33 scc/fcc/ucc registers, and the second represents the device's
34 parameter RAM region (if it has one).
35
36* Multi-User RAM (MURAM)
37
38The multi-user/dual-ported RAM is expressed as a bus under the CPM node.
39
40Ranges must be set up subject to the following restrictions:
41
42- Children's reg nodes must be offsets from the start of all muram, even
43 if the user-data area does not begin at zero.
44- If multiple range entries are used, the difference between the parent
45 address and the child address must be the same in all, so that a single
46 mapping can cover them all while maintaining the ability to determine
47 CPM-side offsets with pointer subtraction. It is recommended that
48 multiple range entries not be used.
49- A child address of zero must be translatable, even if no reg resources
50 contain it.
51
52A child "data" node must exist, compatible with "fsl,cpm-muram-data", to
53indicate the portion of muram that is usable by the OS for arbitrary
54purposes. The data node may have an arbitrary number of reg resources,
55all of which contribute to the allocatable muram pool.
56
57Example, based on mpc8272:
58 muram@0 {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges = <0 0 10000>;
62
63 data@0 {
64 compatible = "fsl,cpm-muram-data";
65 reg = <0 2000 9800 800>;
66 };
67 };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/brg.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/brg.txt
new file mode 100644
index 000000000000..4c7d45eaf025
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/brg.txt
@@ -0,0 +1,21 @@
1* Baud Rate Generators
2
3Currently defined compatibles:
4fsl,cpm-brg
5fsl,cpm1-brg
6fsl,cpm2-brg
7
8Properties:
9- reg : There may be an arbitrary number of reg resources; BRG
10 numbers are assigned to these in order.
11- clock-frequency : Specifies the base frequency driving
12 the BRG.
13
14Example:
15 brg@119f0 {
16 compatible = "fsl,mpc8272-brg",
17 "fsl,cpm2-brg",
18 "fsl,cpm-brg";
19 reg = <119f0 10 115f0 10>;
20 clock-frequency = <d#25000000>;
21 };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/i2c.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/i2c.txt
new file mode 100644
index 000000000000..87bc6048667e
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/i2c.txt
@@ -0,0 +1,41 @@
1* I2C
2
3The I2C controller is expressed as a bus under the CPM node.
4
5Properties:
6- compatible : "fsl,cpm1-i2c", "fsl,cpm2-i2c"
7- reg : On CPM2 devices, the second resource doesn't specify the I2C
8 Parameter RAM itself, but the I2C_BASE field of the CPM2 Parameter RAM
9 (typically 0x8afc 0x2).
10- #address-cells : Should be one. The cell is the i2c device address with
11 the r/w bit set to zero.
12- #size-cells : Should be zero.
13- clock-frequency : Can be used to set the i2c clock frequency. If
14 unspecified, a default frequency of 60kHz is being used.
15The following two properties are deprecated. They are only used by legacy
16i2c drivers to find the bus to probe:
17- linux,i2c-index : Can be used to hard code an i2c bus number. By default,
18 the bus number is dynamically assigned by the i2c core.
19- linux,i2c-class : Can be used to override the i2c class. The class is used
20 by legacy i2c device drivers to find a bus in a specific context like
21 system management, video or sound. By default, I2C_CLASS_HWMON (1) is
22 being used. The definition of the classes can be found in
23 include/i2c/i2c.h
24
25Example, based on mpc823:
26
27 i2c@860 {
28 compatible = "fsl,mpc823-i2c",
29 "fsl,cpm1-i2c";
30 reg = <0x860 0x20 0x3c80 0x30>;
31 interrupts = <16>;
32 interrupt-parent = <&CPM_PIC>;
33 fsl,cpm-command = <0x10>;
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 rtc@68 {
38 compatible = "dallas,ds1307";
39 reg = <0x68>;
40 };
41 };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/pic.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/pic.txt
new file mode 100644
index 000000000000..8e3ee1681618
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/pic.txt
@@ -0,0 +1,18 @@
1* Interrupt Controllers
2
3Currently defined compatibles:
4- fsl,cpm1-pic
5 - only one interrupt cell
6- fsl,pq1-pic
7- fsl,cpm2-pic
8 - second interrupt cell is level/sense:
9 - 2 is falling edge
10 - 8 is active low
11
12Example:
13 interrupt-controller@10c00 {
14 #interrupt-cells = <2>;
15 interrupt-controller;
16 reg = <10c00 80>;
17 compatible = "mpc8272-pic", "fsl,cpm2-pic";
18 };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/usb.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/usb.txt
new file mode 100644
index 000000000000..74bfda4bb824
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/usb.txt
@@ -0,0 +1,15 @@
1* USB (Universal Serial Bus Controller)
2
3Properties:
4- compatible : "fsl,cpm1-usb", "fsl,cpm2-usb", "fsl,qe-usb"
5
6Example:
7 usb@11bc0 {
8 #address-cells = <1>;
9 #size-cells = <0>;
10 compatible = "fsl,cpm2-usb";
11 reg = <11b60 18 8b00 100>;
12 interrupts = <b 8>;
13 interrupt-parent = <&PIC>;
14 fsl,cpm-command = <2e600000>;
15 };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/gpio.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/gpio.txt
new file mode 100644
index 000000000000..349f79fd7076
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/gpio.txt
@@ -0,0 +1,38 @@
1Every GPIO controller node must have #gpio-cells property defined,
2this information will be used to translate gpio-specifiers.
3
4On CPM1 devices, all ports are using slightly different register layouts.
5Ports A, C and D are 16bit ports and Ports B and E are 32bit ports.
6
7On CPM2 devices, all ports are 32bit ports and use a common register layout.
8
9Required properties:
10- compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13- #gpio-cells : Should be two. The first cell is the pin number and the
14 second cell is used to specify optional parameters (currently unused).
15- gpio-controller : Marks the port as GPIO controller.
16
17Example of three SOC GPIO banks defined as gpio-controller nodes:
18
19 CPM1_PIO_A: gpio-controller@950 {
20 #gpio-cells = <2>;
21 compatible = "fsl,cpm1-pario-bank-a";
22 reg = <0x950 0x10>;
23 gpio-controller;
24 };
25
26 CPM1_PIO_B: gpio-controller@ab8 {
27 #gpio-cells = <2>;
28 compatible = "fsl,cpm1-pario-bank-b";
29 reg = <0xab8 0x10>;
30 gpio-controller;
31 };
32
33 CPM1_PIO_E: gpio-controller@ac8 {
34 #gpio-cells = <2>;
35 compatible = "fsl,cpm1-pario-bank-e";
36 reg = <0xac8 0x18>;
37 gpio-controller;
38 };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt
new file mode 100644
index 000000000000..0e4269446580
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt
@@ -0,0 +1,45 @@
1* Network
2
3Currently defined compatibles:
4- fsl,cpm1-scc-enet
5- fsl,cpm2-scc-enet
6- fsl,cpm1-fec-enet
7- fsl,cpm2-fcc-enet (third resource is GFEMR)
8- fsl,qe-enet
9
10Example:
11
12 ethernet@11300 {
13 device_type = "network";
14 compatible = "fsl,mpc8272-fcc-enet",
15 "fsl,cpm2-fcc-enet";
16 reg = <11300 20 8400 100 11390 1>;
17 local-mac-address = [ 00 00 00 00 00 00 ];
18 interrupts = <20 8>;
19 interrupt-parent = <&PIC>;
20 phy-handle = <&PHY0>;
21 fsl,cpm-command = <12000300>;
22 };
23
24* MDIO
25
26Currently defined compatibles:
27fsl,pq1-fec-mdio (reg is same as first resource of FEC device)
28fsl,cpm2-mdio-bitbang (reg is port C registers)
29
30Properties for fsl,cpm2-mdio-bitbang:
31fsl,mdio-pin : pin of port C controlling mdio data
32fsl,mdc-pin : pin of port C controlling mdio clock
33
34Example:
35 mdio@10d40 {
36 device_type = "mdio";
37 compatible = "fsl,mpc8272ads-mdio-bitbang",
38 "fsl,mpc8272-mdio-bitbang",
39 "fsl,cpm2-mdio-bitbang";
40 reg = <10d40 14>;
41 #address-cells = <1>;
42 #size-cells = <0>;
43 fsl,mdio-pin = <12>;
44 fsl,mdc-pin = <13>;
45 };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
new file mode 100644
index 000000000000..4f8930263dd9
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
@@ -0,0 +1,115 @@
1* Freescale QUICC Engine module (QE)
2This represents qe module that is installed on PowerQUICC II Pro.
3
4NOTE: This is an interim binding; it should be updated to fit
5in with the CPM binding later in this document.
6
7Basically, it is a bus of devices, that could act more or less
8as a complete entity (UCC, USB etc ). All of them should be siblings on
9the "root" qe node, using the common properties from there.
10The description below applies to the qe of MPC8360 and
11more nodes and properties would be extended in the future.
12
13i) Root QE device
14
15Required properties:
16- compatible : should be "fsl,qe";
17- model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
18- reg : offset and length of the device registers.
19- bus-frequency : the clock frequency for QUICC Engine.
20- fsl,qe-num-riscs: define how many RISC engines the QE has.
21- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use for the
22 threads.
23
24Optional properties:
25- fsl,firmware-phandle:
26 Usage: required only if there is no fsl,qe-firmware child node
27 Value type: <phandle>
28 Definition: Points to a firmware node (see "QE Firmware Node" below)
29 that contains the firmware that should be uploaded for this QE.
30 The compatible property for the firmware node should say,
31 "fsl,qe-firmware".
32
33Recommended properties
34- brg-frequency : the internal clock source frequency for baud-rate
35 generators in Hz.
36
37Example:
38 qe@e0100000 {
39 #address-cells = <1>;
40 #size-cells = <1>;
41 #interrupt-cells = <2>;
42 compatible = "fsl,qe";
43 ranges = <0 e0100000 00100000>;
44 reg = <e0100000 480>;
45 brg-frequency = <0>;
46 bus-frequency = <179A7B00>;
47 }
48
49* Multi-User RAM (MURAM)
50
51Required properties:
52- compatible : should be "fsl,qe-muram", "fsl,cpm-muram".
53- mode : the could be "host" or "slave".
54- ranges : Should be defined as specified in 1) to describe the
55 translation of MURAM addresses.
56- data-only : sub-node which defines the address area under MURAM
57 bus that can be allocated as data/parameter
58
59Example:
60
61 muram@10000 {
62 compatible = "fsl,qe-muram", "fsl,cpm-muram";
63 ranges = <0 00010000 0000c000>;
64
65 data-only@0{
66 compatible = "fsl,qe-muram-data",
67 "fsl,cpm-muram-data";
68 reg = <0 c000>;
69 };
70 };
71
72* QE Firmware Node
73
74This node defines a firmware binary that is embedded in the device tree, for
75the purpose of passing the firmware from bootloader to the kernel, or from
76the hypervisor to the guest.
77
78The firmware node itself contains the firmware binary contents, a compatible
79property, and any firmware-specific properties. The node should be placed
80inside a QE node that needs it. Doing so eliminates the need for a
81fsl,firmware-phandle property. Other QE nodes that need the same firmware
82should define an fsl,firmware-phandle property that points to the firmware node
83in the first QE node.
84
85The fsl,firmware property can be specified in the DTS (possibly using incbin)
86or can be inserted by the boot loader at boot time.
87
88Required properties:
89 - compatible
90 Usage: required
91 Value type: <string>
92 Definition: A standard property. Specify a string that indicates what
93 kind of firmware it is. For QE, this should be "fsl,qe-firmware".
94
95 - fsl,firmware
96 Usage: required
97 Value type: <prop-encoded-array>, encoded as an array of bytes
98 Definition: A standard property. This property contains the firmware
99 binary "blob".
100
101Example:
102 qe1@e0080000 {
103 compatible = "fsl,qe";
104 qe_firmware:qe-firmware {
105 compatible = "fsl,qe-firmware";
106 fsl,firmware = [0x70 0xcd 0x00 0x00 0x01 0x46 0x45 ...];
107 };
108 ...
109 };
110
111 qe2@e0090000 {
112 compatible = "fsl,qe";
113 fsl,firmware-phandle = <&qe_firmware>;
114 ...
115 };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/firmware.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/firmware.txt
new file mode 100644
index 000000000000..249db3a15d15
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/firmware.txt
@@ -0,0 +1,24 @@
1* Uploaded QE firmware
2
3 If a new firmware has been uploaded to the QE (usually by the
4 boot loader), then a 'firmware' child node should be added to the QE
5 node. This node provides information on the uploaded firmware that
6 device drivers may need.
7
8 Required properties:
9 - id: The string name of the firmware. This is taken from the 'id'
10 member of the qe_firmware structure of the uploaded firmware.
11 Device drivers can search this string to determine if the
12 firmware they want is already present.
13 - extended-modes: The Extended Modes bitfield, taken from the
14 firmware binary. It is a 64-bit number represented
15 as an array of two 32-bit numbers.
16 - virtual-traps: The virtual traps, taken from the firmware binary.
17 It is an array of 8 32-bit numbers.
18
19Example:
20 firmware {
21 id = "Soft-UART";
22 extended-modes = <0 0>;
23 virtual-traps = <0 0 0 0 0 0 0 0>;
24 };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/par_io.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/par_io.txt
new file mode 100644
index 000000000000..60984260207b
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/par_io.txt
@@ -0,0 +1,51 @@
1* Parallel I/O Ports
2
3This node configures Parallel I/O ports for CPUs with QE support.
4The node should reside in the "soc" node of the tree. For each
5device that using parallel I/O ports, a child node should be created.
6See the definition of the Pin configuration nodes below for more
7information.
8
9Required properties:
10- device_type : should be "par_io".
11- reg : offset to the register set and its length.
12- num-ports : number of Parallel I/O ports
13
14Example:
15par_io@1400 {
16 reg = <1400 100>;
17 #address-cells = <1>;
18 #size-cells = <0>;
19 device_type = "par_io";
20 num-ports = <7>;
21 ucc_pin@01 {
22 ......
23 };
24
25Note that "par_io" nodes are obsolete, and should not be used for
26the new device trees. Instead, each Par I/O bank should be represented
27via its own gpio-controller node:
28
29Required properties:
30- #gpio-cells : should be "2".
31- compatible : should be "fsl,<chip>-qe-pario-bank",
32 "fsl,mpc8323-qe-pario-bank".
33- reg : offset to the register set and its length.
34- gpio-controller : node to identify gpio controllers.
35
36Example:
37 qe_pio_a: gpio-controller@1400 {
38 #gpio-cells = <2>;
39 compatible = "fsl,mpc8360-qe-pario-bank",
40 "fsl,mpc8323-qe-pario-bank";
41 reg = <0x1400 0x18>;
42 gpio-controller;
43 };
44
45 qe_pio_e: gpio-controller@1460 {
46 #gpio-cells = <2>;
47 compatible = "fsl,mpc8360-qe-pario-bank",
48 "fsl,mpc8323-qe-pario-bank";
49 reg = <0x1460 0x18>;
50 gpio-controller;
51 };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/pincfg.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/pincfg.txt
new file mode 100644
index 000000000000..c5b43061db3a
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/pincfg.txt
@@ -0,0 +1,60 @@
1* Pin configuration nodes
2
3Required properties:
4- linux,phandle : phandle of this node; likely referenced by a QE
5 device.
6- pio-map : array of pin configurations. Each pin is defined by 6
7 integers. The six numbers are respectively: port, pin, dir,
8 open_drain, assignment, has_irq.
9 - port : port number of the pin; 0-6 represent port A-G in UM.
10 - pin : pin number in the port.
11 - dir : direction of the pin, should encode as follows:
12
13 0 = The pin is disabled
14 1 = The pin is an output
15 2 = The pin is an input
16 3 = The pin is I/O
17
18 - open_drain : indicates the pin is normal or wired-OR:
19
20 0 = The pin is actively driven as an output
21 1 = The pin is an open-drain driver. As an output, the pin is
22 driven active-low, otherwise it is three-stated.
23
24 - assignment : function number of the pin according to the Pin Assignment
25 tables in User Manual. Each pin can have up to 4 possible functions in
26 QE and two options for CPM.
27 - has_irq : indicates if the pin is used as source of external
28 interrupts.
29
30Example:
31 ucc_pin@01 {
32 linux,phandle = <140001>;
33 pio-map = <
34 /* port pin dir open_drain assignment has_irq */
35 0 3 1 0 1 0 /* TxD0 */
36 0 4 1 0 1 0 /* TxD1 */
37 0 5 1 0 1 0 /* TxD2 */
38 0 6 1 0 1 0 /* TxD3 */
39 1 6 1 0 3 0 /* TxD4 */
40 1 7 1 0 1 0 /* TxD5 */
41 1 9 1 0 2 0 /* TxD6 */
42 1 a 1 0 2 0 /* TxD7 */
43 0 9 2 0 1 0 /* RxD0 */
44 0 a 2 0 1 0 /* RxD1 */
45 0 b 2 0 1 0 /* RxD2 */
46 0 c 2 0 1 0 /* RxD3 */
47 0 d 2 0 1 0 /* RxD4 */
48 1 1 2 0 2 0 /* RxD5 */
49 1 0 2 0 2 0 /* RxD6 */
50 1 4 2 0 2 0 /* RxD7 */
51 0 7 1 0 1 0 /* TX_EN */
52 0 8 1 0 1 0 /* TX_ER */
53 0 f 2 0 1 0 /* RX_DV */
54 0 10 2 0 1 0 /* RX_ER */
55 0 0 2 0 1 0 /* RX_CLK */
56 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
57 2 8 2 0 1 0>; /* GTX125 - CLK9 */
58 };
59
60
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/ucc.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/ucc.txt
new file mode 100644
index 000000000000..e47734bee3f0
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/ucc.txt
@@ -0,0 +1,70 @@
1* UCC (Unified Communications Controllers)
2
3Required properties:
4- device_type : should be "network", "hldc", "uart", "transparent"
5 "bisync", "atm", or "serial".
6- compatible : could be "ucc_geth" or "fsl_atm" and so on.
7- cell-index : the ucc number(1-8), corresponding to UCCx in UM.
8- reg : Offset and length of the register set for the device
9- interrupts : <a b> where a is the interrupt number and b is a
10 field that represents an encoding of the sense and level
11 information for the interrupt. This should be encoded based on
12 the information in section 2) depending on the type of interrupt
13 controller you have.
14- interrupt-parent : the phandle for the interrupt controller that
15 services interrupts for this device.
16- pio-handle : The phandle for the Parallel I/O port configuration.
17- port-number : for UART drivers, the port number to use, between 0 and 3.
18 This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0.
19 The port number is added to the minor number of the device. Unlike the
20 CPM UART driver, the port-number is required for the QE UART driver.
21- soft-uart : for UART drivers, if specified this means the QE UART device
22 driver should use "Soft-UART" mode, which is needed on some SOCs that have
23 broken UART hardware. Soft-UART is provided via a microcode upload.
24- rx-clock-name: the UCC receive clock source
25 "none": clock source is disabled
26 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
27 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
28- tx-clock-name: the UCC transmit clock source
29 "none": clock source is disabled
30 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
31 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
32The following two properties are deprecated. rx-clock has been replaced
33with rx-clock-name, and tx-clock has been replaced with tx-clock-name.
34Drivers that currently use the deprecated properties should continue to
35do so, in order to support older device trees, but they should be updated
36to check for the new properties first.
37- rx-clock : represents the UCC receive clock source.
38 0x00 : clock source is disabled;
39 0x1~0x10 : clock source is BRG1~BRG16 respectively;
40 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
41- tx-clock: represents the UCC transmit clock source;
42 0x00 : clock source is disabled;
43 0x1~0x10 : clock source is BRG1~BRG16 respectively;
44 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
45
46Required properties for network device_type:
47- mac-address : list of bytes representing the ethernet address.
48- phy-handle : The phandle for the PHY connected to this controller.
49
50Recommended properties:
51- phy-connection-type : a string naming the controller/PHY interface type,
52 i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
53 Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only),
54 "tbi", or "rtbi".
55
56Example:
57 ucc@2000 {
58 device_type = "network";
59 compatible = "ucc_geth";
60 cell-index = <1>;
61 reg = <2000 200>;
62 interrupts = <a0 0>;
63 interrupt-parent = <700>;
64 mac-address = [ 00 04 9f 00 23 23 ];
65 rx-clock = "none";
66 tx-clock = "clk9";
67 phy-handle = <212000>;
68 phy-connection-type = "gmii";
69 pio-handle = <140001>;
70 };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/usb.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/usb.txt
new file mode 100644
index 000000000000..9ccd5f30405b
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/usb.txt
@@ -0,0 +1,37 @@
1Freescale QUICC Engine USB Controller
2
3Required properties:
4- compatible : should be "fsl,<chip>-qe-usb", "fsl,mpc8323-qe-usb".
5- reg : the first two cells should contain usb registers location and
6 length, the next two two cells should contain PRAM location and
7 length.
8- interrupts : should contain USB interrupt.
9- interrupt-parent : interrupt source phandle.
10- fsl,fullspeed-clock : specifies the full speed USB clock source:
11 "none": clock source is disabled
12 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
13 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
14- fsl,lowspeed-clock : specifies the low speed USB clock source:
15 "none": clock source is disabled
16 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
17 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
18- hub-power-budget : USB power budget for the root hub, in mA.
19- gpios : should specify GPIOs in this order: USBOE, USBTP, USBTN, USBRP,
20 USBRN, SPEED (optional), and POWER (optional).
21
22Example:
23
24usb@6c0 {
25 compatible = "fsl,mpc8360-qe-usb", "fsl,mpc8323-qe-usb";
26 reg = <0x6c0 0x40 0x8b00 0x100>;
27 interrupts = <11>;
28 interrupt-parent = <&qeic>;
29 fsl,fullspeed-clock = "clk21";
30 gpios = <&qe_pio_b 2 0 /* USBOE */
31 &qe_pio_b 3 0 /* USBTP */
32 &qe_pio_b 8 0 /* USBTN */
33 &qe_pio_b 9 0 /* USBRP */
34 &qe_pio_b 11 0 /* USBRN */
35 &qe_pio_e 20 0 /* SPEED */
36 &qe_pio_e 21 0 /* POWER */>;
37};
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/serial.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/serial.txt
new file mode 100644
index 000000000000..2ea76d9d137c
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/serial.txt
@@ -0,0 +1,32 @@
1* Serial
2
3Currently defined compatibles:
4- fsl,cpm1-smc-uart
5- fsl,cpm2-smc-uart
6- fsl,cpm1-scc-uart
7- fsl,cpm2-scc-uart
8- fsl,qe-uart
9
10Modem control lines connected to GPIO controllers are listed in the gpios
11property as described in booting-without-of.txt, section IX.1 in the following
12order:
13
14CTS, RTS, DCD, DSR, DTR, and RI.
15
16The gpios property is optional and can be left out when control lines are
17not used.
18
19Example:
20
21 serial@11a00 {
22 device_type = "serial";
23 compatible = "fsl,mpc8272-scc-uart",
24 "fsl,cpm2-scc-uart";
25 reg = <11a00 20 8000 100>;
26 interrupts = <28 8>;
27 interrupt-parent = <&PIC>;
28 fsl,cpm-brg = <1>;
29 fsl,cpm-command = <00800000>;
30 gpios = <&gpio_c 15 0
31 &gpio_d 29 0>;
32 };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/diu.txt b/Documentation/devicetree/bindings/powerpc/fsl/diu.txt
new file mode 100644
index 000000000000..b66cb6d31d69
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/diu.txt
@@ -0,0 +1,34 @@
1* Freescale Display Interface Unit
2
3The Freescale DIU is a LCD controller, with proper hardware, it can also
4drive DVI monitors.
5
6Required properties:
7- compatible : should be "fsl,diu" or "fsl,mpc5121-diu".
8- reg : should contain at least address and length of the DIU register
9 set.
10- interrupts : one DIU interrupt should be described here.
11- interrupt-parent : the phandle for the interrupt controller that
12 services interrupts for this device.
13
14Optional properties:
15- edid : verbatim EDID data block describing attached display.
16 Data from the detailed timing descriptor will be used to
17 program the display controller.
18
19Example (MPC8610HPCD):
20 display@2c000 {
21 compatible = "fsl,diu";
22 reg = <0x2c000 100>;
23 interrupts = <72 2>;
24 interrupt-parent = <&mpic>;
25 };
26
27Example for MPC5121:
28 display@2100 {
29 compatible = "fsl,mpc5121-diu";
30 reg = <0x2100 0x100>;
31 interrupts = <64 0x8>;
32 interrupt-parent = <&ipic>;
33 edid = [edid-data];
34 };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
new file mode 100644
index 000000000000..2a4b4bce6110
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
@@ -0,0 +1,144 @@
1* Freescale 83xx DMA Controller
2
3Freescale PowerPC 83xx have on chip general purpose DMA controllers.
4
5Required properties:
6
7- compatible : compatible list, contains 2 entries, first is
8 "fsl,CHIP-dma", where CHIP is the processor
9 (mpc8349, mpc8360, etc.) and the second is
10 "fsl,elo-dma"
11- reg : <registers mapping for DMA general status reg>
12- ranges : Should be defined as specified in 1) to describe the
13 DMA controller channels.
14- cell-index : controller index. 0 for controller @ 0x8100
15- interrupts : <interrupt mapping for DMA IRQ>
16- interrupt-parent : optional, if needed for interrupt mapping
17
18
19- DMA channel nodes:
20 - compatible : compatible list, contains 2 entries, first is
21 "fsl,CHIP-dma-channel", where CHIP is the processor
22 (mpc8349, mpc8350, etc.) and the second is
23 "fsl,elo-dma-channel". However, see note below.
24 - reg : <registers mapping for channel>
25 - cell-index : dma channel index starts at 0.
26
27Optional properties:
28 - interrupts : <interrupt mapping for DMA channel IRQ>
29 (on 83xx this is expected to be identical to
30 the interrupts property of the parent node)
31 - interrupt-parent : optional, if needed for interrupt mapping
32
33Example:
34 dma@82a8 {
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
38 reg = <0x82a8 4>;
39 ranges = <0 0x8100 0x1a4>;
40 interrupt-parent = <&ipic>;
41 interrupts = <71 8>;
42 cell-index = <0>;
43 dma-channel@0 {
44 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
45 cell-index = <0>;
46 reg = <0 0x80>;
47 interrupt-parent = <&ipic>;
48 interrupts = <71 8>;
49 };
50 dma-channel@80 {
51 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
52 cell-index = <1>;
53 reg = <0x80 0x80>;
54 interrupt-parent = <&ipic>;
55 interrupts = <71 8>;
56 };
57 dma-channel@100 {
58 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
59 cell-index = <2>;
60 reg = <0x100 0x80>;
61 interrupt-parent = <&ipic>;
62 interrupts = <71 8>;
63 };
64 dma-channel@180 {
65 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
66 cell-index = <3>;
67 reg = <0x180 0x80>;
68 interrupt-parent = <&ipic>;
69 interrupts = <71 8>;
70 };
71 };
72
73* Freescale 85xx/86xx DMA Controller
74
75Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers.
76
77Required properties:
78
79- compatible : compatible list, contains 2 entries, first is
80 "fsl,CHIP-dma", where CHIP is the processor
81 (mpc8540, mpc8540, etc.) and the second is
82 "fsl,eloplus-dma"
83- reg : <registers mapping for DMA general status reg>
84- cell-index : controller index. 0 for controller @ 0x21000,
85 1 for controller @ 0xc000
86- ranges : Should be defined as specified in 1) to describe the
87 DMA controller channels.
88
89- DMA channel nodes:
90 - compatible : compatible list, contains 2 entries, first is
91 "fsl,CHIP-dma-channel", where CHIP is the processor
92 (mpc8540, mpc8560, etc.) and the second is
93 "fsl,eloplus-dma-channel". However, see note below.
94 - cell-index : dma channel index starts at 0.
95 - reg : <registers mapping for channel>
96 - interrupts : <interrupt mapping for DMA channel IRQ>
97 - interrupt-parent : optional, if needed for interrupt mapping
98
99Example:
100 dma@21300 {
101 #address-cells = <1>;
102 #size-cells = <1>;
103 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
104 reg = <0x21300 4>;
105 ranges = <0 0x21100 0x200>;
106 cell-index = <0>;
107 dma-channel@0 {
108 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
109 reg = <0 0x80>;
110 cell-index = <0>;
111 interrupt-parent = <&mpic>;
112 interrupts = <20 2>;
113 };
114 dma-channel@80 {
115 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
116 reg = <0x80 0x80>;
117 cell-index = <1>;
118 interrupt-parent = <&mpic>;
119 interrupts = <21 2>;
120 };
121 dma-channel@100 {
122 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
123 reg = <0x100 0x80>;
124 cell-index = <2>;
125 interrupt-parent = <&mpic>;
126 interrupts = <22 2>;
127 };
128 dma-channel@180 {
129 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
130 reg = <0x180 0x80>;
131 cell-index = <3>;
132 interrupt-parent = <&mpic>;
133 interrupts = <23 2>;
134 };
135 };
136
137Note on DMA channel compatible properties: The compatible property must say
138"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA
139driver (fsldma). Any DMA channel used by fsldma cannot be used by another
140DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any DMA
141channel that should be used for another driver should not use
142"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for
143example, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt
144for more information.
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ecm.txt b/Documentation/devicetree/bindings/powerpc/fsl/ecm.txt
new file mode 100644
index 000000000000..f514f29c67d6
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/ecm.txt
@@ -0,0 +1,64 @@
1=====================================================================
2E500 LAW & Coherency Module Device Tree Binding
3Copyright (C) 2009 Freescale Semiconductor Inc.
4=====================================================================
5
6Local Access Window (LAW) Node
7
8The LAW node represents the region of CCSR space where local access
9windows are configured. For ECM based devices this is the first 4k
10of CCSR space that includes CCSRBAR, ALTCBAR, ALTCAR, BPTR, and some
11number of local access windows as specified by fsl,num-laws.
12
13PROPERTIES
14
15 - compatible
16 Usage: required
17 Value type: <string>
18 Definition: Must include "fsl,ecm-law"
19
20 - reg
21 Usage: required
22 Value type: <prop-encoded-array>
23 Definition: A standard property. The value specifies the
24 physical address offset and length of the CCSR space
25 registers.
26
27 - fsl,num-laws
28 Usage: required
29 Value type: <u32>
30 Definition: The value specifies the number of local access
31 windows for this device.
32
33=====================================================================
34
35E500 Coherency Module Node
36
37The E500 LAW node represents the region of CCSR space where ECM config
38and error reporting registers exist, this is the second 4k (0x1000)
39of CCSR space.
40
41PROPERTIES
42
43 - compatible
44 Usage: required
45 Value type: <string>
46 Definition: Must include "fsl,CHIP-ecm", "fsl,ecm" where
47 CHIP is the processor (mpc8572, mpc8544, etc.)
48
49 - reg
50 Usage: required
51 Value type: <prop-encoded-array>
52 Definition: A standard property. The value specifies the
53 physical address offset and length of the CCSR space
54 registers.
55
56 - interrupts
57 Usage: required
58 Value type: <prop-encoded-array>
59
60 - interrupt-parent
61 Usage: required
62 Value type: <phandle>
63
64=====================================================================
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/gtm.txt b/Documentation/devicetree/bindings/powerpc/fsl/gtm.txt
new file mode 100644
index 000000000000..9a33efded4bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/gtm.txt
@@ -0,0 +1,31 @@
1* Freescale General-purpose Timers Module
2
3Required properties:
4 - compatible : should be
5 "fsl,<chip>-gtm", "fsl,gtm" for SOC GTMs
6 "fsl,<chip>-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs
7 "fsl,<chip>-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs
8 - reg : should contain gtm registers location and length (0x40).
9 - interrupts : should contain four interrupts.
10 - interrupt-parent : interrupt source phandle.
11 - clock-frequency : specifies the frequency driving the timer.
12
13Example:
14
15timer@500 {
16 compatible = "fsl,mpc8360-gtm", "fsl,gtm";
17 reg = <0x500 0x40>;
18 interrupts = <90 8 78 8 84 8 72 8>;
19 interrupt-parent = <&ipic>;
20 /* filled by u-boot */
21 clock-frequency = <0>;
22};
23
24timer@440 {
25 compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm";
26 reg = <0x440 0x40>;
27 interrupts = <12 13 14 15>;
28 interrupt-parent = <&qeic>;
29 /* filled by u-boot */
30 clock-frequency = <0>;
31};
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/guts.txt b/Documentation/devicetree/bindings/powerpc/fsl/guts.txt
new file mode 100644
index 000000000000..9e7a2417dac5
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/guts.txt
@@ -0,0 +1,25 @@
1* Global Utilities Block
2
3The global utilities block controls power management, I/O device
4enabling, power-on-reset configuration monitoring, general-purpose
5I/O signal configuration, alternate function selection for multiplexed
6signals, and clock control.
7
8Required properties:
9
10 - compatible : Should define the compatible device type for
11 global-utilities.
12 - reg : Offset and length of the register set for the device.
13
14Recommended properties:
15
16 - fsl,has-rstcr : Indicates that the global utilities register set
17 contains a functioning "reset control register" (i.e. the board
18 is wired to reset upon setting the HRESET_REQ bit in this register).
19
20Example:
21 global-utilities@e0000 { /* global utilities block */
22 compatible = "fsl,mpc8548-guts";
23 reg = <e0000 1000>;
24 fsl,has-rstcr;
25 };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/lbc.txt b/Documentation/devicetree/bindings/powerpc/fsl/lbc.txt
new file mode 100644
index 000000000000..3300fec501c5
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/lbc.txt
@@ -0,0 +1,35 @@
1* Chipselect/Local Bus
2
3Properties:
4- name : Should be localbus
5- #address-cells : Should be either two or three. The first cell is the
6 chipselect number, and the remaining cells are the
7 offset into the chipselect.
8- #size-cells : Either one or two, depending on how large each chipselect
9 can be.
10- ranges : Each range corresponds to a single chipselect, and cover
11 the entire access window as configured.
12
13Example:
14 localbus@f0010100 {
15 compatible = "fsl,mpc8272-localbus",
16 "fsl,pq2-localbus";
17 #address-cells = <2>;
18 #size-cells = <1>;
19 reg = <f0010100 40>;
20
21 ranges = <0 0 fe000000 02000000
22 1 0 f4500000 00008000>;
23
24 flash@0,0 {
25 compatible = "jedec-flash";
26 reg = <0 0 2000000>;
27 bank-width = <4>;
28 device-width = <1>;
29 };
30
31 board-control@1,0 {
32 reg = <1 0 20>;
33 compatible = "fsl,mpc8272ads-bcsr";
34 };
35 };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mcm.txt b/Documentation/devicetree/bindings/powerpc/fsl/mcm.txt
new file mode 100644
index 000000000000..4ceda9b3b413
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/mcm.txt
@@ -0,0 +1,64 @@
1=====================================================================
2MPX LAW & Coherency Module Device Tree Binding
3Copyright (C) 2009 Freescale Semiconductor Inc.
4=====================================================================
5
6Local Access Window (LAW) Node
7
8The LAW node represents the region of CCSR space where local access
9windows are configured. For MCM based devices this is the first 4k
10of CCSR space that includes CCSRBAR, ALTCBAR, ALTCAR, BPTR, and some
11number of local access windows as specified by fsl,num-laws.
12
13PROPERTIES
14
15 - compatible
16 Usage: required
17 Value type: <string>
18 Definition: Must include "fsl,mcm-law"
19
20 - reg
21 Usage: required
22 Value type: <prop-encoded-array>
23 Definition: A standard property. The value specifies the
24 physical address offset and length of the CCSR space
25 registers.
26
27 - fsl,num-laws
28 Usage: required
29 Value type: <u32>
30 Definition: The value specifies the number of local access
31 windows for this device.
32
33=====================================================================
34
35MPX Coherency Module Node
36
37The MPX LAW node represents the region of CCSR space where MCM config
38and error reporting registers exist, this is the second 4k (0x1000)
39of CCSR space.
40
41PROPERTIES
42
43 - compatible
44 Usage: required
45 Value type: <string>
46 Definition: Must include "fsl,CHIP-mcm", "fsl,mcm" where
47 CHIP is the processor (mpc8641, mpc8610, etc.)
48
49 - reg
50 Usage: required
51 Value type: <prop-encoded-array>
52 Definition: A standard property. The value specifies the
53 physical address offset and length of the CCSR space
54 registers.
55
56 - interrupts
57 Usage: required
58 Value type: <prop-encoded-array>
59
60 - interrupt-parent
61 Usage: required
62 Value type: <phandle>
63
64=====================================================================
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mcu-mpc8349emitx.txt b/Documentation/devicetree/bindings/powerpc/fsl/mcu-mpc8349emitx.txt
new file mode 100644
index 000000000000..0f766333b6eb
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/mcu-mpc8349emitx.txt
@@ -0,0 +1,17 @@
1Freescale MPC8349E-mITX-compatible Power Management Micro Controller Unit (MCU)
2
3Required properties:
4- compatible : "fsl,<mcu-chip>-<board>", "fsl,mcu-mpc8349emitx".
5- reg : should specify I2C address (0x0a).
6- #gpio-cells : should be 2.
7- gpio-controller : should be present.
8
9Example:
10
11mcu@0a {
12 #gpio-cells = <2>;
13 compatible = "fsl,mc9s08qg8-mpc8349emitx",
14 "fsl,mcu-mpc8349emitx";
15 reg = <0x0a>;
16 gpio-controller;
17};
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpc5121-psc.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpc5121-psc.txt
new file mode 100644
index 000000000000..8832e8798912
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/mpc5121-psc.txt
@@ -0,0 +1,70 @@
1MPC5121 PSC Device Tree Bindings
2
3PSC in UART mode
4----------------
5
6For PSC in UART mode the needed PSC serial devices
7are specified by fsl,mpc5121-psc-uart nodes in the
8fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9Controller node fsl,mpc5121-psc-fifo is requered there:
10
11fsl,mpc5121-psc-uart nodes
12--------------------------
13
14Required properties :
15 - compatible : Should contain "fsl,mpc5121-psc-uart" and "fsl,mpc5121-psc"
16 - cell-index : Index of the PSC in hardware
17 - reg : Offset and length of the register set for the PSC device
18 - interrupts : <a b> where a is the interrupt number of the
19 PSC FIFO Controller and b is a field that represents an
20 encoding of the sense and level information for the interrupt.
21 - interrupt-parent : the phandle for the interrupt controller that
22 services interrupts for this device.
23
24Recommended properties :
25 - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4)
26 - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4)
27
28
29fsl,mpc5121-psc-fifo node
30-------------------------
31
32Required properties :
33 - compatible : Should be "fsl,mpc5121-psc-fifo"
34 - reg : Offset and length of the register set for the PSC
35 FIFO Controller
36 - interrupts : <a b> where a is the interrupt number of the
37 PSC FIFO Controller and b is a field that represents an
38 encoding of the sense and level information for the interrupt.
39 - interrupt-parent : the phandle for the interrupt controller that
40 services interrupts for this device.
41
42
43Example for a board using PSC0 and PSC1 devices in serial mode:
44
45serial@11000 {
46 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
47 cell-index = <0>;
48 reg = <0x11000 0x100>;
49 interrupts = <40 0x8>;
50 interrupt-parent = < &ipic >;
51 fsl,rx-fifo-size = <16>;
52 fsl,tx-fifo-size = <16>;
53};
54
55serial@11100 {
56 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
57 cell-index = <1>;
58 reg = <0x11100 0x100>;
59 interrupts = <40 0x8>;
60 interrupt-parent = < &ipic >;
61 fsl,rx-fifo-size = <16>;
62 fsl,tx-fifo-size = <16>;
63};
64
65pscfifo@11f00 {
66 compatible = "fsl,mpc5121-psc-fifo";
67 reg = <0x11f00 0x100>;
68 interrupts = <40 0x8>;
69 interrupt-parent = < &ipic >;
70};
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpc5200.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpc5200.txt
new file mode 100644
index 000000000000..4ccb2cd5df94
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/mpc5200.txt
@@ -0,0 +1,198 @@
1MPC5200 Device Tree Bindings
2----------------------------
3
4(c) 2006-2009 Secret Lab Technologies Ltd
5Grant Likely <grant.likely@secretlab.ca>
6
7Naming conventions
8------------------
9For mpc5200 on-chip devices, the format for each compatible value is
10<chip>-<device>[-<mode>]. The OS should be able to match a device driver
11to the device based solely on the compatible value. If two drivers
12match on the compatible list; the 'most compatible' driver should be
13selected.
14
15The split between the MPC5200 and the MPC5200B leaves a bit of a
16conundrum. How should the compatible property be set up to provide
17maximum compatibility information; but still accurately describe the
18chip? For the MPC5200; the answer is easy. Most of the SoC devices
19originally appeared on the MPC5200. Since they didn't exist anywhere
20else; the 5200 compatible properties will contain only one item;
21"fsl,mpc5200-<device>".
22
23The 5200B is almost the same as the 5200, but not quite. It fixes
24silicon bugs and it adds a small number of enhancements. Most of the
25devices either provide exactly the same interface as on the 5200. A few
26devices have extra functions but still have a backwards compatible mode.
27To express this information as completely as possible, 5200B device trees
28should have two items in the compatible list:
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
30
31It is *strongly* recommended that 5200B device trees follow this convention
32(instead of only listing the base mpc5200 item).
33
34ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
36
37Modal devices, like PSCs, also append the configured function to the
38end of the compatible field. ie. A PSC in i2s mode would specify
39"fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to
40avoid naming conflicts with non-psc devices providing the same
41function. For example, "fsl,mpc5200-spi" and "fsl,mpc5200-psc-spi" describe
42the mpc5200 simple spi device and a PSC spi mode respectively.
43
44At the time of writing, exact chip may be either 'fsl,mpc5200' or
45'fsl,mpc5200b'.
46
47The soc node
48------------
49This node describes the on chip SOC peripherals. Every mpc5200 based
50board will have this node, and as such there is a common naming
51convention for SOC devices.
52
53Required properties:
54name description
55---- -----------
56ranges Memory range of the internal memory mapped registers.
57 Should be <0 [baseaddr] 0xc000>
58reg Should be <[baseaddr] 0x100>
59compatible mpc5200: "fsl,mpc5200-immr"
60 mpc5200b: "fsl,mpc5200b-immr"
61system-frequency 'fsystem' frequency in Hz; XLB, IPB, USB and PCI
62 clocks are derived from the fsystem clock.
63bus-frequency IPB bus frequency in Hz. Clock rate
64 used by most of the soc devices.
65
66soc child nodes
67---------------
68Any on chip SOC devices available to Linux must appear as soc5200 child nodes.
69
70Note: The tables below show the value for the mpc5200. A mpc5200b device
71tree should use the "fsl,mpc5200b-<device>","fsl,mpc5200-<device>" form.
72
73Required soc5200 child nodes:
74name compatible Description
75---- ---------- -----------
76cdm@<addr> fsl,mpc5200-cdm Clock Distribution
77interrupt-controller@<addr> fsl,mpc5200-pic need an interrupt
78 controller to boot
79bestcomm@<addr> fsl,mpc5200-bestcomm Bestcomm DMA controller
80
81Recommended soc5200 child nodes; populate as needed for your board
82name compatible Description
83---- ---------- -----------
84timer@<addr> fsl,mpc5200-gpt General purpose timers
85gpio@<addr> fsl,mpc5200-gpio MPC5200 simple gpio controller
86gpio@<addr> fsl,mpc5200-gpio-wkup MPC5200 wakeup gpio controller
87rtc@<addr> fsl,mpc5200-rtc Real time clock
88mscan@<addr> fsl,mpc5200-mscan CAN bus controller
89pci@<addr> fsl,mpc5200-pci PCI bridge
90serial@<addr> fsl,mpc5200-psc-uart PSC in serial mode
91i2s@<addr> fsl,mpc5200-psc-i2s PSC in i2s mode
92ac97@<addr> fsl,mpc5200-psc-ac97 PSC in ac97 mode
93spi@<addr> fsl,mpc5200-psc-spi PSC in spi mode
94irda@<addr> fsl,mpc5200-psc-irda PSC in IrDA mode
95spi@<addr> fsl,mpc5200-spi MPC5200 spi device
96ethernet@<addr> fsl,mpc5200-fec MPC5200 ethernet device
97ata@<addr> fsl,mpc5200-ata IDE ATA interface
98i2c@<addr> fsl,mpc5200-i2c I2C controller
99usb@<addr> fsl,mpc5200-ohci,ohci-be USB controller
100xlb@<addr> fsl,mpc5200-xlb XLB arbitrator
101
102fsl,mpc5200-gpt nodes
103---------------------
104On the mpc5200 and 5200b, GPT0 has a watchdog timer function. If the board
105design supports the internal wdt, then the device node for GPT0 should
106include the empty property 'fsl,has-wdt'. Note that this does not activate
107the watchdog. The timer will function as a GPT if the timer api is used, and
108it will function as watchdog if the watchdog device is used. The watchdog
109mode has priority over the gpt mode, i.e. if the watchdog is activated, any
110gpt api call to this timer will fail with -EBUSY.
111
112If you add the property
113 fsl,wdt-on-boot = <n>;
114GPT0 will be marked as in-use watchdog, i.e. blocking every gpt access to it.
115If n>0, the watchdog is started with a timeout of n seconds. If n=0, the
116configuration of the watchdog is not touched. This is useful in two cases:
117- just mark GPT0 as watchdog, blocking gpt accesses, and configure it later;
118- do not touch a configuration assigned by the boot loader which supervises
119 the boot process itself.
120
121The watchdog will respect the CONFIG_WATCHDOG_NOWAYOUT option.
122
123An mpc5200-gpt can be used as a single line GPIO controller. To do so,
124add the following properties to the gpt node:
125 gpio-controller;
126 #gpio-cells = <2>;
127When referencing the GPIO line from another node, the first cell must always
128be zero and the second cell represents the gpio flags and described in the
129gpio device tree binding.
130
131An mpc5200-gpt can be used as a single line edge sensitive interrupt
132controller. To do so, add the following properties to the gpt node:
133 interrupt-controller;
134 #interrupt-cells = <1>;
135When referencing the IRQ line from another node, the cell represents the
136sense mode; 1 for edge rising, 2 for edge falling.
137
138fsl,mpc5200-psc nodes
139---------------------
140The PSCs should include a cell-index which is the index of the PSC in
141hardware. cell-index is used to determine which shared SoC registers to
142use when setting up PSC clocking. cell-index number starts at '0'. ie:
143 PSC1 has 'cell-index = <0>'
144 PSC4 has 'cell-index = <3>'
145
146PSC in i2s mode: The mpc5200 and mpc5200b PSCs are not compatible when in
147i2s mode. An 'mpc5200b-psc-i2s' node cannot include 'mpc5200-psc-i2s' in the
148compatible field.
149
150
151fsl,mpc5200-gpio and fsl,mpc5200-gpio-wkup nodes
152------------------------------------------------
153Each GPIO controller node should have the empty property gpio-controller and
154#gpio-cells set to 2. First cell is the GPIO number which is interpreted
155according to the bit numbers in the GPIO control registers. The second cell
156is for flags which is currently unused.
157
158fsl,mpc5200-fec nodes
159---------------------
160The FEC node can specify one of the following properties to configure
161the MII link:
162- fsl,7-wire-mode - An empty property that specifies the link uses 7-wire
163 mode instead of MII
164- current-speed - Specifies that the MII should be configured for a fixed
165 speed. This property should contain two cells. The
166 first cell specifies the speed in Mbps and the second
167 should be '0' for half duplex and '1' for full duplex
168- phy-handle - Contains a phandle to an Ethernet PHY.
169
170Interrupt controller (fsl,mpc5200-pic) node
171-------------------------------------------
172The mpc5200 pic binding splits hardware IRQ numbers into two levels. The
173split reflects the layout of the PIC hardware itself, which groups
174interrupts into one of three groups; CRIT, MAIN or PERP. Also, the
175Bestcomm dma engine has it's own set of interrupt sources which are
176cascaded off of peripheral interrupt 0, which the driver interprets as a
177fourth group, SDMA.
178
179The interrupts property for device nodes using the mpc5200 pic consists
180of three cells; <L1 L2 level>
181
182 L1 := [CRIT=0, MAIN=1, PERP=2, SDMA=3]
183 L2 := interrupt number; directly mapped from the value in the
184 "ICTL PerStat, MainStat, CritStat Encoded Register"
185 level := [LEVEL_HIGH=0, EDGE_RISING=1, EDGE_FALLING=2, LEVEL_LOW=3]
186
187For external IRQs, use the following interrupt property values (how to
188specify external interrupts is a frequently asked question):
189External interrupts:
190 external irq0: interrupts = <0 0 n>;
191 external irq1: interrupts = <1 1 n>;
192 external irq2: interrupts = <1 2 n>;
193 external irq3: interrupts = <1 3 n>;
194'n' is sense (0: level high, 1: edge rising, 2: edge falling 3: level low)
195
196fsl,mpc5200-mscan nodes
197-----------------------
198See file can.txt in this directory.
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
new file mode 100644
index 000000000000..71e39cf3215b
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
@@ -0,0 +1,42 @@
1* OpenPIC and its interrupt numbers on Freescale's e500/e600 cores
2
3The OpenPIC specification does not specify which interrupt source has to
4become which interrupt number. This is up to the software implementation
5of the interrupt controller. The only requirement is that every
6interrupt source has to have an unique interrupt number / vector number.
7To accomplish this the current implementation assigns the number zero to
8the first source, the number one to the second source and so on until
9all interrupt sources have their unique number.
10Usually the assigned vector number equals the interrupt number mentioned
11in the documentation for a given core / CPU. This is however not true
12for the e500 cores (MPC85XX CPUs) where the documentation distinguishes
13between internal and external interrupt sources and starts counting at
14zero for both of them.
15
16So what to write for external interrupt source X or internal interrupt
17source Y into the device tree? Here is an example:
18
19The memory map for the interrupt controller in the MPC8544[0] shows,
20that the first interrupt source starts at 0x5_0000 (PIC Register Address
21Map-Interrupt Source Configuration Registers). This source becomes the
22number zero therefore:
23 External interrupt 0 = interrupt number 0
24 External interrupt 1 = interrupt number 1
25 External interrupt 2 = interrupt number 2
26 ...
27Every interrupt number allocates 0x20 bytes register space. So to get
28its number it is sufficient to shift the lower 16bits to right by five.
29So for the external interrupt 10 we have:
30 0x0140 >> 5 = 10
31
32After the external sources, the internal sources follow. The in core I2C
33controller on the MPC8544 for instance has the internal source number
3427. Oo obtain its interrupt number we take the lower 16bits of its memory
35address (0x5_0560) and shift it right:
36 0x0560 >> 5 = 43
37
38Therefore the I2C device node for the MPC8544 CPU has to have the
39interrupt number 43 specified in the device tree.
40
41[0] MPC8544E PowerQUICCTM III, Integrated Host Processor Family Reference Manual
42 MPC8544ERM Rev. 1 10/2007
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
new file mode 100644
index 000000000000..bcc30bac6831
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
@@ -0,0 +1,36 @@
1* Freescale MSI interrupt controller
2
3Required properties:
4- compatible : compatible list, contains 2 entries,
5 first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
7 the parent type.
8- reg : should contain the address and the length of the shared message
9 interrupt register set.
10- msi-available-ranges: use <start count> style section to define which
11 msi interrupt can be used in the 256 msi interrupts. This property is
12 optional, without this, all the 256 MSI interrupts can be used.
13- interrupts : each one of the interrupts here is one entry per 32 MSIs,
14 and routed to the host interrupt controller. the interrupts should
15 be set as edge sensitive.
16- interrupt-parent: the phandle for the interrupt controller
17 that services interrupts for this device. for 83xx cpu, the interrupts
18 are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
19 to MPIC.
20
21Example:
22 msi@41600 {
23 compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
24 reg = <0x41600 0x80>;
25 msi-available-ranges = <0 0x100>;
26 interrupts = <
27 0xe0 0
28 0xe1 0
29 0xe2 0
30 0xe3 0
31 0xe4 0
32 0xe5 0
33 0xe6 0
34 0xe7 0>;
35 interrupt-parent = <&mpic>;
36 };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
new file mode 100644
index 000000000000..07256b7ffcaa
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
@@ -0,0 +1,63 @@
1* Power Management Controller
2
3Properties:
4- compatible: "fsl,<chip>-pmc".
5
6 "fsl,mpc8349-pmc" should be listed for any chip whose PMC is
7 compatible. "fsl,mpc8313-pmc" should also be listed for any chip
8 whose PMC is compatible, and implies deep-sleep capability.
9
10 "fsl,mpc8548-pmc" should be listed for any chip whose PMC is
11 compatible. "fsl,mpc8536-pmc" should also be listed for any chip
12 whose PMC is compatible, and implies deep-sleep capability.
13
14 "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
15 compatible; all statements below that apply to "fsl,mpc8548-pmc" also
16 apply to "fsl,mpc8641d-pmc".
17
18 Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these
19 bit assignments are indicated via the sleep specifier in each device's
20 sleep property.
21
22- reg: For devices compatible with "fsl,mpc8349-pmc", the first resource
23 is the PMC block, and the second resource is the Clock Configuration
24 block.
25
26 For devices compatible with "fsl,mpc8548-pmc", the first resource
27 is a 32-byte block beginning with DEVDISR.
28
29- interrupts: For "fsl,mpc8349-pmc"-compatible devices, the first
30 resource is the PMC block interrupt.
31
32- fsl,mpc8313-wakeup-timer: For "fsl,mpc8313-pmc"-compatible devices,
33 this is a phandle to an "fsl,gtm" node on which timer 4 can be used as
34 a wakeup source from deep sleep.
35
36Sleep specifiers:
37
38 fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit
39 that is set in the cell, the corresponding bit in SCCR will be saved
40 and cleared on suspend, and restored on resume. This sleep controller
41 supports disabling and resuming devices at any time.
42
43 fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of
44 which will be ORed into PMCDR upon suspend, and cleared from PMCDR
45 upon resume. The first two cells are as described for fsl,mpc8578-pmc.
46 This sleep controller only supports disabling devices during system
47 sleep, or permanently.
48
49 fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the
50 first of which will be ORed into DEVDISR (and the second into
51 DEVDISR2, if present -- this cell should be zero or absent if the
52 hardware does not have DEVDISR2) upon a request for permanent device
53 disabling. This sleep controller does not support configuring devices
54 to disable during system sleep (unless supported by another compatible
55 match), or dynamically.
56
57Example:
58
59 power@b00 {
60 compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
61 reg = <0xb00 0x100 0xa00 0x100>;
62 interrupts = <80 8>;
63 };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/sec.txt b/Documentation/devicetree/bindings/powerpc/fsl/sec.txt
new file mode 100644
index 000000000000..2b6f2d45c45a
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/sec.txt
@@ -0,0 +1,68 @@
1Freescale SoC SEC Security Engines
2
3Required properties:
4
5- compatible : Should contain entries for this and backward compatible
6 SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0"
7- reg : Offset and length of the register set for the device
8- interrupts : the SEC's interrupt number
9- fsl,num-channels : An integer representing the number of channels
10 available.
11- fsl,channel-fifo-len : An integer representing the number of
12 descriptor pointers each channel fetch fifo can hold.
13- fsl,exec-units-mask : The bitmask representing what execution units
14 (EUs) are available. It's a single 32-bit cell. EU information
15 should be encoded following the SEC's Descriptor Header Dword
16 EU_SEL0 field documentation, i.e. as follows:
17
18 bit 0 = reserved - should be 0
19 bit 1 = set if SEC has the ARC4 EU (AFEU)
20 bit 2 = set if SEC has the DES/3DES EU (DEU)
21 bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
22 bit 4 = set if SEC has the random number generator EU (RNG)
23 bit 5 = set if SEC has the public key EU (PKEU)
24 bit 6 = set if SEC has the AES EU (AESU)
25 bit 7 = set if SEC has the Kasumi EU (KEU)
26 bit 8 = set if SEC has the CRC EU (CRCU)
27 bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B)
28
29remaining bits are reserved for future SEC EUs.
30
31- fsl,descriptor-types-mask : The bitmask representing what descriptors
32 are available. It's a single 32-bit cell. Descriptor type information
33 should be encoded following the SEC's Descriptor Header Dword DESC_TYPE
34 field documentation, i.e. as follows:
35
36 bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
37 bit 1 = set if SEC supports the ipsec_esp descriptor type
38 bit 2 = set if SEC supports the common_nonsnoop desc. type
39 bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
40 bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
41 bit 5 = set if SEC supports the srtp descriptor type
42 bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
43 bit 7 = set if SEC supports the pkeu_assemble descriptor type
44 bit 8 = set if SEC supports the aesu_key_expand_output desc.type
45 bit 9 = set if SEC supports the pkeu_ptmul descriptor type
46 bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
47 bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
48
49 ..and so on and so forth.
50
51Optional properties:
52
53- interrupt-parent : the phandle for the interrupt controller that
54 services interrupts for this device.
55
56Example:
57
58 /* MPC8548E */
59 crypto@30000 {
60 compatible = "fsl,sec2.1", "fsl,sec2.0";
61 reg = <0x30000 0x10000>;
62 interrupts = <29 2>;
63 interrupt-parent = <&mpic>;
64 fsl,num-channels = <4>;
65 fsl,channel-fifo-len = <24>;
66 fsl,exec-units-mask = <0xfe>;
67 fsl,descriptor-types-mask = <0x12b0ebf>;
68 };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ssi.txt b/Documentation/devicetree/bindings/powerpc/fsl/ssi.txt
new file mode 100644
index 000000000000..5ff76c9c57d2
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/ssi.txt
@@ -0,0 +1,73 @@
1Freescale Synchronous Serial Interface
2
3The SSI is a serial device that communicates with audio codecs. It can
4be programmed in AC97, I2S, left-justified, or right-justified modes.
5
6Required properties:
7- compatible: Compatible list, contains "fsl,ssi".
8- cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on.
9- reg: Offset and length of the register set for the device.
10- interrupts: <a b> where a is the interrupt number and b is a
11 field that represents an encoding of the sense and
12 level information for the interrupt. This should be
13 encoded based on the information in section 2)
14 depending on the type of interrupt controller you
15 have.
16- interrupt-parent: The phandle for the interrupt controller that
17 services interrupts for this device.
18- fsl,mode: The operating mode for the SSI interface.
19 "i2s-slave" - I2S mode, SSI is clock slave
20 "i2s-master" - I2S mode, SSI is clock master
21 "lj-slave" - left-justified mode, SSI is clock slave
22 "lj-master" - l.j. mode, SSI is clock master
23 "rj-slave" - right-justified mode, SSI is clock slave
24 "rj-master" - r.j., SSI is clock master
25 "ac97-slave" - AC97 mode, SSI is clock slave
26 "ac97-master" - AC97 mode, SSI is clock master
27- fsl,playback-dma: Phandle to a node for the DMA channel to use for
28 playback of audio. This is typically dictated by SOC
29 design. See the notes below.
30- fsl,capture-dma: Phandle to a node for the DMA channel to use for
31 capture (recording) of audio. This is typically dictated
32 by SOC design. See the notes below.
33- fsl,fifo-depth: The number of elements in the transmit and receive FIFOs.
34 This number is the maximum allowed value for SFCSR[TFWM0].
35- fsl,ssi-asynchronous:
36 If specified, the SSI is to be programmed in asynchronous
37 mode. In this mode, pins SRCK, STCK, SRFS, and STFS must
38 all be connected to valid signals. In synchronous mode,
39 SRCK and SRFS are ignored. Asynchronous mode allows
40 playback and capture to use different sample sizes and
41 sample rates. Some drivers may require that SRCK and STCK
42 be connected together, and SRFS and STFS be connected
43 together. This would still allow different sample sizes,
44 but not different sample rates.
45
46Optional properties:
47- codec-handle: Phandle to a 'codec' node that defines an audio
48 codec connected to this SSI. This node is typically
49 a child of an I2C or other control node.
50
51Child 'codec' node required properties:
52- compatible: Compatible list, contains the name of the codec
53
54Child 'codec' node optional properties:
55- clock-frequency: The frequency of the input clock, which typically comes
56 from an on-board dedicated oscillator.
57
58Notes on fsl,playback-dma and fsl,capture-dma:
59
60On SOCs that have an SSI, specific DMA channels are hard-wired for playback
61and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for
62playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for
63playback and DMA channel 3 for capture. The developer can choose which
64DMA controller to use, but the channels themselves are hard-wired. The
65purpose of these two properties is to represent this hardware design.
66
67The device tree nodes for the DMA channels that are referenced by
68"fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
69"fsl,ssi-dma-channel". The SOC-specific compatible string (e.g.
70"fsl,mpc8610-dma-channel") can remain. If these nodes are left as
71"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel", then the generic Elo DMA
72drivers (fsldma) will attempt to use them, and it will conflict with the
73sound drivers.
diff --git a/Documentation/devicetree/bindings/powerpc/nintendo/gamecube.txt b/Documentation/devicetree/bindings/powerpc/nintendo/gamecube.txt
new file mode 100644
index 000000000000..b558585b1aaf
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/nintendo/gamecube.txt
@@ -0,0 +1,109 @@
1
2Nintendo GameCube device tree
3=============================
4
51) The "flipper" node
6
7 This node represents the multi-function "Flipper" chip, which packages
8 many of the devices found in the Nintendo GameCube.
9
10 Required properties:
11
12 - compatible : Should be "nintendo,flipper"
13
141.a) The Video Interface (VI) node
15
16 Represents the interface between the graphics processor and a external
17 video encoder.
18
19 Required properties:
20
21 - compatible : should be "nintendo,flipper-vi"
22 - reg : should contain the VI registers location and length
23 - interrupts : should contain the VI interrupt
24
251.b) The Processor Interface (PI) node
26
27 Represents the data and control interface between the main processor
28 and graphics and audio processor.
29
30 Required properties:
31
32 - compatible : should be "nintendo,flipper-pi"
33 - reg : should contain the PI registers location and length
34
351.b.i) The "Flipper" interrupt controller node
36
37 Represents the interrupt controller within the "Flipper" chip.
38 The node for the "Flipper" interrupt controller must be placed under
39 the PI node.
40
41 Required properties:
42
43 - compatible : should be "nintendo,flipper-pic"
44
451.c) The Digital Signal Procesor (DSP) node
46
47 Represents the digital signal processor interface, designed to offload
48 audio related tasks.
49
50 Required properties:
51
52 - compatible : should be "nintendo,flipper-dsp"
53 - reg : should contain the DSP registers location and length
54 - interrupts : should contain the DSP interrupt
55
561.c.i) The Auxiliary RAM (ARAM) node
57
58 Represents the non cpu-addressable ram designed mainly to store audio
59 related information.
60 The ARAM node must be placed under the DSP node.
61
62 Required properties:
63
64 - compatible : should be "nintendo,flipper-aram"
65 - reg : should contain the ARAM start (zero-based) and length
66
671.d) The Disk Interface (DI) node
68
69 Represents the interface used to communicate with mass storage devices.
70
71 Required properties:
72
73 - compatible : should be "nintendo,flipper-di"
74 - reg : should contain the DI registers location and length
75 - interrupts : should contain the DI interrupt
76
771.e) The Audio Interface (AI) node
78
79 Represents the interface to the external 16-bit stereo digital-to-analog
80 converter.
81
82 Required properties:
83
84 - compatible : should be "nintendo,flipper-ai"
85 - reg : should contain the AI registers location and length
86 - interrupts : should contain the AI interrupt
87
881.f) The Serial Interface (SI) node
89
90 Represents the interface to the four single bit serial interfaces.
91 The SI is a proprietary serial interface used normally to control gamepads.
92 It's NOT a RS232-type interface.
93
94 Required properties:
95
96 - compatible : should be "nintendo,flipper-si"
97 - reg : should contain the SI registers location and length
98 - interrupts : should contain the SI interrupt
99
1001.g) The External Interface (EXI) node
101
102 Represents the multi-channel SPI-like interface.
103
104 Required properties:
105
106 - compatible : should be "nintendo,flipper-exi"
107 - reg : should contain the EXI registers location and length
108 - interrupts : should contain the EXI interrupt
109
diff --git a/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt b/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt
new file mode 100644
index 000000000000..a7e155a023b8
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt
@@ -0,0 +1,184 @@
1
2Nintendo Wii device tree
3========================
4
50) The root node
6
7 This node represents the Nintendo Wii video game console.
8
9 Required properties:
10
11 - model : Should be "nintendo,wii"
12 - compatible : Should be "nintendo,wii"
13
141) The "hollywood" node
15
16 This node represents the multi-function "Hollywood" chip, which packages
17 many of the devices found in the Nintendo Wii.
18
19 Required properties:
20
21 - compatible : Should be "nintendo,hollywood"
22
231.a) The Video Interface (VI) node
24
25 Represents the interface between the graphics processor and a external
26 video encoder.
27
28 Required properties:
29
30 - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi"
31 - reg : should contain the VI registers location and length
32 - interrupts : should contain the VI interrupt
33
341.b) The Processor Interface (PI) node
35
36 Represents the data and control interface between the main processor
37 and graphics and audio processor.
38
39 Required properties:
40
41 - compatible : should be "nintendo,hollywood-pi","nintendo,flipper-pi"
42 - reg : should contain the PI registers location and length
43
441.b.i) The "Flipper" interrupt controller node
45
46 Represents the "Flipper" interrupt controller within the "Hollywood" chip.
47 The node for the "Flipper" interrupt controller must be placed under
48 the PI node.
49
50 Required properties:
51
52 - #interrupt-cells : <1>
53 - compatible : should be "nintendo,flipper-pic"
54 - interrupt-controller
55
561.c) The Digital Signal Procesor (DSP) node
57
58 Represents the digital signal processor interface, designed to offload
59 audio related tasks.
60
61 Required properties:
62
63 - compatible : should be "nintendo,hollywood-dsp","nintendo,flipper-dsp"
64 - reg : should contain the DSP registers location and length
65 - interrupts : should contain the DSP interrupt
66
671.d) The Serial Interface (SI) node
68
69 Represents the interface to the four single bit serial interfaces.
70 The SI is a proprietary serial interface used normally to control gamepads.
71 It's NOT a RS232-type interface.
72
73 Required properties:
74
75 - compatible : should be "nintendo,hollywood-si","nintendo,flipper-si"
76 - reg : should contain the SI registers location and length
77 - interrupts : should contain the SI interrupt
78
791.e) The Audio Interface (AI) node
80
81 Represents the interface to the external 16-bit stereo digital-to-analog
82 converter.
83
84 Required properties:
85
86 - compatible : should be "nintendo,hollywood-ai","nintendo,flipper-ai"
87 - reg : should contain the AI registers location and length
88 - interrupts : should contain the AI interrupt
89
901.f) The External Interface (EXI) node
91
92 Represents the multi-channel SPI-like interface.
93
94 Required properties:
95
96 - compatible : should be "nintendo,hollywood-exi","nintendo,flipper-exi"
97 - reg : should contain the EXI registers location and length
98 - interrupts : should contain the EXI interrupt
99
1001.g) The Open Host Controller Interface (OHCI) nodes
101
102 Represent the USB 1.x Open Host Controller Interfaces.
103
104 Required properties:
105
106 - compatible : should be "nintendo,hollywood-usb-ohci","usb-ohci"
107 - reg : should contain the OHCI registers location and length
108 - interrupts : should contain the OHCI interrupt
109
1101.h) The Enhanced Host Controller Interface (EHCI) node
111
112 Represents the USB 2.0 Enhanced Host Controller Interface.
113
114 Required properties:
115
116 - compatible : should be "nintendo,hollywood-usb-ehci","usb-ehci"
117 - reg : should contain the EHCI registers location and length
118 - interrupts : should contain the EHCI interrupt
119
1201.i) The Secure Digital Host Controller Interface (SDHCI) nodes
121
122 Represent the Secure Digital Host Controller Interfaces.
123
124 Required properties:
125
126 - compatible : should be "nintendo,hollywood-sdhci","sdhci"
127 - reg : should contain the SDHCI registers location and length
128 - interrupts : should contain the SDHCI interrupt
129
1301.j) The Inter-Processsor Communication (IPC) node
131
132 Represent the Inter-Processor Communication interface. This interface
133 enables communications between the Broadway and the Starlet processors.
134
135 - compatible : should be "nintendo,hollywood-ipc"
136 - reg : should contain the IPC registers location and length
137 - interrupts : should contain the IPC interrupt
138
1391.k) The "Hollywood" interrupt controller node
140
141 Represents the "Hollywood" interrupt controller within the
142 "Hollywood" chip.
143
144 Required properties:
145
146 - #interrupt-cells : <1>
147 - compatible : should be "nintendo,hollywood-pic"
148 - reg : should contain the controller registers location and length
149 - interrupt-controller
150 - interrupts : should contain the cascade interrupt of the "flipper" pic
151 - interrupt-parent: should contain the phandle of the "flipper" pic
152
1531.l) The General Purpose I/O (GPIO) controller node
154
155 Represents the dual access 32 GPIO controller interface.
156
157 Required properties:
158
159 - #gpio-cells : <2>
160 - compatible : should be "nintendo,hollywood-gpio"
161 - reg : should contain the IPC registers location and length
162 - gpio-controller
163
1641.m) The control node
165
166 Represents the control interface used to setup several miscellaneous
167 settings of the "Hollywood" chip like boot memory mappings, resets,
168 disk interface mode, etc.
169
170 Required properties:
171
172 - compatible : should be "nintendo,hollywood-control"
173 - reg : should contain the control registers location and length
174
1751.n) The Disk Interface (DI) node
176
177 Represents the interface used to communicate with mass storage devices.
178
179 Required properties:
180
181 - compatible : should be "nintendo,hollywood-di"
182 - reg : should contain the DI registers location and length
183 - interrupts : should contain the DI interrupt
184
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