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1 | Sharp Microelectronics 10.1" WQXGA TFT LCD panel | ||
2 | |||
3 | This panel requires a dual-channel DSI host to operate. It supports two modes: | ||
4 | - left-right: each channel drives the left or right half of the screen | ||
5 | - even-odd: each channel drives the even or odd lines of the screen | ||
6 | |||
7 | Each of the DSI channels controls a separate DSI peripheral. The peripheral | ||
8 | driven by the first link (DSI-LINK1), left or even, is considered the primary | ||
9 | peripheral and controls the device. The 'link2' property contains a phandle | ||
10 | to the peripheral driven by the second link (DSI-LINK2, right or odd). | ||
11 | |||
12 | Note that in video mode the DSI-LINK1 interface always provides the left/even | ||
13 | pixels and DSI-LINK2 always provides the right/odd pixels. In command mode it | ||
14 | is possible to program either link to drive the left/even or right/odd pixels | ||
15 | but for the sake of consistency this binding assumes that the same assignment | ||
16 | is chosen as for video mode. | ||
17 | |||
18 | Required properties: | ||
19 | - compatible: should be "sharp,lq101r1sx01" | ||
20 | - reg: DSI virtual channel of the peripheral | ||
21 | |||
22 | Required properties (for DSI-LINK1 only): | ||
23 | - link2: phandle to the DSI peripheral on the secondary link. Note that the | ||
24 | presence of this property marks the containing node as DSI-LINK1. | ||
25 | - power-supply: phandle of the regulator that provides the supply voltage | ||
26 | |||
27 | Optional properties (for DSI-LINK1 only): | ||
28 | - backlight: phandle of the backlight device attached to the panel | ||
29 | |||
30 | Example: | ||
31 | |||
32 | dsi@54300000 { | ||
33 | panel: panel@0 { | ||
34 | compatible = "sharp,lq101r1sx01"; | ||
35 | reg = <0>; | ||
36 | |||
37 | link2 = <&secondary>; | ||
38 | |||
39 | power-supply = <...>; | ||
40 | backlight = <...>; | ||
41 | }; | ||
42 | }; | ||
43 | |||
44 | dsi@54400000 { | ||
45 | secondary: panel@0 { | ||
46 | compatible = "sharp,lq101r1sx01"; | ||
47 | reg = <0>; | ||
48 | }; | ||
49 | }; | ||