1 files changed, 9 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt
index 458b57f199af..9dce540771fb 100644
--- a/Documentation/devicetree/bindings/mmc/mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/mmc.txt
@@ -26,9 +26,18 @@ Optional properties:
  this system, even if the controller claims it is.
 - cap-sd-highspeed: SD high-speed timing is supported
 - cap-mmc-highspeed: MMC high-speed timing is supported
+- sd-uhs-sdr12: SD UHS SDR12 speed is supported
+- sd-uhs-sdr25: SD UHS SDR25 speed is supported
+- sd-uhs-sdr50: SD UHS SDR50 speed is supported
+- sd-uhs-sdr104: SD UHS SDR104 speed is supported
+- sd-uhs-ddr50: SD UHS DDR50 speed is supported
 - cap-power-off-card: powering off the card is safe
 - cap-sdio-irq: enable SDIO IRQ signalling on this interface
 - full-pwr-cycle: full power cycle of the card is supported
+- mmc-highspeed-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported
+- mmc-highspeed-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported
+- mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported
+- mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported
 *NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line
 polarity properties, we have to fix the meaning of the "normal" and "inverted"

diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt index 458b57f199af..9dce540771fb 100644 --- a/Documentation/devicetree/bindings/mmc/mmc.txt +++ b/Documentation/devicetree/bindings/mmc/mmc.txt
@@ -26,9 +26,18 @@ Optional properties:
26	this system, even if the controller claims it is.	26	this system, even if the controller claims it is.
27	- cap-sd-highspeed: SD high-speed timing is supported	27	- cap-sd-highspeed: SD high-speed timing is supported
28	- cap-mmc-highspeed: MMC high-speed timing is supported	28	- cap-mmc-highspeed: MMC high-speed timing is supported
		29	- sd-uhs-sdr12: SD UHS SDR12 speed is supported
		30	- sd-uhs-sdr25: SD UHS SDR25 speed is supported
		31	- sd-uhs-sdr50: SD UHS SDR50 speed is supported
		32	- sd-uhs-sdr104: SD UHS SDR104 speed is supported
		33	- sd-uhs-ddr50: SD UHS DDR50 speed is supported
29	- cap-power-off-card: powering off the card is safe	34	- cap-power-off-card: powering off the card is safe
30	- cap-sdio-irq: enable SDIO IRQ signalling on this interface	35	- cap-sdio-irq: enable SDIO IRQ signalling on this interface
31	- full-pwr-cycle: full power cycle of the card is supported	36	- full-pwr-cycle: full power cycle of the card is supported
		37	- mmc-highspeed-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported
		38	- mmc-highspeed-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported
		39	- mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported
		40	- mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported
32		41
33	NOTE on CD and WP polarity. To use common for all SD/MMC host controllers line	42	NOTE on CD and WP polarity. To use common for all SD/MMC host controllers line
34	polarity properties, we have to fix the meaning of the "normal" and "inverted"	43	polarity properties, we have to fix the meaning of the "normal" and "inverted"