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1 | * ARM System MMU Architecture Implementation | ||
2 | |||
3 | ARM SoCs may contain an implementation of the ARM System Memory | ||
4 | Management Unit Architecture, which can be used to provide 1 or 2 stages | ||
5 | of address translation to bus masters external to the CPU. | ||
6 | |||
7 | The SMMU may also raise interrupts in response to various fault | ||
8 | conditions. | ||
9 | |||
10 | ** System MMU required properties: | ||
11 | |||
12 | - compatible : Should be one of: | ||
13 | |||
14 | "arm,smmu-v1" | ||
15 | "arm,smmu-v2" | ||
16 | "arm,mmu-400" | ||
17 | "arm,mmu-500" | ||
18 | |||
19 | depending on the particular implementation and/or the | ||
20 | version of the architecture implemented. | ||
21 | |||
22 | - reg : Base address and size of the SMMU. | ||
23 | |||
24 | - #global-interrupts : The number of global interrupts exposed by the | ||
25 | device. | ||
26 | |||
27 | - interrupts : Interrupt list, with the first #global-irqs entries | ||
28 | corresponding to the global interrupts and any | ||
29 | following entries corresponding to context interrupts, | ||
30 | specified in order of their indexing by the SMMU. | ||
31 | |||
32 | For SMMUv2 implementations, there must be exactly one | ||
33 | interrupt per context bank. In the case of a single, | ||
34 | combined interrupt, it must be listed multiple times. | ||
35 | |||
36 | - mmu-masters : A list of phandles to device nodes representing bus | ||
37 | masters for which the SMMU can provide a translation | ||
38 | and their corresponding StreamIDs (see example below). | ||
39 | Each device node linked from this list must have a | ||
40 | "#stream-id-cells" property, indicating the number of | ||
41 | StreamIDs associated with it. | ||
42 | |||
43 | ** System MMU optional properties: | ||
44 | |||
45 | - smmu-parent : When multiple SMMUs are chained together, this | ||
46 | property can be used to provide a phandle to the | ||
47 | parent SMMU (that is the next SMMU on the path going | ||
48 | from the mmu-masters towards memory) node for this | ||
49 | SMMU. | ||
50 | |||
51 | Example: | ||
52 | |||
53 | smmu { | ||
54 | compatible = "arm,smmu-v1"; | ||
55 | reg = <0xba5e0000 0x10000>; | ||
56 | #global-interrupts = <2>; | ||
57 | interrupts = <0 32 4>, | ||
58 | <0 33 4>, | ||
59 | <0 34 4>, /* This is the first context interrupt */ | ||
60 | <0 35 4>, | ||
61 | <0 36 4>, | ||
62 | <0 37 4>; | ||
63 | |||
64 | /* | ||
65 | * Two DMA controllers, the first with two StreamIDs (0xd01d | ||
66 | * and 0xd01e) and the second with only one (0xd11c). | ||
67 | */ | ||
68 | mmu-masters = <&dma0 0xd01d 0xd01e>, | ||
69 | <&dma1 0xd11c>; | ||
70 | }; | ||