7 files changed, 335 insertions, 2 deletions

diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
index e577196a12c0..4659fd952301 100644
--- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
+++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
@@ -47,6 +47,7 @@ The full ID of peripheral types can be found below.
         20      ASRC
         21      ESAI
         22      SSI Dual FIFO   (needs firmware ver >= 2)
+        23      Shared ASRC
 
 The third cell specifies the transfer priority as below.
 
diff --git a/Documentation/devicetree/bindings/dma/mpc512x-dma.txt b/Documentation/devicetree/bindings/dma/mpc512x-dma.txt
new file mode 100644
index 000000000000..a6511df165c5
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mpc512x-dma.txt
@@ -0,0 +1,29 @@
+* Freescale MPC512x and MPC8308 DMA Controller
+
+The DMA controller in Freescale MPC512x and MPC8308 SoCs can move
+blocks of memory contents between memory and peripherals or
+from memory to memory.
+
+Refer to "Generic DMA Controller and DMA request bindings" in
+the dma/dma.txt file for a more detailed description of binding.
+
+Required properties:
+- compatible: should be "fsl,mpc5121-dma" or "fsl,mpc8308-dma";
+- reg: should contain the DMA controller registers location and length;
+- interrupt for the DMA controller: syntax of interrupt client node
+        is described in interrupt-controller/interrupts.txt file.
+- #dma-cells: the length of the DMA specifier, must be <1>.
+        Each channel of this DMA controller has a peripheral request line,
+        the assignment is fixed in hardware. This one cell
+        in dmas property of a client device represents the channel number.
+
+Example:
+
+        dma0: dma@14000 {
+                compatible = "fsl,mpc5121-dma";
+                reg = <0x14000 0x1800>;
+                interrupts = <65 0x8>;
+                #dma-cells = <1>;
+        };
+
+DMA clients must use the format described in dma/dma.txt file.
diff --git a/Documentation/devicetree/bindings/dma/nbpfaxi.txt b/Documentation/devicetree/bindings/dma/nbpfaxi.txt
new file mode 100644
index 000000000000..d5e2522b9ec1
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/nbpfaxi.txt
@@ -0,0 +1,61 @@
+* Renesas "Type-AXI" NBPFAXI* DMA controllers
+
+* DMA controller
+
+Required properties
+
+- compatible:   must be one of
+                "renesas,nbpfaxi64dmac1b4"
+                "renesas,nbpfaxi64dmac1b8"
+                "renesas,nbpfaxi64dmac1b16"
+                "renesas,nbpfaxi64dmac4b4"
+                "renesas,nbpfaxi64dmac4b8"
+                "renesas,nbpfaxi64dmac4b16"
+                "renesas,nbpfaxi64dmac8b4"
+                "renesas,nbpfaxi64dmac8b8"
+                "renesas,nbpfaxi64dmac8b16"
+- #dma-cells:   must be 2: the first integer is a terminal number, to which this
+                slave is connected, the second one is flags. Flags is a bitmask
+                with the following bits defined:
+
+#define NBPF_SLAVE_RQ_HIGH      1
+#define NBPF_SLAVE_RQ_LOW       2
+#define NBPF_SLAVE_RQ_LEVEL     4
+
+Optional properties:
+
+You can use dma-channels and dma-requests as described in dma.txt, although they
+won't be used, this information is derived from the compatibility string.
+
+Example:
+
+        dma: dma-controller@48000000 {
+                compatible = "renesas,nbpfaxi64dmac8b4";
+                reg = <0x48000000 0x400>;
+                interrupts = <0 12 0x4
+                              0 13 0x4
+                              0 14 0x4
+                              0 15 0x4
+                              0 16 0x4
+                              0 17 0x4
+                              0 18 0x4
+                              0 19 0x4>;
+                #dma-cells = <2>;
+                dma-channels = <8>;
+                dma-requests = <8>;
+        };
+
+* DMA client
+
+Required properties:
+
+dmas and dma-names are required, as described in dma.txt.
+
+Example:
+
+#include <dt-bindings/dma/nbpfaxi.h>
+
+...
+                dmas = <&dma 0 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)
+                        &dma 1 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
+                dma-names = "rx", "tx";
diff --git a/Documentation/devicetree/bindings/dma/rcar-audmapp.txt b/Documentation/devicetree/bindings/dma/rcar-audmapp.txt
new file mode 100644
index 000000000000..9f1d750d76de
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/rcar-audmapp.txt
@@ -0,0 +1,29 @@
+* R-Car Audio DMAC peri peri Device Tree bindings
+
+Required properties:
+- compatible:   should be "renesas,rcar-audmapp"
+- #dma-cells:   should be <1>, see "dmas" property below
+
+Example:
+        audmapp: audio-dma-pp@0xec740000 {
+                compatible = "renesas,rcar-audmapp";
+                #dma-cells = <1>;
+
+                reg = <0 0xec740000 0 0x200>;
+        };
+
+
+* DMA client
+
+Required properties:
+- dmas:         a list of <[DMA multiplexer phandle] [SRS/DRS value]> pairs,
+                where SRS/DRS values are fixed handles, specified in the SoC
+                manual as the value that would be written into the PDMACHCR.
+- dma-names:    a list of DMA channel names, one per "dmas" entry
+
+Example:
+
+        dmas = <&audmapp 0x2d00
+                &audmapp 0x3700>;
+        dma-names =  "src0_ssiu0",
+                     "dvc0_ssiu0";
diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
new file mode 100644
index 000000000000..df0f48bcf75a
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
@@ -0,0 +1,98 @@
+* Renesas R-Car DMA Controller Device Tree bindings
+
+Renesas R-Car Generation 2 SoCs have have multiple multi-channel DMA
+controller instances named DMAC capable of serving multiple clients. Channels
+can be dedicated to specific clients or shared between a large number of
+clients.
+
+DMA clients are connected to the DMAC ports referenced by an 8-bit identifier
+called MID/RID.
+
+Each DMA client is connected to one dedicated port of the DMAC, identified by
+an 8-bit port number called the MID/RID. A DMA controller can thus serve up to
+256 clients in total. When the number of hardware channels is lower than the
+number of clients to be served, channels must be shared between multiple DMA
+clients. The association of DMA clients to DMAC channels is fully dynamic and
+not described in these device tree bindings.
+
+Required Properties:
+
+- compatible: must contain "renesas,rcar-dmac"
+
+- reg: base address and length of the registers block for the DMAC
+
+- interrupts: interrupt specifiers for the DMAC, one for each entry in
+  interrupt-names.
+- interrupt-names: one entry per channel, named "ch%u", where %u is the
+  channel number ranging from zero to the number of channels minus one.
+
+- clock-names: "fck" for the functional clock
+- clocks: a list of phandle + clock-specifier pairs, one for each entry
+  in clock-names.
+- clock-names: must contain "fck" for the functional clock.
+
+- #dma-cells: must be <1>, the cell specifies the MID/RID of the DMAC port
+  connected to the DMA client
+- dma-channels: number of DMA channels
+
+Example: R8A7790 (R-Car H2) SYS-DMACs
+
+        dmac0: dma-controller@e6700000 {
+                compatible = "renesas,rcar-dmac";
+                reg = <0 0xe6700000 0 0x20000>;
+                interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
+                              0 200 IRQ_TYPE_LEVEL_HIGH
+                              0 201 IRQ_TYPE_LEVEL_HIGH
+                              0 202 IRQ_TYPE_LEVEL_HIGH
+                              0 203 IRQ_TYPE_LEVEL_HIGH
+                              0 204 IRQ_TYPE_LEVEL_HIGH
+                              0 205 IRQ_TYPE_LEVEL_HIGH
+                              0 206 IRQ_TYPE_LEVEL_HIGH
+                              0 207 IRQ_TYPE_LEVEL_HIGH
+                              0 208 IRQ_TYPE_LEVEL_HIGH
+                              0 209 IRQ_TYPE_LEVEL_HIGH
+                              0 210 IRQ_TYPE_LEVEL_HIGH
+                              0 211 IRQ_TYPE_LEVEL_HIGH
+                              0 212 IRQ_TYPE_LEVEL_HIGH
+                              0 213 IRQ_TYPE_LEVEL_HIGH
+                              0 214 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error",
+                                "ch0", "ch1", "ch2", "ch3",
+                                "ch4", "ch5", "ch6", "ch7",
+                                "ch8", "ch9", "ch10", "ch11",
+                                "ch12", "ch13", "ch14";
+                clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
+                clock-names = "fck";
+                #dma-cells = <1>;
+                dma-channels = <15>;
+        };
+
+        dmac1: dma-controller@e6720000 {
+                compatible = "renesas,rcar-dmac";
+                reg = <0 0xe6720000 0 0x20000>;
+                interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
+                              0 216 IRQ_TYPE_LEVEL_HIGH
+                              0 217 IRQ_TYPE_LEVEL_HIGH
+                              0 218 IRQ_TYPE_LEVEL_HIGH
+                              0 219 IRQ_TYPE_LEVEL_HIGH
+                              0 308 IRQ_TYPE_LEVEL_HIGH
+                              0 309 IRQ_TYPE_LEVEL_HIGH
+                              0 310 IRQ_TYPE_LEVEL_HIGH
+                              0 311 IRQ_TYPE_LEVEL_HIGH
+                              0 312 IRQ_TYPE_LEVEL_HIGH
+                              0 313 IRQ_TYPE_LEVEL_HIGH
+                              0 314 IRQ_TYPE_LEVEL_HIGH
+                              0 315 IRQ_TYPE_LEVEL_HIGH
+                              0 316 IRQ_TYPE_LEVEL_HIGH
+                              0 317 IRQ_TYPE_LEVEL_HIGH
+                              0 318 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error",
+                                "ch0", "ch1", "ch2", "ch3",
+                                "ch4", "ch5", "ch6", "ch7",
+                                "ch8", "ch9", "ch10", "ch11",
+                                "ch12", "ch13", "ch14";
+                clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
+                clock-names = "fck";
+                #dma-cells = <1>;
+                dma-channels = <15>;
+        };
diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
index 1f5729f10621..95800ab37bb0 100644
--- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
+++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
@@ -35,9 +35,11 @@ Required properties:
 
 Each dmas request consists of 4 cells:
   1. A phandle pointing to the DMA controller
-  2. Device Type
+  2. Device signal number, the signal line for single and burst requests
+     connected from the device to the DMA40 engine
   3. The DMA request line number (only when 'use fixed channel' is set)
-  4. A 32bit mask specifying; mode, direction and endianness [NB: This list will grow]
+  4. A 32bit mask specifying; mode, direction and endianness
+     [NB: This list will grow]
         0x00000001: Mode:
                 Logical channel when unset
                 Physical channel when set
@@ -54,6 +56,74 @@ Each dmas request consists of 4 cells:
                 Normal priority when unset
                 High priority when set
 
+Existing signal numbers for the DB8500 ASIC. Unless specified, the signals are
+bidirectional, i.e. the same for RX and TX operations:
+
+0:  SPI controller 0
+1:  SD/MMC controller 0 (unused)
+2:  SD/MMC controller 1 (unused)
+3:  SD/MMC controller 2 (unused)
+4:  I2C port 1
+5:  I2C port 3
+6:  I2C port 2
+7:  I2C port 4
+8:  Synchronous Serial Port SSP0
+9:  Synchronous Serial Port SSP1
+10: Multi-Channel Display Engine MCDE RX
+11: UART port 2
+12: UART port 1
+13: UART port 0
+14: Multirate Serial Port MSP2
+15: I2C port 0
+16: USB OTG in/out endpoints 7 & 15
+17: USB OTG in/out endpoints 6 & 14
+18: USB OTG in/out endpoints 5 & 13
+19: USB OTG in/out endpoints 4 & 12
+20: SLIMbus or HSI channel 0
+21: SLIMbus or HSI channel 1
+22: SLIMbus or HSI channel 2
+23: SLIMbus or HSI channel 3
+24: Multimedia DSP SXA0
+25: Multimedia DSP SXA1
+26: Multimedia DSP SXA2
+27: Multimedia DSP SXA3
+28: SD/MM controller 2
+29: SD/MM controller 0
+30: MSP port 1 on DB8500 v1, MSP port 3 on DB8500 v2
+31: MSP port 0 or SLIMbus channel 0
+32: SD/MM controller 1
+33: SPI controller 2
+34: i2c3 RX2 TX2
+35: SPI controller 1
+36: USB OTG in/out endpoints 3 & 11
+37: USB OTG in/out endpoints 2 & 10
+38: USB OTG in/out endpoints 1 & 9
+39: USB OTG in/out endpoints 8
+40: SPI controller 3
+41: SD/MM controller 3
+42: SD/MM controller 4
+43: SD/MM controller 5
+44: Multimedia DSP SXA4
+45: Multimedia DSP SXA5
+46: SLIMbus channel 8 or Multimedia DSP SXA6
+47: SLIMbus channel 9 or Multimedia DSP SXA7
+48: Crypto Accelerator 1
+49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
+50: Hash Accelerator 1 TX
+51: memcpy TX (to be used by the DMA driver for memcpy operations)
+52: SLIMbus or HSI channel 4
+53: SLIMbus or HSI channel 5
+54: SLIMbus or HSI channel 6
+55: SLIMbus or HSI channel 7
+56: memcpy (to be used by the DMA driver for memcpy operations)
+57: memcpy (to be used by the DMA driver for memcpy operations)
+58: memcpy (to be used by the DMA driver for memcpy operations)
+59: memcpy (to be used by the DMA driver for memcpy operations)
+60: memcpy (to be used by the DMA driver for memcpy operations)
+61: Crypto Accelerator 0
+62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
+63: Hash Accelerator 0 TX
+
 Example:
 
         uart@80120000 {
diff --git a/Documentation/devicetree/bindings/dma/sun6i-dma.txt b/Documentation/devicetree/bindings/dma/sun6i-dma.txt
new file mode 100644
index 000000000000..3e145c1675b1
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/sun6i-dma.txt
@@ -0,0 +1,45 @@
+Allwinner A31 DMA Controller
+
+This driver follows the generic DMA bindings defined in dma.txt.
+
+Required properties:
+
+- compatible:   Must be "allwinner,sun6i-a31-dma"
+- reg:          Should contain the registers base address and length
+- interrupts:   Should contain a reference to the interrupt used by this device
+- clocks:       Should contain a reference to the parent AHB clock
+- resets:       Should contain a reference to the reset controller asserting
+                this device in reset
+- #dma-cells :  Should be 1, a single cell holding a line request number
+
+Example:
+        dma: dma-controller@01c02000 {
+                compatible = "allwinner,sun6i-a31-dma";
+                reg = <0x01c02000 0x1000>;
+                interrupts = <0 50 4>;
+                clocks = <&ahb1_gates 6>;
+                resets = <&ahb1_rst 6>;
+                #dma-cells = <1>;
+        };
+
+Clients:
+
+DMA clients connected to the A31 DMA controller must use the format
+described in the dma.txt file, using a two-cell specifier for each
+channel: a phandle plus one integer cells.
+The two cells in order are:
+
+1. A phandle pointing to the DMA controller.
+2. The port ID as specified in the datasheet
+
+Example:
+spi2: spi@01c6a000 {
+        compatible = "allwinner,sun6i-a31-spi";
+        reg = <0x01c6a000 0x1000>;
+        interrupts = <0 67 4>;
+        clocks = <&ahb1_gates 22>, <&spi2_clk>;
+        clock-names = "ahb", "mod";
+        dmas = <&dma 25>, <&dma 25>;
+        dma-names = "rx", "tx";
+        resets = <&ahb1_rst 22>;
+};