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-rw-r--r--Documentation/devicetree/bindings/clock/imx23-clock.txt2
-rw-r--r--Documentation/devicetree/bindings/clock/imx25-clock.txt162
-rw-r--r--Documentation/devicetree/bindings/clock/imx28-clock.txt4
-rw-r--r--Documentation/devicetree/bindings/clock/imx5-clock.txt191
-rw-r--r--Documentation/devicetree/bindings/clock/imx6q-clock.txt9
-rw-r--r--Documentation/devicetree/bindings/clock/zynq-7000.txt55
6 files changed, 418 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx23-clock.txt b/Documentation/devicetree/bindings/clock/imx23-clock.txt
index a0b867ef8d96..baadbb11fe98 100644
--- a/Documentation/devicetree/bindings/clock/imx23-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx23-clock.txt
@@ -52,7 +52,7 @@ clocks and IDs.
52 lcdif 38 52 lcdif 38
53 etm 39 53 etm 39
54 usb 40 54 usb 40
55 usb_pwr 41 55 usb_phy 41
56 56
57Examples: 57Examples:
58 58
diff --git a/Documentation/devicetree/bindings/clock/imx25-clock.txt b/Documentation/devicetree/bindings/clock/imx25-clock.txt
new file mode 100644
index 000000000000..c2a3525ecb4e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx25-clock.txt
@@ -0,0 +1,162 @@
1* Clock bindings for Freescale i.MX25
2
3Required properties:
4- compatible: Should be "fsl,imx25-ccm"
5- reg: Address and length of the register set
6- interrupts: Should contain CCM interrupt
7- #clock-cells: Should be <1>
8
9The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell. The following is a full list of i.MX25
11clocks and IDs.
12
13 Clock ID
14 ---------------------------
15 dummy 0
16 osc 1
17 mpll 2
18 upll 3
19 mpll_cpu_3_4 4
20 cpu_sel 5
21 cpu 6
22 ahb 7
23 usb_div 8
24 ipg 9
25 per0_sel 10
26 per1_sel 11
27 per2_sel 12
28 per3_sel 13
29 per4_sel 14
30 per5_sel 15
31 per6_sel 16
32 per7_sel 17
33 per8_sel 18
34 per9_sel 19
35 per10_sel 20
36 per11_sel 21
37 per12_sel 22
38 per13_sel 23
39 per14_sel 24
40 per15_sel 25
41 per0 26
42 per1 27
43 per2 28
44 per3 29
45 per4 30
46 per5 31
47 per6 32
48 per7 33
49 per8 34
50 per9 35
51 per10 36
52 per11 37
53 per12 38
54 per13 39
55 per14 40
56 per15 41
57 csi_ipg_per 42
58 epit_ipg_per 43
59 esai_ipg_per 44
60 esdhc1_ipg_per 45
61 esdhc2_ipg_per 46
62 gpt_ipg_per 47
63 i2c_ipg_per 48
64 lcdc_ipg_per 49
65 nfc_ipg_per 50
66 owire_ipg_per 51
67 pwm_ipg_per 52
68 sim1_ipg_per 53
69 sim2_ipg_per 54
70 ssi1_ipg_per 55
71 ssi2_ipg_per 56
72 uart_ipg_per 57
73 ata_ahb 58
74 reserved 59
75 csi_ahb 60
76 emi_ahb 61
77 esai_ahb 62
78 esdhc1_ahb 63
79 esdhc2_ahb 64
80 fec_ahb 65
81 lcdc_ahb 66
82 rtic_ahb 67
83 sdma_ahb 68
84 slcdc_ahb 69
85 usbotg_ahb 70
86 reserved 71
87 reserved 72
88 reserved 73
89 reserved 74
90 can1_ipg 75
91 can2_ipg 76
92 csi_ipg 77
93 cspi1_ipg 78
94 cspi2_ipg 79
95 cspi3_ipg 80
96 dryice_ipg 81
97 ect_ipg 82
98 epit1_ipg 83
99 epit2_ipg 84
100 reserved 85
101 esdhc1_ipg 86
102 esdhc2_ipg 87
103 fec_ipg 88
104 reserved 89
105 reserved 90
106 reserved 91
107 gpt1_ipg 92
108 gpt2_ipg 93
109 gpt3_ipg 94
110 gpt4_ipg 95
111 reserved 96
112 reserved 97
113 reserved 98
114 iim_ipg 99
115 reserved 100
116 reserved 101
117 kpp_ipg 102
118 lcdc_ipg 103
119 reserved 104
120 pwm1_ipg 105
121 pwm2_ipg 106
122 pwm3_ipg 107
123 pwm4_ipg 108
124 rngb_ipg 109
125 reserved 110
126 scc_ipg 111
127 sdma_ipg 112
128 sim1_ipg 113
129 sim2_ipg 114
130 slcdc_ipg 115
131 spba_ipg 116
132 ssi1_ipg 117
133 ssi2_ipg 118
134 tsc_ipg 119
135 uart1_ipg 120
136 uart2_ipg 121
137 uart3_ipg 122
138 uart4_ipg 123
139 uart5_ipg 124
140 reserved 125
141 wdt_ipg 126
142
143Examples:
144
145clks: ccm@53f80000 {
146 compatible = "fsl,imx25-ccm";
147 reg = <0x53f80000 0x4000>;
148 interrupts = <31>;
149 clock-output-names = ...
150 "uart_ipg",
151 "uart_serial",
152 ...;
153};
154
155uart1: serial@43f90000 {
156 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
157 reg = <0x43f90000 0x4000>;
158 interrupts = <45>;
159 clocks = <&clks 79>, <&clks 50>;
160 clock-names = "ipg", "per";
161 status = "disabled";
162};
diff --git a/Documentation/devicetree/bindings/clock/imx28-clock.txt b/Documentation/devicetree/bindings/clock/imx28-clock.txt
index aa2af2866fe8..52a49a4a50b3 100644
--- a/Documentation/devicetree/bindings/clock/imx28-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx28-clock.txt
@@ -73,8 +73,8 @@ clocks and IDs.
73 can1 59 73 can1 59
74 usb0 60 74 usb0 60
75 usb1 61 75 usb1 61
76 usb0_pwr 62 76 usb0_phy 62
77 usb1_pwr 63 77 usb1_phy 63
78 enet_out 64 78 enet_out 64
79 79
80Examples: 80Examples:
diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
new file mode 100644
index 000000000000..04ad47876be0
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -0,0 +1,191 @@
1* Clock bindings for Freescale i.MX5
2
3Required properties:
4- compatible: Should be "fsl,<soc>-ccm" , where <soc> can be imx51 or imx53
5- reg: Address and length of the register set
6- interrupts: Should contain CCM interrupt
7- #clock-cells: Should be <1>
8
9The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell. The following is a full list of i.MX5
11clocks and IDs.
12
13 Clock ID
14 ---------------------------
15 dummy 0
16 ckil 1
17 osc 2
18 ckih1 3
19 ckih2 4
20 ahb 5
21 ipg 6
22 axi_a 7
23 axi_b 8
24 uart_pred 9
25 uart_root 10
26 esdhc_a_pred 11
27 esdhc_b_pred 12
28 esdhc_c_s 13
29 esdhc_d_s 14
30 emi_sel 15
31 emi_slow_podf 16
32 nfc_podf 17
33 ecspi_pred 18
34 ecspi_podf 19
35 usboh3_pred 20
36 usboh3_podf 21
37 usb_phy_pred 22
38 usb_phy_podf 23
39 cpu_podf 24
40 di_pred 25
41 tve_di 26
42 tve_s 27
43 uart1_ipg_gate 28
44 uart1_per_gate 29
45 uart2_ipg_gate 30
46 uart2_per_gate 31
47 uart3_ipg_gate 32
48 uart3_per_gate 33
49 i2c1_gate 34
50 i2c2_gate 35
51 gpt_ipg_gate 36
52 pwm1_ipg_gate 37
53 pwm1_hf_gate 38
54 pwm2_ipg_gate 39
55 pwm2_hf_gate 40
56 gpt_hf_gate 41
57 fec_gate 42
58 usboh3_per_gate 43
59 esdhc1_ipg_gate 44
60 esdhc2_ipg_gate 45
61 esdhc3_ipg_gate 46
62 esdhc4_ipg_gate 47
63 ssi1_ipg_gate 48
64 ssi2_ipg_gate 49
65 ssi3_ipg_gate 50
66 ecspi1_ipg_gate 51
67 ecspi1_per_gate 52
68 ecspi2_ipg_gate 53
69 ecspi2_per_gate 54
70 cspi_ipg_gate 55
71 sdma_gate 56
72 emi_slow_gate 57
73 ipu_s 58
74 ipu_gate 59
75 nfc_gate 60
76 ipu_di1_gate 61
77 vpu_s 62
78 vpu_gate 63
79 vpu_reference_gate 64
80 uart4_ipg_gate 65
81 uart4_per_gate 66
82 uart5_ipg_gate 67
83 uart5_per_gate 68
84 tve_gate 69
85 tve_pred 70
86 esdhc1_per_gate 71
87 esdhc2_per_gate 72
88 esdhc3_per_gate 73
89 esdhc4_per_gate 74
90 usb_phy_gate 75
91 hsi2c_gate 76
92 mipi_hsc1_gate 77
93 mipi_hsc2_gate 78
94 mipi_esc_gate 79
95 mipi_hsp_gate 80
96 ldb_di1_div_3_5 81
97 ldb_di1_div 82
98 ldb_di0_div_3_5 83
99 ldb_di0_div 84
100 ldb_di1_gate 85
101 can2_serial_gate 86
102 can2_ipg_gate 87
103 i2c3_gate 88
104 lp_apm 89
105 periph_apm 90
106 main_bus 91
107 ahb_max 92
108 aips_tz1 93
109 aips_tz2 94
110 tmax1 95
111 tmax2 96
112 tmax3 97
113 spba 98
114 uart_sel 99
115 esdhc_a_sel 100
116 esdhc_b_sel 101
117 esdhc_a_podf 102
118 esdhc_b_podf 103
119 ecspi_sel 104
120 usboh3_sel 105
121 usb_phy_sel 106
122 iim_gate 107
123 usboh3_gate 108
124 emi_fast_gate 109
125 ipu_di0_gate 110
126 gpc_dvfs 111
127 pll1_sw 112
128 pll2_sw 113
129 pll3_sw 114
130 ipu_di0_sel 115
131 ipu_di1_sel 116
132 tve_ext_sel 117
133 mx51_mipi 118
134 pll4_sw 119
135 ldb_di1_sel 120
136 di_pll4_podf 121
137 ldb_di0_sel 122
138 ldb_di0_gate 123
139 usb_phy1_gate 124
140 usb_phy2_gate 125
141 per_lp_apm 126
142 per_pred1 127
143 per_pred2 128
144 per_podf 129
145 per_root 130
146 ssi_apm 131
147 ssi1_root_sel 132
148 ssi2_root_sel 133
149 ssi3_root_sel 134
150 ssi_ext1_sel 135
151 ssi_ext2_sel 136
152 ssi_ext1_com_sel 137
153 ssi_ext2_com_sel 138
154 ssi1_root_pred 139
155 ssi1_root_podf 140
156 ssi2_root_pred 141
157 ssi2_root_podf 142
158 ssi_ext1_pred 143
159 ssi_ext1_podf 144
160 ssi_ext2_pred 145
161 ssi_ext2_podf 146
162 ssi1_root_gate 147
163 ssi2_root_gate 148
164 ssi3_root_gate 149
165 ssi_ext1_gate 150
166 ssi_ext2_gate 151
167 epit1_ipg_gate 152
168 epit1_hf_gate 153
169 epit2_ipg_gate 154
170 epit2_hf_gate 155
171 can_sel 156
172 can1_serial_gate 157
173 can1_ipg_gate 158
174
175Examples (for mx53):
176
177clks: ccm@53fd4000{
178 compatible = "fsl,imx53-ccm";
179 reg = <0x53fd4000 0x4000>;
180 interrupts = <0 71 0x04 0 72 0x04>;
181 #clock-cells = <1>;
182};
183
184can1: can@53fc8000 {
185 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
186 reg = <0x53fc8000 0x4000>;
187 interrupts = <82>;
188 clocks = <&clks 158>, <&clks 157>;
189 clock-names = "ipg", "per";
190 status = "disabled";
191};
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index 492bd991d52a..d77b4e68dc42 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -187,9 +187,9 @@ clocks and IDs.
187 pll3_usb_otg 172 187 pll3_usb_otg 172
188 pll4_audio 173 188 pll4_audio 173
189 pll5_video 174 189 pll5_video 174
190 pll6_mlb 175 190 pll8_mlb 175
191 pll7_usb_host 176 191 pll7_usb_host 176
192 pll8_enet 177 192 pll6_enet 177
193 ssi1_ipg 178 193 ssi1_ipg 178
194 ssi2_ipg 179 194 ssi2_ipg 179
195 ssi3_ipg 180 195 ssi3_ipg 180
@@ -198,6 +198,11 @@ clocks and IDs.
198 usbphy2 183 198 usbphy2 183
199 ldb_di0_div_3_5 184 199 ldb_di0_div_3_5 184
200 ldb_di1_div_3_5 185 200 ldb_di1_div_3_5 185
201 sata_ref 186
202 sata_ref_100m 187
203 pcie_ref 188
204 pcie_ref_125m 189
205 enet_ref 190
201 206
202Examples: 207Examples:
203 208
diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt
new file mode 100644
index 000000000000..23ae1db1bc13
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/zynq-7000.txt
@@ -0,0 +1,55 @@
1Device Tree Clock bindings for the Zynq 7000 EPP
2
3The Zynq EPP has several different clk providers, each with there own bindings.
4The purpose of this document is to document their usage.
5
6See clock_bindings.txt for more information on the generic clock bindings.
7See Chapter 25 of Zynq TRM for more information about Zynq clocks.
8
9== PLLs ==
10
11Used to describe the ARM_PLL, DDR_PLL, and IO_PLL.
12
13Required properties:
14- #clock-cells : shall be 0 (only one clock is output from this node)
15- compatible : "xlnx,zynq-pll"
16- reg : pair of u32 values, which are the address offsets within the SLCR
17 of the relevant PLL_CTRL register and PLL_CFG register respectively
18- clocks : phandle for parent clock. should be the phandle for ps_clk
19
20Optional properties:
21- clock-output-names : name of the output clock
22
23Example:
24 armpll: armpll {
25 #clock-cells = <0>;
26 compatible = "xlnx,zynq-pll";
27 clocks = <&ps_clk>;
28 reg = <0x100 0x110>;
29 clock-output-names = "armpll";
30 };
31
32== Peripheral clocks ==
33
34Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks.
35
36Required properties:
37- #clock-cells : shall be 1
38- compatible : "xlnx,zynq-periph-clock"
39- reg : a single u32 value, describing the offset within the SLCR where
40 the CLK_CTRL register is found for this peripheral
41- clocks : phandle for parent clocks. should hold phandles for
42 the IO_PLL, ARM_PLL, and DDR_PLL in order
43- clock-output-names : names of the output clock(s). For peripherals that have
44 two output clocks (for example, the UART), two clocks
45 should be listed.
46
47Example:
48 uart_clk: uart_clk {
49 #clock-cells = <1>;
50 compatible = "xlnx,zynq-periph-clock";
51 clocks = <&iopll &armpll &ddrpll>;
52 reg = <0x154>;
53 clock-output-names = "uart0_ref_clk",
54 "uart1_ref_clk";
55 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 15:37:07 -0500