Merge tag 'mvebu' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC updates for Marvell mvebu/kirkwood from Olof Johansson:
 "This is a branch with updates for Marvell's mvebu/kirkwood platforms.
  They came in late-ish, and were heavily interdependent such that it
  didn't make sense to split them up across the cross-platform topic
  branches.  So here they are (for the second release in a row) in a
  branch on their own."

* tag 'mvebu' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (88 commits)
  arm: l2x0: add aurora related properties to OF binding
  arm: mvebu: add Aurora L2 Cache Controller to the DT
  arm: mvebu: add L2 cache support
  dma: mv_xor: fix error handling path
  dma: mv_xor: fix error checking of irq_of_parse_and_map()
  dma: mv_xor: use request_irq() instead of devm_request_irq()
  dma: mv_xor: clear the window override control registers
  arm: mvebu: fix address decoding armada_cfg_base() function
  ARM: mvebu: update defconfig with I2C and RTC support
  ARM: mvebu: Add SATA support for OpenBlocks AX3-4
  ARM: mvebu: Add support for the RTC in OpenBlocks AX3-4
  ARM: mvebu: Add support for I2C on OpenBlocks AX3-4
  ARM: mvebu: Add support for I2C controllers in Armada 370/XP
  arm: mvebu: Add hardware I/O Coherency support
  arm: plat-orion: Add coherency attribute when setup mbus target
  arm: dma mapping: Export a dma ops function arm_dma_set_mask
  arm: mvebu: Add SMP support for Armada XP
  arm: mm: Add support for PJ4B cpu and init routines
  arm: mvebu: Add IPI support via doorbells
  arm: mvebu: Add initial support for power managmement service unit
  ...

3 files changed, 187 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
new file mode 100644
index 000000000000..1e662948661e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -0,0 +1,47 @@
+* Core Clock bindings for Marvell MVEBU SoCs
+
+Marvell MVEBU SoCs usually allow to determine core clock frequencies by
+reading the Sample-At-Reset (SAR) register. The core clock consumer should
+specify the desired clock by having the clock ID in its "clocks" phandle cell.
+
+The following is a list of provided IDs and clock names on Armada 370/XP:
+ 0 = tclk    (Internal Bus clock)
+ 1 = cpuclk  (CPU clock)
+ 2 = nbclk   (L2 Cache clock)
+ 3 = hclk    (DRAM control clock)
+ 4 = dramclk (DDR clock)
+
+The following is a list of provided IDs and clock names on Kirkwood and Dove:
+ 0 = tclk   (Internal Bus clock)
+ 1 = cpuclk (CPU0 clock)
+ 2 = l2clk  (L2 Cache clock derived from CPU0 clock)
+ 3 = ddrclk (DDR controller clock derived from CPU0 clock)
+
+Required properties:
+- compatible : shall be one of the following:
+        "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
+        "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
+        "marvell,dove-core-clock" - for Dove SoC core clocks
+        "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
+        "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
+- reg : shall be the register address of the Sample-At-Reset (SAR) register
+- #clock-cells : from common clock binding; shall be set to 1
+
+Optional properties:
+- clock-output-names : from common clock binding; allows overwrite default clock
+        output names ("tclk", "cpuclk", "l2clk", "ddrclk")
+
+Example:
+
+core_clk: core-clocks@d0214 {
+        compatible = "marvell,dove-core-clock";
+        reg = <0xd0214 0x4>;
+        #clock-cells = <1>;
+};
+
+spi0: spi@10600 {
+        compatible = "marvell,orion-spi";
+        /* ... */
+        /* get tclk from core clock provider */
+        clocks = <&core_clk 0>;
+};
diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
new file mode 100644
index 000000000000..feb830130714
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
@@ -0,0 +1,21 @@
+Device Tree Clock bindings for cpu clock of Marvell EBU platforms
+
+Required properties:
+- compatible : shall be one of the following:
+        "marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
+- reg : Address and length of the clock complex register set
+- #clock-cells : should be set to 1.
+- clocks : shall be the input parent clock phandle for the clock.
+
+cpuclk: clock-complex@d0018700 {
+        #clock-cells = <1>;
+        compatible = "marvell,armada-xp-cpu-clock";
+        reg = <0xd0018700 0xA0>;
+        clocks = <&coreclk 1>;
+}
+
+cpu@0 {
+        compatible = "marvell,sheeva-v7";
+        reg = <0>;
+        clocks = <&cpuclk 0>;
+};
diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
new file mode 100644
index 000000000000..7337005ef5e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
@@ -0,0 +1,119 @@
+* Gated Clock bindings for Marvell Orion SoCs
+
+Marvell Dove and Kirkwood allow some peripheral clocks to be gated to save
+some power. The clock consumer should specify the desired clock by having
+the clock ID in its "clocks" phandle cell. The clock ID is directly mapped to
+the corresponding clock gating control bit in HW to ease manual clock lookup
+in datasheet.
+
+The following is a list of provided IDs for Armada 370:
+ID      Clock   Peripheral
+-----------------------------------
+0       Audio   AC97 Cntrl
+1       pex0_en PCIe 0 Clock out
+2       pex1_en PCIe 1 Clock out
+3       ge1     Gigabit Ethernet 1
+4       ge0     Gigabit Ethernet 0
+5       pex0    PCIe Cntrl 0
+9       pex1    PCIe Cntrl 1
+15      sata0   SATA Host 0
+17      sdio    SDHCI Host
+25      tdm     Time Division Mplx
+28      ddr     DDR Cntrl
+30      sata1   SATA Host 0
+
+The following is a list of provided IDs for Armada XP:
+ID      Clock   Peripheral
+-----------------------------------
+0       audio   Audio Cntrl
+1       ge3     Gigabit Ethernet 3
+2       ge2     Gigabit Ethernet 2
+3       ge1     Gigabit Ethernet 1
+4       ge0     Gigabit Ethernet 0
+5       pex0    PCIe Cntrl 0
+6       pex1    PCIe Cntrl 1
+7       pex2    PCIe Cntrl 2
+8       pex3    PCIe Cntrl 3
+13      bp
+14      sata0lnk
+15      sata0   SATA Host 0
+16      lcd     LCD Cntrl
+17      sdio    SDHCI Host
+18      usb0    USB Host 0
+19      usb1    USB Host 1
+20      usb2    USB Host 2
+22      xor0    XOR DMA 0
+23      crypto  CESA engine
+25      tdm     Time Division Mplx
+28      xor1    XOR DMA 1
+29      sata1lnk
+30      sata1   SATA Host 0
+
+The following is a list of provided IDs for Dove:
+ID      Clock   Peripheral
+-----------------------------------
+0       usb0    USB Host 0
+1       usb1    USB Host 1
+2       ge      Gigabit Ethernet
+3       sata    SATA Host
+4       pex0    PCIe Cntrl 0
+5       pex1    PCIe Cntrl 1
+8       sdio0   SDHCI Host 0
+9       sdio1   SDHCI Host 1
+10      nand    NAND Cntrl
+11      camera  Camera Cntrl
+12      i2s0    I2S Cntrl 0
+13      i2s1    I2S Cntrl 1
+15      crypto  CESA engine
+21      ac97    AC97 Cntrl
+22      pdma    Peripheral DMA
+23      xor0    XOR DMA 0
+24      xor1    XOR DMA 1
+30      gephy   Gigabit Ethernel PHY
+Note: gephy(30) is implemented as a parent clock of ge(2)
+
+The following is a list of provided IDs for Kirkwood:
+ID      Clock   Peripheral
+-----------------------------------
+0       ge0     Gigabit Ethernet 0
+2       pex0    PCIe Cntrl 0
+3       usb0    USB Host 0
+4       sdio    SDIO Cntrl
+5       tsu     Transp. Stream Unit
+6       dunit   SDRAM Cntrl
+7       runit   Runit
+8       xor0    XOR DMA 0
+9       audio   I2S Cntrl 0
+14      sata0   SATA Host 0
+15      sata1   SATA Host 1
+16      xor1    XOR DMA 1
+17      crypto  CESA engine
+18      pex1    PCIe Cntrl 1
+19      ge1     Gigabit Ethernet 0
+20      tdm     Time Division Mplx
+
+Required properties:
+- compatible : shall be one of the following:
+        "marvell,dove-gating-clock" - for Dove SoC clock gating
+        "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
+- reg : shall be the register address of the Clock Gating Control register
+- #clock-cells : from common clock binding; shall be set to 1
+
+Optional properties:
+- clocks : default parent clock phandle (e.g. tclk)
+
+Example:
+
+gate_clk: clock-gating-control@d0038 {
+        compatible = "marvell,dove-gating-clock";
+        reg = <0xd0038 0x4>;
+        /* default parent clock is tclk */
+        clocks = <&core_clk 0>;
+        #clock-cells = <1>;
+};
+
+sdio0: sdio@92000 {
+        compatible = "marvell,dove-sdhci";
+        /* get clk gate bit 8 (sdio0) */
+        clocks = <&gate_clk 8>;
+};