1 files changed, 151 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
new file mode 100644
index 000000000000..729f52426fe1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -0,0 +1,151 @@
+Device Tree Clock bindings for arch-sunxi
+This binding uses the common clock binding[1].
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+Required properties:
+- compatible : shall be one of the following:
+        "allwinner,sun4i-osc-clk" - for a gatable oscillator
+        "allwinner,sun4i-pll1-clk" - for the main PLL clock
+        "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
+        "allwinner,sun4i-axi-clk" - for the AXI clock
+        "allwinner,sun4i-axi-gates-clk" - for the AXI gates
+        "allwinner,sun4i-ahb-clk" - for the AHB clock
+        "allwinner,sun4i-ahb-gates-clk" - for the AHB gates
+        "allwinner,sun4i-apb0-clk" - for the APB0 clock
+        "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates
+        "allwinner,sun4i-apb1-clk" - for the APB1 clock
+        "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
+        "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates
+Required properties for all clocks:
+- reg : shall be the control register address for the clock.
+- clocks : shall be the input parent clock(s) phandle for the clock
+- #clock-cells : from common clock binding; shall be set to 0 except for
+        "allwinner,sun4i-*-gates-clk" where it shall be set to 1
+Additionally, "allwinner,sun4i-*-gates-clk" clocks require:
+- clock-output-names : the corresponding gate names that the clock controls
+For example:
+osc24M: osc24M@01c20050 {
+        #clock-cells = <0>;
+        compatible = "allwinner,sun4i-osc-clk";
+        reg = <0x01c20050 0x4>;
+        clocks = <&osc24M_fixed>;
+};
+pll1: pll1@01c20000 {
+        #clock-cells = <0>;
+        compatible = "allwinner,sun4i-pll1-clk";
+        reg = <0x01c20000 0x4>;
+        clocks = <&osc24M>;
+};
+cpu: cpu@01c20054 {
+        #clock-cells = <0>;
+        compatible = "allwinner,sun4i-cpu-clk";
+        reg = <0x01c20054 0x4>;
+        clocks = <&osc32k>, <&osc24M>, <&pll1>;
+};
+Gate clock outputs
+The "allwinner,sun4i-*-gates-clk" clocks provide several gatable outputs;
+their corresponding offsets as present on sun4i are listed below. Note that
+some of these gates are not present on sun5i.
+  * AXI gates ("allwinner,sun4i-axi-gates-clk")
+    DRAM                                                                0
+  * AHB gates ("allwinner,sun4i-ahb-gates-clk")
+    USB0                                                                0
+    EHCI0                                                               1
+    OHCI0                                                               2*
+    EHCI1                                                               3
+    OHCI1                                                               4*
+    SS                                                                  5
+    DMA                                                                 6
+    BIST                                                                7
+    MMC0                                                                8
+    MMC1                                                                9
+    MMC2                                                                10
+    MMC3                                                                11
+    MS                                                                  12**
+    NAND                                                                13
+    SDRAM                                                               14
+    ACE                                                                 16
+    EMAC                                                                17
+    TS                                                                  18
+    SPI0                                                                20
+    SPI1                                                                21
+    SPI2                                                                22
+    SPI3                                                                23
+    PATA                                                                24
+    SATA                                                                25**
+    GPS                                                                 26*
+    VE                                                                  32
+    TVD                                                                 33
+    TVE0                                                                34
+    TVE1                                                                35
+    LCD0                                                                36
+    LCD1                                                                37
+    CSI0                                                                40
+    CSI1                                                                41
+    HDMI                                                                43
+    DE_BE0                                                              44
+    DE_BE1                                                              45
+    DE_FE0                                                              46
+    DE_FE1                                                              47
+    MP                                                                  50
+    MALI400                                                             52
+  * APB0 gates ("allwinner,sun4i-apb0-gates-clk")
+    CODEC                                                               0
+    SPDIF                                                               1*
+    AC97                                                                2
+    IIS                                                                 3
+    PIO                                                                 5
+    IR0                                                                 6
+    IR1                                                                 7
+    KEYPAD                                                              10
+  * APB1 gates ("allwinner,sun4i-apb1-gates-clk")
+    I2C0                                                                0
+    I2C1                                                                1
+    I2C2                                                                2
+    CAN                                                                 4
+    SCR                                                                 5
+    PS20                                                                6
+    PS21                                                                7
+    UART0                                                               16
+    UART1                                                               17
+    UART2                                                               18
+    UART3                                                               19
+    UART4                                                               20
+    UART5                                                               21
+    UART6                                                               22
+    UART7                                                               23
+Notation:
+ [*]:  The datasheet didn't mention these, but they are present on AW code
+ [**]: The datasheet had this marked as "NC" but they are used on AW code

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt new file mode 100644 index 000000000000..729f52426fe1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -0,0 +1,151 @@
	1	Device Tree Clock bindings for arch-sunxi
	2
	3	This binding uses the common clock binding[1].
	4
	5	[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
	6
	7	Required properties:
	8	- compatible : shall be one of the following:
	9	"allwinner,sun4i-osc-clk" - for a gatable oscillator
	10	"allwinner,sun4i-pll1-clk" - for the main PLL clock
	11	"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
	12	"allwinner,sun4i-axi-clk" - for the AXI clock
	13	"allwinner,sun4i-axi-gates-clk" - for the AXI gates
	14	"allwinner,sun4i-ahb-clk" - for the AHB clock
	15	"allwinner,sun4i-ahb-gates-clk" - for the AHB gates
	16	"allwinner,sun4i-apb0-clk" - for the APB0 clock
	17	"allwinner,sun4i-apb0-gates-clk" - for the APB0 gates
	18	"allwinner,sun4i-apb1-clk" - for the APB1 clock
	19	"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
	20	"allwinner,sun4i-apb1-gates-clk" - for the APB1 gates
	21
	22	Required properties for all clocks:
	23	- reg : shall be the control register address for the clock.
	24	- clocks : shall be the input parent clock(s) phandle for the clock
	25	- #clock-cells : from common clock binding; shall be set to 0 except for
	26	"allwinner,sun4i-*-gates-clk" where it shall be set to 1
	27
	28	Additionally, "allwinner,sun4i-*-gates-clk" clocks require:
	29	- clock-output-names : the corresponding gate names that the clock controls
	30
	31	For example:
	32
	33	osc24M: osc24M@01c20050 {
	34	#clock-cells = <0>;
	35	compatible = "allwinner,sun4i-osc-clk";
	36	reg = <0x01c20050 0x4>;
	37	clocks = <&osc24M_fixed>;
	38	};
	39
	40	pll1: pll1@01c20000 {
	41	#clock-cells = <0>;
	42	compatible = "allwinner,sun4i-pll1-clk";
	43	reg = <0x01c20000 0x4>;
	44	clocks = <&osc24M>;
	45	};
	46
	47	cpu: cpu@01c20054 {
	48	#clock-cells = <0>;
	49	compatible = "allwinner,sun4i-cpu-clk";
	50	reg = <0x01c20054 0x4>;
	51	clocks = <&osc32k>, <&osc24M>, <&pll1>;
	52	};
	53
	54
	55
	56	Gate clock outputs
	57
	58	The "allwinner,sun4i-*-gates-clk" clocks provide several gatable outputs;
	59	their corresponding offsets as present on sun4i are listed below. Note that
	60	some of these gates are not present on sun5i.
	61
	62	* AXI gates ("allwinner,sun4i-axi-gates-clk")
	63
	64	DRAM 0
	65
	66	* AHB gates ("allwinner,sun4i-ahb-gates-clk")
	67
	68	USB0 0
	69	EHCI0 1
	70	OHCI0 2*
	71	EHCI1 3
	72	OHCI1 4*
	73	SS 5
	74	DMA 6
	75	BIST 7
	76	MMC0 8
	77	MMC1 9
	78	MMC2 10
	79	MMC3 11
	80	MS 12**
	81	NAND 13
	82	SDRAM 14
	83
	84	ACE 16
	85	EMAC 17
	86	TS 18
	87
	88	SPI0 20
	89	SPI1 21
	90	SPI2 22
	91	SPI3 23
	92	PATA 24
	93	SATA 25**
	94	GPS 26*
	95
	96	VE 32
	97	TVD 33
	98	TVE0 34
	99	TVE1 35
	100	LCD0 36
	101	LCD1 37
	102
	103	CSI0 40
	104	CSI1 41
	105
	106	HDMI 43
	107	DE_BE0 44
	108	DE_BE1 45
	109	DE_FE0 46
	110	DE_FE1 47
	111
	112	MP 50
	113
	114	MALI400 52
	115
	116	* APB0 gates ("allwinner,sun4i-apb0-gates-clk")
	117
	118	CODEC 0
	119	SPDIF 1*
	120	AC97 2
	121	IIS 3
	122
	123	PIO 5
	124	IR0 6
	125	IR1 7
	126
	127	KEYPAD 10
	128
	129	* APB1 gates ("allwinner,sun4i-apb1-gates-clk")
	130
	131	I2C0 0
	132	I2C1 1
	133	I2C2 2
	134
	135	CAN 4
	136	SCR 5
	137	PS20 6
	138	PS21 7
	139
	140	UART0 16
	141	UART1 17
	142	UART2 18
	143	UART3 19
	144	UART4 20
	145	UART5 21
	146	UART6 22
	147	UART7 23
	148
	149	Notation:
	150	[*]: The datasheet didn't mention these, but they are present on AW code
	151	[**]: The datasheet had this marked as "NC" but they are used on AW code