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+* Texas Instruments Davinci NAND
+
+This file provides information, what the device node for the
+davinci nand interface contain.
+
+Required properties:
+- compatible: "ti,davinci-nand";
+- reg : contain 2 offset/length values:
+        - offset and length for the access window
+        - offset and length for accessing the aemif control registers
+- ti,davinci-chipselect: Indicates on the davinci_nand driver which
+                         chipselect is used for accessing the nand.
+
+Recommended properties :
+- ti,davinci-mask-ale: mask for ale
+- ti,davinci-mask-cle: mask for cle
+- ti,davinci-mask-chipsel: mask for chipselect
+- ti,davinci-ecc-mode: ECC mode valid values for davinci driver:
+                - "none"
+                - "soft"
+                - "hw"
+- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
+- ti,davinci-nand-buswidth: buswidth 8 or 16
+- ti,davinci-nand-use-bbt: use flash based bad block table support.
+
+Example (enbw_cmc board):
+aemif@60000000 {
+        compatible = "ti,davinci-aemif";
+        #address-cells = <2>;
+        #size-cells = <1>;
+        reg = <0x68000000 0x80000>;
+        ranges = <2 0 0x60000000 0x02000000
+                  3 0 0x62000000 0x02000000
+                  4 0 0x64000000 0x02000000
+                  5 0 0x66000000 0x02000000
+                  6 0 0x68000000 0x02000000>;
+        nand@3,0 {
+                compatible = "ti,davinci-nand";
+                reg = <3 0x0 0x807ff
+                        6 0x0 0x8000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ti,davinci-chipselect = <1>;
+                ti,davinci-mask-ale = <0>;
+                ti,davinci-mask-cle = <0>;
+                ti,davinci-mask-chipsel = <0>;
+                ti,davinci-ecc-mode = "hw";
+                ti,davinci-ecc-bits = <4>;
+                ti,davinci-nand-use-bbt;
+        };
+};