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1 | README on the SDRAM Controller for the LH7a40X | ||
2 | ============================================== | ||
3 | |||
4 | The standard configuration for the SDRAM controller generates a sparse | ||
5 | memory array. The precise layout is determined by the SDRAM chips. A | ||
6 | default kernel configuration assembles the discontiguous memory | ||
7 | regions into separate memory nodes via the NUMA (Non-Uniform Memory | ||
8 | Architecture) facilities. In this default configuration, the kernel | ||
9 | is forgiving about the precise layout. As long as it is given an | ||
10 | accurate picture of available memory by the bootloader the kernel will | ||
11 | execute correctly. | ||
12 | |||
13 | The SDRC supports a mode where some of the chip select lines are | ||
14 | swapped in order to make SDRAM look like a synchronous ROM. Setting | ||
15 | this bit means that the RAM will present as a contiguous array. Some | ||
16 | programmers prefer this to the discontiguous layout. Be aware that | ||
17 | may be a penalty for this feature where some some configurations of | ||
18 | memory are significantly reduced; i.e. 64MiB of RAM appears as only 32 | ||
19 | MiB. | ||
20 | |||
21 | There are a couple of configuration options to override the default | ||
22 | behavior. When the SROMLL bit is set and memory appears as a | ||
23 | contiguous array, there is no reason to support NUMA. | ||
24 | CONFIG_LH7A40X_CONTIGMEM disables NUMA support. When physical memory | ||
25 | is discontiguous, the memory tables are organized such that there are | ||
26 | two banks per nodes with a small gap between them. This layout wastes | ||
27 | some kernel memory for page tables representing non-existent memory. | ||
28 | CONFIG_LH7A40X_ONE_BANK_PER_NODE optimizes the node tables such that | ||
29 | there are no gaps. These options control the low level organization | ||
30 | of the memory management tables in ways that may prevent the kernel | ||
31 | from booting or may cause the kernel to allocated excessively large | ||
32 | page tables. Be warned. Only change these options if you know what | ||
33 | you are doing. The default behavior is a reasonable compromise that | ||
34 | will suit all users. | ||
35 | |||
36 | -- | ||
37 | |||
38 | A typical 32MiB system with the default configuration options will | ||
39 | find physical memory managed as follows. | ||
40 | |||
41 | node 0: 0xc0000000 4MiB | ||
42 | 0xc1000000 4MiB | ||
43 | node 1: 0xc4000000 4MiB | ||
44 | 0xc5000000 4MiB | ||
45 | node 2: 0xc8000000 4MiB | ||
46 | 0xc9000000 4MiB | ||
47 | node 3: 0xcc000000 4MiB | ||
48 | 0xcd000000 4MiB | ||
49 | |||
50 | Setting CONFIG_LH7A40X_ONE_BANK_PER_NODE will put each bank into a | ||
51 | separate node. | ||