5 files changed, 34 insertions, 47 deletions

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 211d4949a675..9af17fb4f8dc 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4214,10 +4214,7 @@ i915_max_freq_set(void *data, u64 val)
 
         dev_priv->rps.max_freq_softlimit = val;
 
-        if (IS_VALLEYVIEW(dev))
-                valleyview_set_rps(dev, val);
-        else
-                gen6_set_rps(dev, val);
+        intel_set_rps(dev, val);
 
         mutex_unlock(&dev_priv->rps.hw_lock);
 
@@ -4292,10 +4289,7 @@ i915_min_freq_set(void *data, u64 val)
 
         dev_priv->rps.min_freq_softlimit = val;
 
-        if (IS_VALLEYVIEW(dev))
-                valleyview_set_rps(dev, val);
-        else
-                gen6_set_rps(dev, val);
+        intel_set_rps(dev, val);
 
         mutex_unlock(&dev_priv->rps.hw_lock);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d8b4d0a887f8..b6b02f39985d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3183,8 +3183,7 @@ extern void i915_redisable_vga(struct drm_device *dev);
 extern void i915_redisable_vga_power_on(struct drm_device *dev);
 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
 extern void intel_init_pch_refclk(struct drm_device *dev);
-extern void gen6_set_rps(struct drm_device *dev, u8 val);
-extern void valleyview_set_rps(struct drm_device *dev, u8 val);
+extern void intel_set_rps(struct drm_device *dev, u8 val);
 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
                                   bool enable);
 extern void intel_detect_pch(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4145d95902f5..90731195ab52 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1243,10 +1243,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
 
         dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
 
-        if (IS_VALLEYVIEW(dev_priv->dev))
-                valleyview_set_rps(dev_priv->dev, new_delay);
-        else
-                gen6_set_rps(dev_priv->dev, new_delay);
+        intel_set_rps(dev_priv->dev, new_delay);
 
         mutex_unlock(&dev_priv->rps.hw_lock);
 }
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 49f5ade0edb7..cdc9da001484 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -402,10 +402,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
         /* We still need *_set_rps to process the new max_delay and
          * update the interrupt limits and PMINTRMSK even though
          * frequency request may be unchanged. */
-        if (IS_VALLEYVIEW(dev))
-                valleyview_set_rps(dev, val);
-        else
-                gen6_set_rps(dev, val);
+        intel_set_rps(dev, val);
 
         mutex_unlock(&dev_priv->rps.hw_lock);
 
@@ -464,10 +461,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
         /* We still need *_set_rps to process the new min_delay and
          * update the interrupt limits and PMINTRMSK even though
          * frequency request may be unchanged. */
-        if (IS_VALLEYVIEW(dev))
-                valleyview_set_rps(dev, val);
-        else
-                gen6_set_rps(dev, val);
+        intel_set_rps(dev, val);
 
         mutex_unlock(&dev_priv->rps.hw_lock);
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6ece663f3394..bebefe79f7ce 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3750,7 +3750,7 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
 /* gen6_set_rps is called to update the frequency request, but should also be
  * called when the range (min_delay and max_delay) is modified so that we can
  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
-void gen6_set_rps(struct drm_device *dev, u8 val)
+static void gen6_set_rps(struct drm_device *dev, u8 val)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
 
@@ -3786,6 +3786,27 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
         trace_intel_gpu_freq_change(val * 50);
 }
 
+static void valleyview_set_rps(struct drm_device *dev, u8 val)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+        WARN_ON(val > dev_priv->rps.max_freq_softlimit);
+        WARN_ON(val < dev_priv->rps.min_freq_softlimit);
+
+        if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
+                      "Odd GPU freq value\n"))
+                val &= ~1;
+
+        if (val != dev_priv->rps.cur_freq)
+                vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
+
+        I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
+
+        dev_priv->rps.cur_freq = val;
+        trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
+}
+
 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
  *
  * * If Gfx is Idle, then
@@ -3850,38 +3871,20 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
 
 void gen6_rps_boost(struct drm_i915_private *dev_priv)
 {
-        struct drm_device *dev = dev_priv->dev;
-
         mutex_lock(&dev_priv->rps.hw_lock);
         if (dev_priv->rps.enabled) {
-                if (IS_VALLEYVIEW(dev))
-                        valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
-                else
-                        gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
+                intel_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
                 dev_priv->rps.last_adj = 0;
         }
         mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
-void valleyview_set_rps(struct drm_device *dev, u8 val)
+void intel_set_rps(struct drm_device *dev, u8 val)
 {
-        struct drm_i915_private *dev_priv = dev->dev_private;
-
-        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
-        WARN_ON(val > dev_priv->rps.max_freq_softlimit);
-        WARN_ON(val < dev_priv->rps.min_freq_softlimit);
-
-        if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
-                      "Odd GPU freq value\n"))
-                val &= ~1;
-
-        if (val != dev_priv->rps.cur_freq)
-                vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
-
-        I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
-
-        dev_priv->rps.cur_freq = val;
-        trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
+        if (IS_VALLEYVIEW(dev))
+                valleyview_set_rps(dev, val);
+        else
+                gen6_set_rps(dev, val);
 }
 
 static void gen9_disable_rps(struct drm_device *dev)