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-rw-r--r--arch/arm/Kconfig15
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/mach-exynos/Kconfig340
-rw-r--r--arch/arm/mach-exynos/Makefile33
-rw-r--r--arch/arm/mach-exynos/common.c547
-rw-r--r--arch/arm/mach-exynos/common.h4
-rw-r--r--arch/arm/mach-exynos/dev-ahci.c255
-rw-r--r--arch/arm/mach-exynos/dev-audio.c254
-rw-r--r--arch/arm/mach-exynos/dev-ohci.c52
-rw-r--r--arch/arm/mach-exynos/dev-uart.c55
-rw-r--r--arch/arm/mach-exynos/dma.c322
-rw-r--r--arch/arm/mach-exynos/firmware.c22
-rw-r--r--arch/arm/mach-exynos/include/mach/gpio.h289
-rw-r--r--arch/arm/mach-exynos/include/mach/irqs.h476
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h214
-rw-r--r--arch/arm/mach-exynos/include/mach/pm-core.h12
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-gpio.h40
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-usb-phy.h74
-rw-r--r--arch/arm/mach-exynos/mach-armlex4210.c207
-rw-r--r--arch/arm/mach-exynos/mach-exynos4-dt.c8
-rw-r--r--arch/arm/mach-exynos/mach-exynos5-dt.c8
-rw-r--r--arch/arm/mach-exynos/mach-nuri.c1388
-rw-r--r--arch/arm/mach-exynos/mach-origen.c823
-rw-r--r--arch/arm/mach-exynos/mach-smdk4x12.c396
-rw-r--r--arch/arm/mach-exynos/mach-smdkv310.c444
-rw-r--r--arch/arm/mach-exynos/mach-universal_c210.c1159
-rw-r--r--arch/arm/mach-exynos/pm.c1
-rw-r--r--arch/arm/mach-exynos/pm_domains.c101
-rw-r--r--arch/arm/mach-exynos/setup-fimc.c44
-rw-r--r--arch/arm/mach-exynos/setup-fimd0.c43
-rw-r--r--arch/arm/mach-exynos/setup-i2c0.c29
-rw-r--r--arch/arm/mach-exynos/setup-i2c1.c23
-rw-r--r--arch/arm/mach-exynos/setup-i2c2.c23
-rw-r--r--arch/arm/mach-exynos/setup-i2c3.c23
-rw-r--r--arch/arm/mach-exynos/setup-i2c4.c23
-rw-r--r--arch/arm/mach-exynos/setup-i2c5.c23
-rw-r--r--arch/arm/mach-exynos/setup-i2c6.c23
-rw-r--r--arch/arm/mach-exynos/setup-i2c7.c23
-rw-r--r--arch/arm/mach-exynos/setup-keypad.c36
-rw-r--r--arch/arm/mach-exynos/setup-sdhci-gpio.c152
-rw-r--r--arch/arm/mach-exynos/setup-spi.c45
-rw-r--r--arch/arm/mach-exynos/setup-usb-phy.c223
-rw-r--r--arch/arm/plat-samsung/Kconfig47
-rw-r--r--arch/arm/plat-samsung/Makefile11
-rw-r--r--arch/arm/plat-samsung/include/plat/pm.h5
-rw-r--r--arch/arm/plat-samsung/init.c8
-rw-r--r--arch/arm/plat-samsung/pm-gpio.c5
-rw-r--r--arch/arm/plat-samsung/pm.c8
-rw-r--r--arch/arm/plat-samsung/s5p-dev-mfc.c11
-rw-r--r--drivers/gpio/Kconfig7
-rw-r--r--drivers/gpio/Makefile2
-rw-r--r--drivers/media/platform/Kconfig6
-rw-r--r--drivers/media/platform/exynos4-is/Kconfig3
-rw-r--r--drivers/media/platform/s5p-tv/Kconfig2
-rw-r--r--drivers/thermal/exynos_thermal.c3
-rw-r--r--drivers/usb/Kconfig1
-rw-r--r--drivers/usb/host/Kconfig2
57 files changed, 136 insertions, 8258 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 102bf5798501..4fd8ed7021ce 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -697,6 +697,7 @@ config ARCH_S3C24XX
697 select CLKDEV_LOOKUP 697 select CLKDEV_LOOKUP
698 select CLKSRC_MMIO 698 select CLKSRC_MMIO
699 select GENERIC_CLOCKEVENTS 699 select GENERIC_CLOCKEVENTS
700 select GPIO_SAMSUNG
700 select HAVE_CLK 701 select HAVE_CLK
701 select HAVE_S3C2410_I2C if I2C 702 select HAVE_S3C2410_I2C if I2C
702 select HAVE_S3C2410_WATCHDOG if WATCHDOG 703 select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -704,6 +705,7 @@ config ARCH_S3C24XX
704 select MULTI_IRQ_HANDLER 705 select MULTI_IRQ_HANDLER
705 select NEED_MACH_GPIO_H 706 select NEED_MACH_GPIO_H
706 select NEED_MACH_IO_H 707 select NEED_MACH_IO_H
708 select SAMSUNG_ATAGS
707 help 709 help
708 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 710 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
709 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 711 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
@@ -719,6 +721,7 @@ config ARCH_S3C64XX
719 select CLKSRC_MMIO 721 select CLKSRC_MMIO
720 select CPU_V6 722 select CPU_V6
721 select GENERIC_CLOCKEVENTS 723 select GENERIC_CLOCKEVENTS
724 select GPIO_SAMSUNG
722 select HAVE_CLK 725 select HAVE_CLK
723 select HAVE_S3C2410_I2C if I2C 726 select HAVE_S3C2410_I2C if I2C
724 select HAVE_S3C2410_WATCHDOG if WATCHDOG 727 select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -728,6 +731,7 @@ config ARCH_S3C64XX
728 select PLAT_SAMSUNG 731 select PLAT_SAMSUNG
729 select S3C_DEV_NAND 732 select S3C_DEV_NAND
730 select S3C_GPIO_TRACK 733 select S3C_GPIO_TRACK
734 select SAMSUNG_ATAGS
731 select SAMSUNG_CLKSRC 735 select SAMSUNG_CLKSRC
732 select SAMSUNG_GPIOLIB_4BIT 736 select SAMSUNG_GPIOLIB_4BIT
733 select SAMSUNG_IRQ_VIC_TIMER 737 select SAMSUNG_IRQ_VIC_TIMER
@@ -741,11 +745,13 @@ config ARCH_S5P64X0
741 select CLKSRC_MMIO 745 select CLKSRC_MMIO
742 select CPU_V6 746 select CPU_V6
743 select GENERIC_CLOCKEVENTS 747 select GENERIC_CLOCKEVENTS
748 select GPIO_SAMSUNG
744 select HAVE_CLK 749 select HAVE_CLK
745 select HAVE_S3C2410_I2C if I2C 750 select HAVE_S3C2410_I2C if I2C
746 select HAVE_S3C2410_WATCHDOG if WATCHDOG 751 select HAVE_S3C2410_WATCHDOG if WATCHDOG
747 select HAVE_S3C_RTC if RTC_CLASS 752 select HAVE_S3C_RTC if RTC_CLASS
748 select NEED_MACH_GPIO_H 753 select NEED_MACH_GPIO_H
754 select SAMSUNG_ATAGS
749 help 755 help
750 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, 756 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
751 SMDK6450. 757 SMDK6450.
@@ -757,11 +763,13 @@ config ARCH_S5PC100
757 select CLKSRC_MMIO 763 select CLKSRC_MMIO
758 select CPU_V7 764 select CPU_V7
759 select GENERIC_CLOCKEVENTS 765 select GENERIC_CLOCKEVENTS
766 select GPIO_SAMSUNG
760 select HAVE_CLK 767 select HAVE_CLK
761 select HAVE_S3C2410_I2C if I2C 768 select HAVE_S3C2410_I2C if I2C
762 select HAVE_S3C2410_WATCHDOG if WATCHDOG 769 select HAVE_S3C2410_WATCHDOG if WATCHDOG
763 select HAVE_S3C_RTC if RTC_CLASS 770 select HAVE_S3C_RTC if RTC_CLASS
764 select NEED_MACH_GPIO_H 771 select NEED_MACH_GPIO_H
772 select SAMSUNG_ATAGS
765 help 773 help
766 Samsung S5PC100 series based systems 774 Samsung S5PC100 series based systems
767 775
@@ -774,12 +782,14 @@ config ARCH_S5PV210
774 select CLKSRC_MMIO 782 select CLKSRC_MMIO
775 select CPU_V7 783 select CPU_V7
776 select GENERIC_CLOCKEVENTS 784 select GENERIC_CLOCKEVENTS
785 select GPIO_SAMSUNG
777 select HAVE_CLK 786 select HAVE_CLK
778 select HAVE_S3C2410_I2C if I2C 787 select HAVE_S3C2410_I2C if I2C
779 select HAVE_S3C2410_WATCHDOG if WATCHDOG 788 select HAVE_S3C2410_WATCHDOG if WATCHDOG
780 select HAVE_S3C_RTC if RTC_CLASS 789 select HAVE_S3C_RTC if RTC_CLASS
781 select NEED_MACH_GPIO_H 790 select NEED_MACH_GPIO_H
782 select NEED_MACH_MEMORY_H 791 select NEED_MACH_MEMORY_H
792 select SAMSUNG_ATAGS
783 help 793 help
784 Samsung S5PV210/S5PC110 series based systems 794 Samsung S5PV210/S5PC110 series based systems
785 795
@@ -787,7 +797,9 @@ config ARCH_EXYNOS
787 bool "Samsung EXYNOS" 797 bool "Samsung EXYNOS"
788 select ARCH_HAS_CPUFREQ 798 select ARCH_HAS_CPUFREQ
789 select ARCH_HAS_HOLES_MEMORYMODEL 799 select ARCH_HAS_HOLES_MEMORYMODEL
800 select ARCH_REQUIRE_GPIOLIB
790 select ARCH_SPARSEMEM_ENABLE 801 select ARCH_SPARSEMEM_ENABLE
802 select ARM_GIC
791 select CLKDEV_LOOKUP 803 select CLKDEV_LOOKUP
792 select COMMON_CLK 804 select COMMON_CLK
793 select CPU_V7 805 select CPU_V7
@@ -796,8 +808,9 @@ config ARCH_EXYNOS
796 select HAVE_S3C2410_I2C if I2C 808 select HAVE_S3C2410_I2C if I2C
797 select HAVE_S3C2410_WATCHDOG if WATCHDOG 809 select HAVE_S3C2410_WATCHDOG if WATCHDOG
798 select HAVE_S3C_RTC if RTC_CLASS 810 select HAVE_S3C_RTC if RTC_CLASS
799 select NEED_MACH_GPIO_H
800 select NEED_MACH_MEMORY_H 811 select NEED_MACH_MEMORY_H
812 select SPARSE_IRQ
813 select USE_OF
801 help 814 help
802 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) 815 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
803 816
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 650be0f10416..5a1c48ac5bc5 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -199,6 +199,7 @@ machine-$(CONFIG_ARCH_KEYSTONE) += keystone
199 199
200# Platform directory name. This list is sorted alphanumerically 200# Platform directory name. This list is sorted alphanumerically
201# by CONFIG_* macro name. 201# by CONFIG_* macro name.
202plat-$(CONFIG_ARCH_EXYNOS) += samsung
202plat-$(CONFIG_ARCH_OMAP) += omap 203plat-$(CONFIG_ARCH_OMAP) += omap
203plat-$(CONFIG_ARCH_S3C64XX) += samsung 204plat-$(CONFIG_ARCH_S3C64XX) += samsung
204plat-$(CONFIG_PLAT_IOP) += iop 205plat-$(CONFIG_PLAT_IOP) += iop
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index e51d99060d33..1e0e3999c17a 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -14,6 +14,7 @@ menu "SAMSUNG EXYNOS SoCs Support"
14config ARCH_EXYNOS4 14config ARCH_EXYNOS4
15 bool "SAMSUNG EXYNOS4" 15 bool "SAMSUNG EXYNOS4"
16 default y 16 default y
17 select GIC_NON_BANKED
17 select HAVE_ARM_SCU if SMP 18 select HAVE_ARM_SCU if SMP
18 select HAVE_SMP 19 select HAVE_SMP
19 select MIGHT_HAVE_CACHE_L2X0 20 select MIGHT_HAVE_CACHE_L2X0
@@ -89,329 +90,11 @@ config SOC_EXYNOS5440
89 help 90 help
90 Enable EXYNOS5440 SoC support 91 Enable EXYNOS5440 SoC support
91 92
92config EXYNOS_ATAGS
93 bool "ATAGS based boot for EXYNOS (deprecated)"
94 depends on !ARCH_MULTIPLATFORM
95 depends on ATAGS
96 default y
97 help
98 The EXYNOS platform is moving towards being completely probed
99 through device tree. This enables support for board files using
100 the traditional ATAGS boot format.
101 Note that this option is not available for multiplatform builds.
102
103if EXYNOS_ATAGS
104
105config EXYNOS_DEV_DMA
106 bool
107 help
108 Compile in amba device definitions for DMA controller
109
110config EXYNOS4_DEV_AHCI
111 bool
112 help
113 Compile in platform device definitions for AHCI
114
115config EXYNOS4_SETUP_FIMD0
116 bool
117 help
118 Common setup code for FIMD0.
119
120config EXYNOS4_DEV_USB_OHCI
121 bool
122 help
123 Compile in platform device definition for USB OHCI
124
125config EXYNOS4_SETUP_I2C1
126 bool
127 help
128 Common setup code for i2c bus 1.
129
130config EXYNOS4_SETUP_I2C2
131 bool
132 help
133 Common setup code for i2c bus 2.
134
135config EXYNOS4_SETUP_I2C3
136 bool
137 help
138 Common setup code for i2c bus 3.
139
140config EXYNOS4_SETUP_I2C4
141 bool
142 help
143 Common setup code for i2c bus 4.
144
145config EXYNOS4_SETUP_I2C5
146 bool
147 help
148 Common setup code for i2c bus 5.
149
150config EXYNOS4_SETUP_I2C6
151 bool
152 help
153 Common setup code for i2c bus 6.
154
155config EXYNOS4_SETUP_I2C7
156 bool
157 help
158 Common setup code for i2c bus 7.
159
160config EXYNOS4_SETUP_KEYPAD
161 bool
162 help
163 Common setup code for keypad.
164
165config EXYNOS4_SETUP_SDHCI
166 bool
167 select EXYNOS4_SETUP_SDHCI_GPIO
168 help
169 Internal helper functions for EXYNOS4 based SDHCI systems.
170
171config EXYNOS4_SETUP_SDHCI_GPIO
172 bool
173 help
174 Common setup code for SDHCI gpio.
175
176config EXYNOS4_SETUP_FIMC
177 bool
178 help
179 Common setup code for the camera interfaces.
180
181config EXYNOS4_SETUP_USB_PHY
182 bool
183 help
184 Common setup code for USB PHY controller
185
186config EXYNOS_SETUP_SPI
187 bool
188 help
189 Common setup code for SPI GPIO configurations.
190
191# machine support
192
193if ARCH_EXYNOS4
194
195comment "EXYNOS4210 Boards"
196
197config MACH_SMDKC210
198 bool "SMDKC210"
199 select MACH_SMDKV310
200 help
201 Machine support for Samsung SMDKC210
202
203config MACH_SMDKV310
204 bool "SMDKV310"
205 select CPU_EXYNOS4210
206 select EXYNOS4_DEV_AHCI
207 select EXYNOS4_DEV_USB_OHCI
208 select EXYNOS4_SETUP_FIMD0
209 select EXYNOS4_SETUP_I2C1
210 select EXYNOS4_SETUP_KEYPAD
211 select EXYNOS4_SETUP_SDHCI
212 select EXYNOS4_SETUP_USB_PHY
213 select EXYNOS_DEV_DMA
214 select EXYNOS_DEV_SYSMMU
215 select S3C24XX_PWM
216 select S3C_DEV_HSMMC
217 select S3C_DEV_HSMMC1
218 select S3C_DEV_HSMMC2
219 select S3C_DEV_HSMMC3
220 select S3C_DEV_I2C1
221 select S3C_DEV_RTC
222 select S3C_DEV_USB_HSOTG
223 select S3C_DEV_WDT
224 select S5P_DEV_FIMC0
225 select S5P_DEV_FIMC1
226 select S5P_DEV_FIMC2
227 select S5P_DEV_FIMC3
228 select S5P_DEV_FIMD0
229 select S5P_DEV_G2D
230 select S5P_DEV_I2C_HDMIPHY
231 select S5P_DEV_JPEG
232 select S5P_DEV_MFC
233 select S5P_DEV_TV
234 select S5P_DEV_USB_EHCI
235 select SAMSUNG_DEV_BACKLIGHT
236 select SAMSUNG_DEV_KEYPAD
237 select SAMSUNG_DEV_PWM
238 help
239 Machine support for Samsung SMDKV310
240
241config MACH_ARMLEX4210
242 bool "ARMLEX4210"
243 select CPU_EXYNOS4210
244 select EXYNOS4_DEV_AHCI
245 select EXYNOS4_SETUP_SDHCI
246 select EXYNOS_DEV_DMA
247 select S3C_DEV_HSMMC
248 select S3C_DEV_HSMMC2
249 select S3C_DEV_HSMMC3
250 select S3C_DEV_RTC
251 select S3C_DEV_WDT
252 help
253 Machine support for Samsung ARMLEX4210 based on EXYNOS4210
254
255config MACH_UNIVERSAL_C210
256 bool "Mobile UNIVERSAL_C210 Board"
257 select CLKSRC_MMIO
258 select CLKSRC_SAMSUNG_PWM
259 select CPU_EXYNOS4210
260 select EXYNOS4_SETUP_FIMC
261 select EXYNOS4_SETUP_FIMD0
262 select EXYNOS4_SETUP_I2C1
263 select EXYNOS4_SETUP_I2C3
264 select EXYNOS4_SETUP_I2C5
265 select EXYNOS4_SETUP_SDHCI
266 select EXYNOS4_SETUP_USB_PHY
267 select EXYNOS_DEV_DMA
268 select EXYNOS_DEV_SYSMMU
269 select S3C_DEV_HSMMC
270 select S3C_DEV_HSMMC2
271 select S3C_DEV_HSMMC3
272 select S3C_DEV_I2C1
273 select S3C_DEV_I2C3
274 select S3C_DEV_I2C5
275 select S3C_DEV_USB_HSOTG
276 select S5P_DEV_CSIS0
277 select S5P_DEV_FIMC0
278 select S5P_DEV_FIMC1
279 select S5P_DEV_FIMC2
280 select S5P_DEV_FIMC3
281 select S5P_DEV_FIMD0
282 select S5P_DEV_G2D
283 select S5P_DEV_I2C_HDMIPHY
284 select S5P_DEV_JPEG
285 select S5P_DEV_MFC
286 select S5P_DEV_ONENAND
287 select S5P_DEV_TV
288 select S5P_GPIO_INT
289 select S5P_SETUP_MIPIPHY
290 help
291 Machine support for Samsung Mobile Universal S5PC210 Reference
292 Board.
293
294config MACH_NURI
295 bool "Mobile NURI Board"
296 select CPU_EXYNOS4210
297 select EXYNOS4_SETUP_FIMC
298 select EXYNOS4_SETUP_FIMD0
299 select EXYNOS4_SETUP_I2C1
300 select EXYNOS4_SETUP_I2C3
301 select EXYNOS4_SETUP_I2C5
302 select EXYNOS4_SETUP_I2C6
303 select EXYNOS4_SETUP_SDHCI
304 select EXYNOS4_SETUP_USB_PHY
305 select EXYNOS_DEV_DMA
306 select S3C_DEV_HSMMC
307 select S3C_DEV_HSMMC2
308 select S3C_DEV_HSMMC3
309 select S3C_DEV_I2C1
310 select S3C_DEV_I2C3
311 select S3C_DEV_I2C5
312 select S3C_DEV_I2C6
313 select S3C_DEV_RTC
314 select S3C_DEV_USB_HSOTG
315 select S3C_DEV_WDT
316 select S5P_DEV_CSIS0
317 select S5P_DEV_FIMC0
318 select S5P_DEV_FIMC1
319 select S5P_DEV_FIMC2
320 select S5P_DEV_FIMC3
321 select S5P_DEV_FIMD0
322 select S5P_DEV_G2D
323 select S5P_DEV_JPEG
324 select S5P_DEV_MFC
325 select S5P_DEV_USB_EHCI
326 select S5P_GPIO_INT
327 select S5P_SETUP_MIPIPHY
328 select SAMSUNG_DEV_ADC
329 select SAMSUNG_DEV_PWM
330 help
331 Machine support for Samsung Mobile NURI Board.
332
333config MACH_ORIGEN
334 bool "ORIGEN"
335 select CPU_EXYNOS4210
336 select EXYNOS4_DEV_USB_OHCI
337 select EXYNOS4_SETUP_FIMD0
338 select EXYNOS4_SETUP_SDHCI
339 select EXYNOS4_SETUP_USB_PHY
340 select EXYNOS_DEV_DMA
341 select EXYNOS_DEV_SYSMMU
342 select S3C24XX_PWM
343 select S3C_DEV_HSMMC
344 select S3C_DEV_HSMMC2
345 select S3C_DEV_RTC
346 select S3C_DEV_USB_HSOTG
347 select S3C_DEV_WDT
348 select S5P_DEV_FIMC0
349 select S5P_DEV_FIMC1
350 select S5P_DEV_FIMC2
351 select S5P_DEV_FIMC3
352 select S5P_DEV_FIMD0
353 select S5P_DEV_G2D
354 select S5P_DEV_I2C_HDMIPHY
355 select S5P_DEV_JPEG
356 select S5P_DEV_MFC
357 select S5P_DEV_TV
358 select S5P_DEV_USB_EHCI
359 select SAMSUNG_DEV_BACKLIGHT
360 select SAMSUNG_DEV_PWM
361 help
362 Machine support for ORIGEN based on Samsung EXYNOS4210
363
364comment "EXYNOS4212 Boards"
365
366config MACH_SMDK4212
367 bool "SMDK4212"
368 select EXYNOS4_SETUP_FIMD0
369 select EXYNOS4_SETUP_I2C1
370 select EXYNOS4_SETUP_I2C3
371 select EXYNOS4_SETUP_I2C7
372 select EXYNOS4_SETUP_KEYPAD
373 select EXYNOS4_SETUP_SDHCI
374 select EXYNOS4_SETUP_USB_PHY
375 select EXYNOS_DEV_DMA
376 select EXYNOS_DEV_SYSMMU
377 select S3C24XX_PWM
378 select S3C_DEV_HSMMC2
379 select S3C_DEV_HSMMC3
380 select S3C_DEV_I2C1
381 select S3C_DEV_I2C3
382 select S3C_DEV_I2C7
383 select S3C_DEV_RTC
384 select S3C_DEV_USB_HSOTG
385 select S3C_DEV_WDT
386 select S5P_DEV_FIMC0
387 select S5P_DEV_FIMC1
388 select S5P_DEV_FIMC2
389 select S5P_DEV_FIMC3
390 select S5P_DEV_FIMD0
391 select S5P_DEV_MFC
392 select SAMSUNG_DEV_BACKLIGHT
393 select SAMSUNG_DEV_KEYPAD
394 select SAMSUNG_DEV_PWM
395 select SOC_EXYNOS4212
396 help
397 Machine support for Samsung SMDK4212
398
399comment "EXYNOS4412 Boards"
400
401config MACH_SMDK4412
402 bool "SMDK4412"
403 select MACH_SMDK4212
404 select SOC_EXYNOS4412
405 help
406 Machine support for Samsung SMDK4412
407endif
408
409endif
410
411comment "Flattened Device Tree based board for EXYNOS SoCs" 93comment "Flattened Device Tree based board for EXYNOS SoCs"
412 94
413config MACH_EXYNOS4_DT 95config MACH_EXYNOS4_DT
414 bool "Samsung Exynos4 Machine using device tree" 96 bool "Samsung Exynos4 Machine using device tree"
97 default y
415 depends on ARCH_EXYNOS4 98 depends on ARCH_EXYNOS4
416 select ARM_AMBA 99 select ARM_AMBA
417 select CLKSRC_OF 100 select CLKSRC_OF
@@ -419,7 +102,6 @@ config MACH_EXYNOS4_DT
419 select CPU_EXYNOS4210 102 select CPU_EXYNOS4210
420 select KEYBOARD_SAMSUNG if INPUT_KEYBOARD 103 select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
421 select S5P_DEV_MFC 104 select S5P_DEV_MFC
422 select USE_OF
423 help 105 help
424 Machine support for Samsung Exynos4 machine with device tree enabled. 106 Machine support for Samsung Exynos4 machine with device tree enabled.
425 Select this if a fdt blob is available for the Exynos4 SoC based board. 107 Select this if a fdt blob is available for the Exynos4 SoC based board.
@@ -433,28 +115,10 @@ config MACH_EXYNOS5_DT
433 select ARM_AMBA 115 select ARM_AMBA
434 select CLKSRC_OF 116 select CLKSRC_OF
435 select USB_ARCH_HAS_XHCI 117 select USB_ARCH_HAS_XHCI
436 select USE_OF
437 help 118 help
438 Machine support for Samsung EXYNOS5 machine with device tree enabled. 119 Machine support for Samsung EXYNOS5 machine with device tree enabled.
439 Select this if a fdt blob is available for the EXYNOS5 SoC based board. 120 Select this if a fdt blob is available for the EXYNOS5 SoC based board.
440 121
441if ARCH_EXYNOS4
442
443comment "Configuration for HSMMC 8-bit bus width"
444
445config EXYNOS4_SDHCI_CH0_8BIT
446 bool "Channel 0 with 8-bit bus"
447 help
448 Support HSMMC Channel 0 8-bit bus.
449 If selected, Channel 1 is disabled.
450
451config EXYNOS4_SDHCI_CH2_8BIT
452 bool "Channel 2 with 8-bit bus"
453 help
454 Support HSMMC Channel 2 8-bit bus.
455 If selected, Channel 3 is disabled.
456endif
457
458endmenu 122endmenu
459 123
460endif 124endif
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index b09b027178f3..e970a7a4e278 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -32,38 +32,5 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
32 32
33# machine support 33# machine support
34 34
35obj-$(CONFIG_MACH_SMDKC210) += mach-smdkv310.o
36obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o
37obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o
38obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
39obj-$(CONFIG_MACH_NURI) += mach-nuri.o
40obj-$(CONFIG_MACH_ORIGEN) += mach-origen.o
41
42obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o
43obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o
44
45obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o 35obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
46obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o 36obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
47
48# device support
49
50obj-y += dev-uart.o
51obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
52obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
53obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o
54obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
55
56obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
57obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
58obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
59obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
60obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o
61obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o
62obj-$(CONFIG_EXYNOS4_SETUP_I2C4) += setup-i2c4.o
63obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o
64obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o
65obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
66obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
67obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
68obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o
69obj-$(CONFIG_EXYNOS_SETUP_SPI) += setup-spi.o
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index f7e504b7874d..81e6320ca091 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -40,20 +40,9 @@
40 40
41#include <mach/regs-irq.h> 41#include <mach/regs-irq.h>
42#include <mach/regs-pmu.h> 42#include <mach/regs-pmu.h>
43#include <mach/regs-gpio.h>
44#include <mach/irqs.h>
45 43
46#include <plat/cpu.h> 44#include <plat/cpu.h>
47#include <plat/devs.h>
48#include <plat/pm.h> 45#include <plat/pm.h>
49#include <plat/sdhci.h>
50#include <plat/gpio-cfg.h>
51#include <plat/adc-core.h>
52#include <plat/fb-core.h>
53#include <plat/fimc-core.h>
54#include <plat/iic-core.h>
55#include <plat/tv-core.h>
56#include <plat/spi-core.h>
57#include <plat/regs-serial.h> 46#include <plat/regs-serial.h>
58 47
59#include "common.h" 48#include "common.h"
@@ -69,31 +58,25 @@ static const char name_exynos5440[] = "EXYNOS5440";
69static void exynos4_map_io(void); 58static void exynos4_map_io(void);
70static void exynos5_map_io(void); 59static void exynos5_map_io(void);
71static void exynos5440_map_io(void); 60static void exynos5440_map_io(void);
72static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
73static int exynos_init(void); 61static int exynos_init(void);
74 62
75unsigned long xxti_f = 0, xusbxti_f = 0;
76
77static struct cpu_table cpu_ids[] __initdata = { 63static struct cpu_table cpu_ids[] __initdata = {
78 { 64 {
79 .idcode = EXYNOS4210_CPU_ID, 65 .idcode = EXYNOS4210_CPU_ID,
80 .idmask = EXYNOS4_CPU_MASK, 66 .idmask = EXYNOS4_CPU_MASK,
81 .map_io = exynos4_map_io, 67 .map_io = exynos4_map_io,
82 .init_uarts = exynos4_init_uarts,
83 .init = exynos_init, 68 .init = exynos_init,
84 .name = name_exynos4210, 69 .name = name_exynos4210,
85 }, { 70 }, {
86 .idcode = EXYNOS4212_CPU_ID, 71 .idcode = EXYNOS4212_CPU_ID,
87 .idmask = EXYNOS4_CPU_MASK, 72 .idmask = EXYNOS4_CPU_MASK,
88 .map_io = exynos4_map_io, 73 .map_io = exynos4_map_io,
89 .init_uarts = exynos4_init_uarts,
90 .init = exynos_init, 74 .init = exynos_init,
91 .name = name_exynos4212, 75 .name = name_exynos4212,
92 }, { 76 }, {
93 .idcode = EXYNOS4412_CPU_ID, 77 .idcode = EXYNOS4412_CPU_ID,
94 .idmask = EXYNOS4_CPU_MASK, 78 .idmask = EXYNOS4_CPU_MASK,
95 .map_io = exynos4_map_io, 79 .map_io = exynos4_map_io,
96 .init_uarts = exynos4_init_uarts,
97 .init = exynos_init, 80 .init = exynos_init,
98 .name = name_exynos4412, 81 .name = name_exynos4412,
99 }, { 82 }, {
@@ -113,15 +96,6 @@ static struct cpu_table cpu_ids[] __initdata = {
113 96
114/* Initial IO mappings */ 97/* Initial IO mappings */
115 98
116static struct map_desc exynos_iodesc[] __initdata = {
117 {
118 .virtual = (unsigned long)S5P_VA_CHIPID,
119 .pfn = __phys_to_pfn(EXYNOS_PA_CHIPID),
120 .length = SZ_4K,
121 .type = MT_DEVICE,
122 },
123};
124
125static struct map_desc exynos4_iodesc[] __initdata = { 99static struct map_desc exynos4_iodesc[] __initdata = {
126 { 100 {
127 .virtual = (unsigned long)S3C_VA_SYS, 101 .virtual = (unsigned long)S3C_VA_SYS,
@@ -304,13 +278,6 @@ static struct map_desc exynos5440_iodesc0[] __initdata = {
304 }, 278 },
305}; 279};
306 280
307static struct samsung_pwm_variant exynos4_pwm_variant = {
308 .bits = 32,
309 .div_base = 0,
310 .has_tint_cstat = true,
311 .tclk_mask = 0,
312};
313
314void exynos4_restart(char mode, const char *cmd) 281void exynos4_restart(char mode, const char *cmd)
315{ 282{
316 __raw_writel(0x1, S5P_SWRESET); 283 __raw_writel(0x1, S5P_SWRESET);
@@ -353,8 +320,7 @@ void __init exynos_init_late(void)
353 exynos_pm_late_initcall(); 320 exynos_pm_late_initcall();
354} 321}
355 322
356#ifdef CONFIG_OF 323static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
357int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
358 int depth, void *data) 324 int depth, void *data)
359{ 325{
360 struct map_desc iodesc; 326 struct map_desc iodesc;
@@ -376,7 +342,6 @@ int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
376 iotable_init(&iodesc, 1); 342 iotable_init(&iodesc, 1);
377 return 1; 343 return 1;
378} 344}
379#endif
380 345
381/* 346/*
382 * exynos_map_io 347 * exynos_map_io
@@ -384,19 +349,11 @@ int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
384 * register the standard cpu IO areas 349 * register the standard cpu IO areas
385 */ 350 */
386 351
387void __init exynos_init_io(struct map_desc *mach_desc, int size) 352void __init exynos_init_io(void)
388{ 353{
389 debug_ll_io_init(); 354 debug_ll_io_init();
390 355
391#ifdef CONFIG_OF 356 of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
392 if (initial_boot_params)
393 of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
394 else
395#endif
396 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
397
398 if (mach_desc)
399 iotable_init(mach_desc, size);
400 357
401 /* detect cpu id and rev. */ 358 /* detect cpu id and rev. */
402 s5p_init_cpu(S5P_VA_CHIPID); 359 s5p_init_cpu(S5P_VA_CHIPID);
@@ -417,34 +374,6 @@ static void __init exynos4_map_io(void)
417 iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc)); 374 iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
418 if (soc_is_exynos4212() || soc_is_exynos4412()) 375 if (soc_is_exynos4212() || soc_is_exynos4412())
419 iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc)); 376 iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
420
421 /* initialize device information early */
422 exynos4_default_sdhci0();
423 exynos4_default_sdhci1();
424 exynos4_default_sdhci2();
425 exynos4_default_sdhci3();
426
427 s3c_adc_setname("samsung-adc-v3");
428
429 s3c_fimc_setname(0, "exynos4-fimc");
430 s3c_fimc_setname(1, "exynos4-fimc");
431 s3c_fimc_setname(2, "exynos4-fimc");
432 s3c_fimc_setname(3, "exynos4-fimc");
433
434 s3c_sdhci_setname(0, "exynos4-sdhci");
435 s3c_sdhci_setname(1, "exynos4-sdhci");
436 s3c_sdhci_setname(2, "exynos4-sdhci");
437 s3c_sdhci_setname(3, "exynos4-sdhci");
438
439 /* The I2C bus controllers are directly compatible with s3c2440 */
440 s3c_i2c0_setname("s3c2440-i2c");
441 s3c_i2c1_setname("s3c2440-i2c");
442 s3c_i2c2_setname("s3c2440-i2c");
443
444 s5p_fb_setname(0, "exynos4-fb");
445 s5p_hdmi_setname("exynos4-hdmi");
446
447 s3c64xx_spi_setname("exynos4210-spi");
448} 377}
449 378
450static void __init exynos5_map_io(void) 379static void __init exynos5_map_io(void)
@@ -460,81 +389,10 @@ static void __init exynos5440_map_io(void)
460 iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0)); 389 iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
461} 390}
462 391
463void __init exynos_set_timer_source(u8 channels)
464{
465 exynos4_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
466 exynos4_pwm_variant.output_mask &= ~channels;
467}
468
469void __init exynos_init_time(void) 392void __init exynos_init_time(void)
470{ 393{
471 unsigned int timer_irqs[SAMSUNG_PWM_NUM] = { 394 of_clk_init(NULL);
472 EXYNOS4_IRQ_TIMER0_VIC, EXYNOS4_IRQ_TIMER1_VIC, 395 clocksource_of_init();
473 EXYNOS4_IRQ_TIMER2_VIC, EXYNOS4_IRQ_TIMER3_VIC,
474 EXYNOS4_IRQ_TIMER4_VIC,
475 };
476
477 if (of_have_populated_dt()) {
478#ifdef CONFIG_OF
479 of_clk_init(NULL);
480 clocksource_of_init();
481#endif
482 } else {
483 /* todo: remove after migrating legacy E4 platforms to dt */
484#ifdef CONFIG_ARCH_EXYNOS4
485 exynos4_clk_init(NULL, !soc_is_exynos4210(), S5P_VA_CMU, readl(S5P_VA_CHIPID + 8) & 1);
486 exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
487#endif
488#ifdef CONFIG_CLKSRC_SAMSUNG_PWM
489 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
490 samsung_pwm_clocksource_init(S3C_VA_TIMER,
491 timer_irqs, &exynos4_pwm_variant);
492 else
493#endif
494 mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0,
495 EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1);
496 }
497}
498
499static unsigned int max_combiner_nr(void)
500{
501 if (soc_is_exynos5250())
502 return EXYNOS5_MAX_COMBINER_NR;
503 else if (soc_is_exynos4412())
504 return EXYNOS4412_MAX_COMBINER_NR;
505 else if (soc_is_exynos4212())
506 return EXYNOS4212_MAX_COMBINER_NR;
507 else
508 return EXYNOS4210_MAX_COMBINER_NR;
509}
510
511
512void __init exynos4_init_irq(void)
513{
514 unsigned int gic_bank_offset;
515
516 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
517
518 if (!of_have_populated_dt())
519 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
520#ifdef CONFIG_OF
521 else
522 irqchip_init();
523#endif
524
525 if (!of_have_populated_dt())
526 combiner_init(S5P_VA_COMBINER_BASE, NULL,
527 max_combiner_nr(), COMBINER_IRQ(0, 0));
528
529 gic_arch_extn.irq_set_wake = s3c_irq_wake;
530}
531
532void __init exynos5_init_irq(void)
533{
534#ifdef CONFIG_OF
535 irqchip_init();
536#endif
537 gic_arch_extn.irq_set_wake = s3c_irq_wake;
538} 396}
539 397
540struct bus_type exynos_subsys = { 398struct bus_type exynos_subsys = {
@@ -552,59 +410,19 @@ static int __init exynos_core_init(void)
552} 410}
553core_initcall(exynos_core_init); 411core_initcall(exynos_core_init);
554 412
555#ifdef CONFIG_CACHE_L2X0
556static int __init exynos4_l2x0_cache_init(void) 413static int __init exynos4_l2x0_cache_init(void)
557{ 414{
558 int ret; 415 int ret;
559 416
560 if (soc_is_exynos5250() || soc_is_exynos5440())
561 return 0;
562
563 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK); 417 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
564 if (!ret) { 418 if (ret)
565 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); 419 return ret;
566 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
567 return 0;
568 }
569
570 if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
571 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
572 /* TAG, Data Latency Control: 2 cycles */
573 l2x0_saved_regs.tag_latency = 0x110;
574
575 if (soc_is_exynos4212() || soc_is_exynos4412())
576 l2x0_saved_regs.data_latency = 0x120;
577 else
578 l2x0_saved_regs.data_latency = 0x110;
579
580 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
581 l2x0_saved_regs.pwr_ctrl =
582 (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
583
584 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
585 420
586 __raw_writel(l2x0_saved_regs.tag_latency, 421 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
587 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); 422 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
588 __raw_writel(l2x0_saved_regs.data_latency,
589 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
590
591 /* L2X0 Prefetch Control */
592 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
593 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
594
595 /* L2X0 Power Control */
596 __raw_writel(l2x0_saved_regs.pwr_ctrl,
597 S5P_VA_L2CC + L2X0_POWER_CTRL);
598
599 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
600 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
601 }
602
603 l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
604 return 0; 423 return 0;
605} 424}
606early_initcall(exynos4_l2x0_cache_init); 425early_initcall(exynos4_l2x0_cache_init);
607#endif
608 426
609static int __init exynos_init(void) 427static int __init exynos_init(void)
610{ 428{
@@ -612,350 +430,3 @@ static int __init exynos_init(void)
612 430
613 return device_register(&exynos4_dev); 431 return device_register(&exynos4_dev);
614} 432}
615
616/* uart registration process */
617
618static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
619{
620 struct s3c2410_uartcfg *tcfg = cfg;
621 u32 ucnt;
622
623 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
624 tcfg->has_fracval = 1;
625
626 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
627}
628
629static void __iomem *exynos_eint_base;
630
631static DEFINE_SPINLOCK(eint_lock);
632
633static unsigned int eint0_15_data[16];
634
635static inline int exynos4_irq_to_gpio(unsigned int irq)
636{
637 if (irq < IRQ_EINT(0))
638 return -EINVAL;
639
640 irq -= IRQ_EINT(0);
641 if (irq < 8)
642 return EXYNOS4_GPX0(irq);
643
644 irq -= 8;
645 if (irq < 8)
646 return EXYNOS4_GPX1(irq);
647
648 irq -= 8;
649 if (irq < 8)
650 return EXYNOS4_GPX2(irq);
651
652 irq -= 8;
653 if (irq < 8)
654 return EXYNOS4_GPX3(irq);
655
656 return -EINVAL;
657}
658
659static inline int exynos5_irq_to_gpio(unsigned int irq)
660{
661 if (irq < IRQ_EINT(0))
662 return -EINVAL;
663
664 irq -= IRQ_EINT(0);
665 if (irq < 8)
666 return EXYNOS5_GPX0(irq);
667
668 irq -= 8;
669 if (irq < 8)
670 return EXYNOS5_GPX1(irq);
671
672 irq -= 8;
673 if (irq < 8)
674 return EXYNOS5_GPX2(irq);
675
676 irq -= 8;
677 if (irq < 8)
678 return EXYNOS5_GPX3(irq);
679
680 return -EINVAL;
681}
682
683static unsigned int exynos4_eint0_15_src_int[16] = {
684 EXYNOS4_IRQ_EINT0,
685 EXYNOS4_IRQ_EINT1,
686 EXYNOS4_IRQ_EINT2,
687 EXYNOS4_IRQ_EINT3,
688 EXYNOS4_IRQ_EINT4,
689 EXYNOS4_IRQ_EINT5,
690 EXYNOS4_IRQ_EINT6,
691 EXYNOS4_IRQ_EINT7,
692 EXYNOS4_IRQ_EINT8,
693 EXYNOS4_IRQ_EINT9,
694 EXYNOS4_IRQ_EINT10,
695 EXYNOS4_IRQ_EINT11,
696 EXYNOS4_IRQ_EINT12,
697 EXYNOS4_IRQ_EINT13,
698 EXYNOS4_IRQ_EINT14,
699 EXYNOS4_IRQ_EINT15,
700};
701
702static unsigned int exynos5_eint0_15_src_int[16] = {
703 EXYNOS5_IRQ_EINT0,
704 EXYNOS5_IRQ_EINT1,
705 EXYNOS5_IRQ_EINT2,
706 EXYNOS5_IRQ_EINT3,
707 EXYNOS5_IRQ_EINT4,
708 EXYNOS5_IRQ_EINT5,
709 EXYNOS5_IRQ_EINT6,
710 EXYNOS5_IRQ_EINT7,
711 EXYNOS5_IRQ_EINT8,
712 EXYNOS5_IRQ_EINT9,
713 EXYNOS5_IRQ_EINT10,
714 EXYNOS5_IRQ_EINT11,
715 EXYNOS5_IRQ_EINT12,
716 EXYNOS5_IRQ_EINT13,
717 EXYNOS5_IRQ_EINT14,
718 EXYNOS5_IRQ_EINT15,
719};
720static inline void exynos_irq_eint_mask(struct irq_data *data)
721{
722 u32 mask;
723
724 spin_lock(&eint_lock);
725 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
726 mask |= EINT_OFFSET_BIT(data->irq);
727 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
728 spin_unlock(&eint_lock);
729}
730
731static void exynos_irq_eint_unmask(struct irq_data *data)
732{
733 u32 mask;
734
735 spin_lock(&eint_lock);
736 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
737 mask &= ~(EINT_OFFSET_BIT(data->irq));
738 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
739 spin_unlock(&eint_lock);
740}
741
742static inline void exynos_irq_eint_ack(struct irq_data *data)
743{
744 __raw_writel(EINT_OFFSET_BIT(data->irq),
745 EINT_PEND(exynos_eint_base, data->irq));
746}
747
748static void exynos_irq_eint_maskack(struct irq_data *data)
749{
750 exynos_irq_eint_mask(data);
751 exynos_irq_eint_ack(data);
752}
753
754static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
755{
756 int offs = EINT_OFFSET(data->irq);
757 int shift;
758 u32 ctrl, mask;
759 u32 newvalue = 0;
760
761 switch (type) {
762 case IRQ_TYPE_EDGE_RISING:
763 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
764 break;
765
766 case IRQ_TYPE_EDGE_FALLING:
767 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
768 break;
769
770 case IRQ_TYPE_EDGE_BOTH:
771 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
772 break;
773
774 case IRQ_TYPE_LEVEL_LOW:
775 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
776 break;
777
778 case IRQ_TYPE_LEVEL_HIGH:
779 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
780 break;
781
782 default:
783 printk(KERN_ERR "No such irq type %d", type);
784 return -EINVAL;
785 }
786
787 shift = (offs & 0x7) * 4;
788 mask = 0x7 << shift;
789
790 spin_lock(&eint_lock);
791 ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
792 ctrl &= ~mask;
793 ctrl |= newvalue << shift;
794 __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
795 spin_unlock(&eint_lock);
796
797 if (soc_is_exynos5250())
798 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
799 else
800 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
801
802 return 0;
803}
804
805static struct irq_chip exynos_irq_eint = {
806 .name = "exynos-eint",
807 .irq_mask = exynos_irq_eint_mask,
808 .irq_unmask = exynos_irq_eint_unmask,
809 .irq_mask_ack = exynos_irq_eint_maskack,
810 .irq_ack = exynos_irq_eint_ack,
811 .irq_set_type = exynos_irq_eint_set_type,
812#ifdef CONFIG_PM
813 .irq_set_wake = s3c_irqext_wake,
814#endif
815};
816
817/*
818 * exynos4_irq_demux_eint
819 *
820 * This function demuxes the IRQ from from EINTs 16 to 31.
821 * It is designed to be inlined into the specific handler
822 * s5p_irq_demux_eintX_Y.
823 *
824 * Each EINT pend/mask registers handle eight of them.
825 */
826static inline void exynos_irq_demux_eint(unsigned int start)
827{
828 unsigned int irq;
829
830 u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
831 u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
832
833 status &= ~mask;
834 status &= 0xff;
835
836 while (status) {
837 irq = fls(status) - 1;
838 generic_handle_irq(irq + start);
839 status &= ~(1 << irq);
840 }
841}
842
843static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
844{
845 struct irq_chip *chip = irq_get_chip(irq);
846 chained_irq_enter(chip, desc);
847 exynos_irq_demux_eint(IRQ_EINT(16));
848 exynos_irq_demux_eint(IRQ_EINT(24));
849 chained_irq_exit(chip, desc);
850}
851
852static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
853{
854 u32 *irq_data = irq_get_handler_data(irq);
855 struct irq_chip *chip = irq_get_chip(irq);
856
857 chained_irq_enter(chip, desc);
858 generic_handle_irq(*irq_data);
859 chained_irq_exit(chip, desc);
860}
861
862static int __init exynos_init_irq_eint(void)
863{
864 int irq;
865
866#ifdef CONFIG_PINCTRL_SAMSUNG
867 /*
868 * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
869 * functionality along with support for external gpio and wakeup
870 * interrupts. If the samsung pinctrl driver is enabled and includes
871 * the wakeup interrupt support, then the setting up external wakeup
872 * interrupts here can be skipped. This check here is temporary to
873 * allow exynos4 platforms that do not use Samsung pinctrl driver to
874 * co-exist with platforms that do. When all of the Samsung Exynos4
875 * platforms switch over to using the pinctrl driver, the wakeup
876 * interrupt support code here can be completely removed.
877 */
878 static const struct of_device_id exynos_pinctrl_ids[] = {
879 { .compatible = "samsung,exynos4210-pinctrl", },
880 { .compatible = "samsung,exynos4x12-pinctrl", },
881 { .compatible = "samsung,exynos5250-pinctrl", },
882 };
883 struct device_node *pctrl_np, *wkup_np;
884 const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
885
886 for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
887 if (of_device_is_available(pctrl_np)) {
888 wkup_np = of_find_compatible_node(pctrl_np, NULL,
889 wkup_compat);
890 if (wkup_np)
891 return -ENODEV;
892 }
893 }
894#endif
895 if (soc_is_exynos5440())
896 return 0;
897
898 if (soc_is_exynos5250())
899 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
900 else
901 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
902
903 if (exynos_eint_base == NULL) {
904 pr_err("unable to ioremap for EINT base address\n");
905 return -ENOMEM;
906 }
907
908 for (irq = 0 ; irq <= 31 ; irq++) {
909 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
910 handle_level_irq);
911 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
912 }
913
914 irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
915
916 for (irq = 0 ; irq <= 15 ; irq++) {
917 eint0_15_data[irq] = IRQ_EINT(irq);
918
919 if (soc_is_exynos5250()) {
920 irq_set_handler_data(exynos5_eint0_15_src_int[irq],
921 &eint0_15_data[irq]);
922 irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
923 exynos_irq_eint0_15);
924 } else {
925 irq_set_handler_data(exynos4_eint0_15_src_int[irq],
926 &eint0_15_data[irq]);
927 irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
928 exynos_irq_eint0_15);
929 }
930 }
931
932 return 0;
933}
934arch_initcall(exynos_init_irq_eint);
935
936static struct resource exynos4_pmu_resource[] = {
937 DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
938 DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
939#if defined(CONFIG_SOC_EXYNOS4412)
940 DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
941 DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
942#endif
943};
944
945static struct platform_device exynos4_device_pmu = {
946 .name = "arm-pmu",
947 .num_resources = ARRAY_SIZE(exynos4_pmu_resource),
948 .resource = exynos4_pmu_resource,
949};
950
951static int __init exynos_armpmu_init(void)
952{
953 if (!of_have_populated_dt()) {
954 if (soc_is_exynos4210() || soc_is_exynos4212())
955 exynos4_device_pmu.num_resources = 2;
956 platform_device_register(&exynos4_device_pmu);
957 }
958
959 return 0;
960}
961arch_initcall(exynos_armpmu_init);
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 11fc1e29819b..38d45fd23be4 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -19,9 +19,7 @@ void exynos_init_time(void);
19extern unsigned long xxti_f, xusbxti_f; 19extern unsigned long xxti_f, xusbxti_f;
20 20
21struct map_desc; 21struct map_desc;
22void exynos_init_io(struct map_desc *mach_desc, int size); 22void exynos_init_io(void);
23void exynos4_init_irq(void);
24void exynos5_init_irq(void);
25void exynos4_restart(char mode, const char *cmd); 23void exynos4_restart(char mode, const char *cmd);
26void exynos5_restart(char mode, const char *cmd); 24void exynos5_restart(char mode, const char *cmd);
27void exynos_init_late(void); 25void exynos_init_late(void);
diff --git a/arch/arm/mach-exynos/dev-ahci.c b/arch/arm/mach-exynos/dev-ahci.c
deleted file mode 100644
index ce1aad3eeeb9..000000000000
--- a/arch/arm/mach-exynos/dev-ahci.c
+++ /dev/null
@@ -1,255 +0,0 @@
1/* linux/arch/arm/mach-exynos4/dev-ahci.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - AHCI support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/dma-mapping.h>
16#include <linux/platform_device.h>
17#include <linux/ahci_platform.h>
18
19#include <plat/cpu.h>
20
21#include <mach/irqs.h>
22#include <mach/map.h>
23#include <mach/regs-pmu.h>
24
25/* PHY Control Register */
26#define SATA_CTRL0 0x0
27/* PHY Link Control Register */
28#define SATA_CTRL1 0x4
29/* PHY Status Register */
30#define SATA_PHY_STATUS 0x8
31
32#define SATA_CTRL0_RX_DATA_VALID(x) (x << 27)
33#define SATA_CTRL0_SPEED_MODE (1 << 26)
34#define SATA_CTRL0_M_PHY_CAL (1 << 19)
35#define SATA_CTRL0_PHY_CMU_RST_N (1 << 10)
36#define SATA_CTRL0_M_PHY_LN_RST_N (1 << 9)
37#define SATA_CTRL0_PHY_POR_N (1 << 8)
38
39#define SATA_CTRL1_RST_PMALIVE_N (1 << 8)
40#define SATA_CTRL1_RST_RXOOB_N (1 << 7)
41#define SATA_CTRL1_RST_RX_N (1 << 6)
42#define SATA_CTRL1_RST_TX_N (1 << 5)
43
44#define SATA_PHY_STATUS_CMU_OK (1 << 18)
45#define SATA_PHY_STATUS_LANE_OK (1 << 16)
46
47#define LANE0 0x200
48#define COM_LANE 0xA00
49
50#define HOST_PORTS_IMPL 0xC
51#define SCLK_SATA_FREQ (67 * MHZ)
52
53static void __iomem *phy_base, *phy_ctrl;
54
55struct phy_reg {
56 u8 reg;
57 u8 val;
58};
59
60/* SATA PHY setup */
61static const struct phy_reg exynos4_sataphy_cmu[] = {
62 { 0x00, 0x06 }, { 0x02, 0x80 }, { 0x22, 0xa0 }, { 0x23, 0x42 },
63 { 0x2e, 0x04 }, { 0x2f, 0x50 }, { 0x30, 0x70 }, { 0x31, 0x02 },
64 { 0x32, 0x25 }, { 0x33, 0x40 }, { 0x34, 0x01 }, { 0x35, 0x40 },
65 { 0x61, 0x2e }, { 0x63, 0x5e }, { 0x65, 0x42 }, { 0x66, 0xd1 },
66 { 0x67, 0x20 }, { 0x68, 0x28 }, { 0x69, 0x78 }, { 0x6a, 0x04 },
67 { 0x6b, 0xc8 }, { 0x6c, 0x06 },
68};
69
70static const struct phy_reg exynos4_sataphy_lane[] = {
71 { 0x00, 0x02 }, { 0x05, 0x10 }, { 0x06, 0x84 }, { 0x07, 0x04 },
72 { 0x08, 0xe0 }, { 0x10, 0x23 }, { 0x13, 0x05 }, { 0x14, 0x30 },
73 { 0x15, 0x00 }, { 0x17, 0x70 }, { 0x18, 0xf2 }, { 0x19, 0x1e },
74 { 0x1a, 0x18 }, { 0x1b, 0x0d }, { 0x1c, 0x08 }, { 0x50, 0x60 },
75 { 0x51, 0x0f },
76};
77
78static const struct phy_reg exynos4_sataphy_comlane[] = {
79 { 0x01, 0x20 }, { 0x03, 0x40 }, { 0x04, 0x3c }, { 0x05, 0x7d },
80 { 0x06, 0x1d }, { 0x07, 0xcf }, { 0x08, 0x05 }, { 0x09, 0x63 },
81 { 0x0a, 0x29 }, { 0x0b, 0xc4 }, { 0x0c, 0x01 }, { 0x0d, 0x03 },
82 { 0x0e, 0x28 }, { 0x0f, 0x98 }, { 0x10, 0x19 }, { 0x13, 0x80 },
83 { 0x14, 0xf0 }, { 0x15, 0xd0 }, { 0x39, 0xa0 }, { 0x3a, 0xa0 },
84 { 0x3b, 0xa0 }, { 0x3c, 0xa0 }, { 0x3d, 0xa0 }, { 0x3e, 0xa0 },
85 { 0x3f, 0xa0 }, { 0x40, 0x42 }, { 0x42, 0x80 }, { 0x43, 0x58 },
86 { 0x45, 0x44 }, { 0x46, 0x5c }, { 0x47, 0x86 }, { 0x48, 0x8d },
87 { 0x49, 0xd0 }, { 0x4a, 0x09 }, { 0x4b, 0x90 }, { 0x4c, 0x07 },
88 { 0x4d, 0x40 }, { 0x51, 0x20 }, { 0x52, 0x32 }, { 0x7f, 0xd8 },
89 { 0x80, 0x1a }, { 0x81, 0xff }, { 0x82, 0x11 }, { 0x83, 0x00 },
90 { 0x87, 0xf0 }, { 0x87, 0xff }, { 0x87, 0xff }, { 0x87, 0xff },
91 { 0x87, 0xff }, { 0x8c, 0x1c }, { 0x8d, 0xc2 }, { 0x8e, 0xc3 },
92 { 0x8f, 0x3f }, { 0x90, 0x0a }, { 0x96, 0xf8 },
93};
94
95static int wait_for_phy_ready(void __iomem *reg, unsigned long bit)
96{
97 unsigned long timeout;
98
99 /* wait for maximum of 3 sec */
100 timeout = jiffies + msecs_to_jiffies(3000);
101 while (!(__raw_readl(reg) & bit)) {
102 if (time_after(jiffies, timeout))
103 return -1;
104 cpu_relax();
105 }
106 return 0;
107}
108
109static int ahci_phy_init(void __iomem *mmio)
110{
111 int i, ctrl0;
112
113 for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_cmu); i++)
114 __raw_writeb(exynos4_sataphy_cmu[i].val,
115 phy_base + (exynos4_sataphy_cmu[i].reg * 4));
116
117 for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_lane); i++)
118 __raw_writeb(exynos4_sataphy_lane[i].val,
119 phy_base + (LANE0 + exynos4_sataphy_lane[i].reg) * 4);
120
121 for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_comlane); i++)
122 __raw_writeb(exynos4_sataphy_comlane[i].val,
123 phy_base + (COM_LANE + exynos4_sataphy_comlane[i].reg) * 4);
124
125 __raw_writeb(0x07, phy_base);
126
127 ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
128 ctrl0 |= SATA_CTRL0_PHY_CMU_RST_N;
129 __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
130
131 if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
132 SATA_PHY_STATUS_CMU_OK) < 0) {
133 printk(KERN_ERR "PHY CMU not ready\n");
134 return -EBUSY;
135 }
136
137 __raw_writeb(0x03, phy_base + (COM_LANE * 4));
138
139 ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
140 ctrl0 |= SATA_CTRL0_M_PHY_LN_RST_N;
141 __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
142
143 if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
144 SATA_PHY_STATUS_LANE_OK) < 0) {
145 printk(KERN_ERR "PHY LANE not ready\n");
146 return -EBUSY;
147 }
148
149 ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
150 ctrl0 |= SATA_CTRL0_M_PHY_CAL;
151 __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
152
153 return 0;
154}
155
156static int exynos4_ahci_init(struct device *dev, void __iomem *mmio)
157{
158 struct clk *clk_sata, *clk_sataphy, *clk_sclk_sata;
159 int val, ret;
160
161 phy_base = ioremap(EXYNOS4_PA_SATAPHY, SZ_64K);
162 if (!phy_base) {
163 dev_err(dev, "failed to allocate memory for SATA PHY\n");
164 return -ENOMEM;
165 }
166
167 phy_ctrl = ioremap(EXYNOS4_PA_SATAPHY_CTRL, SZ_16);
168 if (!phy_ctrl) {
169 dev_err(dev, "failed to allocate memory for SATA PHY CTRL\n");
170 ret = -ENOMEM;
171 goto err1;
172 }
173
174 clk_sata = clk_get(dev, "sata");
175 if (IS_ERR(clk_sata)) {
176 dev_err(dev, "failed to get sata clock\n");
177 ret = PTR_ERR(clk_sata);
178 clk_sata = NULL;
179 goto err2;
180
181 }
182 clk_enable(clk_sata);
183
184 clk_sataphy = clk_get(dev, "sataphy");
185 if (IS_ERR(clk_sataphy)) {
186 dev_err(dev, "failed to get sataphy clock\n");
187 ret = PTR_ERR(clk_sataphy);
188 clk_sataphy = NULL;
189 goto err3;
190 }
191 clk_enable(clk_sataphy);
192
193 clk_sclk_sata = clk_get(dev, "sclk_sata");
194 if (IS_ERR(clk_sclk_sata)) {
195 dev_err(dev, "failed to get sclk_sata\n");
196 ret = PTR_ERR(clk_sclk_sata);
197 clk_sclk_sata = NULL;
198 goto err4;
199 }
200 clk_enable(clk_sclk_sata);
201 clk_set_rate(clk_sclk_sata, SCLK_SATA_FREQ);
202
203 __raw_writel(S5P_PMU_SATA_PHY_CONTROL_EN, S5P_PMU_SATA_PHY_CONTROL);
204
205 /* Enable PHY link control */
206 val = SATA_CTRL1_RST_PMALIVE_N | SATA_CTRL1_RST_RXOOB_N |
207 SATA_CTRL1_RST_RX_N | SATA_CTRL1_RST_TX_N;
208 __raw_writel(val, phy_ctrl + SATA_CTRL1);
209
210 /* Set communication speed as 3Gbps and enable PHY power */
211 val = SATA_CTRL0_RX_DATA_VALID(3) | SATA_CTRL0_SPEED_MODE |
212 SATA_CTRL0_PHY_POR_N;
213 __raw_writel(val, phy_ctrl + SATA_CTRL0);
214
215 /* Port0 is available */
216 __raw_writel(0x1, mmio + HOST_PORTS_IMPL);
217
218 return ahci_phy_init(mmio);
219
220err4:
221 clk_disable(clk_sataphy);
222 clk_put(clk_sataphy);
223err3:
224 clk_disable(clk_sata);
225 clk_put(clk_sata);
226err2:
227 iounmap(phy_ctrl);
228err1:
229 iounmap(phy_base);
230
231 return ret;
232}
233
234static struct ahci_platform_data exynos4_ahci_pdata = {
235 .init = exynos4_ahci_init,
236};
237
238static struct resource exynos4_ahci_resource[] = {
239 [0] = DEFINE_RES_MEM(EXYNOS4_PA_SATA, SZ_64K),
240 [1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_SATA),
241};
242
243static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32);
244
245struct platform_device exynos4_device_ahci = {
246 .name = "ahci",
247 .id = -1,
248 .resource = exynos4_ahci_resource,
249 .num_resources = ARRAY_SIZE(exynos4_ahci_resource),
250 .dev = {
251 .platform_data = &exynos4_ahci_pdata,
252 .dma_mask = &exynos4_ahci_dmamask,
253 .coherent_dma_mask = DMA_BIT_MASK(32),
254 },
255};
diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c
deleted file mode 100644
index c662c89794b2..000000000000
--- a/arch/arm/mach-exynos/dev-audio.c
+++ /dev/null
@@ -1,254 +0,0 @@
1/* linux/arch/arm/mach-exynos4/dev-audio.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (c) 2010 Samsung Electronics Co. Ltd
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
16#include <linux/gpio.h>
17#include <linux/platform_data/asoc-s3c.h>
18
19#include <plat/gpio-cfg.h>
20
21#include <mach/map.h>
22#include <mach/dma.h>
23#include <mach/irqs.h>
24
25#define EXYNOS4_AUDSS_INT_MEM (0x03000000)
26
27static int exynos4_cfg_i2s(struct platform_device *pdev)
28{
29 /* configure GPIO for i2s port */
30 switch (pdev->id) {
31 case 0:
32 s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2));
33 break;
34 case 1:
35 s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2));
36 break;
37 case 2:
38 s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(4));
39 break;
40 default:
41 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
42 return -EINVAL;
43 }
44
45 return 0;
46}
47
48static struct s3c_audio_pdata i2sv5_pdata = {
49 .cfg_gpio = exynos4_cfg_i2s,
50 .type = {
51 .i2s = {
52 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
53 | QUIRK_NEED_RSTCLR,
54 .idma_addr = EXYNOS4_AUDSS_INT_MEM,
55 },
56 },
57};
58
59static struct resource exynos4_i2s0_resource[] = {
60 [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S0, SZ_256),
61 [1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
62 [2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
63 [3] = DEFINE_RES_DMA(DMACH_I2S0S_TX),
64};
65
66struct platform_device exynos4_device_i2s0 = {
67 .name = "samsung-i2s",
68 .id = 0,
69 .num_resources = ARRAY_SIZE(exynos4_i2s0_resource),
70 .resource = exynos4_i2s0_resource,
71 .dev = {
72 .platform_data = &i2sv5_pdata,
73 },
74};
75
76static struct s3c_audio_pdata i2sv3_pdata = {
77 .cfg_gpio = exynos4_cfg_i2s,
78 .type = {
79 .i2s = {
80 .quirks = QUIRK_NO_MUXPSR,
81 },
82 },
83};
84
85static struct resource exynos4_i2s1_resource[] = {
86 [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S1, SZ_256),
87 [1] = DEFINE_RES_DMA(DMACH_I2S1_TX),
88 [2] = DEFINE_RES_DMA(DMACH_I2S1_RX),
89};
90
91struct platform_device exynos4_device_i2s1 = {
92 .name = "samsung-i2s",
93 .id = 1,
94 .num_resources = ARRAY_SIZE(exynos4_i2s1_resource),
95 .resource = exynos4_i2s1_resource,
96 .dev = {
97 .platform_data = &i2sv3_pdata,
98 },
99};
100
101static struct resource exynos4_i2s2_resource[] = {
102 [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S2, SZ_256),
103 [1] = DEFINE_RES_DMA(DMACH_I2S2_TX),
104 [2] = DEFINE_RES_DMA(DMACH_I2S2_RX),
105};
106
107struct platform_device exynos4_device_i2s2 = {
108 .name = "samsung-i2s",
109 .id = 2,
110 .num_resources = ARRAY_SIZE(exynos4_i2s2_resource),
111 .resource = exynos4_i2s2_resource,
112 .dev = {
113 .platform_data = &i2sv3_pdata,
114 },
115};
116
117/* PCM Controller platform_devices */
118
119static int exynos4_pcm_cfg_gpio(struct platform_device *pdev)
120{
121 switch (pdev->id) {
122 case 0:
123 s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 5, S3C_GPIO_SFN(3));
124 break;
125 case 1:
126 s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3));
127 break;
128 case 2:
129 s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3));
130 break;
131 default:
132 printk(KERN_DEBUG "Invalid PCM Controller number!");
133 return -EINVAL;
134 }
135
136 return 0;
137}
138
139static struct s3c_audio_pdata s3c_pcm_pdata = {
140 .cfg_gpio = exynos4_pcm_cfg_gpio,
141};
142
143static struct resource exynos4_pcm0_resource[] = {
144 [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM0, SZ_256),
145 [1] = DEFINE_RES_DMA(DMACH_PCM0_TX),
146 [2] = DEFINE_RES_DMA(DMACH_PCM0_RX),
147};
148
149struct platform_device exynos4_device_pcm0 = {
150 .name = "samsung-pcm",
151 .id = 0,
152 .num_resources = ARRAY_SIZE(exynos4_pcm0_resource),
153 .resource = exynos4_pcm0_resource,
154 .dev = {
155 .platform_data = &s3c_pcm_pdata,
156 },
157};
158
159static struct resource exynos4_pcm1_resource[] = {
160 [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM1, SZ_256),
161 [1] = DEFINE_RES_DMA(DMACH_PCM1_TX),
162 [2] = DEFINE_RES_DMA(DMACH_PCM1_RX),
163};
164
165struct platform_device exynos4_device_pcm1 = {
166 .name = "samsung-pcm",
167 .id = 1,
168 .num_resources = ARRAY_SIZE(exynos4_pcm1_resource),
169 .resource = exynos4_pcm1_resource,
170 .dev = {
171 .platform_data = &s3c_pcm_pdata,
172 },
173};
174
175static struct resource exynos4_pcm2_resource[] = {
176 [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM2, SZ_256),
177 [1] = DEFINE_RES_DMA(DMACH_PCM2_TX),
178 [2] = DEFINE_RES_DMA(DMACH_PCM2_RX),
179};
180
181struct platform_device exynos4_device_pcm2 = {
182 .name = "samsung-pcm",
183 .id = 2,
184 .num_resources = ARRAY_SIZE(exynos4_pcm2_resource),
185 .resource = exynos4_pcm2_resource,
186 .dev = {
187 .platform_data = &s3c_pcm_pdata,
188 },
189};
190
191/* AC97 Controller platform devices */
192
193static int exynos4_ac97_cfg_gpio(struct platform_device *pdev)
194{
195 return s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(4));
196}
197
198static struct resource exynos4_ac97_resource[] = {
199 [0] = DEFINE_RES_MEM(EXYNOS4_PA_AC97, SZ_256),
200 [1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT),
201 [2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN),
202 [3] = DEFINE_RES_DMA(DMACH_AC97_MICIN),
203 [4] = DEFINE_RES_IRQ(EXYNOS4_IRQ_AC97),
204};
205
206static struct s3c_audio_pdata s3c_ac97_pdata = {
207 .cfg_gpio = exynos4_ac97_cfg_gpio,
208};
209
210static u64 exynos4_ac97_dmamask = DMA_BIT_MASK(32);
211
212struct platform_device exynos4_device_ac97 = {
213 .name = "samsung-ac97",
214 .id = -1,
215 .num_resources = ARRAY_SIZE(exynos4_ac97_resource),
216 .resource = exynos4_ac97_resource,
217 .dev = {
218 .platform_data = &s3c_ac97_pdata,
219 .dma_mask = &exynos4_ac97_dmamask,
220 .coherent_dma_mask = DMA_BIT_MASK(32),
221 },
222};
223
224/* S/PDIF Controller platform_device */
225
226static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
227{
228 s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4));
229
230 return 0;
231}
232
233static struct resource exynos4_spdif_resource[] = {
234 [0] = DEFINE_RES_MEM(EXYNOS4_PA_SPDIF, SZ_256),
235 [1] = DEFINE_RES_DMA(DMACH_SPDIF),
236};
237
238static struct s3c_audio_pdata samsung_spdif_pdata = {
239 .cfg_gpio = exynos4_spdif_cfg_gpio,
240};
241
242static u64 exynos4_spdif_dmamask = DMA_BIT_MASK(32);
243
244struct platform_device exynos4_device_spdif = {
245 .name = "samsung-spdif",
246 .id = -1,
247 .num_resources = ARRAY_SIZE(exynos4_spdif_resource),
248 .resource = exynos4_spdif_resource,
249 .dev = {
250 .platform_data = &samsung_spdif_pdata,
251 .dma_mask = &exynos4_spdif_dmamask,
252 .coherent_dma_mask = DMA_BIT_MASK(32),
253 },
254};
diff --git a/arch/arm/mach-exynos/dev-ohci.c b/arch/arm/mach-exynos/dev-ohci.c
deleted file mode 100644
index d5bc129e6bb7..000000000000
--- a/arch/arm/mach-exynos/dev-ohci.c
+++ /dev/null
@@ -1,52 +0,0 @@
1/* linux/arch/arm/mach-exynos/dev-ohci.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS - OHCI support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/dma-mapping.h>
14#include <linux/platform_device.h>
15#include <linux/platform_data/usb-ohci-exynos.h>
16
17#include <mach/irqs.h>
18#include <mach/map.h>
19
20#include <plat/devs.h>
21#include <plat/usb-phy.h>
22
23static struct resource exynos4_ohci_resource[] = {
24 [0] = DEFINE_RES_MEM(EXYNOS4_PA_OHCI, SZ_256),
25 [1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
26};
27
28static u64 exynos4_ohci_dma_mask = DMA_BIT_MASK(32);
29
30struct platform_device exynos4_device_ohci = {
31 .name = "exynos-ohci",
32 .id = -1,
33 .num_resources = ARRAY_SIZE(exynos4_ohci_resource),
34 .resource = exynos4_ohci_resource,
35 .dev = {
36 .dma_mask = &exynos4_ohci_dma_mask,
37 .coherent_dma_mask = DMA_BIT_MASK(32),
38 }
39};
40
41void __init exynos4_ohci_set_platdata(struct exynos4_ohci_platdata *pd)
42{
43 struct exynos4_ohci_platdata *npd;
44
45 npd = s3c_set_platdata(pd, sizeof(struct exynos4_ohci_platdata),
46 &exynos4_device_ohci);
47
48 if (!npd->phy_init)
49 npd->phy_init = s5p_usb_phy_init;
50 if (!npd->phy_exit)
51 npd->phy_exit = s5p_usb_phy_exit;
52}
diff --git a/arch/arm/mach-exynos/dev-uart.c b/arch/arm/mach-exynos/dev-uart.c
deleted file mode 100644
index c48aff02c786..000000000000
--- a/arch/arm/mach-exynos/dev-uart.c
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Base EXYNOS UART resource and device definitions
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/ioport.h>
17#include <linux/platform_device.h>
18
19#include <asm/mach/arch.h>
20#include <asm/mach/irq.h>
21#include <mach/hardware.h>
22#include <mach/map.h>
23#include <mach/irqs.h>
24
25#include <plat/devs.h>
26
27#define EXYNOS_UART_RESOURCE(_series, _nr) \
28static struct resource exynos##_series##_uart##_nr##_resource[] = { \
29 [0] = DEFINE_RES_MEM(EXYNOS##_series##_PA_UART##_nr, EXYNOS##_series##_SZ_UART), \
30 [1] = DEFINE_RES_IRQ(EXYNOS##_series##_IRQ_UART##_nr), \
31};
32
33EXYNOS_UART_RESOURCE(4, 0)
34EXYNOS_UART_RESOURCE(4, 1)
35EXYNOS_UART_RESOURCE(4, 2)
36EXYNOS_UART_RESOURCE(4, 3)
37
38struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
39 [0] = {
40 .resources = exynos4_uart0_resource,
41 .nr_resources = ARRAY_SIZE(exynos4_uart0_resource),
42 },
43 [1] = {
44 .resources = exynos4_uart1_resource,
45 .nr_resources = ARRAY_SIZE(exynos4_uart1_resource),
46 },
47 [2] = {
48 .resources = exynos4_uart2_resource,
49 .nr_resources = ARRAY_SIZE(exynos4_uart2_resource),
50 },
51 [3] = {
52 .resources = exynos4_uart3_resource,
53 .nr_resources = ARRAY_SIZE(exynos4_uart3_resource),
54 },
55};
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
deleted file mode 100644
index 87e07d6fc615..000000000000
--- a/arch/arm/mach-exynos/dma.c
+++ /dev/null
@@ -1,322 +0,0 @@
1/* linux/arch/arm/mach-exynos4/dma.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/dma-mapping.h>
25#include <linux/amba/bus.h>
26#include <linux/amba/pl330.h>
27#include <linux/of.h>
28
29#include <asm/irq.h>
30#include <plat/devs.h>
31#include <plat/irqs.h>
32#include <plat/cpu.h>
33
34#include <mach/map.h>
35#include <mach/irqs.h>
36#include <mach/dma.h>
37
38static u8 exynos4210_pdma0_peri[] = {
39 DMACH_PCM0_RX,
40 DMACH_PCM0_TX,
41 DMACH_PCM2_RX,
42 DMACH_PCM2_TX,
43 DMACH_MSM_REQ0,
44 DMACH_MSM_REQ2,
45 DMACH_SPI0_RX,
46 DMACH_SPI0_TX,
47 DMACH_SPI2_RX,
48 DMACH_SPI2_TX,
49 DMACH_I2S0S_TX,
50 DMACH_I2S0_RX,
51 DMACH_I2S0_TX,
52 DMACH_I2S2_RX,
53 DMACH_I2S2_TX,
54 DMACH_UART0_RX,
55 DMACH_UART0_TX,
56 DMACH_UART2_RX,
57 DMACH_UART2_TX,
58 DMACH_UART4_RX,
59 DMACH_UART4_TX,
60 DMACH_SLIMBUS0_RX,
61 DMACH_SLIMBUS0_TX,
62 DMACH_SLIMBUS2_RX,
63 DMACH_SLIMBUS2_TX,
64 DMACH_SLIMBUS4_RX,
65 DMACH_SLIMBUS4_TX,
66 DMACH_AC97_MICIN,
67 DMACH_AC97_PCMIN,
68 DMACH_AC97_PCMOUT,
69};
70
71static u8 exynos4212_pdma0_peri[] = {
72 DMACH_PCM0_RX,
73 DMACH_PCM0_TX,
74 DMACH_PCM2_RX,
75 DMACH_PCM2_TX,
76 DMACH_MIPI_HSI0,
77 DMACH_MIPI_HSI1,
78 DMACH_SPI0_RX,
79 DMACH_SPI0_TX,
80 DMACH_SPI2_RX,
81 DMACH_SPI2_TX,
82 DMACH_I2S0S_TX,
83 DMACH_I2S0_RX,
84 DMACH_I2S0_TX,
85 DMACH_I2S2_RX,
86 DMACH_I2S2_TX,
87 DMACH_UART0_RX,
88 DMACH_UART0_TX,
89 DMACH_UART2_RX,
90 DMACH_UART2_TX,
91 DMACH_UART4_RX,
92 DMACH_UART4_TX,
93 DMACH_SLIMBUS0_RX,
94 DMACH_SLIMBUS0_TX,
95 DMACH_SLIMBUS2_RX,
96 DMACH_SLIMBUS2_TX,
97 DMACH_SLIMBUS4_RX,
98 DMACH_SLIMBUS4_TX,
99 DMACH_AC97_MICIN,
100 DMACH_AC97_PCMIN,
101 DMACH_AC97_PCMOUT,
102 DMACH_MIPI_HSI4,
103 DMACH_MIPI_HSI5,
104};
105
106static u8 exynos5250_pdma0_peri[] = {
107 DMACH_PCM0_RX,
108 DMACH_PCM0_TX,
109 DMACH_PCM2_RX,
110 DMACH_PCM2_TX,
111 DMACH_SPI0_RX,
112 DMACH_SPI0_TX,
113 DMACH_SPI2_RX,
114 DMACH_SPI2_TX,
115 DMACH_I2S0S_TX,
116 DMACH_I2S0_RX,
117 DMACH_I2S0_TX,
118 DMACH_I2S2_RX,
119 DMACH_I2S2_TX,
120 DMACH_UART0_RX,
121 DMACH_UART0_TX,
122 DMACH_UART2_RX,
123 DMACH_UART2_TX,
124 DMACH_UART4_RX,
125 DMACH_UART4_TX,
126 DMACH_SLIMBUS0_RX,
127 DMACH_SLIMBUS0_TX,
128 DMACH_SLIMBUS2_RX,
129 DMACH_SLIMBUS2_TX,
130 DMACH_SLIMBUS4_RX,
131 DMACH_SLIMBUS4_TX,
132 DMACH_AC97_MICIN,
133 DMACH_AC97_PCMIN,
134 DMACH_AC97_PCMOUT,
135 DMACH_MIPI_HSI0,
136 DMACH_MIPI_HSI2,
137 DMACH_MIPI_HSI4,
138 DMACH_MIPI_HSI6,
139};
140
141static struct dma_pl330_platdata exynos_pdma0_pdata;
142
143static AMBA_AHB_DEVICE(exynos_pdma0, "dma-pl330.0", 0x00041330,
144 EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos_pdma0_pdata);
145
146static u8 exynos4210_pdma1_peri[] = {
147 DMACH_PCM0_RX,
148 DMACH_PCM0_TX,
149 DMACH_PCM1_RX,
150 DMACH_PCM1_TX,
151 DMACH_MSM_REQ1,
152 DMACH_MSM_REQ3,
153 DMACH_SPI1_RX,
154 DMACH_SPI1_TX,
155 DMACH_I2S0S_TX,
156 DMACH_I2S0_RX,
157 DMACH_I2S0_TX,
158 DMACH_I2S1_RX,
159 DMACH_I2S1_TX,
160 DMACH_UART0_RX,
161 DMACH_UART0_TX,
162 DMACH_UART1_RX,
163 DMACH_UART1_TX,
164 DMACH_UART3_RX,
165 DMACH_UART3_TX,
166 DMACH_SLIMBUS1_RX,
167 DMACH_SLIMBUS1_TX,
168 DMACH_SLIMBUS3_RX,
169 DMACH_SLIMBUS3_TX,
170 DMACH_SLIMBUS5_RX,
171 DMACH_SLIMBUS5_TX,
172};
173
174static u8 exynos4212_pdma1_peri[] = {
175 DMACH_PCM0_RX,
176 DMACH_PCM0_TX,
177 DMACH_PCM1_RX,
178 DMACH_PCM1_TX,
179 DMACH_MIPI_HSI2,
180 DMACH_MIPI_HSI3,
181 DMACH_SPI1_RX,
182 DMACH_SPI1_TX,
183 DMACH_I2S0S_TX,
184 DMACH_I2S0_RX,
185 DMACH_I2S0_TX,
186 DMACH_I2S1_RX,
187 DMACH_I2S1_TX,
188 DMACH_UART0_RX,
189 DMACH_UART0_TX,
190 DMACH_UART1_RX,
191 DMACH_UART1_TX,
192 DMACH_UART3_RX,
193 DMACH_UART3_TX,
194 DMACH_SLIMBUS1_RX,
195 DMACH_SLIMBUS1_TX,
196 DMACH_SLIMBUS3_RX,
197 DMACH_SLIMBUS3_TX,
198 DMACH_SLIMBUS5_RX,
199 DMACH_SLIMBUS5_TX,
200 DMACH_SLIMBUS0AUX_RX,
201 DMACH_SLIMBUS0AUX_TX,
202 DMACH_SPDIF,
203 DMACH_MIPI_HSI6,
204 DMACH_MIPI_HSI7,
205};
206
207static u8 exynos5250_pdma1_peri[] = {
208 DMACH_PCM0_RX,
209 DMACH_PCM0_TX,
210 DMACH_PCM1_RX,
211 DMACH_PCM1_TX,
212 DMACH_SPI1_RX,
213 DMACH_SPI1_TX,
214 DMACH_PWM,
215 DMACH_SPDIF,
216 DMACH_I2S0S_TX,
217 DMACH_I2S0_RX,
218 DMACH_I2S0_TX,
219 DMACH_I2S1_RX,
220 DMACH_I2S1_TX,
221 DMACH_UART0_RX,
222 DMACH_UART0_TX,
223 DMACH_UART1_RX,
224 DMACH_UART1_TX,
225 DMACH_UART3_RX,
226 DMACH_UART3_TX,
227 DMACH_SLIMBUS1_RX,
228 DMACH_SLIMBUS1_TX,
229 DMACH_SLIMBUS3_RX,
230 DMACH_SLIMBUS3_TX,
231 DMACH_SLIMBUS5_RX,
232 DMACH_SLIMBUS5_TX,
233 DMACH_SLIMBUS0AUX_RX,
234 DMACH_SLIMBUS0AUX_TX,
235 DMACH_DISP1,
236 DMACH_MIPI_HSI1,
237 DMACH_MIPI_HSI3,
238 DMACH_MIPI_HSI5,
239 DMACH_MIPI_HSI7,
240};
241
242static struct dma_pl330_platdata exynos_pdma1_pdata;
243
244static AMBA_AHB_DEVICE(exynos_pdma1, "dma-pl330.1", 0x00041330,
245 EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos_pdma1_pdata);
246
247static u8 mdma_peri[] = {
248 DMACH_MTOM_0,
249 DMACH_MTOM_1,
250 DMACH_MTOM_2,
251 DMACH_MTOM_3,
252 DMACH_MTOM_4,
253 DMACH_MTOM_5,
254 DMACH_MTOM_6,
255 DMACH_MTOM_7,
256};
257
258static struct dma_pl330_platdata exynos_mdma1_pdata = {
259 .nr_valid_peri = ARRAY_SIZE(mdma_peri),
260 .peri_id = mdma_peri,
261};
262
263static AMBA_AHB_DEVICE(exynos_mdma1, "dma-pl330.2", 0x00041330,
264 EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata);
265
266static int __init exynos_dma_init(void)
267{
268 if (of_have_populated_dt())
269 return 0;
270
271 if (soc_is_exynos4210()) {
272 exynos_pdma0_pdata.nr_valid_peri =
273 ARRAY_SIZE(exynos4210_pdma0_peri);
274 exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
275 exynos_pdma1_pdata.nr_valid_peri =
276 ARRAY_SIZE(exynos4210_pdma1_peri);
277 exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
278
279 if (samsung_rev() == EXYNOS4210_REV_0)
280 exynos_mdma1_device.res.start = EXYNOS4_PA_S_MDMA1;
281 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
282 exynos_pdma0_pdata.nr_valid_peri =
283 ARRAY_SIZE(exynos4212_pdma0_peri);
284 exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
285 exynos_pdma1_pdata.nr_valid_peri =
286 ARRAY_SIZE(exynos4212_pdma1_peri);
287 exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
288 } else if (soc_is_exynos5250()) {
289 exynos_pdma0_pdata.nr_valid_peri =
290 ARRAY_SIZE(exynos5250_pdma0_peri);
291 exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri;
292 exynos_pdma1_pdata.nr_valid_peri =
293 ARRAY_SIZE(exynos5250_pdma1_peri);
294 exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri;
295
296 exynos_pdma0_device.res.start = EXYNOS5_PA_PDMA0;
297 exynos_pdma0_device.res.end = EXYNOS5_PA_PDMA0 + SZ_4K;
298 exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA0;
299 exynos_pdma1_device.res.start = EXYNOS5_PA_PDMA1;
300 exynos_pdma1_device.res.end = EXYNOS5_PA_PDMA1 + SZ_4K;
301 exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA1;
302 exynos_mdma1_device.res.start = EXYNOS5_PA_MDMA1;
303 exynos_mdma1_device.res.end = EXYNOS5_PA_MDMA1 + SZ_4K;
304 exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_MDMA1;
305 }
306
307 dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
308 dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
309 dma_cap_set(DMA_PRIVATE, exynos_pdma0_pdata.cap_mask);
310 amba_device_register(&exynos_pdma0_device, &iomem_resource);
311
312 dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
313 dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
314 dma_cap_set(DMA_PRIVATE, exynos_pdma1_pdata.cap_mask);
315 amba_device_register(&exynos_pdma1_device, &iomem_resource);
316
317 dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask);
318 amba_device_register(&exynos_mdma1_device, &iomem_resource);
319
320 return 0;
321}
322arch_initcall(exynos_dma_init);
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index ed11f100d479..932129ef26c6 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -48,20 +48,18 @@ static const struct firmware_ops exynos_firmware_ops = {
48 48
49void __init exynos_firmware_init(void) 49void __init exynos_firmware_init(void)
50{ 50{
51 if (of_have_populated_dt()) { 51 struct device_node *nd;
52 struct device_node *nd; 52 const __be32 *addr;
53 const __be32 *addr;
54 53
55 nd = of_find_compatible_node(NULL, NULL, 54 nd = of_find_compatible_node(NULL, NULL,
56 "samsung,secure-firmware"); 55 "samsung,secure-firmware");
57 if (!nd) 56 if (!nd)
58 return; 57 return;
59 58
60 addr = of_get_address(nd, 0, NULL, NULL); 59 addr = of_get_address(nd, 0, NULL, NULL);
61 if (!addr) { 60 if (!addr) {
62 pr_err("%s: No address specified.\n", __func__); 61 pr_err("%s: No address specified.\n", __func__);
63 return; 62 return;
64 }
65 } 63 }
66 64
67 pr_info("Running under secure firmware.\n"); 65 pr_info("Running under secure firmware.\n");
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
deleted file mode 100644
index eb24f1eb8e3b..000000000000
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ /dev/null
@@ -1,289 +0,0 @@
1/*
2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS - GPIO lib support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __ASM_ARCH_GPIO_H
13#define __ASM_ARCH_GPIO_H __FILE__
14
15/* Macro for EXYNOS GPIO numbering */
16
17#define EXYNOS_GPIO_NEXT(__gpio) \
18 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
19
20/* EXYNOS4 GPIO bank sizes */
21
22#define EXYNOS4_GPIO_A0_NR (8)
23#define EXYNOS4_GPIO_A1_NR (6)
24#define EXYNOS4_GPIO_B_NR (8)
25#define EXYNOS4_GPIO_C0_NR (5)
26#define EXYNOS4_GPIO_C1_NR (5)
27#define EXYNOS4_GPIO_D0_NR (4)
28#define EXYNOS4_GPIO_D1_NR (4)
29#define EXYNOS4_GPIO_E0_NR (5)
30#define EXYNOS4_GPIO_E1_NR (8)
31#define EXYNOS4_GPIO_E2_NR (6)
32#define EXYNOS4_GPIO_E3_NR (8)
33#define EXYNOS4_GPIO_E4_NR (8)
34#define EXYNOS4_GPIO_F0_NR (8)
35#define EXYNOS4_GPIO_F1_NR (8)
36#define EXYNOS4_GPIO_F2_NR (8)
37#define EXYNOS4_GPIO_F3_NR (6)
38#define EXYNOS4_GPIO_J0_NR (8)
39#define EXYNOS4_GPIO_J1_NR (5)
40#define EXYNOS4_GPIO_K0_NR (7)
41#define EXYNOS4_GPIO_K1_NR (7)
42#define EXYNOS4_GPIO_K2_NR (7)
43#define EXYNOS4_GPIO_K3_NR (7)
44#define EXYNOS4_GPIO_L0_NR (8)
45#define EXYNOS4_GPIO_L1_NR (3)
46#define EXYNOS4_GPIO_L2_NR (8)
47#define EXYNOS4_GPIO_X0_NR (8)
48#define EXYNOS4_GPIO_X1_NR (8)
49#define EXYNOS4_GPIO_X2_NR (8)
50#define EXYNOS4_GPIO_X3_NR (8)
51#define EXYNOS4_GPIO_Y0_NR (6)
52#define EXYNOS4_GPIO_Y1_NR (4)
53#define EXYNOS4_GPIO_Y2_NR (6)
54#define EXYNOS4_GPIO_Y3_NR (8)
55#define EXYNOS4_GPIO_Y4_NR (8)
56#define EXYNOS4_GPIO_Y5_NR (8)
57#define EXYNOS4_GPIO_Y6_NR (8)
58#define EXYNOS4_GPIO_Z_NR (7)
59
60/* EXYNOS4 GPIO bank numbers */
61
62enum exynos4_gpio_number {
63 EXYNOS4_GPIO_A0_START = 0,
64 EXYNOS4_GPIO_A1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A0),
65 EXYNOS4_GPIO_B_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A1),
66 EXYNOS4_GPIO_C0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_B),
67 EXYNOS4_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
68 EXYNOS4_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
69 EXYNOS4_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
70 EXYNOS4_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
71 EXYNOS4_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E0),
72 EXYNOS4_GPIO_E2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E1),
73 EXYNOS4_GPIO_E3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E2),
74 EXYNOS4_GPIO_E4_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E3),
75 EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4),
76 EXYNOS4_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
77 EXYNOS4_GPIO_F2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
78 EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
79 EXYNOS4_GPIO_J0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F3),
80 EXYNOS4_GPIO_J1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J0),
81 EXYNOS4_GPIO_K0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J1),
82 EXYNOS4_GPIO_K1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K0),
83 EXYNOS4_GPIO_K2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K1),
84 EXYNOS4_GPIO_K3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K2),
85 EXYNOS4_GPIO_L0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K3),
86 EXYNOS4_GPIO_L1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L0),
87 EXYNOS4_GPIO_L2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L1),
88 EXYNOS4_GPIO_X0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L2),
89 EXYNOS4_GPIO_X1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X0),
90 EXYNOS4_GPIO_X2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X1),
91 EXYNOS4_GPIO_X3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X2),
92 EXYNOS4_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X3),
93 EXYNOS4_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y0),
94 EXYNOS4_GPIO_Y2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y1),
95 EXYNOS4_GPIO_Y3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y2),
96 EXYNOS4_GPIO_Y4_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y3),
97 EXYNOS4_GPIO_Y5_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y4),
98 EXYNOS4_GPIO_Y6_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y5),
99 EXYNOS4_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y6),
100};
101
102/* EXYNOS4 GPIO number definitions */
103
104#define EXYNOS4_GPA0(_nr) (EXYNOS4_GPIO_A0_START + (_nr))
105#define EXYNOS4_GPA1(_nr) (EXYNOS4_GPIO_A1_START + (_nr))
106#define EXYNOS4_GPB(_nr) (EXYNOS4_GPIO_B_START + (_nr))
107#define EXYNOS4_GPC0(_nr) (EXYNOS4_GPIO_C0_START + (_nr))
108#define EXYNOS4_GPC1(_nr) (EXYNOS4_GPIO_C1_START + (_nr))
109#define EXYNOS4_GPD0(_nr) (EXYNOS4_GPIO_D0_START + (_nr))
110#define EXYNOS4_GPD1(_nr) (EXYNOS4_GPIO_D1_START + (_nr))
111#define EXYNOS4_GPE0(_nr) (EXYNOS4_GPIO_E0_START + (_nr))
112#define EXYNOS4_GPE1(_nr) (EXYNOS4_GPIO_E1_START + (_nr))
113#define EXYNOS4_GPE2(_nr) (EXYNOS4_GPIO_E2_START + (_nr))
114#define EXYNOS4_GPE3(_nr) (EXYNOS4_GPIO_E3_START + (_nr))
115#define EXYNOS4_GPE4(_nr) (EXYNOS4_GPIO_E4_START + (_nr))
116#define EXYNOS4_GPF0(_nr) (EXYNOS4_GPIO_F0_START + (_nr))
117#define EXYNOS4_GPF1(_nr) (EXYNOS4_GPIO_F1_START + (_nr))
118#define EXYNOS4_GPF2(_nr) (EXYNOS4_GPIO_F2_START + (_nr))
119#define EXYNOS4_GPF3(_nr) (EXYNOS4_GPIO_F3_START + (_nr))
120#define EXYNOS4_GPJ0(_nr) (EXYNOS4_GPIO_J0_START + (_nr))
121#define EXYNOS4_GPJ1(_nr) (EXYNOS4_GPIO_J1_START + (_nr))
122#define EXYNOS4_GPK0(_nr) (EXYNOS4_GPIO_K0_START + (_nr))
123#define EXYNOS4_GPK1(_nr) (EXYNOS4_GPIO_K1_START + (_nr))
124#define EXYNOS4_GPK2(_nr) (EXYNOS4_GPIO_K2_START + (_nr))
125#define EXYNOS4_GPK3(_nr) (EXYNOS4_GPIO_K3_START + (_nr))
126#define EXYNOS4_GPL0(_nr) (EXYNOS4_GPIO_L0_START + (_nr))
127#define EXYNOS4_GPL1(_nr) (EXYNOS4_GPIO_L1_START + (_nr))
128#define EXYNOS4_GPL2(_nr) (EXYNOS4_GPIO_L2_START + (_nr))
129#define EXYNOS4_GPX0(_nr) (EXYNOS4_GPIO_X0_START + (_nr))
130#define EXYNOS4_GPX1(_nr) (EXYNOS4_GPIO_X1_START + (_nr))
131#define EXYNOS4_GPX2(_nr) (EXYNOS4_GPIO_X2_START + (_nr))
132#define EXYNOS4_GPX3(_nr) (EXYNOS4_GPIO_X3_START + (_nr))
133#define EXYNOS4_GPY0(_nr) (EXYNOS4_GPIO_Y0_START + (_nr))
134#define EXYNOS4_GPY1(_nr) (EXYNOS4_GPIO_Y1_START + (_nr))
135#define EXYNOS4_GPY2(_nr) (EXYNOS4_GPIO_Y2_START + (_nr))
136#define EXYNOS4_GPY3(_nr) (EXYNOS4_GPIO_Y3_START + (_nr))
137#define EXYNOS4_GPY4(_nr) (EXYNOS4_GPIO_Y4_START + (_nr))
138#define EXYNOS4_GPY5(_nr) (EXYNOS4_GPIO_Y5_START + (_nr))
139#define EXYNOS4_GPY6(_nr) (EXYNOS4_GPIO_Y6_START + (_nr))
140#define EXYNOS4_GPZ(_nr) (EXYNOS4_GPIO_Z_START + (_nr))
141
142/* the end of the EXYNOS4 specific gpios */
143
144#define EXYNOS4_GPIO_END (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
145
146/* EXYNOS5 GPIO bank sizes */
147
148#define EXYNOS5_GPIO_A0_NR (8)
149#define EXYNOS5_GPIO_A1_NR (6)
150#define EXYNOS5_GPIO_A2_NR (8)
151#define EXYNOS5_GPIO_B0_NR (5)
152#define EXYNOS5_GPIO_B1_NR (5)
153#define EXYNOS5_GPIO_B2_NR (4)
154#define EXYNOS5_GPIO_B3_NR (4)
155#define EXYNOS5_GPIO_C0_NR (7)
156#define EXYNOS5_GPIO_C1_NR (4)
157#define EXYNOS5_GPIO_C2_NR (7)
158#define EXYNOS5_GPIO_C3_NR (7)
159#define EXYNOS5_GPIO_C4_NR (7)
160#define EXYNOS5_GPIO_D0_NR (4)
161#define EXYNOS5_GPIO_D1_NR (8)
162#define EXYNOS5_GPIO_Y0_NR (6)
163#define EXYNOS5_GPIO_Y1_NR (4)
164#define EXYNOS5_GPIO_Y2_NR (6)
165#define EXYNOS5_GPIO_Y3_NR (8)
166#define EXYNOS5_GPIO_Y4_NR (8)
167#define EXYNOS5_GPIO_Y5_NR (8)
168#define EXYNOS5_GPIO_Y6_NR (8)
169#define EXYNOS5_GPIO_X0_NR (8)
170#define EXYNOS5_GPIO_X1_NR (8)
171#define EXYNOS5_GPIO_X2_NR (8)
172#define EXYNOS5_GPIO_X3_NR (8)
173#define EXYNOS5_GPIO_E0_NR (8)
174#define EXYNOS5_GPIO_E1_NR (2)
175#define EXYNOS5_GPIO_F0_NR (4)
176#define EXYNOS5_GPIO_F1_NR (4)
177#define EXYNOS5_GPIO_G0_NR (8)
178#define EXYNOS5_GPIO_G1_NR (8)
179#define EXYNOS5_GPIO_G2_NR (2)
180#define EXYNOS5_GPIO_H0_NR (4)
181#define EXYNOS5_GPIO_H1_NR (8)
182#define EXYNOS5_GPIO_V0_NR (8)
183#define EXYNOS5_GPIO_V1_NR (8)
184#define EXYNOS5_GPIO_V2_NR (8)
185#define EXYNOS5_GPIO_V3_NR (8)
186#define EXYNOS5_GPIO_V4_NR (2)
187#define EXYNOS5_GPIO_Z_NR (7)
188
189/* EXYNOS5 GPIO bank numbers */
190
191enum exynos5_gpio_number {
192 EXYNOS5_GPIO_A0_START = 0,
193 EXYNOS5_GPIO_A1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A0),
194 EXYNOS5_GPIO_A2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A1),
195 EXYNOS5_GPIO_B0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A2),
196 EXYNOS5_GPIO_B1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B0),
197 EXYNOS5_GPIO_B2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B1),
198 EXYNOS5_GPIO_B3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B2),
199 EXYNOS5_GPIO_C0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B3),
200 EXYNOS5_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
201 EXYNOS5_GPIO_C2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
202 EXYNOS5_GPIO_C3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
203 EXYNOS5_GPIO_C4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
204 EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
205 EXYNOS5_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
206 EXYNOS5_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
207 EXYNOS5_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
208 EXYNOS5_GPIO_Y2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y1),
209 EXYNOS5_GPIO_Y3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y2),
210 EXYNOS5_GPIO_Y4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y3),
211 EXYNOS5_GPIO_Y5_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y4),
212 EXYNOS5_GPIO_Y6_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y5),
213 EXYNOS5_GPIO_X0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y6),
214 EXYNOS5_GPIO_X1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X0),
215 EXYNOS5_GPIO_X2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X1),
216 EXYNOS5_GPIO_X3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X2),
217 EXYNOS5_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X3),
218 EXYNOS5_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E0),
219 EXYNOS5_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E1),
220 EXYNOS5_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F0),
221 EXYNOS5_GPIO_G0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F1),
222 EXYNOS5_GPIO_G1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G0),
223 EXYNOS5_GPIO_G2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G1),
224 EXYNOS5_GPIO_H0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G2),
225 EXYNOS5_GPIO_H1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H0),
226 EXYNOS5_GPIO_V0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H1),
227 EXYNOS5_GPIO_V1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V0),
228 EXYNOS5_GPIO_V2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V1),
229 EXYNOS5_GPIO_V3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V2),
230 EXYNOS5_GPIO_V4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V3),
231 EXYNOS5_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V4),
232};
233
234/* EXYNOS5 GPIO number definitions */
235
236#define EXYNOS5_GPA0(_nr) (EXYNOS5_GPIO_A0_START + (_nr))
237#define EXYNOS5_GPA1(_nr) (EXYNOS5_GPIO_A1_START + (_nr))
238#define EXYNOS5_GPA2(_nr) (EXYNOS5_GPIO_A2_START + (_nr))
239#define EXYNOS5_GPB0(_nr) (EXYNOS5_GPIO_B0_START + (_nr))
240#define EXYNOS5_GPB1(_nr) (EXYNOS5_GPIO_B1_START + (_nr))
241#define EXYNOS5_GPB2(_nr) (EXYNOS5_GPIO_B2_START + (_nr))
242#define EXYNOS5_GPB3(_nr) (EXYNOS5_GPIO_B3_START + (_nr))
243#define EXYNOS5_GPC0(_nr) (EXYNOS5_GPIO_C0_START + (_nr))
244#define EXYNOS5_GPC1(_nr) (EXYNOS5_GPIO_C1_START + (_nr))
245#define EXYNOS5_GPC2(_nr) (EXYNOS5_GPIO_C2_START + (_nr))
246#define EXYNOS5_GPC3(_nr) (EXYNOS5_GPIO_C3_START + (_nr))
247#define EXYNOS5_GPC4(_nr) (EXYNOS5_GPIO_C4_START + (_nr))
248#define EXYNOS5_GPD0(_nr) (EXYNOS5_GPIO_D0_START + (_nr))
249#define EXYNOS5_GPD1(_nr) (EXYNOS5_GPIO_D1_START + (_nr))
250#define EXYNOS5_GPY0(_nr) (EXYNOS5_GPIO_Y0_START + (_nr))
251#define EXYNOS5_GPY1(_nr) (EXYNOS5_GPIO_Y1_START + (_nr))
252#define EXYNOS5_GPY2(_nr) (EXYNOS5_GPIO_Y2_START + (_nr))
253#define EXYNOS5_GPY3(_nr) (EXYNOS5_GPIO_Y3_START + (_nr))
254#define EXYNOS5_GPY4(_nr) (EXYNOS5_GPIO_Y4_START + (_nr))
255#define EXYNOS5_GPY5(_nr) (EXYNOS5_GPIO_Y5_START + (_nr))
256#define EXYNOS5_GPY6(_nr) (EXYNOS5_GPIO_Y6_START + (_nr))
257#define EXYNOS5_GPX0(_nr) (EXYNOS5_GPIO_X0_START + (_nr))
258#define EXYNOS5_GPX1(_nr) (EXYNOS5_GPIO_X1_START + (_nr))
259#define EXYNOS5_GPX2(_nr) (EXYNOS5_GPIO_X2_START + (_nr))
260#define EXYNOS5_GPX3(_nr) (EXYNOS5_GPIO_X3_START + (_nr))
261#define EXYNOS5_GPE0(_nr) (EXYNOS5_GPIO_E0_START + (_nr))
262#define EXYNOS5_GPE1(_nr) (EXYNOS5_GPIO_E1_START + (_nr))
263#define EXYNOS5_GPF0(_nr) (EXYNOS5_GPIO_F0_START + (_nr))
264#define EXYNOS5_GPF1(_nr) (EXYNOS5_GPIO_F1_START + (_nr))
265#define EXYNOS5_GPG0(_nr) (EXYNOS5_GPIO_G0_START + (_nr))
266#define EXYNOS5_GPG1(_nr) (EXYNOS5_GPIO_G1_START + (_nr))
267#define EXYNOS5_GPG2(_nr) (EXYNOS5_GPIO_G2_START + (_nr))
268#define EXYNOS5_GPH0(_nr) (EXYNOS5_GPIO_H0_START + (_nr))
269#define EXYNOS5_GPH1(_nr) (EXYNOS5_GPIO_H1_START + (_nr))
270#define EXYNOS5_GPV0(_nr) (EXYNOS5_GPIO_V0_START + (_nr))
271#define EXYNOS5_GPV1(_nr) (EXYNOS5_GPIO_V1_START + (_nr))
272#define EXYNOS5_GPV2(_nr) (EXYNOS5_GPIO_V2_START + (_nr))
273#define EXYNOS5_GPV3(_nr) (EXYNOS5_GPIO_V3_START + (_nr))
274#define EXYNOS5_GPV4(_nr) (EXYNOS5_GPIO_V4_START + (_nr))
275#define EXYNOS5_GPZ(_nr) (EXYNOS5_GPIO_Z_START + (_nr))
276
277/* the end of the EXYNOS5 specific gpios */
278
279#define EXYNOS5_GPIO_END (EXYNOS5_GPZ(EXYNOS5_GPIO_Z_NR) + 1)
280
281/* actually, EXYNOS5_GPIO_END is bigger than EXYNOS4 */
282
283#define S3C_GPIO_END (EXYNOS5_GPIO_END)
284
285/* define the number of gpios */
286
287#define ARCH_NR_GPIOS (CONFIG_SAMSUNG_GPIO_EXTRA + S3C_GPIO_END)
288
289#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
deleted file mode 100644
index c72f59d91fce..000000000000
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ /dev/null
@@ -1,476 +0,0 @@
1/*
2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS - IRQ definitions
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __ASM_ARCH_IRQS_H
13#define __ASM_ARCH_IRQS_H __FILE__
14
15#include <plat/irqs.h>
16
17/* PPI: Private Peripheral Interrupt */
18
19#define IRQ_PPI(x) (x + 16)
20
21/* SPI: Shared Peripheral Interrupt */
22
23#define IRQ_SPI(x) (x + 32)
24
25/* COMBINER */
26
27#define MAX_IRQ_IN_COMBINER 8
28#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
29#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
30
31/* For EXYNOS4 and EXYNOS5 */
32
33#define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32)
34
35/* For EXYNOS4 SoCs */
36
37#define EXYNOS4_IRQ_EINT0 IRQ_SPI(16)
38#define EXYNOS4_IRQ_EINT1 IRQ_SPI(17)
39#define EXYNOS4_IRQ_EINT2 IRQ_SPI(18)
40#define EXYNOS4_IRQ_EINT3 IRQ_SPI(19)
41#define EXYNOS4_IRQ_EINT4 IRQ_SPI(20)
42#define EXYNOS4_IRQ_EINT5 IRQ_SPI(21)
43#define EXYNOS4_IRQ_EINT6 IRQ_SPI(22)
44#define EXYNOS4_IRQ_EINT7 IRQ_SPI(23)
45#define EXYNOS4_IRQ_EINT8 IRQ_SPI(24)
46#define EXYNOS4_IRQ_EINT9 IRQ_SPI(25)
47#define EXYNOS4_IRQ_EINT10 IRQ_SPI(26)
48#define EXYNOS4_IRQ_EINT11 IRQ_SPI(27)
49#define EXYNOS4_IRQ_EINT12 IRQ_SPI(28)
50#define EXYNOS4_IRQ_EINT13 IRQ_SPI(29)
51#define EXYNOS4_IRQ_EINT14 IRQ_SPI(30)
52#define EXYNOS4_IRQ_EINT15 IRQ_SPI(31)
53
54#define EXYNOS4_IRQ_MDMA0 IRQ_SPI(33)
55#define EXYNOS4_IRQ_MDMA1 IRQ_SPI(34)
56#define EXYNOS4_IRQ_PDMA0 IRQ_SPI(35)
57#define EXYNOS4_IRQ_PDMA1 IRQ_SPI(36)
58#define EXYNOS4_IRQ_TIMER0_VIC IRQ_SPI(37)
59#define EXYNOS4_IRQ_TIMER1_VIC IRQ_SPI(38)
60#define EXYNOS4_IRQ_TIMER2_VIC IRQ_SPI(39)
61#define EXYNOS4_IRQ_TIMER3_VIC IRQ_SPI(40)
62#define EXYNOS4_IRQ_TIMER4_VIC IRQ_SPI(41)
63#define EXYNOS4_IRQ_MCT_L0 IRQ_SPI(42)
64#define EXYNOS4_IRQ_WDT IRQ_SPI(43)
65#define EXYNOS4_IRQ_RTC_ALARM IRQ_SPI(44)
66#define EXYNOS4_IRQ_RTC_TIC IRQ_SPI(45)
67#define EXYNOS4_IRQ_GPIO_XB IRQ_SPI(46)
68#define EXYNOS4_IRQ_GPIO_XA IRQ_SPI(47)
69#define EXYNOS4_IRQ_MCT_L1 IRQ_SPI(48)
70
71#define EXYNOS4_IRQ_UART0 IRQ_SPI(52)
72#define EXYNOS4_IRQ_UART1 IRQ_SPI(53)
73#define EXYNOS4_IRQ_UART2 IRQ_SPI(54)
74#define EXYNOS4_IRQ_UART3 IRQ_SPI(55)
75#define EXYNOS4_IRQ_UART4 IRQ_SPI(56)
76#define EXYNOS4_IRQ_MCT_G0 IRQ_SPI(57)
77#define EXYNOS4_IRQ_IIC IRQ_SPI(58)
78#define EXYNOS4_IRQ_IIC1 IRQ_SPI(59)
79#define EXYNOS4_IRQ_IIC2 IRQ_SPI(60)
80#define EXYNOS4_IRQ_IIC3 IRQ_SPI(61)
81#define EXYNOS4_IRQ_IIC4 IRQ_SPI(62)
82#define EXYNOS4_IRQ_IIC5 IRQ_SPI(63)
83#define EXYNOS4_IRQ_IIC6 IRQ_SPI(64)
84#define EXYNOS4_IRQ_IIC7 IRQ_SPI(65)
85#define EXYNOS4_IRQ_SPI0 IRQ_SPI(66)
86#define EXYNOS4_IRQ_SPI1 IRQ_SPI(67)
87#define EXYNOS4_IRQ_SPI2 IRQ_SPI(68)
88
89#define EXYNOS4_IRQ_USB_HOST IRQ_SPI(70)
90#define EXYNOS4_IRQ_USB_HSOTG IRQ_SPI(71)
91#define EXYNOS4_IRQ_MODEM_IF IRQ_SPI(72)
92#define EXYNOS4_IRQ_HSMMC0 IRQ_SPI(73)
93#define EXYNOS4_IRQ_HSMMC1 IRQ_SPI(74)
94#define EXYNOS4_IRQ_HSMMC2 IRQ_SPI(75)
95#define EXYNOS4_IRQ_HSMMC3 IRQ_SPI(76)
96#define EXYNOS4_IRQ_DWMCI IRQ_SPI(77)
97
98#define EXYNOS4_IRQ_MIPI_CSIS0 IRQ_SPI(78)
99#define EXYNOS4_IRQ_MIPI_CSIS1 IRQ_SPI(80)
100
101#define EXYNOS4_IRQ_ONENAND_AUDI IRQ_SPI(82)
102#define EXYNOS4_IRQ_ROTATOR IRQ_SPI(83)
103#define EXYNOS4_IRQ_FIMC0 IRQ_SPI(84)
104#define EXYNOS4_IRQ_FIMC1 IRQ_SPI(85)
105#define EXYNOS4_IRQ_FIMC2 IRQ_SPI(86)
106#define EXYNOS4_IRQ_FIMC3 IRQ_SPI(87)
107#define EXYNOS4_IRQ_JPEG IRQ_SPI(88)
108#define EXYNOS4_IRQ_2D IRQ_SPI(89)
109#define EXYNOS4_IRQ_PCIE IRQ_SPI(90)
110
111#define EXYNOS4_IRQ_MIXER IRQ_SPI(91)
112#define EXYNOS4_IRQ_HDMI IRQ_SPI(92)
113#define EXYNOS4_IRQ_IIC_HDMIPHY IRQ_SPI(93)
114#define EXYNOS4_IRQ_MFC IRQ_SPI(94)
115#define EXYNOS4_IRQ_SDO IRQ_SPI(95)
116
117#define EXYNOS4_IRQ_AUDIO_SS IRQ_SPI(96)
118#define EXYNOS4_IRQ_I2S0 IRQ_SPI(97)
119#define EXYNOS4_IRQ_I2S1 IRQ_SPI(98)
120#define EXYNOS4_IRQ_I2S2 IRQ_SPI(99)
121#define EXYNOS4_IRQ_AC97 IRQ_SPI(100)
122
123#define EXYNOS4_IRQ_SPDIF IRQ_SPI(104)
124#define EXYNOS4_IRQ_ADC0 IRQ_SPI(105)
125#define EXYNOS4_IRQ_PEN0 IRQ_SPI(106)
126#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107)
127#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108)
128#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109)
129#define EXYNOS4_IRQ_POWER_PMU IRQ_SPI(110)
130#define EXYNOS4_IRQ_GPS IRQ_SPI(111)
131#define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
132#define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113)
133
134#define EXYNOS4_IRQ_TSI IRQ_SPI(115)
135#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
136
137#define EXYNOS4_IRQ_PMU COMBINER_IRQ(2, 2)
138#define EXYNOS4_IRQ_PMU_CPU1 COMBINER_IRQ(3, 2)
139#define EXYNOS4_IRQ_PMU_CPU2 COMBINER_IRQ(18, 2)
140#define EXYNOS4_IRQ_PMU_CPU3 COMBINER_IRQ(19, 2)
141
142#define EXYNOS4_IRQ_TMU_TRIG0 COMBINER_IRQ(2, 4)
143#define EXYNOS4_IRQ_TMU_TRIG1 COMBINER_IRQ(3, 4)
144
145#define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
146#define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
147#define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
148#define EXYNOS4_IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3)
149#define EXYNOS4_IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4)
150#define EXYNOS4_IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5)
151#define EXYNOS4_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6)
152#define EXYNOS4_IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7)
153
154#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0)
155#define EXYNOS4_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1)
156#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2)
157#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3)
158#define EXYNOS4_IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4)
159#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5)
160#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
161#define EXYNOS4_IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
162
163#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE0_0 COMBINER_IRQ(16, 0)
164#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE1_0 COMBINER_IRQ(16, 1)
165#define EXYNOS4_IRQ_SYSMMU_FIMC_ISP_0 COMBINER_IRQ(16, 2)
166#define EXYNOS4_IRQ_SYSMMU_FIMC_DRC_0 COMBINER_IRQ(16, 3)
167#define EXYNOS4_IRQ_SYSMMU_FIMC_FD_0 COMBINER_IRQ(16, 4)
168#define EXYNOS4_IRQ_SYSMMU_FIMC_CX_0 COMBINER_IRQ(16, 5)
169
170#define EXYNOS4_IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
171#define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
172#define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
173
174#define EXYNOS4210_MAX_COMBINER_NR 16
175#define EXYNOS4212_MAX_COMBINER_NR 18
176#define EXYNOS4412_MAX_COMBINER_NR 20
177#define EXYNOS4_MAX_COMBINER_NR EXYNOS4412_MAX_COMBINER_NR
178
179#define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16
180#define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9
181
182/*
183 * For Compatibility:
184 * the default is for EXYNOS4, and
185 * for exynos5, should be re-mapped at function
186 */
187
188#define IRQ_TIMER0_VIC EXYNOS4_IRQ_TIMER0_VIC
189#define IRQ_TIMER1_VIC EXYNOS4_IRQ_TIMER1_VIC
190#define IRQ_TIMER2_VIC EXYNOS4_IRQ_TIMER2_VIC
191#define IRQ_TIMER3_VIC EXYNOS4_IRQ_TIMER3_VIC
192#define IRQ_TIMER4_VIC EXYNOS4_IRQ_TIMER4_VIC
193
194#define IRQ_WDT EXYNOS4_IRQ_WDT
195#define IRQ_RTC_ALARM EXYNOS4_IRQ_RTC_ALARM
196#define IRQ_RTC_TIC EXYNOS4_IRQ_RTC_TIC
197#define IRQ_GPIO_XB EXYNOS4_IRQ_GPIO_XB
198#define IRQ_GPIO_XA EXYNOS4_IRQ_GPIO_XA
199
200#define IRQ_IIC EXYNOS4_IRQ_IIC
201#define IRQ_IIC1 EXYNOS4_IRQ_IIC1
202#define IRQ_IIC3 EXYNOS4_IRQ_IIC3
203#define IRQ_IIC5 EXYNOS4_IRQ_IIC5
204#define IRQ_IIC6 EXYNOS4_IRQ_IIC6
205#define IRQ_IIC7 EXYNOS4_IRQ_IIC7
206
207#define IRQ_SPI0 EXYNOS4_IRQ_SPI0
208#define IRQ_SPI1 EXYNOS4_IRQ_SPI1
209#define IRQ_SPI2 EXYNOS4_IRQ_SPI2
210
211#define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST
212#define IRQ_OTG EXYNOS4_IRQ_USB_HSOTG
213
214#define IRQ_HSMMC0 EXYNOS4_IRQ_HSMMC0
215#define IRQ_HSMMC1 EXYNOS4_IRQ_HSMMC1
216#define IRQ_HSMMC2 EXYNOS4_IRQ_HSMMC2
217#define IRQ_HSMMC3 EXYNOS4_IRQ_HSMMC3
218
219#define IRQ_MIPI_CSIS0 EXYNOS4_IRQ_MIPI_CSIS0
220
221#define IRQ_ONENAND_AUDI EXYNOS4_IRQ_ONENAND_AUDI
222
223#define IRQ_FIMC0 EXYNOS4_IRQ_FIMC0
224#define IRQ_FIMC1 EXYNOS4_IRQ_FIMC1
225#define IRQ_FIMC2 EXYNOS4_IRQ_FIMC2
226#define IRQ_FIMC3 EXYNOS4_IRQ_FIMC3
227#define IRQ_JPEG EXYNOS4_IRQ_JPEG
228#define IRQ_2D EXYNOS4_IRQ_2D
229
230#define IRQ_MIXER EXYNOS4_IRQ_MIXER
231#define IRQ_HDMI EXYNOS4_IRQ_HDMI
232#define IRQ_IIC_HDMIPHY EXYNOS4_IRQ_IIC_HDMIPHY
233#define IRQ_MFC EXYNOS4_IRQ_MFC
234#define IRQ_SDO EXYNOS4_IRQ_SDO
235
236#define IRQ_I2S0 EXYNOS4_IRQ_I2S0
237
238#define IRQ_ADC EXYNOS4_IRQ_ADC0
239#define IRQ_TC EXYNOS4_IRQ_PEN0
240
241#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
242
243#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
244#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC
245#define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM
246
247#define IRQ_GPIO1_NR_GROUPS EXYNOS4_IRQ_GPIO1_NR_GROUPS
248#define IRQ_GPIO2_NR_GROUPS EXYNOS4_IRQ_GPIO2_NR_GROUPS
249
250/* For EXYNOS5 SoCs */
251
252#define EXYNOS5_IRQ_MDMA0 IRQ_SPI(33)
253#define EXYNOS5_IRQ_PDMA0 IRQ_SPI(34)
254#define EXYNOS5_IRQ_PDMA1 IRQ_SPI(35)
255#define EXYNOS5_IRQ_TIMER0_VIC IRQ_SPI(36)
256#define EXYNOS5_IRQ_TIMER1_VIC IRQ_SPI(37)
257#define EXYNOS5_IRQ_TIMER2_VIC IRQ_SPI(38)
258#define EXYNOS5_IRQ_TIMER3_VIC IRQ_SPI(39)
259#define EXYNOS5_IRQ_TIMER4_VIC IRQ_SPI(40)
260#define EXYNOS5_IRQ_RTIC IRQ_SPI(41)
261#define EXYNOS5_IRQ_WDT IRQ_SPI(42)
262#define EXYNOS5_IRQ_RTC_ALARM IRQ_SPI(43)
263#define EXYNOS5_IRQ_RTC_TIC IRQ_SPI(44)
264#define EXYNOS5_IRQ_GPIO_XB IRQ_SPI(45)
265#define EXYNOS5_IRQ_GPIO_XA IRQ_SPI(46)
266#define EXYNOS5_IRQ_GPIO IRQ_SPI(47)
267#define EXYNOS5_IRQ_IEM_IEC IRQ_SPI(48)
268#define EXYNOS5_IRQ_IEM_APC IRQ_SPI(49)
269#define EXYNOS5_IRQ_GPIO_C2C IRQ_SPI(50)
270#define EXYNOS5_IRQ_IIC IRQ_SPI(56)
271#define EXYNOS5_IRQ_IIC1 IRQ_SPI(57)
272#define EXYNOS5_IRQ_IIC2 IRQ_SPI(58)
273#define EXYNOS5_IRQ_IIC3 IRQ_SPI(59)
274#define EXYNOS5_IRQ_IIC4 IRQ_SPI(60)
275#define EXYNOS5_IRQ_IIC5 IRQ_SPI(61)
276#define EXYNOS5_IRQ_IIC6 IRQ_SPI(62)
277#define EXYNOS5_IRQ_IIC7 IRQ_SPI(63)
278#define EXYNOS5_IRQ_IIC_HDMIPHY IRQ_SPI(64)
279#define EXYNOS5_IRQ_TMU IRQ_SPI(65)
280#define EXYNOS5_IRQ_FIQ_0 IRQ_SPI(66)
281#define EXYNOS5_IRQ_FIQ_1 IRQ_SPI(67)
282#define EXYNOS5_IRQ_SPI0 IRQ_SPI(68)
283#define EXYNOS5_IRQ_SPI1 IRQ_SPI(69)
284#define EXYNOS5_IRQ_SPI2 IRQ_SPI(70)
285#define EXYNOS5_IRQ_USB_HOST IRQ_SPI(71)
286#define EXYNOS5_IRQ_USB3_DRD IRQ_SPI(72)
287#define EXYNOS5_IRQ_MIPI_HSI IRQ_SPI(73)
288#define EXYNOS5_IRQ_USB_HSOTG IRQ_SPI(74)
289#define EXYNOS5_IRQ_HSMMC0 IRQ_SPI(75)
290#define EXYNOS5_IRQ_HSMMC1 IRQ_SPI(76)
291#define EXYNOS5_IRQ_HSMMC2 IRQ_SPI(77)
292#define EXYNOS5_IRQ_HSMMC3 IRQ_SPI(78)
293#define EXYNOS5_IRQ_MIPICSI0 IRQ_SPI(79)
294#define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80)
295#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81)
296#define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82)
297#define EXYNOS5_IRQ_WDT_IOP IRQ_SPI(83)
298#define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84)
299#define EXYNOS5_IRQ_GSC0 IRQ_SPI(85)
300#define EXYNOS5_IRQ_GSC1 IRQ_SPI(86)
301#define EXYNOS5_IRQ_GSC2 IRQ_SPI(87)
302#define EXYNOS5_IRQ_GSC3 IRQ_SPI(88)
303#define EXYNOS5_IRQ_JPEG IRQ_SPI(89)
304#define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90)
305#define EXYNOS5_IRQ_2D IRQ_SPI(91)
306#define EXYNOS5_IRQ_EFNFCON_0 IRQ_SPI(92)
307#define EXYNOS5_IRQ_EFNFCON_1 IRQ_SPI(93)
308#define EXYNOS5_IRQ_MIXER IRQ_SPI(94)
309#define EXYNOS5_IRQ_HDMI IRQ_SPI(95)
310#define EXYNOS5_IRQ_MFC IRQ_SPI(96)
311#define EXYNOS5_IRQ_AUDIO_SS IRQ_SPI(97)
312#define EXYNOS5_IRQ_I2S0 IRQ_SPI(98)
313#define EXYNOS5_IRQ_I2S1 IRQ_SPI(99)
314#define EXYNOS5_IRQ_I2S2 IRQ_SPI(100)
315#define EXYNOS5_IRQ_AC97 IRQ_SPI(101)
316#define EXYNOS5_IRQ_PCM0 IRQ_SPI(102)
317#define EXYNOS5_IRQ_PCM1 IRQ_SPI(103)
318#define EXYNOS5_IRQ_PCM2 IRQ_SPI(104)
319#define EXYNOS5_IRQ_SPDIF IRQ_SPI(105)
320#define EXYNOS5_IRQ_ADC0 IRQ_SPI(106)
321#define EXYNOS5_IRQ_ADC1 IRQ_SPI(107)
322#define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108)
323#define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109)
324#define EXYNOS5_IRQ_CAM_C IRQ_SPI(110)
325#define EXYNOS5_IRQ_EAGLE_PMU IRQ_SPI(111)
326#define EXYNOS5_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
327#define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113)
328#define EXYNOS5_IRQ_CEC IRQ_SPI(114)
329#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
330
331#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
332#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
333#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
334#define EXYNOS5_IRQ_FIMC_LITE1 IRQ_SPI(126)
335#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127)
336
337/* EXYNOS5440 */
338
339#define EXYNOS5440_IRQ_UART0 IRQ_SPI(2)
340#define EXYNOS5440_IRQ_UART1 IRQ_SPI(3)
341
342#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2)
343
344#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0)
345#define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1)
346#define EXYNOS5_IRQ_SYSMMU_GSC1_0 COMBINER_IRQ(2, 2)
347#define EXYNOS5_IRQ_SYSMMU_GSC1_1 COMBINER_IRQ(2, 3)
348#define EXYNOS5_IRQ_SYSMMU_GSC2_0 COMBINER_IRQ(2, 4)
349#define EXYNOS5_IRQ_SYSMMU_GSC2_1 COMBINER_IRQ(2, 5)
350#define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6)
351#define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7)
352
353#define EXYNOS5_IRQ_SYSMMU_LITE2_0 COMBINER_IRQ(3, 0)
354#define EXYNOS5_IRQ_SYSMMU_LITE2_1 COMBINER_IRQ(3, 1)
355#define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2)
356#define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3)
357#define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4)
358#define EXYNOS5_IRQ_SYSMMU_LITE0_1 COMBINER_IRQ(3, 5)
359#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0 COMBINER_IRQ(3, 6)
360#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1 COMBINER_IRQ(3, 7)
361
362#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(4, 0)
363#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1 COMBINER_IRQ(4, 1)
364#define EXYNOS5_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 2)
365#define EXYNOS5_IRQ_SYSMMU_JPEG_1 COMBINER_IRQ(4, 3)
366
367#define EXYNOS5_IRQ_SYSMMU_FD_0 COMBINER_IRQ(5, 0)
368#define EXYNOS5_IRQ_SYSMMU_FD_1 COMBINER_IRQ(5, 1)
369#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0 COMBINER_IRQ(5, 2)
370#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1 COMBINER_IRQ(5, 3)
371#define EXYNOS5_IRQ_SYSMMU_MCUISP_0 COMBINER_IRQ(5, 4)
372#define EXYNOS5_IRQ_SYSMMU_MCUISP_1 COMBINER_IRQ(5, 5)
373#define EXYNOS5_IRQ_SYSMMU_3DNR_0 COMBINER_IRQ(5, 6)
374#define EXYNOS5_IRQ_SYSMMU_3DNR_1 COMBINER_IRQ(5, 7)
375
376#define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0)
377#define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1)
378#define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(6, 2)
379#define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(6, 3)
380#define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4)
381#define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5)
382#define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6)
383#define EXYNOS5_IRQ_SYSMMU_SSS_1 COMBINER_IRQ(6, 7)
384
385#define EXYNOS5_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(7, 0)
386#define EXYNOS5_IRQ_SYSMMU_MDMA0_1 COMBINER_IRQ(7, 1)
387#define EXYNOS5_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(7, 2)
388#define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3)
389#define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4)
390#define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5)
391
392#define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(8, 5)
393#define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(8, 6)
394
395#define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4)
396#define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5)
397
398#define EXYNOS5_IRQ_DP COMBINER_IRQ(10, 3)
399#define EXYNOS5_IRQ_SYSMMU_DIS0_0 COMBINER_IRQ(10, 4)
400#define EXYNOS5_IRQ_SYSMMU_DIS0_1 COMBINER_IRQ(10, 5)
401#define EXYNOS5_IRQ_SYSMMU_ISP_0 COMBINER_IRQ(10, 6)
402#define EXYNOS5_IRQ_SYSMMU_ISP_1 COMBINER_IRQ(10, 7)
403
404#define EXYNOS5_IRQ_SYSMMU_ODC_0 COMBINER_IRQ(11, 0)
405#define EXYNOS5_IRQ_SYSMMU_ODC_1 COMBINER_IRQ(11, 1)
406#define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6)
407#define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7)
408
409#define EXYNOS5_IRQ_MDMA1_ABORT COMBINER_IRQ(13, 1)
410
411#define EXYNOS5_IRQ_MDMA0_ABORT COMBINER_IRQ(15, 3)
412
413#define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4)
414#define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5)
415#define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6)
416
417#define EXYNOS5_IRQ_ARMIOP_GIC COMBINER_IRQ(19, 0)
418#define EXYNOS5_IRQ_ARMISP_GIC COMBINER_IRQ(19, 1)
419#define EXYNOS5_IRQ_IOP_GIC COMBINER_IRQ(19, 3)
420#define EXYNOS5_IRQ_ISP_GIC COMBINER_IRQ(19, 4)
421
422#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4)
423
424#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
425
426#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
427#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
428#define EXYNOS5_IRQ_SYSMMU_LITE1_1 COMBINER_IRQ(24, 2)
429#define EXYNOS5_IRQ_SYSMMU_2D_0 COMBINER_IRQ(24, 5)
430#define EXYNOS5_IRQ_SYSMMU_2D_1 COMBINER_IRQ(24, 6)
431
432#define EXYNOS5_IRQ_EINT2 COMBINER_IRQ(25, 0)
433#define EXYNOS5_IRQ_EINT3 COMBINER_IRQ(25, 1)
434
435#define EXYNOS5_IRQ_EINT4 COMBINER_IRQ(26, 0)
436#define EXYNOS5_IRQ_EINT5 COMBINER_IRQ(26, 1)
437
438#define EXYNOS5_IRQ_EINT6 COMBINER_IRQ(27, 0)
439#define EXYNOS5_IRQ_EINT7 COMBINER_IRQ(27, 1)
440
441#define EXYNOS5_IRQ_EINT8 COMBINER_IRQ(28, 0)
442#define EXYNOS5_IRQ_EINT9 COMBINER_IRQ(28, 1)
443
444#define EXYNOS5_IRQ_EINT10 COMBINER_IRQ(29, 0)
445#define EXYNOS5_IRQ_EINT11 COMBINER_IRQ(29, 1)
446
447#define EXYNOS5_IRQ_EINT12 COMBINER_IRQ(30, 0)
448#define EXYNOS5_IRQ_EINT13 COMBINER_IRQ(30, 1)
449
450#define EXYNOS5_IRQ_EINT14 COMBINER_IRQ(31, 0)
451#define EXYNOS5_IRQ_EINT15 COMBINER_IRQ(31, 1)
452
453#define EXYNOS5_MAX_COMBINER_NR 32
454
455#define EXYNOS5_IRQ_GPIO1_NR_GROUPS 14
456#define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9
457#define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5
458#define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1
459
460#define MAX_COMBINER_NR (EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \
461 EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR)
462
463#define S5P_EINT_BASE1 COMBINER_IRQ(MAX_COMBINER_NR, 0)
464#define S5P_EINT_BASE2 (S5P_EINT_BASE1 + 16)
465#define S5P_GPIOINT_BASE (S5P_EINT_BASE1 + 32)
466#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
467#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64)
468
469/* Set the default NR_IRQS */
470#define EXYNOS_NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
471
472#ifndef CONFIG_SPARSE_IRQ
473#define NR_IRQS EXYNOS_NR_IRQS
474#endif
475
476#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 92b29bb583cb..7b046b59d9ec 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -30,31 +30,6 @@
30#define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000 30#define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000
31#define EXYNOS5250_PA_SYSRAM_NS 0x0204F000 31#define EXYNOS5250_PA_SYSRAM_NS 0x0204F000
32 32
33#define EXYNOS4_PA_FIMC0 0x11800000
34#define EXYNOS4_PA_FIMC1 0x11810000
35#define EXYNOS4_PA_FIMC2 0x11820000
36#define EXYNOS4_PA_FIMC3 0x11830000
37
38#define EXYNOS4_PA_JPEG 0x11840000
39
40/* x = 0...1 */
41#define EXYNOS4_PA_FIMC_LITE(x) (0x12390000 + ((x) * 0x10000))
42
43#define EXYNOS4_PA_G2D 0x12800000
44
45#define EXYNOS4_PA_I2S0 0x03830000
46#define EXYNOS4_PA_I2S1 0xE3100000
47#define EXYNOS4_PA_I2S2 0xE2A00000
48
49#define EXYNOS4_PA_PCM0 0x03840000
50#define EXYNOS4_PA_PCM1 0x13980000
51#define EXYNOS4_PA_PCM2 0x13990000
52
53#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
54
55#define EXYNOS4_PA_ONENAND 0x0C000000
56#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
57
58#define EXYNOS_PA_CHIPID 0x10000000 33#define EXYNOS_PA_CHIPID 0x10000000
59 34
60#define EXYNOS4_PA_SYSCON 0x10010000 35#define EXYNOS4_PA_SYSCON 0x10010000
@@ -71,10 +46,6 @@
71#define EXYNOS4_PA_WATCHDOG 0x10060000 46#define EXYNOS4_PA_WATCHDOG 0x10060000
72#define EXYNOS5_PA_WATCHDOG 0x101D0000 47#define EXYNOS5_PA_WATCHDOG 0x101D0000
73 48
74#define EXYNOS4_PA_RTC 0x10070000
75
76#define EXYNOS4_PA_KEYPAD 0x100A0000
77
78#define EXYNOS4_PA_DMC0 0x10400000 49#define EXYNOS4_PA_DMC0 0x10400000
79#define EXYNOS4_PA_DMC1 0x10410000 50#define EXYNOS4_PA_DMC1 0x10410000
80 51
@@ -87,207 +58,22 @@
87#define EXYNOS5_PA_GIC_DIST 0x10481000 58#define EXYNOS5_PA_GIC_DIST 0x10481000
88 59
89#define EXYNOS4_PA_COREPERI 0x10500000 60#define EXYNOS4_PA_COREPERI 0x10500000
90#define EXYNOS4_PA_TWD 0x10500600
91#define EXYNOS4_PA_L2CC 0x10502000 61#define EXYNOS4_PA_L2CC 0x10502000
92 62
93#define EXYNOS4_PA_TMU 0x100C0000
94
95#define EXYNOS4_PA_MDMA0 0x10810000
96#define EXYNOS4_PA_MDMA1 0x12850000
97#define EXYNOS4_PA_S_MDMA1 0x12840000
98#define EXYNOS4_PA_PDMA0 0x12680000
99#define EXYNOS4_PA_PDMA1 0x12690000
100#define EXYNOS5_PA_MDMA0 0x10800000
101#define EXYNOS5_PA_MDMA1 0x11C10000
102#define EXYNOS5_PA_PDMA0 0x121A0000
103#define EXYNOS5_PA_PDMA1 0x121B0000
104
105#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
106#define EXYNOS4_PA_SYSMMU_2D_ACP 0x10A40000
107#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
108#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
109#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
110#define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000
111#define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000
112#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
113#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
114#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
115#define EXYNOS4_PA_SYSMMU_FIMC_ISP 0x12260000
116#define EXYNOS4_PA_SYSMMU_FIMC_DRC 0x12270000
117#define EXYNOS4_PA_SYSMMU_FIMC_FD 0x122A0000
118#define EXYNOS4_PA_SYSMMU_ISPCPU 0x122B0000
119#define EXYNOS4_PA_SYSMMU_FIMC_LITE0 0x123B0000
120#define EXYNOS4_PA_SYSMMU_FIMC_LITE1 0x123C0000
121#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
122#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
123#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
124#define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000
125#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
126#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
127#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
128
129#define EXYNOS5_PA_GSC0 0x13E00000
130#define EXYNOS5_PA_GSC1 0x13E10000
131#define EXYNOS5_PA_GSC2 0x13E20000
132#define EXYNOS5_PA_GSC3 0x13E30000
133
134#define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000
135#define EXYNOS5_PA_SYSMMU_SSS 0x10A50000
136#define EXYNOS5_PA_SYSMMU_2D 0x10A60000
137#define EXYNOS5_PA_SYSMMU_MFC_L 0x11200000
138#define EXYNOS5_PA_SYSMMU_MFC_R 0x11210000
139#define EXYNOS5_PA_SYSMMU_ROTATOR 0x11D40000
140#define EXYNOS5_PA_SYSMMU_MDMA2 0x11D50000
141#define EXYNOS5_PA_SYSMMU_JPEG 0x11F20000
142#define EXYNOS5_PA_SYSMMU_IOP 0x12360000
143#define EXYNOS5_PA_SYSMMU_RTIC 0x12370000
144#define EXYNOS5_PA_SYSMMU_ISP 0x13260000
145#define EXYNOS5_PA_SYSMMU_DRC 0x12370000
146#define EXYNOS5_PA_SYSMMU_SCALERC 0x13280000
147#define EXYNOS5_PA_SYSMMU_SCALERP 0x13290000
148#define EXYNOS5_PA_SYSMMU_FD 0x132A0000
149#define EXYNOS5_PA_SYSMMU_ISPCPU 0x132B0000
150#define EXYNOS5_PA_SYSMMU_ODC 0x132C0000
151#define EXYNOS5_PA_SYSMMU_DIS0 0x132D0000
152#define EXYNOS5_PA_SYSMMU_DIS1 0x132E0000
153#define EXYNOS5_PA_SYSMMU_3DNR 0x132F0000
154#define EXYNOS5_PA_SYSMMU_LITE0 0x13C40000
155#define EXYNOS5_PA_SYSMMU_LITE1 0x13C50000
156#define EXYNOS5_PA_SYSMMU_GSC0 0x13E80000
157#define EXYNOS5_PA_SYSMMU_GSC1 0x13E90000
158#define EXYNOS5_PA_SYSMMU_GSC2 0x13EA0000
159#define EXYNOS5_PA_SYSMMU_GSC3 0x13EB0000
160#define EXYNOS5_PA_SYSMMU_FIMD1 0x14640000
161#define EXYNOS5_PA_SYSMMU_TV 0x14650000
162
163#define EXYNOS4_PA_SPI0 0x13920000
164#define EXYNOS4_PA_SPI1 0x13930000
165#define EXYNOS4_PA_SPI2 0x13940000
166#define EXYNOS5_PA_SPI0 0x12D20000
167#define EXYNOS5_PA_SPI1 0x12D30000
168#define EXYNOS5_PA_SPI2 0x12D40000
169
170#define EXYNOS4_PA_GPIO1 0x11400000
171#define EXYNOS4_PA_GPIO2 0x11000000
172#define EXYNOS4_PA_GPIO3 0x03860000
173#define EXYNOS5_PA_GPIO1 0x11400000
174#define EXYNOS5_PA_GPIO2 0x13400000
175#define EXYNOS5_PA_GPIO3 0x10D10000
176#define EXYNOS5_PA_GPIO4 0x03860000
177
178#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
179#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
180
181#define EXYNOS4_PA_FIMD0 0x11C00000
182
183#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
184#define EXYNOS4_PA_DWMCI 0x12550000
185#define EXYNOS5_PA_DWMCI0 0x12200000
186#define EXYNOS5_PA_DWMCI1 0x12210000
187#define EXYNOS5_PA_DWMCI2 0x12220000
188#define EXYNOS5_PA_DWMCI3 0x12230000
189
190#define EXYNOS4_PA_HSOTG 0x12480000
191#define EXYNOS4_PA_USB_HSPHY 0x125B0000
192
193#define EXYNOS4_PA_SATA 0x12560000
194#define EXYNOS4_PA_SATAPHY 0x125D0000
195#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
196
197#define EXYNOS4_PA_SROMC 0x12570000 63#define EXYNOS4_PA_SROMC 0x12570000
198#define EXYNOS5_PA_SROMC 0x12250000 64#define EXYNOS5_PA_SROMC 0x12250000
199 65
200#define EXYNOS4_PA_EHCI 0x12580000
201#define EXYNOS4_PA_OHCI 0x12590000
202#define EXYNOS4_PA_HSPHY 0x125B0000 66#define EXYNOS4_PA_HSPHY 0x125B0000
203#define EXYNOS4_PA_MFC 0x13400000
204 67
205#define EXYNOS4_PA_UART 0x13800000 68#define EXYNOS4_PA_UART 0x13800000
206#define EXYNOS5_PA_UART 0x12C00000 69#define EXYNOS5_PA_UART 0x12C00000
207 70
208#define EXYNOS4_PA_VP 0x12C00000
209#define EXYNOS4_PA_MIXER 0x12C10000
210#define EXYNOS4_PA_SDO 0x12C20000
211#define EXYNOS4_PA_HDMI 0x12D00000
212#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
213
214#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
215#define EXYNOS5_PA_IIC(x) (0x12C60000 + ((x) * 0x10000))
216
217#define EXYNOS4_PA_ADC 0x13910000
218#define EXYNOS4_PA_ADC1 0x13911000
219
220#define EXYNOS4_PA_AC97 0x139A0000
221
222#define EXYNOS4_PA_SPDIF 0x139B0000
223
224#define EXYNOS4_PA_TIMER 0x139D0000 71#define EXYNOS4_PA_TIMER 0x139D0000
225#define EXYNOS5_PA_TIMER 0x12DD0000 72#define EXYNOS5_PA_TIMER 0x12DD0000
226 73
227#define EXYNOS4_PA_SDRAM 0x40000000
228#define EXYNOS5_PA_SDRAM 0x40000000
229
230/* Compatibiltiy Defines */
231
232#define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0)
233#define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1)
234#define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2)
235#define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3)
236#define S3C_PA_IIC EXYNOS4_PA_IIC(0)
237#define S3C_PA_IIC1 EXYNOS4_PA_IIC(1)
238#define S3C_PA_IIC2 EXYNOS4_PA_IIC(2)
239#define S3C_PA_IIC3 EXYNOS4_PA_IIC(3)
240#define S3C_PA_IIC4 EXYNOS4_PA_IIC(4)
241#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
242#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
243#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
244#define S3C_PA_RTC EXYNOS4_PA_RTC
245#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
246#define S3C_PA_SPI0 EXYNOS4_PA_SPI0
247#define S3C_PA_SPI1 EXYNOS4_PA_SPI1
248#define S3C_PA_SPI2 EXYNOS4_PA_SPI2
249#define S3C_PA_USB_HSOTG EXYNOS4_PA_HSOTG
250
251#define S5P_PA_EHCI EXYNOS4_PA_EHCI
252#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
253#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
254#define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2
255#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
256#define S5P_PA_JPEG EXYNOS4_PA_JPEG
257#define S5P_PA_G2D EXYNOS4_PA_G2D
258#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
259#define S5P_PA_HDMI EXYNOS4_PA_HDMI
260#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY
261#define S5P_PA_MFC EXYNOS4_PA_MFC
262#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
263#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
264#define S5P_PA_MIXER EXYNOS4_PA_MIXER
265#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
266#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
267#define S5P_PA_SDO EXYNOS4_PA_SDO
268#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
269#define S5P_PA_VP EXYNOS4_PA_VP
270
271#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
272#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
273#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
274
275/* Compatibility UART */ 74/* Compatibility UART */
276 75
277#define EXYNOS4_PA_UART0 0x13800000
278#define EXYNOS4_PA_UART1 0x13810000
279#define EXYNOS4_PA_UART2 0x13820000
280#define EXYNOS4_PA_UART3 0x13830000
281#define EXYNOS4_SZ_UART SZ_256
282
283#define EXYNOS5_PA_UART0 0x12C00000
284#define EXYNOS5_PA_UART1 0x12C10000
285#define EXYNOS5_PA_UART2 0x12C20000
286#define EXYNOS5_PA_UART3 0x12C30000
287
288#define EXYNOS5440_PA_UART0 0x000B0000 76#define EXYNOS5440_PA_UART0 0x000B0000
289#define EXYNOS5440_PA_UART1 0x000C0000
290#define EXYNOS5440_SZ_UART SZ_256
291 77
292#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 78#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
293 79
diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
index 296090e7f423..2b00833b6641 100644
--- a/arch/arm/mach-exynos/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos/include/mach/pm-core.h
@@ -34,12 +34,7 @@ static inline void s3c_pm_debug_init_uart(void)
34 34
35static inline void s3c_pm_arch_prepare_irqs(void) 35static inline void s3c_pm_arch_prepare_irqs(void)
36{ 36{
37 u32 eintmask = s3c_irqwake_eintmask; 37 __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
38
39 if (of_have_populated_dt())
40 eintmask = exynos_get_eint_wake_mask();
41
42 __raw_writel(eintmask, S5P_EINT_WAKEUP_MASK);
43 __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); 38 __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
44} 39}
45 40
@@ -69,4 +64,9 @@ static inline void samsung_pm_saved_gpios(void)
69 /* nothing here yet */ 64 /* nothing here yet */
70} 65}
71 66
67/* Compatibility definitions to make plat-samsung/pm.c compile */
68#define IRQ_EINT_BIT(x) 1
69#define s3c_irqwake_intallow 0
70#define s3c_irqwake_eintallow 0
71
72#endif /* __ASM_ARCH_PM_CORE_H */ 72#endif /* __ASM_ARCH_PM_CORE_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
deleted file mode 100644
index e4b5b60dcb85..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/* linux/arch/arm/mach-exynos4/include/mach/regs-gpio.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - GPIO (including EINT) register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15
16#include <mach/map.h>
17#include <mach/irqs.h>
18
19#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
20#define EINT_CON(b, x) (b + 0xE00 + (EINT_REG_NR(x) * 4))
21#define EINT_FLTCON(b, x) (b + 0xE80 + (EINT_REG_NR(x) * 4))
22#define EINT_MASK(b, x) (b + 0xF00 + (EINT_REG_NR(x) * 4))
23#define EINT_PEND(b, x) (b + 0xF40 + (EINT_REG_NR(x) * 4))
24
25#define EINT_OFFSET_BIT(x) (1 << (EINT_OFFSET(x) & 0x7))
26
27/* compatibility for plat-s5p/irq-pm.c */
28#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00)
29#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4))
30
31#define EXYNOS4_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80)
32#define S5P_EINT_FLTCON(x) (EXYNOS4_EINT40FLTCON0 + ((x) * 0x4))
33
34#define EXYNOS4_EINT40MASK (S5P_VA_GPIO2 + 0xF00)
35#define S5P_EINT_MASK(x) (EXYNOS4_EINT40MASK + ((x) * 0x4))
36
37#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
38#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4))
39
40#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
deleted file mode 100644
index 07277735252e..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
+++ /dev/null
@@ -1,74 +0,0 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#ifndef __PLAT_S5P_REGS_USB_PHY_H
12#define __PLAT_S5P_REGS_USB_PHY_H
13
14#define EXYNOS4_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY)
15
16#define EXYNOS4_PHYPWR EXYNOS4_HSOTG_PHYREG(0x00)
17#define PHY1_HSIC_NORMAL_MASK (0xf << 9)
18#define PHY1_HSIC1_SLEEP (1 << 12)
19#define PHY1_HSIC1_FORCE_SUSPEND (1 << 11)
20#define PHY1_HSIC0_SLEEP (1 << 10)
21#define PHY1_HSIC0_FORCE_SUSPEND (1 << 9)
22
23#define PHY1_STD_NORMAL_MASK (0x7 << 6)
24#define PHY1_STD_SLEEP (1 << 8)
25#define PHY1_STD_ANALOG_POWERDOWN (1 << 7)
26#define PHY1_STD_FORCE_SUSPEND (1 << 6)
27
28#define PHY0_NORMAL_MASK (0x39 << 0)
29#define PHY0_SLEEP (1 << 5)
30#define PHY0_OTG_DISABLE (1 << 4)
31#define PHY0_ANALOG_POWERDOWN (1 << 3)
32#define PHY0_FORCE_SUSPEND (1 << 0)
33
34#define EXYNOS4_PHYCLK EXYNOS4_HSOTG_PHYREG(0x04)
35#define PHY1_COMMON_ON_N (1 << 7)
36#define PHY0_COMMON_ON_N (1 << 4)
37#define PHY0_ID_PULLUP (1 << 2)
38
39#define EXYNOS4_CLKSEL_SHIFT (0)
40
41#define EXYNOS4210_CLKSEL_MASK (0x3 << 0)
42#define EXYNOS4210_CLKSEL_48M (0x0 << 0)
43#define EXYNOS4210_CLKSEL_12M (0x2 << 0)
44#define EXYNOS4210_CLKSEL_24M (0x3 << 0)
45
46#define EXYNOS4X12_CLKSEL_MASK (0x7 << 0)
47#define EXYNOS4X12_CLKSEL_9600K (0x0 << 0)
48#define EXYNOS4X12_CLKSEL_10M (0x1 << 0)
49#define EXYNOS4X12_CLKSEL_12M (0x2 << 0)
50#define EXYNOS4X12_CLKSEL_19200K (0x3 << 0)
51#define EXYNOS4X12_CLKSEL_20M (0x4 << 0)
52#define EXYNOS4X12_CLKSEL_24M (0x5 << 0)
53
54#define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08)
55#define HOST_LINK_PORT_SWRST_MASK (0xf << 6)
56#define HOST_LINK_PORT2_SWRST (1 << 9)
57#define HOST_LINK_PORT1_SWRST (1 << 8)
58#define HOST_LINK_PORT0_SWRST (1 << 7)
59#define HOST_LINK_ALL_SWRST (1 << 6)
60
61#define PHY1_SWRST_MASK (0x7 << 3)
62#define PHY1_HSIC_SWRST (1 << 5)
63#define PHY1_STD_SWRST (1 << 4)
64#define PHY1_ALL_SWRST (1 << 3)
65
66#define PHY0_SWRST_MASK (0x7 << 0)
67#define PHY0_PHYLINK_SWRST (1 << 2)
68#define PHY0_HLINK_SWRST (1 << 1)
69#define PHY0_SWRST (1 << 0)
70
71#define EXYNOS4_PHY1CON EXYNOS4_HSOTG_PHYREG(0x34)
72#define FPENABLEN (1 << 0)
73
74#endif /* __PLAT_S5P_REGS_USB_PHY_H */
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
deleted file mode 100644
index 5f0f55701374..000000000000
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ /dev/null
@@ -1,207 +0,0 @@
1/* linux/arch/arm/mach-exynos4/mach-armlex4210.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/gpio.h>
12#include <linux/io.h>
13#include <linux/mmc/host.h>
14#include <linux/platform_device.h>
15#include <linux/serial_core.h>
16#include <linux/smsc911x.h>
17
18#include <asm/mach/arch.h>
19#include <asm/mach-types.h>
20
21#include <plat/cpu.h>
22#include <plat/devs.h>
23#include <plat/gpio-cfg.h>
24#include <plat/regs-serial.h>
25#include <plat/regs-srom.h>
26#include <plat/sdhci.h>
27
28#include <mach/irqs.h>
29#include <mach/map.h>
30
31#include "common.h"
32
33/* Following are default values for UCON, ULCON and UFCON UART registers */
34#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
35 S3C2410_UCON_RXILEVEL | \
36 S3C2410_UCON_TXIRQMODE | \
37 S3C2410_UCON_RXIRQMODE | \
38 S3C2410_UCON_RXFIFO_TOI | \
39 S3C2443_UCON_RXERR_IRQEN)
40
41#define ARMLEX4210_ULCON_DEFAULT S3C2410_LCON_CS8
42
43#define ARMLEX4210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
44 S5PV210_UFCON_TXTRIG4 | \
45 S5PV210_UFCON_RXTRIG4)
46
47static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
48 [0] = {
49 .hwport = 0,
50 .flags = 0,
51 .ucon = ARMLEX4210_UCON_DEFAULT,
52 .ulcon = ARMLEX4210_ULCON_DEFAULT,
53 .ufcon = ARMLEX4210_UFCON_DEFAULT,
54 },
55 [1] = {
56 .hwport = 1,
57 .flags = 0,
58 .ucon = ARMLEX4210_UCON_DEFAULT,
59 .ulcon = ARMLEX4210_ULCON_DEFAULT,
60 .ufcon = ARMLEX4210_UFCON_DEFAULT,
61 },
62 [2] = {
63 .hwport = 2,
64 .flags = 0,
65 .ucon = ARMLEX4210_UCON_DEFAULT,
66 .ulcon = ARMLEX4210_ULCON_DEFAULT,
67 .ufcon = ARMLEX4210_UFCON_DEFAULT,
68 },
69 [3] = {
70 .hwport = 3,
71 .flags = 0,
72 .ucon = ARMLEX4210_UCON_DEFAULT,
73 .ulcon = ARMLEX4210_ULCON_DEFAULT,
74 .ufcon = ARMLEX4210_UFCON_DEFAULT,
75 },
76};
77
78static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
79 .cd_type = S3C_SDHCI_CD_PERMANENT,
80#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
81 .max_width = 8,
82 .host_caps = MMC_CAP_8_BIT_DATA,
83#endif
84};
85
86static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
87 .cd_type = S3C_SDHCI_CD_GPIO,
88 .ext_cd_gpio = EXYNOS4_GPX2(5),
89 .ext_cd_gpio_invert = 1,
90 .max_width = 4,
91};
92
93static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
94 .cd_type = S3C_SDHCI_CD_PERMANENT,
95 .max_width = 4,
96};
97
98static void __init armlex4210_sdhci_init(void)
99{
100 s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata);
101 s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata);
102 s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata);
103}
104
105static void __init armlex4210_wlan_init(void)
106{
107 /* enable */
108 s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf));
109 s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP);
110
111 /* reset */
112 s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf));
113 s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP);
114
115 /* wakeup */
116 s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf));
117 s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP);
118}
119
120static struct resource armlex4210_smsc911x_resources[] = {
121 [0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(3), SZ_64K),
122 [1] = DEFINE_RES_NAMED(IRQ_EINT(27), 1, NULL, IORESOURCE_IRQ \
123 | IRQF_TRIGGER_HIGH),
124};
125
126static struct smsc911x_platform_config smsc9215_config = {
127 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
128 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
129 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
130 .phy_interface = PHY_INTERFACE_MODE_MII,
131 .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
132};
133
134static struct platform_device armlex4210_smsc911x = {
135 .name = "smsc911x",
136 .id = -1,
137 .num_resources = ARRAY_SIZE(armlex4210_smsc911x_resources),
138 .resource = armlex4210_smsc911x_resources,
139 .dev = {
140 .platform_data = &smsc9215_config,
141 },
142};
143
144static struct platform_device *armlex4210_devices[] __initdata = {
145 &s3c_device_hsmmc0,
146 &s3c_device_hsmmc2,
147 &s3c_device_hsmmc3,
148 &s3c_device_rtc,
149 &s3c_device_wdt,
150 &armlex4210_smsc911x,
151 &exynos4_device_ahci,
152};
153
154static void __init armlex4210_smsc911x_init(void)
155{
156 u32 cs1;
157
158 /* configure nCS1 width to 16 bits */
159 cs1 = __raw_readl(S5P_SROM_BW) &
160 ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
161 cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
162 (0 << S5P_SROM_BW__WAITENABLE__SHIFT) |
163 (1 << S5P_SROM_BW__ADDRMODE__SHIFT) |
164 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
165 S5P_SROM_BW__NCS1__SHIFT;
166 __raw_writel(cs1, S5P_SROM_BW);
167
168 /* set timing for nCS1 suitable for ethernet chip */
169 __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
170 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
171 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
172 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
173 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
174 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
175 (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
176}
177
178static void __init armlex4210_map_io(void)
179{
180 exynos_init_io(NULL, 0);
181 s3c24xx_init_uarts(armlex4210_uartcfgs,
182 ARRAY_SIZE(armlex4210_uartcfgs));
183}
184
185static void __init armlex4210_machine_init(void)
186{
187 armlex4210_smsc911x_init();
188
189 armlex4210_sdhci_init();
190
191 armlex4210_wlan_init();
192
193 platform_add_devices(armlex4210_devices,
194 ARRAY_SIZE(armlex4210_devices));
195}
196
197MACHINE_START(ARMLEX4210, "ARMLEX4210")
198 /* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
199 .atag_offset = 0x100,
200 .smp = smp_ops(exynos_smp_ops),
201 .init_irq = exynos4_init_irq,
202 .map_io = armlex4210_map_io,
203 .init_machine = armlex4210_machine_init,
204 .init_late = exynos_init_late,
205 .init_time = exynos_init_time,
206 .restart = exynos4_restart,
207MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index b9ed834a7eee..0099c6c13bba 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -23,11 +23,6 @@
23 23
24#include "common.h" 24#include "common.h"
25 25
26static void __init exynos4_dt_map_io(void)
27{
28 exynos_init_io(NULL, 0);
29}
30
31static void __init exynos4_dt_machine_init(void) 26static void __init exynos4_dt_machine_init(void)
32{ 27{
33 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 28 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
@@ -55,8 +50,7 @@ static void __init exynos4_reserve(void)
55DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") 50DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
56 /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */ 51 /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
57 .smp = smp_ops(exynos_smp_ops), 52 .smp = smp_ops(exynos_smp_ops),
58 .init_irq = exynos4_init_irq, 53 .map_io = exynos_init_io,
59 .map_io = exynos4_dt_map_io,
60 .init_early = exynos_firmware_init, 54 .init_early = exynos_firmware_init,
61 .init_machine = exynos4_dt_machine_init, 55 .init_machine = exynos4_dt_machine_init,
62 .init_late = exynos_init_late, 56 .init_late = exynos_init_late,
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 753b94f3fca7..d5c8afdeaa39 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -23,11 +23,6 @@
23 23
24#include "common.h" 24#include "common.h"
25 25
26static void __init exynos5_dt_map_io(void)
27{
28 exynos_init_io(NULL, 0);
29}
30
31static void __init exynos5_dt_machine_init(void) 26static void __init exynos5_dt_machine_init(void)
32{ 27{
33 struct device_node *i2c_np; 28 struct device_node *i2c_np;
@@ -76,9 +71,8 @@ static void __init exynos5_reserve(void)
76 71
77DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)") 72DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
78 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 73 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
79 .init_irq = exynos5_init_irq,
80 .smp = smp_ops(exynos_smp_ops), 74 .smp = smp_ops(exynos_smp_ops),
81 .map_io = exynos5_dt_map_io, 75 .map_io = exynos_init_io,
82 .init_machine = exynos5_dt_machine_init, 76 .init_machine = exynos5_dt_machine_init,
83 .init_late = exynos_init_late, 77 .init_late = exynos_init_late,
84 .init_time = exynos_init_time, 78 .init_time = exynos_init_time,
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
deleted file mode 100644
index 5c8b2878dbbd..000000000000
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ /dev/null
@@ -1,1388 +0,0 @@
1/*
2 * linux/arch/arm/mach-exynos4/mach-nuri.c
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/serial_core.h>
13#include <linux/input.h>
14#include <linux/i2c.h>
15#include <linux/i2c/atmel_mxt_ts.h>
16#include <linux/i2c-gpio.h>
17#include <linux/gpio_keys.h>
18#include <linux/gpio.h>
19#include <linux/power/max8903_charger.h>
20#include <linux/power/max17042_battery.h>
21#include <linux/regulator/machine.h>
22#include <linux/regulator/fixed.h>
23#include <linux/mfd/max8997.h>
24#include <linux/mfd/max8997-private.h>
25#include <linux/mmc/host.h>
26#include <linux/fb.h>
27#include <linux/pwm_backlight.h>
28#include <linux/platform_data/i2c-s3c2410.h>
29#include <linux/platform_data/mipi-csis.h>
30#include <linux/platform_data/s3c-hsotg.h>
31#include <linux/platform_data/usb-ehci-s5p.h>
32#include <drm/exynos_drm.h>
33
34#include <video/platform_lcd.h>
35#include <video/samsung_fimd.h>
36#include <media/m5mols.h>
37#include <media/s5k6aa.h>
38#include <media/s5p_fimc.h>
39#include <media/v4l2-mediabus.h>
40
41#include <asm/mach/arch.h>
42#include <asm/mach-types.h>
43
44#include <plat/adc.h>
45#include <plat/regs-serial.h>
46#include <plat/cpu.h>
47#include <plat/devs.h>
48#include <plat/fb.h>
49#include <plat/sdhci.h>
50#include <plat/clock.h>
51#include <plat/gpio-cfg.h>
52#include <plat/mfc.h>
53#include <plat/fimc-core.h>
54#include <plat/camport.h>
55
56#include <mach/irqs.h>
57#include <mach/map.h>
58
59#include "common.h"
60
61/* Following are default values for UCON, ULCON and UFCON UART registers */
62#define NURI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
63 S3C2410_UCON_RXILEVEL | \
64 S3C2410_UCON_TXIRQMODE | \
65 S3C2410_UCON_RXIRQMODE | \
66 S3C2410_UCON_RXFIFO_TOI | \
67 S3C2443_UCON_RXERR_IRQEN)
68
69#define NURI_ULCON_DEFAULT S3C2410_LCON_CS8
70
71#define NURI_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
72 S5PV210_UFCON_TXTRIG256 | \
73 S5PV210_UFCON_RXTRIG256)
74
75enum fixed_regulator_id {
76 FIXED_REG_ID_MMC = 0,
77 FIXED_REG_ID_MAX8903,
78 FIXED_REG_ID_CAM_A28V,
79 FIXED_REG_ID_CAM_12V,
80 FIXED_REG_ID_CAM_VT_15V,
81};
82
83static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
84 {
85 .hwport = 0,
86 .ucon = NURI_UCON_DEFAULT,
87 .ulcon = NURI_ULCON_DEFAULT,
88 .ufcon = NURI_UFCON_DEFAULT,
89 },
90 {
91 .hwport = 1,
92 .ucon = NURI_UCON_DEFAULT,
93 .ulcon = NURI_ULCON_DEFAULT,
94 .ufcon = NURI_UFCON_DEFAULT,
95 },
96 {
97 .hwport = 2,
98 .ucon = NURI_UCON_DEFAULT,
99 .ulcon = NURI_ULCON_DEFAULT,
100 .ufcon = NURI_UFCON_DEFAULT,
101 },
102 {
103 .hwport = 3,
104 .ucon = NURI_UCON_DEFAULT,
105 .ulcon = NURI_ULCON_DEFAULT,
106 .ufcon = NURI_UFCON_DEFAULT,
107 },
108};
109
110/* eMMC */
111static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
112 .max_width = 8,
113 .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
114 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
115 MMC_CAP_ERASE),
116 .cd_type = S3C_SDHCI_CD_PERMANENT,
117};
118
119static struct regulator_consumer_supply emmc_supplies[] = {
120 REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
121 REGULATOR_SUPPLY("vmmc", "dw_mmc"),
122};
123
124static struct regulator_init_data emmc_fixed_voltage_init_data = {
125 .constraints = {
126 .name = "VMEM_VDD_2.8V",
127 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
128 },
129 .num_consumer_supplies = ARRAY_SIZE(emmc_supplies),
130 .consumer_supplies = emmc_supplies,
131};
132
133static struct fixed_voltage_config emmc_fixed_voltage_config = {
134 .supply_name = "MASSMEMORY_EN (inverted)",
135 .microvolts = 2800000,
136 .gpio = EXYNOS4_GPL1(1),
137 .enable_high = false,
138 .init_data = &emmc_fixed_voltage_init_data,
139};
140
141static struct platform_device emmc_fixed_voltage = {
142 .name = "reg-fixed-voltage",
143 .id = FIXED_REG_ID_MMC,
144 .dev = {
145 .platform_data = &emmc_fixed_voltage_config,
146 },
147};
148
149/* SD */
150static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = {
151 .max_width = 4,
152 .host_caps = MMC_CAP_4_BIT_DATA |
153 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
154 .ext_cd_gpio = EXYNOS4_GPX3(3), /* XEINT_27 */
155 .ext_cd_gpio_invert = 1,
156 .cd_type = S3C_SDHCI_CD_GPIO,
157};
158
159/* WLAN */
160static struct s3c_sdhci_platdata nuri_hsmmc3_data __initdata = {
161 .max_width = 4,
162 .host_caps = MMC_CAP_4_BIT_DATA |
163 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
164 .cd_type = S3C_SDHCI_CD_EXTERNAL,
165};
166
167static void __init nuri_sdhci_init(void)
168{
169 s3c_sdhci0_set_platdata(&nuri_hsmmc0_data);
170 s3c_sdhci2_set_platdata(&nuri_hsmmc2_data);
171 s3c_sdhci3_set_platdata(&nuri_hsmmc3_data);
172}
173
174/* GPIO KEYS */
175static struct gpio_keys_button nuri_gpio_keys_tables[] = {
176 {
177 .code = KEY_VOLUMEUP,
178 .gpio = EXYNOS4_GPX2(0), /* XEINT16 */
179 .desc = "gpio-keys: KEY_VOLUMEUP",
180 .type = EV_KEY,
181 .active_low = 1,
182 .debounce_interval = 1,
183 }, {
184 .code = KEY_VOLUMEDOWN,
185 .gpio = EXYNOS4_GPX2(1), /* XEINT17 */
186 .desc = "gpio-keys: KEY_VOLUMEDOWN",
187 .type = EV_KEY,
188 .active_low = 1,
189 .debounce_interval = 1,
190 }, {
191 .code = KEY_POWER,
192 .gpio = EXYNOS4_GPX2(7), /* XEINT23 */
193 .desc = "gpio-keys: KEY_POWER",
194 .type = EV_KEY,
195 .active_low = 1,
196 .wakeup = 1,
197 .debounce_interval = 1,
198 },
199};
200
201static struct gpio_keys_platform_data nuri_gpio_keys_data = {
202 .buttons = nuri_gpio_keys_tables,
203 .nbuttons = ARRAY_SIZE(nuri_gpio_keys_tables),
204};
205
206static struct platform_device nuri_gpio_keys = {
207 .name = "gpio-keys",
208 .dev = {
209 .platform_data = &nuri_gpio_keys_data,
210 },
211};
212
213#ifdef CONFIG_DRM_EXYNOS
214static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
215 .panel = {
216 .timing = {
217 .xres = 1024,
218 .yres = 600,
219 .hsync_len = 40,
220 .left_margin = 79,
221 .right_margin = 200,
222 .vsync_len = 10,
223 .upper_margin = 10,
224 .lower_margin = 11,
225 .refresh = 60,
226 },
227 },
228 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
229 VIDCON0_CLKSEL_LCD,
230 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
231 .default_win = 3,
232 .bpp = 32,
233};
234
235#else
236/* Frame Buffer */
237static struct s3c_fb_pd_win nuri_fb_win0 = {
238 .max_bpp = 24,
239 .default_bpp = 16,
240 .xres = 1024,
241 .yres = 600,
242 .virtual_x = 1024,
243 .virtual_y = 2 * 600,
244};
245
246static struct fb_videomode nuri_lcd_timing = {
247 .left_margin = 64,
248 .right_margin = 16,
249 .upper_margin = 64,
250 .lower_margin = 1,
251 .hsync_len = 48,
252 .vsync_len = 3,
253 .xres = 1024,
254 .yres = 600,
255 .refresh = 60,
256};
257
258static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
259 .win[0] = &nuri_fb_win0,
260 .vtiming = &nuri_lcd_timing,
261 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
262 VIDCON0_CLKSEL_LCD,
263 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
264 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
265};
266#endif
267
268static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
269{
270 int gpio = EXYNOS4_GPE1(5);
271
272 gpio_request(gpio, "LVDS_nSHDN");
273 gpio_direction_output(gpio, power);
274 gpio_free(gpio);
275}
276
277static int nuri_bl_init(struct device *dev)
278{
279 return gpio_request_one(EXYNOS4_GPE2(3), GPIOF_OUT_INIT_LOW,
280 "LCD_LD0_EN");
281}
282
283static int nuri_bl_notify(struct device *dev, int brightness)
284{
285 if (brightness < 1)
286 brightness = 0;
287
288 gpio_set_value(EXYNOS4_GPE2(3), 1);
289
290 return brightness;
291}
292
293static void nuri_bl_exit(struct device *dev)
294{
295 gpio_free(EXYNOS4_GPE2(3));
296}
297
298/* nuri pwm backlight */
299static struct platform_pwm_backlight_data nuri_backlight_data = {
300 .pwm_id = 0,
301 .pwm_period_ns = 30000,
302 .max_brightness = 100,
303 .dft_brightness = 50,
304 .init = nuri_bl_init,
305 .notify = nuri_bl_notify,
306 .exit = nuri_bl_exit,
307};
308
309static struct platform_device nuri_backlight_device = {
310 .name = "pwm-backlight",
311 .id = -1,
312 .dev = {
313 .parent = &s3c_device_timer[0].dev,
314 .platform_data = &nuri_backlight_data,
315 },
316};
317
318static struct plat_lcd_data nuri_lcd_platform_data = {
319 .set_power = nuri_lcd_power_on,
320};
321
322static struct platform_device nuri_lcd_device = {
323 .name = "platform-lcd",
324 .id = -1,
325 .dev = {
326 .platform_data = &nuri_lcd_platform_data,
327 },
328};
329
330/* I2C1 */
331static struct i2c_board_info i2c1_devs[] __initdata = {
332 /* Gyro, To be updated */
333};
334
335/* TSP */
336static struct mxt_platform_data mxt_platform_data = {
337 .x_line = 18,
338 .y_line = 11,
339 .x_size = 1024,
340 .y_size = 600,
341 .blen = 0x1,
342 .threshold = 0x28,
343 .voltage = 2800000, /* 2.8V */
344 .orient = MXT_DIAGONAL_COUNTER,
345 .irqflags = IRQF_TRIGGER_FALLING,
346};
347
348static struct s3c2410_platform_i2c i2c3_data __initdata = {
349 .flags = 0,
350 .bus_num = 3,
351 .slave_addr = 0x10,
352 .frequency = 400 * 1000,
353 .sda_delay = 100,
354};
355
356static struct i2c_board_info i2c3_devs[] __initdata = {
357 {
358 I2C_BOARD_INFO("atmel_mxt_ts", 0x4a),
359 .platform_data = &mxt_platform_data,
360 .irq = IRQ_EINT(4),
361 },
362};
363
364static void __init nuri_tsp_init(void)
365{
366 int gpio;
367
368 /* TOUCH_INT: XEINT_4 */
369 gpio = EXYNOS4_GPX0(4);
370 gpio_request(gpio, "TOUCH_INT");
371 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
372 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
373}
374
375static struct regulator_consumer_supply __initdata max8997_ldo1_[] = {
376 REGULATOR_SUPPLY("vdd", "s5p-adc"), /* Used by CPU's ADC drv */
377};
378static struct regulator_consumer_supply __initdata max8997_ldo3_[] = {
379 REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* USB */
380 REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /* MIPI */
381};
382static struct regulator_consumer_supply __initdata max8997_ldo4_[] = {
383 REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */
384};
385static struct regulator_consumer_supply __initdata max8997_ldo5_[] = {
386 REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */
387};
388static struct regulator_consumer_supply nuri_max8997_ldo6_consumer[] = {
389 REGULATOR_SUPPLY("vdd_reg", "6-003c"), /* S5K6AA camera */
390};
391static struct regulator_consumer_supply __initdata max8997_ldo7_[] = {
392 REGULATOR_SUPPLY("dig_18", "0-001f"), /* HCD803 */
393};
394static struct regulator_consumer_supply __initdata max8997_ldo8_[] = {
395 REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), /* USB */
396 REGULATOR_SUPPLY("vdac", NULL), /* Used by CPU */
397};
398static struct regulator_consumer_supply __initdata max8997_ldo11_[] = {
399 REGULATOR_SUPPLY("vcc", "platform-lcd"), /* U804 LVDS */
400};
401static struct regulator_consumer_supply __initdata max8997_ldo12_[] = {
402 REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */
403};
404static struct regulator_consumer_supply __initdata max8997_ldo13_[] = {
405 REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.2"), /* TFLASH */
406};
407static struct regulator_consumer_supply __initdata max8997_ldo14_[] = {
408 REGULATOR_SUPPLY("inmotor", "max8997-haptic"),
409};
410static struct regulator_consumer_supply __initdata max8997_ldo15_[] = {
411 REGULATOR_SUPPLY("avdd", "3-004a"), /* Touch Screen */
412};
413static struct regulator_consumer_supply __initdata max8997_ldo16_[] = {
414 REGULATOR_SUPPLY("d_sensor", "0-001f"), /* HDC803 */
415};
416static struct regulator_consumer_supply __initdata max8997_ldo18_[] = {
417 REGULATOR_SUPPLY("vdd", "3-004a"), /* Touch Screen */
418};
419static struct regulator_consumer_supply __initdata max8997_buck1_[] = {
420 REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
421};
422static struct regulator_consumer_supply __initdata max8997_buck2_[] = {
423 REGULATOR_SUPPLY("vdd_int", "exynos4210-busfreq.0"), /* CPUFREQ */
424};
425static struct regulator_consumer_supply __initdata max8997_buck3_[] = {
426 REGULATOR_SUPPLY("vdd", "mali_dev.0"), /* G3D of Exynos 4 */
427};
428static struct regulator_consumer_supply __initdata max8997_buck4_[] = {
429 REGULATOR_SUPPLY("core", "0-001f"), /* HDC803 */
430};
431static struct regulator_consumer_supply __initdata max8997_buck6_[] = {
432 REGULATOR_SUPPLY("dig_28", "0-001f"), /* pin "7" of HDC803 */
433};
434static struct regulator_consumer_supply __initdata max8997_esafeout1_[] = {
435 REGULATOR_SUPPLY("usb_vbus", NULL), /* CPU's USB OTG */
436};
437static struct regulator_consumer_supply __initdata max8997_esafeout2_[] = {
438 REGULATOR_SUPPLY("usb_vbus", "modemctl"), /* VBUS of Modem */
439};
440
441static struct regulator_consumer_supply __initdata max8997_charger_[] = {
442 REGULATOR_SUPPLY("vinchg1", "charger-manager.0"),
443};
444static struct regulator_consumer_supply __initdata max8997_chg_toff_[] = {
445 REGULATOR_SUPPLY("vinchg_stop", NULL), /* for jack interrupt handlers */
446};
447
448static struct regulator_consumer_supply __initdata max8997_32khz_ap_[] = {
449 REGULATOR_SUPPLY("gps_clk", "bcm4751"),
450 REGULATOR_SUPPLY("bt_clk", "bcm4330-b1"),
451 REGULATOR_SUPPLY("wifi_clk", "bcm433-b1"),
452};
453
454static struct regulator_init_data __initdata max8997_ldo1_data = {
455 .constraints = {
456 .name = "VADC_3.3V_C210",
457 .min_uV = 3300000,
458 .max_uV = 3300000,
459 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
460 .apply_uV = 1,
461 .state_mem = {
462 .disabled = 1,
463 },
464 },
465 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo1_),
466 .consumer_supplies = max8997_ldo1_,
467};
468
469static struct regulator_init_data __initdata max8997_ldo2_data = {
470 .constraints = {
471 .name = "VALIVE_1.1V_C210",
472 .min_uV = 1100000,
473 .max_uV = 1100000,
474 .apply_uV = 1,
475 .always_on = 1,
476 .state_mem = {
477 .enabled = 1,
478 },
479 },
480};
481
482static struct regulator_init_data __initdata max8997_ldo3_data = {
483 .constraints = {
484 .name = "VUSB_1.1V_C210",
485 .min_uV = 1100000,
486 .max_uV = 1100000,
487 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
488 .apply_uV = 1,
489 .state_mem = {
490 .disabled = 1,
491 },
492 },
493 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo3_),
494 .consumer_supplies = max8997_ldo3_,
495};
496
497static struct regulator_init_data __initdata max8997_ldo4_data = {
498 .constraints = {
499 .name = "VMIPI_1.8V",
500 .min_uV = 1800000,
501 .max_uV = 1800000,
502 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
503 .apply_uV = 1,
504 .state_mem = {
505 .disabled = 1,
506 },
507 },
508 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo4_),
509 .consumer_supplies = max8997_ldo4_,
510};
511
512static struct regulator_init_data __initdata max8997_ldo5_data = {
513 .constraints = {
514 .name = "VHSIC_1.2V_C210",
515 .min_uV = 1200000,
516 .max_uV = 1200000,
517 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
518 .apply_uV = 1,
519 .state_mem = {
520 .disabled = 1,
521 },
522 },
523 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo5_),
524 .consumer_supplies = max8997_ldo5_,
525};
526
527static struct regulator_init_data __initdata max8997_ldo6_data = {
528 .constraints = {
529 .name = "VCC_1.8V_PDA",
530 .min_uV = 1800000,
531 .max_uV = 1800000,
532 .apply_uV = 1,
533 .always_on = 1,
534 .state_mem = {
535 .enabled = 1,
536 },
537 },
538 .num_consumer_supplies = ARRAY_SIZE(nuri_max8997_ldo6_consumer),
539 .consumer_supplies = nuri_max8997_ldo6_consumer,
540};
541
542static struct regulator_init_data __initdata max8997_ldo7_data = {
543 .constraints = {
544 .name = "CAM_ISP_1.8V",
545 .min_uV = 1800000,
546 .max_uV = 1800000,
547 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
548 .apply_uV = 1,
549 .state_mem = {
550 .disabled = 1,
551 },
552 },
553 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo7_),
554 .consumer_supplies = max8997_ldo7_,
555};
556
557static struct regulator_init_data __initdata max8997_ldo8_data = {
558 .constraints = {
559 .name = "VUSB+VDAC_3.3V_C210",
560 .min_uV = 3300000,
561 .max_uV = 3300000,
562 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
563 .apply_uV = 1,
564 .state_mem = {
565 .disabled = 1,
566 },
567 },
568 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo8_),
569 .consumer_supplies = max8997_ldo8_,
570};
571
572static struct regulator_init_data __initdata max8997_ldo9_data = {
573 .constraints = {
574 .name = "VCC_2.8V_PDA",
575 .min_uV = 2800000,
576 .max_uV = 2800000,
577 .apply_uV = 1,
578 .always_on = 1,
579 .state_mem = {
580 .enabled = 1,
581 },
582 },
583};
584
585static struct regulator_init_data __initdata max8997_ldo10_data = {
586 .constraints = {
587 .name = "VPLL_1.1V_C210",
588 .min_uV = 1100000,
589 .max_uV = 1100000,
590 .apply_uV = 1,
591 .always_on = 1,
592 .state_mem = {
593 .disabled = 1,
594 },
595 },
596};
597
598static struct regulator_init_data __initdata max8997_ldo11_data = {
599 .constraints = {
600 .name = "LVDS_VDD3.3V",
601 .min_uV = 3300000,
602 .max_uV = 3300000,
603 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
604 .apply_uV = 1,
605 .boot_on = 1,
606 .state_mem = {
607 .disabled = 1,
608 },
609 },
610 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo11_),
611 .consumer_supplies = max8997_ldo11_,
612};
613
614static struct regulator_init_data __initdata max8997_ldo12_data = {
615 .constraints = {
616 .name = "VT_CAM_1.8V",
617 .min_uV = 1800000,
618 .max_uV = 1800000,
619 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
620 .apply_uV = 1,
621 .state_mem = {
622 .disabled = 1,
623 },
624 },
625 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo12_),
626 .consumer_supplies = max8997_ldo12_,
627};
628
629static struct regulator_init_data __initdata max8997_ldo13_data = {
630 .constraints = {
631 .name = "VTF_2.8V",
632 .min_uV = 2800000,
633 .max_uV = 2800000,
634 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
635 .apply_uV = 1,
636 .state_mem = {
637 .disabled = 1,
638 },
639 },
640 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo13_),
641 .consumer_supplies = max8997_ldo13_,
642};
643
644static struct regulator_init_data __initdata max8997_ldo14_data = {
645 .constraints = {
646 .name = "VCC_3.0V_MOTOR",
647 .min_uV = 3000000,
648 .max_uV = 3000000,
649 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
650 .apply_uV = 1,
651 .state_mem = {
652 .disabled = 1,
653 },
654 },
655 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo14_),
656 .consumer_supplies = max8997_ldo14_,
657};
658
659static struct regulator_init_data __initdata max8997_ldo15_data = {
660 .constraints = {
661 .name = "VTOUCH_ADVV2.8V",
662 .min_uV = 2800000,
663 .max_uV = 2800000,
664 .apply_uV = 1,
665 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
666 .state_mem = {
667 .disabled = 1,
668 },
669 },
670 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo15_),
671 .consumer_supplies = max8997_ldo15_,
672};
673
674static struct regulator_init_data __initdata max8997_ldo16_data = {
675 .constraints = {
676 .name = "CAM_SENSOR_IO_1.8V",
677 .min_uV = 1800000,
678 .max_uV = 1800000,
679 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
680 .apply_uV = 1,
681 .state_mem = {
682 .disabled = 1,
683 },
684 },
685 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo16_),
686 .consumer_supplies = max8997_ldo16_,
687};
688
689static struct regulator_init_data __initdata max8997_ldo18_data = {
690 .constraints = {
691 .name = "VTOUCH_VDD2.8V",
692 .min_uV = 2800000,
693 .max_uV = 2800000,
694 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
695 .apply_uV = 1,
696 .state_mem = {
697 .disabled = 1,
698 },
699 },
700 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo18_),
701 .consumer_supplies = max8997_ldo18_,
702};
703
704static struct regulator_init_data __initdata max8997_ldo21_data = {
705 .constraints = {
706 .name = "VDDQ_M1M2_1.2V",
707 .min_uV = 1200000,
708 .max_uV = 1200000,
709 .apply_uV = 1,
710 .always_on = 1,
711 .state_mem = {
712 .disabled = 1,
713 },
714 },
715};
716
717static struct regulator_init_data __initdata max8997_buck1_data = {
718 .constraints = {
719 .name = "VARM_1.2V_C210",
720 .min_uV = 900000,
721 .max_uV = 1350000,
722 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
723 .always_on = 1,
724 .state_mem = {
725 .disabled = 1,
726 },
727 },
728 .num_consumer_supplies = ARRAY_SIZE(max8997_buck1_),
729 .consumer_supplies = max8997_buck1_,
730};
731
732static struct regulator_init_data __initdata max8997_buck2_data = {
733 .constraints = {
734 .name = "VINT_1.1V_C210",
735 .min_uV = 900000,
736 .max_uV = 1200000,
737 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
738 .always_on = 1,
739 .state_mem = {
740 .disabled = 1,
741 },
742 },
743 .num_consumer_supplies = ARRAY_SIZE(max8997_buck2_),
744 .consumer_supplies = max8997_buck2_,
745};
746
747static struct regulator_init_data __initdata max8997_buck3_data = {
748 .constraints = {
749 .name = "VG3D_1.1V_C210",
750 .min_uV = 900000,
751 .max_uV = 1100000,
752 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
753 REGULATOR_CHANGE_STATUS,
754 .state_mem = {
755 .disabled = 1,
756 },
757 },
758 .num_consumer_supplies = ARRAY_SIZE(max8997_buck3_),
759 .consumer_supplies = max8997_buck3_,
760};
761
762static struct regulator_init_data __initdata max8997_buck4_data = {
763 .constraints = {
764 .name = "CAM_ISP_CORE_1.2V",
765 .min_uV = 1200000,
766 .max_uV = 1200000,
767 .apply_uV = 1,
768 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
769 .state_mem = {
770 .disabled = 1,
771 },
772 },
773 .num_consumer_supplies = ARRAY_SIZE(max8997_buck4_),
774 .consumer_supplies = max8997_buck4_,
775};
776
777static struct regulator_init_data __initdata max8997_buck5_data = {
778 .constraints = {
779 .name = "VMEM_1.2V_C210",
780 .min_uV = 1200000,
781 .max_uV = 1200000,
782 .apply_uV = 1,
783 .always_on = 1,
784 .state_mem = {
785 .enabled = 1,
786 },
787 },
788};
789
790static struct regulator_init_data __initdata max8997_buck6_data = {
791 .constraints = {
792 .name = "CAM_AF_2.8V",
793 .min_uV = 2800000,
794 .max_uV = 2800000,
795 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
796 .state_mem = {
797 .disabled = 1,
798 },
799 },
800 .num_consumer_supplies = ARRAY_SIZE(max8997_buck6_),
801 .consumer_supplies = max8997_buck6_,
802};
803
804static struct regulator_init_data __initdata max8997_buck7_data = {
805 .constraints = {
806 .name = "VCC_SUB_2.0V",
807 .min_uV = 2000000,
808 .max_uV = 2000000,
809 .apply_uV = 1,
810 .always_on = 1,
811 .state_mem = {
812 .enabled = 1,
813 },
814 },
815};
816
817static struct regulator_init_data __initdata max8997_32khz_ap_data = {
818 .constraints = {
819 .name = "32KHz AP",
820 .always_on = 1,
821 .state_mem = {
822 .enabled = 1,
823 },
824 },
825 .num_consumer_supplies = ARRAY_SIZE(max8997_32khz_ap_),
826 .consumer_supplies = max8997_32khz_ap_,
827};
828
829static struct regulator_init_data __initdata max8997_32khz_cp_data = {
830 .constraints = {
831 .name = "32KHz CP",
832 .state_mem = {
833 .disabled = 1,
834 },
835 },
836};
837
838static struct regulator_init_data __initdata max8997_vichg_data = {
839 .constraints = {
840 .name = "VICHG",
841 .state_mem = {
842 .disabled = 1,
843 },
844 },
845};
846
847static struct regulator_init_data __initdata max8997_esafeout1_data = {
848 .constraints = {
849 .name = "SAFEOUT1",
850 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
851 .always_on = 1,
852 .state_mem = {
853 .disabled = 1,
854 },
855 },
856 .num_consumer_supplies = ARRAY_SIZE(max8997_esafeout1_),
857 .consumer_supplies = max8997_esafeout1_,
858};
859
860static struct regulator_init_data __initdata max8997_esafeout2_data = {
861 .constraints = {
862 .name = "SAFEOUT2",
863 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
864 .state_mem = {
865 .disabled = 1,
866 },
867 },
868 .num_consumer_supplies = ARRAY_SIZE(max8997_esafeout2_),
869 .consumer_supplies = max8997_esafeout2_,
870};
871
872static struct regulator_init_data __initdata max8997_charger_cv_data = {
873 .constraints = {
874 .name = "CHARGER_CV",
875 .min_uV = 4200000,
876 .max_uV = 4200000,
877 .apply_uV = 1,
878 },
879};
880
881static struct regulator_init_data __initdata max8997_charger_data = {
882 .constraints = {
883 .name = "CHARGER",
884 .min_uA = 200000,
885 .max_uA = 950000,
886 .boot_on = 1,
887 .valid_ops_mask = REGULATOR_CHANGE_STATUS |
888 REGULATOR_CHANGE_CURRENT,
889 },
890 .num_consumer_supplies = ARRAY_SIZE(max8997_charger_),
891 .consumer_supplies = max8997_charger_,
892};
893
894static struct regulator_init_data __initdata max8997_charger_topoff_data = {
895 .constraints = {
896 .name = "CHARGER TOPOFF",
897 .min_uA = 50000,
898 .max_uA = 200000,
899 .valid_ops_mask = REGULATOR_CHANGE_CURRENT,
900 },
901 .num_consumer_supplies = ARRAY_SIZE(max8997_chg_toff_),
902 .consumer_supplies = max8997_chg_toff_,
903};
904
905static struct max8997_regulator_data __initdata nuri_max8997_regulators[] = {
906 { MAX8997_LDO1, &max8997_ldo1_data },
907 { MAX8997_LDO2, &max8997_ldo2_data },
908 { MAX8997_LDO3, &max8997_ldo3_data },
909 { MAX8997_LDO4, &max8997_ldo4_data },
910 { MAX8997_LDO5, &max8997_ldo5_data },
911 { MAX8997_LDO6, &max8997_ldo6_data },
912 { MAX8997_LDO7, &max8997_ldo7_data },
913 { MAX8997_LDO8, &max8997_ldo8_data },
914 { MAX8997_LDO9, &max8997_ldo9_data },
915 { MAX8997_LDO10, &max8997_ldo10_data },
916 { MAX8997_LDO11, &max8997_ldo11_data },
917 { MAX8997_LDO12, &max8997_ldo12_data },
918 { MAX8997_LDO13, &max8997_ldo13_data },
919 { MAX8997_LDO14, &max8997_ldo14_data },
920 { MAX8997_LDO15, &max8997_ldo15_data },
921 { MAX8997_LDO16, &max8997_ldo16_data },
922
923 { MAX8997_LDO18, &max8997_ldo18_data },
924 { MAX8997_LDO21, &max8997_ldo21_data },
925
926 { MAX8997_BUCK1, &max8997_buck1_data },
927 { MAX8997_BUCK2, &max8997_buck2_data },
928 { MAX8997_BUCK3, &max8997_buck3_data },
929 { MAX8997_BUCK4, &max8997_buck4_data },
930 { MAX8997_BUCK5, &max8997_buck5_data },
931 { MAX8997_BUCK6, &max8997_buck6_data },
932 { MAX8997_BUCK7, &max8997_buck7_data },
933
934 { MAX8997_EN32KHZ_AP, &max8997_32khz_ap_data },
935 { MAX8997_EN32KHZ_CP, &max8997_32khz_cp_data },
936
937 { MAX8997_ENVICHG, &max8997_vichg_data },
938 { MAX8997_ESAFEOUT1, &max8997_esafeout1_data },
939 { MAX8997_ESAFEOUT2, &max8997_esafeout2_data },
940 { MAX8997_CHARGER_CV, &max8997_charger_cv_data },
941 { MAX8997_CHARGER, &max8997_charger_data },
942 { MAX8997_CHARGER_TOPOFF, &max8997_charger_topoff_data },
943};
944
945static struct max8997_platform_data __initdata nuri_max8997_pdata = {
946 .wakeup = 1,
947
948 .num_regulators = ARRAY_SIZE(nuri_max8997_regulators),
949 .regulators = nuri_max8997_regulators,
950
951 .buck125_gpios = { EXYNOS4_GPX0(5), EXYNOS4_GPX0(6), EXYNOS4_GPL0(0) },
952
953 .buck1_voltage[0] = 1350000, /* 1.35V */
954 .buck1_voltage[1] = 1300000, /* 1.3V */
955 .buck1_voltage[2] = 1250000, /* 1.25V */
956 .buck1_voltage[3] = 1200000, /* 1.2V */
957 .buck1_voltage[4] = 1150000, /* 1.15V */
958 .buck1_voltage[5] = 1100000, /* 1.1V */
959 .buck1_voltage[6] = 1000000, /* 1.0V */
960 .buck1_voltage[7] = 950000, /* 0.95V */
961
962 .buck2_voltage[0] = 1100000, /* 1.1V */
963 .buck2_voltage[1] = 1000000, /* 1.0V */
964 .buck2_voltage[2] = 950000, /* 0.95V */
965 .buck2_voltage[3] = 900000, /* 0.9V */
966 .buck2_voltage[4] = 1100000, /* 1.1V */
967 .buck2_voltage[5] = 1000000, /* 1.0V */
968 .buck2_voltage[6] = 950000, /* 0.95V */
969 .buck2_voltage[7] = 900000, /* 0.9V */
970
971 .buck5_voltage[0] = 1200000, /* 1.2V */
972 .buck5_voltage[1] = 1200000, /* 1.2V */
973 .buck5_voltage[2] = 1200000, /* 1.2V */
974 .buck5_voltage[3] = 1200000, /* 1.2V */
975 .buck5_voltage[4] = 1200000, /* 1.2V */
976 .buck5_voltage[5] = 1200000, /* 1.2V */
977 .buck5_voltage[6] = 1200000, /* 1.2V */
978 .buck5_voltage[7] = 1200000, /* 1.2V */
979};
980
981/* GPIO I2C 5 (PMIC) */
982enum { I2C5_MAX8997 };
983static struct i2c_board_info i2c5_devs[] __initdata = {
984 [I2C5_MAX8997] = {
985 I2C_BOARD_INFO("max8997", 0xCC >> 1),
986 .platform_data = &nuri_max8997_pdata,
987 },
988};
989
990static struct max17042_platform_data nuri_battery_platform_data = {
991};
992
993/* GPIO I2C 9 (Fuel Gauge) */
994static struct i2c_gpio_platform_data i2c9_gpio_data = {
995 .sda_pin = EXYNOS4_GPY4(0), /* XM0ADDR_8 */
996 .scl_pin = EXYNOS4_GPY4(1), /* XM0ADDR_9 */
997};
998static struct platform_device i2c9_gpio = {
999 .name = "i2c-gpio",
1000 .id = 9,
1001 .dev = {
1002 .platform_data = &i2c9_gpio_data,
1003 },
1004};
1005enum { I2C9_MAX17042};
1006static struct i2c_board_info i2c9_devs[] __initdata = {
1007 [I2C9_MAX17042] = {
1008 I2C_BOARD_INFO("max17042", 0x36),
1009 .platform_data = &nuri_battery_platform_data,
1010 },
1011};
1012
1013/* MAX8903 Secondary Charger */
1014static struct regulator_consumer_supply supplies_max8903[] = {
1015 REGULATOR_SUPPLY("vinchg2", "charger-manager.0"),
1016};
1017
1018static struct regulator_init_data max8903_charger_en_data = {
1019 .constraints = {
1020 .name = "VOUT_CHARGER",
1021 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1022 .boot_on = 1,
1023 },
1024 .num_consumer_supplies = ARRAY_SIZE(supplies_max8903),
1025 .consumer_supplies = supplies_max8903,
1026};
1027
1028static struct fixed_voltage_config max8903_charger_en = {
1029 .supply_name = "VOUT_CHARGER",
1030 .microvolts = 5000000, /* Assume 5VDC */
1031 .gpio = EXYNOS4_GPY4(5), /* TA_EN negaged */
1032 .enable_high = 0, /* Enable = Low */
1033 .enabled_at_boot = 1,
1034 .init_data = &max8903_charger_en_data,
1035};
1036
1037static struct platform_device max8903_fixed_reg_dev = {
1038 .name = "reg-fixed-voltage",
1039 .id = FIXED_REG_ID_MAX8903,
1040 .dev = { .platform_data = &max8903_charger_en },
1041};
1042
1043static struct max8903_pdata nuri_max8903 = {
1044 /*
1045 * cen: don't control with the driver, let it be
1046 * controlled by regulator above
1047 */
1048 .dok = EXYNOS4_GPX1(4), /* TA_nCONNECTED */
1049 /* uok, usus: not connected */
1050 .chg = EXYNOS4_GPE2(0), /* TA_nCHG */
1051 /* flt: vcc_1.8V_pda */
1052 .dcm = EXYNOS4_GPL0(1), /* CURR_ADJ */
1053
1054 .dc_valid = true,
1055 .usb_valid = false, /* USB is not wired to MAX8903 */
1056};
1057
1058static struct platform_device nuri_max8903_device = {
1059 .name = "max8903-charger",
1060 .dev = {
1061 .platform_data = &nuri_max8903,
1062 },
1063};
1064
1065static void __init nuri_power_init(void)
1066{
1067 int gpio;
1068 int ta_en = 0;
1069
1070 gpio = EXYNOS4_GPX0(7);
1071 gpio_request(gpio, "AP_PMIC_IRQ");
1072 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
1073 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
1074
1075 gpio = EXYNOS4_GPX2(3);
1076 gpio_request(gpio, "FUEL_ALERT");
1077 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
1078 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
1079
1080 gpio = nuri_max8903.dok;
1081 gpio_request(gpio, "TA_nCONNECTED");
1082 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
1083 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
1084 ta_en = gpio_get_value(gpio) ? 0 : 1;
1085
1086 gpio = nuri_max8903.chg;
1087 gpio_request(gpio, "TA_nCHG");
1088 gpio_direction_input(gpio);
1089
1090 gpio = nuri_max8903.dcm;
1091 gpio_request(gpio, "CURR_ADJ");
1092 gpio_direction_output(gpio, ta_en);
1093}
1094
1095/* USB EHCI */
1096static struct s5p_ehci_platdata nuri_ehci_pdata;
1097
1098static void __init nuri_ehci_init(void)
1099{
1100 struct s5p_ehci_platdata *pdata = &nuri_ehci_pdata;
1101
1102 s5p_ehci_set_platdata(pdata);
1103}
1104
1105/* USB OTG */
1106static struct s3c_hsotg_plat nuri_hsotg_pdata;
1107
1108/* CAMERA */
1109static struct regulator_consumer_supply cam_vt_cam15_supply =
1110 REGULATOR_SUPPLY("vdd_core", "6-003c");
1111
1112static struct regulator_init_data cam_vt_cam15_reg_init_data = {
1113 .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
1114 .num_consumer_supplies = 1,
1115 .consumer_supplies = &cam_vt_cam15_supply,
1116};
1117
1118static struct fixed_voltage_config cam_vt_cam15_fixed_voltage_cfg = {
1119 .supply_name = "VT_CAM_1.5V",
1120 .microvolts = 1500000,
1121 .gpio = EXYNOS4_GPE2(2), /* VT_CAM_1.5V_EN */
1122 .enable_high = 1,
1123 .init_data = &cam_vt_cam15_reg_init_data,
1124};
1125
1126static struct platform_device cam_vt_cam15_fixed_rdev = {
1127 .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_VT_15V,
1128 .dev = { .platform_data = &cam_vt_cam15_fixed_voltage_cfg },
1129};
1130
1131static struct regulator_consumer_supply cam_vdda_supply[] = {
1132 REGULATOR_SUPPLY("vdda", "6-003c"),
1133 REGULATOR_SUPPLY("a_sensor", "0-001f"),
1134};
1135
1136static struct regulator_init_data cam_vdda_reg_init_data = {
1137 .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
1138 .num_consumer_supplies = ARRAY_SIZE(cam_vdda_supply),
1139 .consumer_supplies = cam_vdda_supply,
1140};
1141
1142static struct fixed_voltage_config cam_vdda_fixed_voltage_cfg = {
1143 .supply_name = "CAM_IO_EN",
1144 .microvolts = 2800000,
1145 .gpio = EXYNOS4_GPE2(1), /* CAM_IO_EN */
1146 .enable_high = 1,
1147 .init_data = &cam_vdda_reg_init_data,
1148};
1149
1150static struct platform_device cam_vdda_fixed_rdev = {
1151 .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_A28V,
1152 .dev = { .platform_data = &cam_vdda_fixed_voltage_cfg },
1153};
1154
1155static struct regulator_consumer_supply camera_8m_12v_supply =
1156 REGULATOR_SUPPLY("dig_12", "0-001f");
1157
1158static struct regulator_init_data cam_8m_12v_reg_init_data = {
1159 .num_consumer_supplies = 1,
1160 .consumer_supplies = &camera_8m_12v_supply,
1161 .constraints = {
1162 .valid_ops_mask = REGULATOR_CHANGE_STATUS
1163 },
1164};
1165
1166static struct fixed_voltage_config cam_8m_12v_fixed_voltage_cfg = {
1167 .supply_name = "8M_1.2V",
1168 .microvolts = 1200000,
1169 .gpio = EXYNOS4_GPE2(5), /* 8M_1.2V_EN */
1170 .enable_high = 1,
1171 .init_data = &cam_8m_12v_reg_init_data,
1172};
1173
1174static struct platform_device cam_8m_12v_fixed_rdev = {
1175 .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_12V,
1176 .dev = { .platform_data = &cam_8m_12v_fixed_voltage_cfg },
1177};
1178
1179static struct s5p_platform_mipi_csis mipi_csis_platdata = {
1180 .clk_rate = 166000000UL,
1181 .lanes = 2,
1182 .hs_settle = 12,
1183};
1184
1185#define GPIO_CAM_MEGA_RST EXYNOS4_GPY3(7) /* ISP_RESET */
1186#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPL2(5)
1187#define GPIO_CAM_VT_NSTBY EXYNOS4_GPL2(0)
1188#define GPIO_CAM_VT_NRST EXYNOS4_GPL2(1)
1189
1190static struct s5k6aa_platform_data s5k6aa_pldata = {
1191 .mclk_frequency = 24000000UL,
1192 .gpio_reset = { GPIO_CAM_VT_NRST, 0 },
1193 .gpio_stby = { GPIO_CAM_VT_NSTBY, 0 },
1194 .bus_type = V4L2_MBUS_PARALLEL,
1195 .horiz_flip = 1,
1196};
1197
1198static struct i2c_board_info s5k6aa_board_info = {
1199 I2C_BOARD_INFO("S5K6AA", 0x3c),
1200 .platform_data = &s5k6aa_pldata,
1201};
1202
1203static struct m5mols_platform_data m5mols_platdata = {
1204 .gpio_reset = GPIO_CAM_MEGA_RST,
1205};
1206
1207static struct i2c_board_info m5mols_board_info = {
1208 I2C_BOARD_INFO("M5MOLS", 0x1F),
1209 .platform_data = &m5mols_platdata,
1210};
1211
1212static struct fimc_source_info nuri_camera_sensors[] = {
1213 {
1214 .flags = V4L2_MBUS_PCLK_SAMPLE_RISING |
1215 V4L2_MBUS_VSYNC_ACTIVE_LOW,
1216 .fimc_bus_type = FIMC_BUS_TYPE_ITU_601,
1217 .board_info = &s5k6aa_board_info,
1218 .clk_frequency = 24000000UL,
1219 .i2c_bus_num = 6,
1220 }, {
1221 .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
1222 V4L2_MBUS_VSYNC_ACTIVE_LOW,
1223 .fimc_bus_type = FIMC_BUS_TYPE_MIPI_CSI2,
1224 .board_info = &m5mols_board_info,
1225 .clk_frequency = 24000000UL,
1226 },
1227};
1228
1229static struct s5p_platform_fimc fimc_md_platdata = {
1230 .source_info = nuri_camera_sensors,
1231 .num_clients = ARRAY_SIZE(nuri_camera_sensors),
1232};
1233
1234static struct gpio nuri_camera_gpios[] = {
1235 { GPIO_CAM_VT_NSTBY, GPIOF_OUT_INIT_LOW, "CAM_VGA_NSTBY" },
1236 { GPIO_CAM_VT_NRST, GPIOF_OUT_INIT_LOW, "CAM_VGA_NRST" },
1237 { GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" },
1238 { GPIO_CAM_MEGA_RST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
1239};
1240
1241static void __init nuri_camera_init(void)
1242{
1243 s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
1244 &s5p_device_mipi_csis0);
1245 s3c_set_platdata(&fimc_md_platdata, sizeof(fimc_md_platdata),
1246 &s5p_device_fimc_md);
1247
1248 if (gpio_request_array(nuri_camera_gpios,
1249 ARRAY_SIZE(nuri_camera_gpios))) {
1250 pr_err("%s: GPIO request failed\n", __func__);
1251 return;
1252 }
1253
1254 m5mols_board_info.irq = s5p_register_gpio_interrupt(GPIO_CAM_8M_ISP_INT);
1255 if (m5mols_board_info.irq >= 0)
1256 s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xF));
1257 else
1258 pr_err("%s: Failed to configure 8M_ISP_INT GPIO\n", __func__);
1259
1260 /* Free GPIOs controlled directly by the sensor drivers. */
1261 gpio_free(GPIO_CAM_VT_NRST);
1262 gpio_free(GPIO_CAM_VT_NSTBY);
1263 gpio_free(GPIO_CAM_MEGA_RST);
1264
1265 if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A)) {
1266 pr_err("%s: Camera port A setup failed\n", __func__);
1267 return;
1268 }
1269 /* Increase drive strength of the sensor clock output */
1270 s5p_gpio_set_drvstr(EXYNOS4_GPJ1(3), S5P_GPIO_DRVSTR_LV4);
1271}
1272
1273static struct s3c2410_platform_i2c nuri_i2c6_platdata __initdata = {
1274 .frequency = 400000U,
1275 .sda_delay = 200,
1276 .bus_num = 6,
1277};
1278
1279static struct s3c2410_platform_i2c nuri_i2c0_platdata __initdata = {
1280 .frequency = 400000U,
1281 .sda_delay = 200,
1282};
1283
1284/* DEVFREQ controlling memory/bus */
1285static struct platform_device exynos4_bus_devfreq = {
1286 .name = "exynos4210-busfreq",
1287};
1288
1289static struct platform_device *nuri_devices[] __initdata = {
1290 /* Samsung Platform Devices */
1291 &s3c_device_i2c5, /* PMIC should initialize first */
1292 &s3c_device_i2c0,
1293 &s3c_device_i2c6,
1294 &emmc_fixed_voltage,
1295 &s5p_device_mipi_csis0,
1296 &s5p_device_fimc0,
1297 &s5p_device_fimc1,
1298 &s5p_device_fimc2,
1299 &s5p_device_fimc3,
1300 &s5p_device_fimd0,
1301 &s3c_device_hsmmc0,
1302 &s3c_device_hsmmc2,
1303 &s3c_device_hsmmc3,
1304 &s3c_device_wdt,
1305 &s3c_device_timer[0],
1306 &s5p_device_ehci,
1307 &s3c_device_i2c3,
1308 &i2c9_gpio,
1309 &s3c_device_adc,
1310 &s5p_device_g2d,
1311 &s5p_device_jpeg,
1312 &s3c_device_rtc,
1313 &s5p_device_mfc,
1314 &s5p_device_mfc_l,
1315 &s5p_device_mfc_r,
1316 &s5p_device_fimc_md,
1317 &s3c_device_usb_hsotg,
1318
1319 /* NURI Devices */
1320 &nuri_gpio_keys,
1321 &nuri_lcd_device,
1322 &nuri_backlight_device,
1323 &max8903_fixed_reg_dev,
1324 &nuri_max8903_device,
1325 &cam_vt_cam15_fixed_rdev,
1326 &cam_vdda_fixed_rdev,
1327 &cam_8m_12v_fixed_rdev,
1328 &exynos4_bus_devfreq,
1329};
1330
1331static void __init nuri_map_io(void)
1332{
1333 exynos_init_io(NULL, 0);
1334 s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
1335 xxti_f = 0;
1336 xusbxti_f = 24000000;
1337}
1338
1339static void __init nuri_reserve(void)
1340{
1341 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
1342}
1343
1344static void __init nuri_machine_init(void)
1345{
1346 nuri_sdhci_init();
1347 nuri_tsp_init();
1348 nuri_power_init();
1349
1350 s3c_i2c0_set_platdata(&nuri_i2c0_platdata);
1351 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
1352 s3c_i2c3_set_platdata(&i2c3_data);
1353 i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
1354 s3c_i2c5_set_platdata(NULL);
1355 i2c5_devs[I2C5_MAX8997].irq = gpio_to_irq(EXYNOS4_GPX0(7));
1356 i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
1357 i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
1358 i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
1359 s3c_i2c6_set_platdata(&nuri_i2c6_platdata);
1360
1361#ifdef CONFIG_DRM_EXYNOS
1362 s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
1363 exynos4_fimd0_gpio_setup_24bpp();
1364#else
1365 s5p_fimd0_set_platdata(&nuri_fb_pdata);
1366#endif
1367
1368 nuri_camera_init();
1369
1370 nuri_ehci_init();
1371 s3c_hsotg_set_platdata(&nuri_hsotg_pdata);
1372
1373 /* Last */
1374 platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
1375}
1376
1377MACHINE_START(NURI, "NURI")
1378 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
1379 .atag_offset = 0x100,
1380 .smp = smp_ops(exynos_smp_ops),
1381 .init_irq = exynos4_init_irq,
1382 .map_io = nuri_map_io,
1383 .init_machine = nuri_machine_init,
1384 .init_late = exynos_init_late,
1385 .init_time = exynos_init_time,
1386 .reserve = &nuri_reserve,
1387 .restart = exynos4_restart,
1388MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
deleted file mode 100644
index 27f03ed5d067..000000000000
--- a/arch/arm/mach-exynos/mach-origen.c
+++ /dev/null
@@ -1,823 +0,0 @@
1/* linux/arch/arm/mach-exynos4/mach-origen.c
2 *
3 * Copyright (c) 2011 Insignal Co., Ltd.
4 * http://www.insignal.co.kr/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/serial_core.h>
12#include <linux/leds.h>
13#include <linux/gpio.h>
14#include <linux/mmc/host.h>
15#include <linux/platform_device.h>
16#include <linux/io.h>
17#include <linux/input.h>
18#include <linux/pwm.h>
19#include <linux/pwm_backlight.h>
20#include <linux/gpio_keys.h>
21#include <linux/i2c.h>
22#include <linux/regulator/machine.h>
23#include <linux/mfd/max8997.h>
24#include <linux/lcd.h>
25#include <linux/rfkill-gpio.h>
26#include <linux/platform_data/i2c-s3c2410.h>
27#include <linux/platform_data/s3c-hsotg.h>
28#include <linux/platform_data/usb-ehci-s5p.h>
29#include <linux/platform_data/usb-ohci-exynos.h>
30
31#include <asm/mach/arch.h>
32#include <asm/mach-types.h>
33
34#include <video/platform_lcd.h>
35#include <video/samsung_fimd.h>
36
37#include <plat/regs-serial.h>
38#include <plat/cpu.h>
39#include <plat/devs.h>
40#include <plat/sdhci.h>
41#include <plat/clock.h>
42#include <plat/gpio-cfg.h>
43#include <plat/backlight.h>
44#include <plat/fb.h>
45#include <plat/mfc.h>
46#include <plat/hdmi.h>
47
48#include <mach/map.h>
49#include <mach/irqs.h>
50
51#include <drm/exynos_drm.h>
52#include "common.h"
53
54/* Following are default values for UCON, ULCON and UFCON UART registers */
55#define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
56 S3C2410_UCON_RXILEVEL | \
57 S3C2410_UCON_TXIRQMODE | \
58 S3C2410_UCON_RXIRQMODE | \
59 S3C2410_UCON_RXFIFO_TOI | \
60 S3C2443_UCON_RXERR_IRQEN)
61
62#define ORIGEN_ULCON_DEFAULT S3C2410_LCON_CS8
63
64#define ORIGEN_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
65 S5PV210_UFCON_TXTRIG4 | \
66 S5PV210_UFCON_RXTRIG4)
67
68static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = {
69 [0] = {
70 .hwport = 0,
71 .flags = 0,
72 .ucon = ORIGEN_UCON_DEFAULT,
73 .ulcon = ORIGEN_ULCON_DEFAULT,
74 .ufcon = ORIGEN_UFCON_DEFAULT,
75 },
76 [1] = {
77 .hwport = 1,
78 .flags = 0,
79 .ucon = ORIGEN_UCON_DEFAULT,
80 .ulcon = ORIGEN_ULCON_DEFAULT,
81 .ufcon = ORIGEN_UFCON_DEFAULT,
82 },
83 [2] = {
84 .hwport = 2,
85 .flags = 0,
86 .ucon = ORIGEN_UCON_DEFAULT,
87 .ulcon = ORIGEN_ULCON_DEFAULT,
88 .ufcon = ORIGEN_UFCON_DEFAULT,
89 },
90 [3] = {
91 .hwport = 3,
92 .flags = 0,
93 .ucon = ORIGEN_UCON_DEFAULT,
94 .ulcon = ORIGEN_ULCON_DEFAULT,
95 .ufcon = ORIGEN_UFCON_DEFAULT,
96 },
97};
98
99static struct regulator_consumer_supply __initdata ldo3_consumer[] = {
100 REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /* MIPI */
101 REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), /* HDMI */
102 REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), /* HDMI */
103 REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), /* OTG */
104};
105static struct regulator_consumer_supply __initdata ldo6_consumer[] = {
106 REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */
107};
108static struct regulator_consumer_supply __initdata ldo7_consumer[] = {
109 REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */
110};
111static struct regulator_consumer_supply __initdata ldo8_consumer[] = {
112 REGULATOR_SUPPLY("vdd", "s5p-adc"), /* ADC */
113 REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), /* HDMI */
114 REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* OTG */
115};
116static struct regulator_consumer_supply __initdata ldo9_consumer[] = {
117 REGULATOR_SUPPLY("dvdd", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
118};
119static struct regulator_consumer_supply __initdata ldo11_consumer[] = {
120 REGULATOR_SUPPLY("dvdd", "alc5625"), /* Realtek ALC5625 */
121};
122static struct regulator_consumer_supply __initdata ldo14_consumer[] = {
123 REGULATOR_SUPPLY("avdd18", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
124};
125static struct regulator_consumer_supply __initdata ldo17_consumer[] = {
126 REGULATOR_SUPPLY("vdd33", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
127};
128static struct regulator_consumer_supply __initdata buck1_consumer[] = {
129 REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
130};
131static struct regulator_consumer_supply __initdata buck2_consumer[] = {
132 REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
133};
134static struct regulator_consumer_supply __initdata buck3_consumer[] = {
135 REGULATOR_SUPPLY("vdd_g3d", "mali_drm"), /* G3D */
136};
137static struct regulator_consumer_supply __initdata buck7_consumer[] = {
138 REGULATOR_SUPPLY("vcc", "platform-lcd"), /* LCD */
139};
140
141static struct regulator_init_data __initdata max8997_ldo1_data = {
142 .constraints = {
143 .name = "VDD_ABB_3.3V",
144 .min_uV = 3300000,
145 .max_uV = 3300000,
146 .apply_uV = 1,
147 .state_mem = {
148 .disabled = 1,
149 },
150 },
151};
152
153static struct regulator_init_data __initdata max8997_ldo2_data = {
154 .constraints = {
155 .name = "VDD_ALIVE_1.1V",
156 .min_uV = 1100000,
157 .max_uV = 1100000,
158 .apply_uV = 1,
159 .always_on = 1,
160 .state_mem = {
161 .enabled = 1,
162 },
163 },
164};
165
166static struct regulator_init_data __initdata max8997_ldo3_data = {
167 .constraints = {
168 .name = "VMIPI_1.1V",
169 .min_uV = 1100000,
170 .max_uV = 1100000,
171 .apply_uV = 1,
172 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
173 .state_mem = {
174 .disabled = 1,
175 },
176 },
177 .num_consumer_supplies = ARRAY_SIZE(ldo3_consumer),
178 .consumer_supplies = ldo3_consumer,
179};
180
181static struct regulator_init_data __initdata max8997_ldo4_data = {
182 .constraints = {
183 .name = "VDD_RTC_1.8V",
184 .min_uV = 1800000,
185 .max_uV = 1800000,
186 .apply_uV = 1,
187 .always_on = 1,
188 .state_mem = {
189 .disabled = 1,
190 },
191 },
192};
193
194static struct regulator_init_data __initdata max8997_ldo6_data = {
195 .constraints = {
196 .name = "VMIPI_1.8V",
197 .min_uV = 1800000,
198 .max_uV = 1800000,
199 .apply_uV = 1,
200 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
201 .state_mem = {
202 .disabled = 1,
203 },
204 },
205 .num_consumer_supplies = ARRAY_SIZE(ldo6_consumer),
206 .consumer_supplies = ldo6_consumer,
207};
208
209static struct regulator_init_data __initdata max8997_ldo7_data = {
210 .constraints = {
211 .name = "VDD_AUD_1.8V",
212 .min_uV = 1800000,
213 .max_uV = 1800000,
214 .apply_uV = 1,
215 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
216 .state_mem = {
217 .disabled = 1,
218 },
219 },
220 .num_consumer_supplies = ARRAY_SIZE(ldo7_consumer),
221 .consumer_supplies = ldo7_consumer,
222};
223
224static struct regulator_init_data __initdata max8997_ldo8_data = {
225 .constraints = {
226 .name = "VADC_3.3V",
227 .min_uV = 3300000,
228 .max_uV = 3300000,
229 .apply_uV = 1,
230 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
231 .state_mem = {
232 .disabled = 1,
233 },
234 },
235 .num_consumer_supplies = ARRAY_SIZE(ldo8_consumer),
236 .consumer_supplies = ldo8_consumer,
237};
238
239static struct regulator_init_data __initdata max8997_ldo9_data = {
240 .constraints = {
241 .name = "DVDD_SWB_2.8V",
242 .min_uV = 2800000,
243 .max_uV = 2800000,
244 .apply_uV = 1,
245 .always_on = 1,
246 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
247 .state_mem = {
248 .disabled = 1,
249 },
250 },
251 .num_consumer_supplies = ARRAY_SIZE(ldo9_consumer),
252 .consumer_supplies = ldo9_consumer,
253};
254
255static struct regulator_init_data __initdata max8997_ldo10_data = {
256 .constraints = {
257 .name = "VDD_PLL_1.1V",
258 .min_uV = 1100000,
259 .max_uV = 1100000,
260 .apply_uV = 1,
261 .always_on = 1,
262 .state_mem = {
263 .disabled = 1,
264 },
265 },
266};
267
268static struct regulator_init_data __initdata max8997_ldo11_data = {
269 .constraints = {
270 .name = "VDD_AUD_3V",
271 .min_uV = 3000000,
272 .max_uV = 3000000,
273 .apply_uV = 1,
274 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
275 .state_mem = {
276 .disabled = 1,
277 },
278 },
279 .num_consumer_supplies = ARRAY_SIZE(ldo11_consumer),
280 .consumer_supplies = ldo11_consumer,
281};
282
283static struct regulator_init_data __initdata max8997_ldo14_data = {
284 .constraints = {
285 .name = "AVDD18_SWB_1.8V",
286 .min_uV = 1800000,
287 .max_uV = 1800000,
288 .apply_uV = 1,
289 .always_on = 1,
290 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
291 .state_mem = {
292 .disabled = 1,
293 },
294 },
295 .num_consumer_supplies = ARRAY_SIZE(ldo14_consumer),
296 .consumer_supplies = ldo14_consumer,
297};
298
299static struct regulator_init_data __initdata max8997_ldo17_data = {
300 .constraints = {
301 .name = "VDD_SWB_3.3V",
302 .min_uV = 3300000,
303 .max_uV = 3300000,
304 .apply_uV = 1,
305 .always_on = 1,
306 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
307 .state_mem = {
308 .disabled = 1,
309 },
310 },
311 .num_consumer_supplies = ARRAY_SIZE(ldo17_consumer),
312 .consumer_supplies = ldo17_consumer,
313};
314
315static struct regulator_init_data __initdata max8997_ldo21_data = {
316 .constraints = {
317 .name = "VDD_MIF_1.2V",
318 .min_uV = 1200000,
319 .max_uV = 1200000,
320 .apply_uV = 1,
321 .always_on = 1,
322 .state_mem = {
323 .disabled = 1,
324 },
325 },
326};
327
328static struct regulator_init_data __initdata max8997_buck1_data = {
329 .constraints = {
330 .name = "VDD_ARM_1.2V",
331 .min_uV = 950000,
332 .max_uV = 1350000,
333 .always_on = 1,
334 .boot_on = 1,
335 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
336 .state_mem = {
337 .disabled = 1,
338 },
339 },
340 .num_consumer_supplies = ARRAY_SIZE(buck1_consumer),
341 .consumer_supplies = buck1_consumer,
342};
343
344static struct regulator_init_data __initdata max8997_buck2_data = {
345 .constraints = {
346 .name = "VDD_INT_1.1V",
347 .min_uV = 900000,
348 .max_uV = 1100000,
349 .always_on = 1,
350 .boot_on = 1,
351 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
352 .state_mem = {
353 .disabled = 1,
354 },
355 },
356 .num_consumer_supplies = ARRAY_SIZE(buck2_consumer),
357 .consumer_supplies = buck2_consumer,
358};
359
360static struct regulator_init_data __initdata max8997_buck3_data = {
361 .constraints = {
362 .name = "VDD_G3D_1.1V",
363 .min_uV = 900000,
364 .max_uV = 1100000,
365 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
366 REGULATOR_CHANGE_STATUS,
367 .state_mem = {
368 .disabled = 1,
369 },
370 },
371 .num_consumer_supplies = ARRAY_SIZE(buck3_consumer),
372 .consumer_supplies = buck3_consumer,
373};
374
375static struct regulator_init_data __initdata max8997_buck5_data = {
376 .constraints = {
377 .name = "VDDQ_M1M2_1.2V",
378 .min_uV = 1200000,
379 .max_uV = 1200000,
380 .apply_uV = 1,
381 .always_on = 1,
382 .state_mem = {
383 .disabled = 1,
384 },
385 },
386};
387
388static struct regulator_init_data __initdata max8997_buck7_data = {
389 .constraints = {
390 .name = "VDD_LCD_3.3V",
391 .min_uV = 3300000,
392 .max_uV = 3300000,
393 .boot_on = 1,
394 .apply_uV = 1,
395 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
396 .state_mem = {
397 .disabled = 1
398 },
399 },
400 .num_consumer_supplies = ARRAY_SIZE(buck7_consumer),
401 .consumer_supplies = buck7_consumer,
402};
403
404static struct max8997_regulator_data __initdata origen_max8997_regulators[] = {
405 { MAX8997_LDO1, &max8997_ldo1_data },
406 { MAX8997_LDO2, &max8997_ldo2_data },
407 { MAX8997_LDO3, &max8997_ldo3_data },
408 { MAX8997_LDO4, &max8997_ldo4_data },
409 { MAX8997_LDO6, &max8997_ldo6_data },
410 { MAX8997_LDO7, &max8997_ldo7_data },
411 { MAX8997_LDO8, &max8997_ldo8_data },
412 { MAX8997_LDO9, &max8997_ldo9_data },
413 { MAX8997_LDO10, &max8997_ldo10_data },
414 { MAX8997_LDO11, &max8997_ldo11_data },
415 { MAX8997_LDO14, &max8997_ldo14_data },
416 { MAX8997_LDO17, &max8997_ldo17_data },
417 { MAX8997_LDO21, &max8997_ldo21_data },
418 { MAX8997_BUCK1, &max8997_buck1_data },
419 { MAX8997_BUCK2, &max8997_buck2_data },
420 { MAX8997_BUCK3, &max8997_buck3_data },
421 { MAX8997_BUCK5, &max8997_buck5_data },
422 { MAX8997_BUCK7, &max8997_buck7_data },
423};
424
425static struct max8997_platform_data __initdata origen_max8997_pdata = {
426 .num_regulators = ARRAY_SIZE(origen_max8997_regulators),
427 .regulators = origen_max8997_regulators,
428
429 .wakeup = true,
430 .buck1_gpiodvs = false,
431 .buck2_gpiodvs = false,
432 .buck5_gpiodvs = false,
433
434 .ignore_gpiodvs_side_effect = true,
435 .buck125_default_idx = 0x0,
436
437 .buck125_gpios[0] = EXYNOS4_GPX0(0),
438 .buck125_gpios[1] = EXYNOS4_GPX0(1),
439 .buck125_gpios[2] = EXYNOS4_GPX0(2),
440
441 .buck1_voltage[0] = 1350000,
442 .buck1_voltage[1] = 1300000,
443 .buck1_voltage[2] = 1250000,
444 .buck1_voltage[3] = 1200000,
445 .buck1_voltage[4] = 1150000,
446 .buck1_voltage[5] = 1100000,
447 .buck1_voltage[6] = 1000000,
448 .buck1_voltage[7] = 950000,
449
450 .buck2_voltage[0] = 1100000,
451 .buck2_voltage[1] = 1100000,
452 .buck2_voltage[2] = 1100000,
453 .buck2_voltage[3] = 1100000,
454 .buck2_voltage[4] = 1000000,
455 .buck2_voltage[5] = 1000000,
456 .buck2_voltage[6] = 1000000,
457 .buck2_voltage[7] = 1000000,
458
459 .buck5_voltage[0] = 1200000,
460 .buck5_voltage[1] = 1200000,
461 .buck5_voltage[2] = 1200000,
462 .buck5_voltage[3] = 1200000,
463 .buck5_voltage[4] = 1200000,
464 .buck5_voltage[5] = 1200000,
465 .buck5_voltage[6] = 1200000,
466 .buck5_voltage[7] = 1200000,
467};
468
469/* I2C0 */
470static struct i2c_board_info i2c0_devs[] __initdata = {
471 {
472 I2C_BOARD_INFO("max8997", (0xCC >> 1)),
473 .platform_data = &origen_max8997_pdata,
474 .irq = IRQ_EINT(4),
475 },
476};
477
478static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = {
479 .cd_type = S3C_SDHCI_CD_INTERNAL,
480};
481
482static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = {
483 .cd_type = S3C_SDHCI_CD_INTERNAL,
484};
485
486/* USB EHCI */
487static struct s5p_ehci_platdata origen_ehci_pdata;
488
489static void __init origen_ehci_init(void)
490{
491 struct s5p_ehci_platdata *pdata = &origen_ehci_pdata;
492
493 s5p_ehci_set_platdata(pdata);
494}
495
496/* USB OHCI */
497static struct exynos4_ohci_platdata origen_ohci_pdata;
498
499static void __init origen_ohci_init(void)
500{
501 struct exynos4_ohci_platdata *pdata = &origen_ohci_pdata;
502
503 exynos4_ohci_set_platdata(pdata);
504}
505
506/* USB OTG */
507static struct s3c_hsotg_plat origen_hsotg_pdata;
508
509static struct gpio_led origen_gpio_leds[] = {
510 {
511 .name = "origen::status1",
512 .default_trigger = "heartbeat",
513 .gpio = EXYNOS4_GPX1(3),
514 .active_low = 1,
515 },
516 {
517 .name = "origen::status2",
518 .default_trigger = "mmc0",
519 .gpio = EXYNOS4_GPX1(4),
520 .active_low = 1,
521 },
522};
523
524static struct gpio_led_platform_data origen_gpio_led_info = {
525 .leds = origen_gpio_leds,
526 .num_leds = ARRAY_SIZE(origen_gpio_leds),
527};
528
529static struct platform_device origen_leds_gpio = {
530 .name = "leds-gpio",
531 .id = -1,
532 .dev = {
533 .platform_data = &origen_gpio_led_info,
534 },
535};
536
537static struct gpio_keys_button origen_gpio_keys_table[] = {
538 {
539 .code = KEY_MENU,
540 .gpio = EXYNOS4_GPX1(5),
541 .desc = "gpio-keys: KEY_MENU",
542 .type = EV_KEY,
543 .active_low = 1,
544 .wakeup = 1,
545 .debounce_interval = 1,
546 }, {
547 .code = KEY_HOME,
548 .gpio = EXYNOS4_GPX1(6),
549 .desc = "gpio-keys: KEY_HOME",
550 .type = EV_KEY,
551 .active_low = 1,
552 .wakeup = 1,
553 .debounce_interval = 1,
554 }, {
555 .code = KEY_BACK,
556 .gpio = EXYNOS4_GPX1(7),
557 .desc = "gpio-keys: KEY_BACK",
558 .type = EV_KEY,
559 .active_low = 1,
560 .wakeup = 1,
561 .debounce_interval = 1,
562 }, {
563 .code = KEY_UP,
564 .gpio = EXYNOS4_GPX2(0),
565 .desc = "gpio-keys: KEY_UP",
566 .type = EV_KEY,
567 .active_low = 1,
568 .wakeup = 1,
569 .debounce_interval = 1,
570 }, {
571 .code = KEY_DOWN,
572 .gpio = EXYNOS4_GPX2(1),
573 .desc = "gpio-keys: KEY_DOWN",
574 .type = EV_KEY,
575 .active_low = 1,
576 .wakeup = 1,
577 .debounce_interval = 1,
578 },
579};
580
581static struct gpio_keys_platform_data origen_gpio_keys_data = {
582 .buttons = origen_gpio_keys_table,
583 .nbuttons = ARRAY_SIZE(origen_gpio_keys_table),
584};
585
586static struct platform_device origen_device_gpiokeys = {
587 .name = "gpio-keys",
588 .dev = {
589 .platform_data = &origen_gpio_keys_data,
590 },
591};
592
593static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power)
594{
595 int ret;
596
597 if (power)
598 ret = gpio_request_one(EXYNOS4_GPE3(4),
599 GPIOF_OUT_INIT_HIGH, "GPE3_4");
600 else
601 ret = gpio_request_one(EXYNOS4_GPE3(4),
602 GPIOF_OUT_INIT_LOW, "GPE3_4");
603
604 gpio_free(EXYNOS4_GPE3(4));
605
606 if (ret)
607 pr_err("failed to request gpio for LCD power: %d\n", ret);
608}
609
610static struct plat_lcd_data origen_lcd_hv070wsa_data = {
611 .set_power = lcd_hv070wsa_set_power,
612};
613
614static struct platform_device origen_lcd_hv070wsa = {
615 .name = "platform-lcd",
616 .dev.parent = &s5p_device_fimd0.dev,
617 .dev.platform_data = &origen_lcd_hv070wsa_data,
618};
619
620static struct pwm_lookup origen_pwm_lookup[] = {
621 PWM_LOOKUP("s3c24xx-pwm.0", 0, "pwm-backlight.0", NULL),
622};
623
624#ifdef CONFIG_DRM_EXYNOS_FIMD
625static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
626 .panel = {
627 .timing = {
628 .left_margin = 64,
629 .right_margin = 16,
630 .upper_margin = 64,
631 .lower_margin = 16,
632 .hsync_len = 48,
633 .vsync_len = 3,
634 .xres = 1024,
635 .yres = 600,
636 },
637 },
638 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
639 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
640 VIDCON1_INV_VCLK,
641 .default_win = 0,
642 .bpp = 32,
643};
644#else
645static struct s3c_fb_pd_win origen_fb_win0 = {
646 .xres = 1024,
647 .yres = 600,
648 .max_bpp = 32,
649 .default_bpp = 24,
650 .virtual_x = 1024,
651 .virtual_y = 2 * 600,
652};
653
654static struct fb_videomode origen_lcd_timing = {
655 .left_margin = 64,
656 .right_margin = 16,
657 .upper_margin = 64,
658 .lower_margin = 16,
659 .hsync_len = 48,
660 .vsync_len = 3,
661 .xres = 1024,
662 .yres = 600,
663};
664
665static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
666 .win[0] = &origen_fb_win0,
667 .vtiming = &origen_lcd_timing,
668 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
669 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
670 VIDCON1_INV_VCLK,
671 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
672};
673#endif
674
675/* Bluetooth rfkill gpio platform data */
676static struct rfkill_gpio_platform_data origen_bt_pdata = {
677 .reset_gpio = EXYNOS4_GPX2(2),
678 .shutdown_gpio = -1,
679 .type = RFKILL_TYPE_BLUETOOTH,
680 .name = "origen-bt",
681};
682
683/* Bluetooth Platform device */
684static struct platform_device origen_device_bluetooth = {
685 .name = "rfkill_gpio",
686 .id = -1,
687 .dev = {
688 .platform_data = &origen_bt_pdata,
689 },
690};
691
692static struct platform_device *origen_devices[] __initdata = {
693 &s3c_device_hsmmc2,
694 &s3c_device_hsmmc0,
695 &s3c_device_i2c0,
696 &s3c_device_rtc,
697 &s3c_device_usb_hsotg,
698 &s3c_device_wdt,
699 &s5p_device_ehci,
700 &s5p_device_fimc0,
701 &s5p_device_fimc1,
702 &s5p_device_fimc2,
703 &s5p_device_fimc3,
704 &s5p_device_fimc_md,
705 &s5p_device_fimd0,
706 &s5p_device_g2d,
707 &s5p_device_hdmi,
708 &s5p_device_i2c_hdmiphy,
709 &s5p_device_jpeg,
710 &s5p_device_mfc,
711 &s5p_device_mfc_l,
712 &s5p_device_mfc_r,
713 &s5p_device_mixer,
714 &exynos4_device_ohci,
715 &origen_device_gpiokeys,
716 &origen_lcd_hv070wsa,
717 &origen_leds_gpio,
718 &origen_device_bluetooth,
719};
720
721/* LCD Backlight data */
722static struct samsung_bl_gpio_info origen_bl_gpio_info = {
723 .no = EXYNOS4_GPD0(0),
724 .func = S3C_GPIO_SFN(2),
725};
726
727static struct platform_pwm_backlight_data origen_bl_data = {
728 .pwm_id = 0,
729 .pwm_period_ns = 1000,
730};
731
732static void __init origen_bt_setup(void)
733{
734 gpio_request(EXYNOS4_GPA0(0), "GPIO BT_UART");
735 /* 4 UART Pins configuration */
736 s3c_gpio_cfgrange_nopull(EXYNOS4_GPA0(0), 4, S3C_GPIO_SFN(2));
737 /* Setup BT Reset, this gpio will be requesed by rfkill-gpio */
738 s3c_gpio_cfgpin(EXYNOS4_GPX2(2), S3C_GPIO_OUTPUT);
739 s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_NONE);
740}
741
742/* I2C module and id for HDMIPHY */
743static struct i2c_board_info hdmiphy_info = {
744 I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38),
745};
746
747static void s5p_tv_setup(void)
748{
749 /* Direct HPD to HDMI chip */
750 gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
751 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
752 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
753}
754
755static void __init origen_map_io(void)
756{
757 exynos_init_io(NULL, 0);
758 s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
759 xxti_f = 0;
760 xusbxti_f = 24000000;
761}
762
763static void __init origen_power_init(void)
764{
765 gpio_request(EXYNOS4_GPX0(4), "PMIC_IRQ");
766 s3c_gpio_cfgpin(EXYNOS4_GPX0(4), S3C_GPIO_SFN(0xf));
767 s3c_gpio_setpull(EXYNOS4_GPX0(4), S3C_GPIO_PULL_NONE);
768}
769
770static void __init origen_reserve(void)
771{
772 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
773}
774
775static void __init origen_machine_init(void)
776{
777 origen_power_init();
778
779 s3c_i2c0_set_platdata(NULL);
780 i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
781
782 /*
783 * Since sdhci instance 2 can contain a bootable media,
784 * sdhci instance 0 is registered after instance 2.
785 */
786 s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata);
787 s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata);
788
789 origen_ehci_init();
790 origen_ohci_init();
791 s3c_hsotg_set_platdata(&origen_hsotg_pdata);
792
793 s5p_tv_setup();
794 s5p_i2c_hdmiphy_set_platdata(NULL);
795 s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0);
796
797#ifdef CONFIG_DRM_EXYNOS_FIMD
798 s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
799 exynos4_fimd0_gpio_setup_24bpp();
800#else
801 s5p_fimd0_set_platdata(&origen_lcd_pdata);
802#endif
803
804 platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
805
806 pwm_add_table(origen_pwm_lookup, ARRAY_SIZE(origen_pwm_lookup));
807 samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
808
809 origen_bt_setup();
810}
811
812MACHINE_START(ORIGEN, "ORIGEN")
813 /* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */
814 .atag_offset = 0x100,
815 .smp = smp_ops(exynos_smp_ops),
816 .init_irq = exynos4_init_irq,
817 .map_io = origen_map_io,
818 .init_machine = origen_machine_init,
819 .init_late = exynos_init_late,
820 .init_time = exynos_init_time,
821 .reserve = &origen_reserve,
822 .restart = exynos4_restart,
823MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
deleted file mode 100644
index 2c8af9617920..000000000000
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ /dev/null
@@ -1,396 +0,0 @@
1/*
2 * linux/arch/arm/mach-exynos4/mach-smdk4x12.c
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/gpio.h>
13#include <linux/i2c.h>
14#include <linux/input.h>
15#include <linux/io.h>
16#include <linux/lcd.h>
17#include <linux/mfd/max8997.h>
18#include <linux/mmc/host.h>
19#include <linux/platform_device.h>
20#include <linux/pwm.h>
21#include <linux/pwm_backlight.h>
22#include <linux/regulator/machine.h>
23#include <linux/serial_core.h>
24#include <linux/platform_data/i2c-s3c2410.h>
25#include <linux/platform_data/s3c-hsotg.h>
26
27#include <asm/mach/arch.h>
28#include <asm/mach-types.h>
29
30#include <video/samsung_fimd.h>
31#include <plat/backlight.h>
32#include <plat/clock.h>
33#include <plat/cpu.h>
34#include <plat/devs.h>
35#include <plat/fb.h>
36#include <plat/gpio-cfg.h>
37#include <plat/keypad.h>
38#include <plat/mfc.h>
39#include <plat/regs-serial.h>
40#include <plat/sdhci.h>
41
42#include <mach/irqs.h>
43#include <mach/map.h>
44
45#include <drm/exynos_drm.h>
46#include "common.h"
47
48/* Following are default values for UCON, ULCON and UFCON UART registers */
49#define SMDK4X12_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
50 S3C2410_UCON_RXILEVEL | \
51 S3C2410_UCON_TXIRQMODE | \
52 S3C2410_UCON_RXIRQMODE | \
53 S3C2410_UCON_RXFIFO_TOI | \
54 S3C2443_UCON_RXERR_IRQEN)
55
56#define SMDK4X12_ULCON_DEFAULT S3C2410_LCON_CS8
57
58#define SMDK4X12_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
59 S5PV210_UFCON_TXTRIG4 | \
60 S5PV210_UFCON_RXTRIG4)
61
62static struct s3c2410_uartcfg smdk4x12_uartcfgs[] __initdata = {
63 [0] = {
64 .hwport = 0,
65 .flags = 0,
66 .ucon = SMDK4X12_UCON_DEFAULT,
67 .ulcon = SMDK4X12_ULCON_DEFAULT,
68 .ufcon = SMDK4X12_UFCON_DEFAULT,
69 },
70 [1] = {
71 .hwport = 1,
72 .flags = 0,
73 .ucon = SMDK4X12_UCON_DEFAULT,
74 .ulcon = SMDK4X12_ULCON_DEFAULT,
75 .ufcon = SMDK4X12_UFCON_DEFAULT,
76 },
77 [2] = {
78 .hwport = 2,
79 .flags = 0,
80 .ucon = SMDK4X12_UCON_DEFAULT,
81 .ulcon = SMDK4X12_ULCON_DEFAULT,
82 .ufcon = SMDK4X12_UFCON_DEFAULT,
83 },
84 [3] = {
85 .hwport = 3,
86 .flags = 0,
87 .ucon = SMDK4X12_UCON_DEFAULT,
88 .ulcon = SMDK4X12_ULCON_DEFAULT,
89 .ufcon = SMDK4X12_UFCON_DEFAULT,
90 },
91};
92
93static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = {
94 .cd_type = S3C_SDHCI_CD_INTERNAL,
95#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
96 .max_width = 8,
97 .host_caps = MMC_CAP_8_BIT_DATA,
98#endif
99};
100
101static struct s3c_sdhci_platdata smdk4x12_hsmmc3_pdata __initdata = {
102 .cd_type = S3C_SDHCI_CD_INTERNAL,
103};
104
105static struct regulator_consumer_supply max8997_buck1 =
106 REGULATOR_SUPPLY("vdd_arm", NULL);
107
108static struct regulator_consumer_supply max8997_buck2 =
109 REGULATOR_SUPPLY("vdd_int", NULL);
110
111static struct regulator_consumer_supply max8997_buck3 =
112 REGULATOR_SUPPLY("vdd_g3d", NULL);
113
114static struct regulator_init_data max8997_buck1_data = {
115 .constraints = {
116 .name = "VDD_ARM_SMDK4X12",
117 .min_uV = 925000,
118 .max_uV = 1350000,
119 .always_on = 1,
120 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
121 .state_mem = {
122 .disabled = 1,
123 },
124 },
125 .num_consumer_supplies = 1,
126 .consumer_supplies = &max8997_buck1,
127};
128
129static struct regulator_init_data max8997_buck2_data = {
130 .constraints = {
131 .name = "VDD_INT_SMDK4X12",
132 .min_uV = 950000,
133 .max_uV = 1150000,
134 .always_on = 1,
135 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
136 .state_mem = {
137 .disabled = 1,
138 },
139 },
140 .num_consumer_supplies = 1,
141 .consumer_supplies = &max8997_buck2,
142};
143
144static struct regulator_init_data max8997_buck3_data = {
145 .constraints = {
146 .name = "VDD_G3D_SMDK4X12",
147 .min_uV = 950000,
148 .max_uV = 1150000,
149 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
150 REGULATOR_CHANGE_STATUS,
151 .state_mem = {
152 .disabled = 1,
153 },
154 },
155 .num_consumer_supplies = 1,
156 .consumer_supplies = &max8997_buck3,
157};
158
159static struct max8997_regulator_data smdk4x12_max8997_regulators[] = {
160 { MAX8997_BUCK1, &max8997_buck1_data },
161 { MAX8997_BUCK2, &max8997_buck2_data },
162 { MAX8997_BUCK3, &max8997_buck3_data },
163};
164
165static struct max8997_platform_data smdk4x12_max8997_pdata = {
166 .num_regulators = ARRAY_SIZE(smdk4x12_max8997_regulators),
167 .regulators = smdk4x12_max8997_regulators,
168
169 .buck1_voltage[0] = 1100000, /* 1.1V */
170 .buck1_voltage[1] = 1100000, /* 1.1V */
171 .buck1_voltage[2] = 1100000, /* 1.1V */
172 .buck1_voltage[3] = 1100000, /* 1.1V */
173 .buck1_voltage[4] = 1100000, /* 1.1V */
174 .buck1_voltage[5] = 1100000, /* 1.1V */
175 .buck1_voltage[6] = 1000000, /* 1.0V */
176 .buck1_voltage[7] = 950000, /* 0.95V */
177
178 .buck2_voltage[0] = 1100000, /* 1.1V */
179 .buck2_voltage[1] = 1000000, /* 1.0V */
180 .buck2_voltage[2] = 950000, /* 0.95V */
181 .buck2_voltage[3] = 900000, /* 0.9V */
182 .buck2_voltage[4] = 1100000, /* 1.1V */
183 .buck2_voltage[5] = 1000000, /* 1.0V */
184 .buck2_voltage[6] = 950000, /* 0.95V */
185 .buck2_voltage[7] = 900000, /* 0.9V */
186
187 .buck5_voltage[0] = 1100000, /* 1.1V */
188 .buck5_voltage[1] = 1100000, /* 1.1V */
189 .buck5_voltage[2] = 1100000, /* 1.1V */
190 .buck5_voltage[3] = 1100000, /* 1.1V */
191 .buck5_voltage[4] = 1100000, /* 1.1V */
192 .buck5_voltage[5] = 1100000, /* 1.1V */
193 .buck5_voltage[6] = 1100000, /* 1.1V */
194 .buck5_voltage[7] = 1100000, /* 1.1V */
195};
196
197static struct i2c_board_info smdk4x12_i2c_devs0[] __initdata = {
198 {
199 I2C_BOARD_INFO("max8997", 0x66),
200 .platform_data = &smdk4x12_max8997_pdata,
201 }
202};
203
204static struct i2c_board_info smdk4x12_i2c_devs1[] __initdata = {
205 { I2C_BOARD_INFO("wm8994", 0x1a), }
206};
207
208static struct i2c_board_info smdk4x12_i2c_devs3[] __initdata = {
209 /* nothing here yet */
210};
211
212static struct i2c_board_info smdk4x12_i2c_devs7[] __initdata = {
213 /* nothing here yet */
214};
215
216static struct samsung_bl_gpio_info smdk4x12_bl_gpio_info = {
217 .no = EXYNOS4_GPD0(1),
218 .func = S3C_GPIO_SFN(2),
219};
220
221static struct platform_pwm_backlight_data smdk4x12_bl_data = {
222 .pwm_id = 1,
223 .pwm_period_ns = 1000,
224};
225
226static struct pwm_lookup smdk4x12_pwm_lookup[] = {
227 PWM_LOOKUP("s3c24xx-pwm.1", 0, "pwm-backlight.0", NULL),
228};
229
230static uint32_t smdk4x12_keymap[] __initdata = {
231 /* KEY(row, col, keycode) */
232 KEY(1, 3, KEY_1), KEY(1, 4, KEY_2), KEY(1, 5, KEY_3),
233 KEY(1, 6, KEY_4), KEY(1, 7, KEY_5),
234 KEY(2, 5, KEY_D), KEY(2, 6, KEY_A), KEY(2, 7, KEY_B),
235 KEY(0, 7, KEY_E), KEY(0, 5, KEY_C)
236};
237
238static struct matrix_keymap_data smdk4x12_keymap_data __initdata = {
239 .keymap = smdk4x12_keymap,
240 .keymap_size = ARRAY_SIZE(smdk4x12_keymap),
241};
242
243static struct samsung_keypad_platdata smdk4x12_keypad_data __initdata = {
244 .keymap_data = &smdk4x12_keymap_data,
245 .rows = 3,
246 .cols = 8,
247};
248
249#ifdef CONFIG_DRM_EXYNOS_FIMD
250static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
251 .panel = {
252 .timing = {
253 .left_margin = 8,
254 .right_margin = 8,
255 .upper_margin = 6,
256 .lower_margin = 6,
257 .hsync_len = 6,
258 .vsync_len = 4,
259 .xres = 480,
260 .yres = 800,
261 },
262 },
263 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
264 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
265 .default_win = 0,
266 .bpp = 32,
267};
268#else
269static struct s3c_fb_pd_win smdk4x12_fb_win0 = {
270 .xres = 480,
271 .yres = 800,
272 .virtual_x = 480,
273 .virtual_y = 800 * 2,
274 .max_bpp = 32,
275 .default_bpp = 24,
276};
277
278static struct fb_videomode smdk4x12_lcd_timing = {
279 .left_margin = 8,
280 .right_margin = 8,
281 .upper_margin = 6,
282 .lower_margin = 6,
283 .hsync_len = 6,
284 .vsync_len = 4,
285 .xres = 480,
286 .yres = 800,
287};
288
289static struct s3c_fb_platdata smdk4x12_lcd_pdata __initdata = {
290 .win[0] = &smdk4x12_fb_win0,
291 .vtiming = &smdk4x12_lcd_timing,
292 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
293 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
294 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
295};
296#endif
297
298/* USB OTG */
299static struct s3c_hsotg_plat smdk4x12_hsotg_pdata;
300
301static struct platform_device *smdk4x12_devices[] __initdata = {
302 &s3c_device_hsmmc2,
303 &s3c_device_hsmmc3,
304 &s3c_device_i2c0,
305 &s3c_device_i2c1,
306 &s3c_device_i2c3,
307 &s3c_device_i2c7,
308 &s3c_device_rtc,
309 &s3c_device_usb_hsotg,
310 &s3c_device_wdt,
311 &s5p_device_fimc0,
312 &s5p_device_fimc1,
313 &s5p_device_fimc2,
314 &s5p_device_fimc3,
315 &s5p_device_fimc_md,
316 &s5p_device_fimd0,
317 &s5p_device_mfc,
318 &s5p_device_mfc_l,
319 &s5p_device_mfc_r,
320 &samsung_device_keypad,
321};
322
323static void __init smdk4x12_map_io(void)
324{
325 exynos_init_io(NULL, 0);
326 s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
327}
328
329static void __init smdk4x12_reserve(void)
330{
331 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
332}
333
334static void __init smdk4x12_machine_init(void)
335{
336 s3c_i2c0_set_platdata(NULL);
337 i2c_register_board_info(0, smdk4x12_i2c_devs0,
338 ARRAY_SIZE(smdk4x12_i2c_devs0));
339
340 s3c_i2c1_set_platdata(NULL);
341 i2c_register_board_info(1, smdk4x12_i2c_devs1,
342 ARRAY_SIZE(smdk4x12_i2c_devs1));
343
344 s3c_i2c3_set_platdata(NULL);
345 i2c_register_board_info(3, smdk4x12_i2c_devs3,
346 ARRAY_SIZE(smdk4x12_i2c_devs3));
347
348 s3c_i2c7_set_platdata(NULL);
349 i2c_register_board_info(7, smdk4x12_i2c_devs7,
350 ARRAY_SIZE(smdk4x12_i2c_devs7));
351
352 samsung_bl_set(&smdk4x12_bl_gpio_info, &smdk4x12_bl_data);
353 pwm_add_table(smdk4x12_pwm_lookup, ARRAY_SIZE(smdk4x12_pwm_lookup));
354
355 samsung_keypad_set_platdata(&smdk4x12_keypad_data);
356
357 s3c_sdhci2_set_platdata(&smdk4x12_hsmmc2_pdata);
358 s3c_sdhci3_set_platdata(&smdk4x12_hsmmc3_pdata);
359
360 s3c_hsotg_set_platdata(&smdk4x12_hsotg_pdata);
361
362#ifdef CONFIG_DRM_EXYNOS_FIMD
363 s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
364 exynos4_fimd0_gpio_setup_24bpp();
365#else
366 s5p_fimd0_set_platdata(&smdk4x12_lcd_pdata);
367#endif
368
369 platform_add_devices(smdk4x12_devices, ARRAY_SIZE(smdk4x12_devices));
370}
371
372MACHINE_START(SMDK4212, "SMDK4212")
373 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
374 .atag_offset = 0x100,
375 .smp = smp_ops(exynos_smp_ops),
376 .init_irq = exynos4_init_irq,
377 .map_io = smdk4x12_map_io,
378 .init_machine = smdk4x12_machine_init,
379 .init_time = exynos_init_time,
380 .restart = exynos4_restart,
381 .reserve = &smdk4x12_reserve,
382MACHINE_END
383
384MACHINE_START(SMDK4412, "SMDK4412")
385 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
386 /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
387 .atag_offset = 0x100,
388 .smp = smp_ops(exynos_smp_ops),
389 .init_irq = exynos4_init_irq,
390 .map_io = smdk4x12_map_io,
391 .init_machine = smdk4x12_machine_init,
392 .init_late = exynos_init_late,
393 .init_time = exynos_init_time,
394 .restart = exynos4_restart,
395 .reserve = &smdk4x12_reserve,
396MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
deleted file mode 100644
index d95b8cf85253..000000000000
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ /dev/null
@@ -1,444 +0,0 @@
1/* linux/arch/arm/mach-exynos4/mach-smdkv310.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/serial_core.h>
12#include <linux/delay.h>
13#include <linux/gpio.h>
14#include <linux/lcd.h>
15#include <linux/mmc/host.h>
16#include <linux/platform_device.h>
17#include <linux/smsc911x.h>
18#include <linux/io.h>
19#include <linux/i2c.h>
20#include <linux/input.h>
21#include <linux/pwm.h>
22#include <linux/pwm_backlight.h>
23#include <linux/platform_data/i2c-s3c2410.h>
24#include <linux/platform_data/s3c-hsotg.h>
25#include <linux/platform_data/usb-ehci-s5p.h>
26#include <linux/platform_data/usb-ohci-exynos.h>
27
28#include <asm/mach/arch.h>
29#include <asm/mach-types.h>
30
31#include <video/platform_lcd.h>
32#include <video/samsung_fimd.h>
33#include <plat/regs-serial.h>
34#include <plat/regs-srom.h>
35#include <plat/cpu.h>
36#include <plat/devs.h>
37#include <plat/fb.h>
38#include <plat/keypad.h>
39#include <plat/sdhci.h>
40#include <plat/gpio-cfg.h>
41#include <plat/backlight.h>
42#include <plat/mfc.h>
43#include <plat/clock.h>
44#include <plat/hdmi.h>
45
46#include <mach/irqs.h>
47#include <mach/map.h>
48
49#include <drm/exynos_drm.h>
50#include "common.h"
51
52/* Following are default values for UCON, ULCON and UFCON UART registers */
53#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
54 S3C2410_UCON_RXILEVEL | \
55 S3C2410_UCON_TXIRQMODE | \
56 S3C2410_UCON_RXIRQMODE | \
57 S3C2410_UCON_RXFIFO_TOI | \
58 S3C2443_UCON_RXERR_IRQEN)
59
60#define SMDKV310_ULCON_DEFAULT S3C2410_LCON_CS8
61
62#define SMDKV310_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
63 S5PV210_UFCON_TXTRIG4 | \
64 S5PV210_UFCON_RXTRIG4)
65
66static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
67 [0] = {
68 .hwport = 0,
69 .flags = 0,
70 .ucon = SMDKV310_UCON_DEFAULT,
71 .ulcon = SMDKV310_ULCON_DEFAULT,
72 .ufcon = SMDKV310_UFCON_DEFAULT,
73 },
74 [1] = {
75 .hwport = 1,
76 .flags = 0,
77 .ucon = SMDKV310_UCON_DEFAULT,
78 .ulcon = SMDKV310_ULCON_DEFAULT,
79 .ufcon = SMDKV310_UFCON_DEFAULT,
80 },
81 [2] = {
82 .hwport = 2,
83 .flags = 0,
84 .ucon = SMDKV310_UCON_DEFAULT,
85 .ulcon = SMDKV310_ULCON_DEFAULT,
86 .ufcon = SMDKV310_UFCON_DEFAULT,
87 },
88 [3] = {
89 .hwport = 3,
90 .flags = 0,
91 .ucon = SMDKV310_UCON_DEFAULT,
92 .ulcon = SMDKV310_ULCON_DEFAULT,
93 .ufcon = SMDKV310_UFCON_DEFAULT,
94 },
95};
96
97static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
98 .cd_type = S3C_SDHCI_CD_INTERNAL,
99#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
100 .max_width = 8,
101 .host_caps = MMC_CAP_8_BIT_DATA,
102#endif
103};
104
105static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
106 .cd_type = S3C_SDHCI_CD_GPIO,
107 .ext_cd_gpio = EXYNOS4_GPK0(2),
108 .ext_cd_gpio_invert = 1,
109};
110
111static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
112 .cd_type = S3C_SDHCI_CD_INTERNAL,
113#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
114 .max_width = 8,
115 .host_caps = MMC_CAP_8_BIT_DATA,
116#endif
117};
118
119static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
120 .cd_type = S3C_SDHCI_CD_GPIO,
121 .ext_cd_gpio = EXYNOS4_GPK2(2),
122 .ext_cd_gpio_invert = 1,
123};
124
125static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
126 unsigned int power)
127{
128 if (power) {
129#if !defined(CONFIG_BACKLIGHT_PWM)
130 gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
131 gpio_free(EXYNOS4_GPD0(1));
132#endif
133 /* fire nRESET on power up */
134 gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0");
135 mdelay(100);
136
137 gpio_set_value(EXYNOS4_GPX0(6), 0);
138 mdelay(10);
139
140 gpio_set_value(EXYNOS4_GPX0(6), 1);
141 mdelay(10);
142
143 gpio_free(EXYNOS4_GPX0(6));
144 } else {
145#if !defined(CONFIG_BACKLIGHT_PWM)
146 gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
147 gpio_free(EXYNOS4_GPD0(1));
148#endif
149 }
150}
151
152static struct plat_lcd_data smdkv310_lcd_lte480wv_data = {
153 .set_power = lcd_lte480wv_set_power,
154};
155
156static struct platform_device smdkv310_lcd_lte480wv = {
157 .name = "platform-lcd",
158 .dev.parent = &s5p_device_fimd0.dev,
159 .dev.platform_data = &smdkv310_lcd_lte480wv_data,
160};
161
162#ifdef CONFIG_DRM_EXYNOS_FIMD
163static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
164 .panel = {
165 .timing = {
166 .left_margin = 13,
167 .right_margin = 8,
168 .upper_margin = 7,
169 .lower_margin = 5,
170 .hsync_len = 3,
171 .vsync_len = 1,
172 .xres = 800,
173 .yres = 480,
174 },
175 },
176 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
177 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
178 .default_win = 0,
179 .bpp = 32,
180};
181#else
182static struct s3c_fb_pd_win smdkv310_fb_win0 = {
183 .max_bpp = 32,
184 .default_bpp = 24,
185 .xres = 800,
186 .yres = 480,
187};
188
189static struct fb_videomode smdkv310_lcd_timing = {
190 .left_margin = 13,
191 .right_margin = 8,
192 .upper_margin = 7,
193 .lower_margin = 5,
194 .hsync_len = 3,
195 .vsync_len = 1,
196 .xres = 800,
197 .yres = 480,
198};
199
200static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
201 .win[0] = &smdkv310_fb_win0,
202 .vtiming = &smdkv310_lcd_timing,
203 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
204 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
205 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
206};
207#endif
208
209static struct resource smdkv310_smsc911x_resources[] = {
210 [0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(1), SZ_64K),
211 [1] = DEFINE_RES_NAMED(IRQ_EINT(5), 1, NULL, IORESOURCE_IRQ \
212 | IRQF_TRIGGER_LOW),
213};
214
215static struct smsc911x_platform_config smsc9215_config = {
216 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
217 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
218 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
219 .phy_interface = PHY_INTERFACE_MODE_MII,
220 .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
221};
222
223static struct platform_device smdkv310_smsc911x = {
224 .name = "smsc911x",
225 .id = -1,
226 .num_resources = ARRAY_SIZE(smdkv310_smsc911x_resources),
227 .resource = smdkv310_smsc911x_resources,
228 .dev = {
229 .platform_data = &smsc9215_config,
230 },
231};
232
233static uint32_t smdkv310_keymap[] __initdata = {
234 /* KEY(row, col, keycode) */
235 KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
236 KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
237 KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
238 KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
239};
240
241static struct matrix_keymap_data smdkv310_keymap_data __initdata = {
242 .keymap = smdkv310_keymap,
243 .keymap_size = ARRAY_SIZE(smdkv310_keymap),
244};
245
246static struct samsung_keypad_platdata smdkv310_keypad_data __initdata = {
247 .keymap_data = &smdkv310_keymap_data,
248 .rows = 2,
249 .cols = 8,
250};
251
252static struct i2c_board_info i2c_devs1[] __initdata = {
253 {I2C_BOARD_INFO("wm8994", 0x1a),},
254};
255
256/* USB EHCI */
257static struct s5p_ehci_platdata smdkv310_ehci_pdata;
258
259static void __init smdkv310_ehci_init(void)
260{
261 struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata;
262
263 s5p_ehci_set_platdata(pdata);
264}
265
266/* USB OHCI */
267static struct exynos4_ohci_platdata smdkv310_ohci_pdata;
268
269static void __init smdkv310_ohci_init(void)
270{
271 struct exynos4_ohci_platdata *pdata = &smdkv310_ohci_pdata;
272
273 exynos4_ohci_set_platdata(pdata);
274}
275
276/* USB OTG */
277static struct s3c_hsotg_plat smdkv310_hsotg_pdata;
278
279/* Audio device */
280static struct platform_device smdkv310_device_audio = {
281 .name = "smdk-audio",
282 .id = -1,
283};
284
285static struct platform_device *smdkv310_devices[] __initdata = {
286 &s3c_device_hsmmc0,
287 &s3c_device_hsmmc1,
288 &s3c_device_hsmmc2,
289 &s3c_device_hsmmc3,
290 &s3c_device_i2c1,
291 &s5p_device_i2c_hdmiphy,
292 &s3c_device_rtc,
293 &s3c_device_usb_hsotg,
294 &s3c_device_wdt,
295 &s5p_device_ehci,
296 &s5p_device_fimc0,
297 &s5p_device_fimc1,
298 &s5p_device_fimc2,
299 &s5p_device_fimc3,
300 &s5p_device_fimc_md,
301 &s5p_device_g2d,
302 &s5p_device_jpeg,
303 &exynos4_device_ac97,
304 &exynos4_device_i2s0,
305 &exynos4_device_ohci,
306 &samsung_device_keypad,
307 &s5p_device_mfc,
308 &s5p_device_mfc_l,
309 &s5p_device_mfc_r,
310 &exynos4_device_spdif,
311 &samsung_asoc_idma,
312 &s5p_device_fimd0,
313 &smdkv310_device_audio,
314 &smdkv310_lcd_lte480wv,
315 &smdkv310_smsc911x,
316 &exynos4_device_ahci,
317 &s5p_device_hdmi,
318 &s5p_device_mixer,
319};
320
321static void __init smdkv310_smsc911x_init(void)
322{
323 u32 cs1;
324
325 /* configure nCS1 width to 16 bits */
326 cs1 = __raw_readl(S5P_SROM_BW) &
327 ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
328 cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
329 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
330 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
331 S5P_SROM_BW__NCS1__SHIFT;
332 __raw_writel(cs1, S5P_SROM_BW);
333
334 /* set timing for nCS1 suitable for ethernet chip */
335 __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
336 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
337 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
338 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
339 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
340 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
341 (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
342}
343
344/* LCD Backlight data */
345static struct samsung_bl_gpio_info smdkv310_bl_gpio_info = {
346 .no = EXYNOS4_GPD0(1),
347 .func = S3C_GPIO_SFN(2),
348};
349
350static struct platform_pwm_backlight_data smdkv310_bl_data = {
351 .pwm_id = 1,
352 .pwm_period_ns = 1000,
353};
354
355/* I2C module and id for HDMIPHY */
356static struct i2c_board_info hdmiphy_info = {
357 I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38),
358};
359
360static struct pwm_lookup smdkv310_pwm_lookup[] = {
361 PWM_LOOKUP("s3c24xx-pwm.1", 0, "pwm-backlight.0", NULL),
362};
363
364static void s5p_tv_setup(void)
365{
366 /* direct HPD to HDMI chip */
367 WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"));
368 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
369 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
370}
371
372static void __init smdkv310_map_io(void)
373{
374 exynos_init_io(NULL, 0);
375 s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
376 xxti_f = 12000000;
377 xusbxti_f = 24000000;
378}
379
380static void __init smdkv310_reserve(void)
381{
382 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
383}
384
385static void __init smdkv310_machine_init(void)
386{
387 s3c_i2c1_set_platdata(NULL);
388 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
389
390 smdkv310_smsc911x_init();
391
392 s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
393 s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata);
394 s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
395 s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
396
397 s5p_tv_setup();
398 s5p_i2c_hdmiphy_set_platdata(NULL);
399 s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0);
400
401 samsung_keypad_set_platdata(&smdkv310_keypad_data);
402
403 samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
404 pwm_add_table(smdkv310_pwm_lookup, ARRAY_SIZE(smdkv310_pwm_lookup));
405
406#ifdef CONFIG_DRM_EXYNOS_FIMD
407 s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
408 exynos4_fimd0_gpio_setup_24bpp();
409#else
410 s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
411#endif
412
413 smdkv310_ehci_init();
414 smdkv310_ohci_init();
415 s3c_hsotg_set_platdata(&smdkv310_hsotg_pdata);
416
417 platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
418}
419
420MACHINE_START(SMDKV310, "SMDKV310")
421 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
422 /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
423 .atag_offset = 0x100,
424 .smp = smp_ops(exynos_smp_ops),
425 .init_irq = exynos4_init_irq,
426 .map_io = smdkv310_map_io,
427 .init_machine = smdkv310_machine_init,
428 .init_time = exynos_init_time,
429 .reserve = &smdkv310_reserve,
430 .restart = exynos4_restart,
431MACHINE_END
432
433MACHINE_START(SMDKC210, "SMDKC210")
434 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
435 .atag_offset = 0x100,
436 .smp = smp_ops(exynos_smp_ops),
437 .init_irq = exynos4_init_irq,
438 .map_io = smdkv310_map_io,
439 .init_machine = smdkv310_machine_init,
440 .init_late = exynos_init_late,
441 .init_time = exynos_init_time,
442 .reserve = &smdkv310_reserve,
443 .restart = exynos4_restart,
444MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
deleted file mode 100644
index 74ddb2b55614..000000000000
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ /dev/null
@@ -1,1159 +0,0 @@
1/* linux/arch/arm/mach-exynos4/mach-universal_c210.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8*/
9
10#include <linux/platform_device.h>
11#include <linux/serial_core.h>
12#include <linux/input.h>
13#include <linux/i2c.h>
14#include <linux/gpio_keys.h>
15#include <linux/gpio.h>
16#include <linux/interrupt.h>
17#include <linux/fb.h>
18#include <linux/mfd/max8998.h>
19#include <linux/regulator/machine.h>
20#include <linux/regulator/fixed.h>
21#include <linux/regulator/max8952.h>
22#include <linux/mmc/host.h>
23#include <linux/i2c-gpio.h>
24#include <linux/i2c/mcs.h>
25#include <linux/i2c/atmel_mxt_ts.h>
26#include <linux/platform_data/i2c-s3c2410.h>
27#include <linux/platform_data/mipi-csis.h>
28#include <linux/platform_data/s3c-hsotg.h>
29#include <drm/exynos_drm.h>
30
31#include <asm/mach/arch.h>
32#include <asm/mach-types.h>
33
34#include <video/samsung_fimd.h>
35#include <plat/regs-serial.h>
36#include <plat/clock.h>
37#include <plat/cpu.h>
38#include <plat/devs.h>
39#include <plat/gpio-cfg.h>
40#include <plat/fb.h>
41#include <plat/mfc.h>
42#include <plat/sdhci.h>
43#include <plat/fimc-core.h>
44#include <plat/camport.h>
45
46#include <mach/map.h>
47
48#include <media/v4l2-mediabus.h>
49#include <media/s5p_fimc.h>
50#include <media/m5mols.h>
51#include <media/s5k6aa.h>
52
53#include "common.h"
54
55/* Following are default values for UCON, ULCON and UFCON UART registers */
56#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
57 S3C2410_UCON_RXILEVEL | \
58 S3C2410_UCON_TXIRQMODE | \
59 S3C2410_UCON_RXIRQMODE | \
60 S3C2410_UCON_RXFIFO_TOI | \
61 S3C2443_UCON_RXERR_IRQEN)
62
63#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8
64
65#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
66 S5PV210_UFCON_TXTRIG256 | \
67 S5PV210_UFCON_RXTRIG256)
68
69static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
70 [0] = {
71 .hwport = 0,
72 .ucon = UNIVERSAL_UCON_DEFAULT,
73 .ulcon = UNIVERSAL_ULCON_DEFAULT,
74 .ufcon = UNIVERSAL_UFCON_DEFAULT,
75 },
76 [1] = {
77 .hwport = 1,
78 .ucon = UNIVERSAL_UCON_DEFAULT,
79 .ulcon = UNIVERSAL_ULCON_DEFAULT,
80 .ufcon = UNIVERSAL_UFCON_DEFAULT,
81 },
82 [2] = {
83 .hwport = 2,
84 .ucon = UNIVERSAL_UCON_DEFAULT,
85 .ulcon = UNIVERSAL_ULCON_DEFAULT,
86 .ufcon = UNIVERSAL_UFCON_DEFAULT,
87 },
88 [3] = {
89 .hwport = 3,
90 .ucon = UNIVERSAL_UCON_DEFAULT,
91 .ulcon = UNIVERSAL_ULCON_DEFAULT,
92 .ufcon = UNIVERSAL_UFCON_DEFAULT,
93 },
94};
95
96static struct regulator_consumer_supply max8952_consumer =
97 REGULATOR_SUPPLY("vdd_arm", NULL);
98
99static struct regulator_init_data universal_max8952_reg_data = {
100 .constraints = {
101 .name = "VARM_1.2V",
102 .min_uV = 770000,
103 .max_uV = 1400000,
104 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
105 .always_on = 1,
106 .boot_on = 1,
107 },
108 .num_consumer_supplies = 1,
109 .consumer_supplies = &max8952_consumer,
110};
111
112static struct max8952_platform_data universal_max8952_pdata __initdata = {
113 .gpio_vid0 = EXYNOS4_GPX0(3),
114 .gpio_vid1 = EXYNOS4_GPX0(4),
115 .gpio_en = -1, /* Not controllable, set "Always High" */
116 .default_mode = 0, /* vid0 = 0, vid1 = 0 */
117 .dvs_mode = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */
118 .sync_freq = 0, /* default: fastest */
119 .ramp_speed = 0, /* default: fastest */
120 .reg_data = &universal_max8952_reg_data,
121};
122
123static struct regulator_consumer_supply lp3974_buck1_consumer =
124 REGULATOR_SUPPLY("vdd_int", NULL);
125
126static struct regulator_consumer_supply lp3974_buck2_consumer =
127 REGULATOR_SUPPLY("vddg3d", NULL);
128
129static struct regulator_consumer_supply lp3974_buck3_consumer[] = {
130 REGULATOR_SUPPLY("vdet", "s5p-sdo"),
131 REGULATOR_SUPPLY("vdd_reg", "0-003c"),
132};
133
134static struct regulator_init_data lp3974_buck1_data = {
135 .constraints = {
136 .name = "VINT_1.1V",
137 .min_uV = 750000,
138 .max_uV = 1500000,
139 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
140 REGULATOR_CHANGE_STATUS,
141 .boot_on = 1,
142 .state_mem = {
143 .disabled = 1,
144 },
145 },
146 .num_consumer_supplies = 1,
147 .consumer_supplies = &lp3974_buck1_consumer,
148};
149
150static struct regulator_init_data lp3974_buck2_data = {
151 .constraints = {
152 .name = "VG3D_1.1V",
153 .min_uV = 750000,
154 .max_uV = 1500000,
155 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
156 REGULATOR_CHANGE_STATUS,
157 .boot_on = 1,
158 .state_mem = {
159 .disabled = 1,
160 },
161 },
162 .num_consumer_supplies = 1,
163 .consumer_supplies = &lp3974_buck2_consumer,
164};
165
166static struct regulator_init_data lp3974_buck3_data = {
167 .constraints = {
168 .name = "VCC_1.8V",
169 .min_uV = 1800000,
170 .max_uV = 1800000,
171 .apply_uV = 1,
172 .always_on = 1,
173 .state_mem = {
174 .enabled = 1,
175 },
176 },
177 .num_consumer_supplies = ARRAY_SIZE(lp3974_buck3_consumer),
178 .consumer_supplies = lp3974_buck3_consumer,
179};
180
181static struct regulator_init_data lp3974_buck4_data = {
182 .constraints = {
183 .name = "VMEM_1.2V",
184 .min_uV = 1200000,
185 .max_uV = 1200000,
186 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
187 .apply_uV = 1,
188 .state_mem = {
189 .disabled = 1,
190 },
191 },
192};
193
194static struct regulator_init_data lp3974_ldo2_data = {
195 .constraints = {
196 .name = "VALIVE_1.2V",
197 .min_uV = 1200000,
198 .max_uV = 1200000,
199 .apply_uV = 1,
200 .always_on = 1,
201 .state_mem = {
202 .enabled = 1,
203 },
204 },
205};
206
207static struct regulator_consumer_supply lp3974_ldo3_consumer[] = {
208 REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"),
209 REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
210 REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
211 REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"),
212};
213
214static struct regulator_init_data lp3974_ldo3_data = {
215 .constraints = {
216 .name = "VUSB+MIPI_1.1V",
217 .min_uV = 1100000,
218 .max_uV = 1100000,
219 .apply_uV = 1,
220 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
221 .state_mem = {
222 .disabled = 1,
223 },
224 },
225 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo3_consumer),
226 .consumer_supplies = lp3974_ldo3_consumer,
227};
228
229static struct regulator_consumer_supply lp3974_ldo4_consumer[] = {
230 REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"),
231};
232
233static struct regulator_init_data lp3974_ldo4_data = {
234 .constraints = {
235 .name = "VADC_3.3V",
236 .min_uV = 3300000,
237 .max_uV = 3300000,
238 .apply_uV = 1,
239 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
240 .state_mem = {
241 .disabled = 1,
242 },
243 },
244 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo4_consumer),
245 .consumer_supplies = lp3974_ldo4_consumer,
246};
247
248static struct regulator_init_data lp3974_ldo5_data = {
249 .constraints = {
250 .name = "VTF_2.8V",
251 .min_uV = 2800000,
252 .max_uV = 2800000,
253 .apply_uV = 1,
254 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
255 .state_mem = {
256 .disabled = 1,
257 },
258 },
259};
260
261static struct regulator_init_data lp3974_ldo6_data = {
262 .constraints = {
263 .name = "LDO6",
264 .min_uV = 2000000,
265 .max_uV = 2000000,
266 .apply_uV = 1,
267 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
268 .state_mem = {
269 .disabled = 1,
270 },
271 },
272};
273
274static struct regulator_consumer_supply lp3974_ldo7_consumer[] = {
275 REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"),
276};
277
278static struct regulator_init_data lp3974_ldo7_data = {
279 .constraints = {
280 .name = "VLCD+VMIPI_1.8V",
281 .min_uV = 1800000,
282 .max_uV = 1800000,
283 .apply_uV = 1,
284 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
285 .state_mem = {
286 .disabled = 1,
287 },
288 },
289 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo7_consumer),
290 .consumer_supplies = lp3974_ldo7_consumer,
291};
292
293static struct regulator_consumer_supply lp3974_ldo8_consumer[] = {
294 REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"),
295 REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
296};
297
298static struct regulator_init_data lp3974_ldo8_data = {
299 .constraints = {
300 .name = "VUSB+VDAC_3.3V",
301 .min_uV = 3300000,
302 .max_uV = 3300000,
303 .apply_uV = 1,
304 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
305 .state_mem = {
306 .disabled = 1,
307 },
308 },
309 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo8_consumer),
310 .consumer_supplies = lp3974_ldo8_consumer,
311};
312
313static struct regulator_consumer_supply lp3974_ldo9_consumer =
314 REGULATOR_SUPPLY("vddio", "0-003c");
315
316static struct regulator_init_data lp3974_ldo9_data = {
317 .constraints = {
318 .name = "VCC_2.8V",
319 .min_uV = 2800000,
320 .max_uV = 2800000,
321 .apply_uV = 1,
322 .always_on = 1,
323 .state_mem = {
324 .enabled = 1,
325 },
326 },
327 .num_consumer_supplies = 1,
328 .consumer_supplies = &lp3974_ldo9_consumer,
329};
330
331static struct regulator_init_data lp3974_ldo10_data = {
332 .constraints = {
333 .name = "VPLL_1.1V",
334 .min_uV = 1100000,
335 .max_uV = 1100000,
336 .boot_on = 1,
337 .apply_uV = 1,
338 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
339 .state_mem = {
340 .disabled = 1,
341 },
342 },
343};
344
345static struct regulator_consumer_supply lp3974_ldo11_consumer =
346 REGULATOR_SUPPLY("dig_28", "0-001f");
347
348static struct regulator_init_data lp3974_ldo11_data = {
349 .constraints = {
350 .name = "CAM_AF_3.3V",
351 .min_uV = 3300000,
352 .max_uV = 3300000,
353 .apply_uV = 1,
354 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
355 .state_mem = {
356 .disabled = 1,
357 },
358 },
359 .num_consumer_supplies = 1,
360 .consumer_supplies = &lp3974_ldo11_consumer,
361};
362
363static struct regulator_init_data lp3974_ldo12_data = {
364 .constraints = {
365 .name = "PS_2.8V",
366 .min_uV = 2800000,
367 .max_uV = 2800000,
368 .apply_uV = 1,
369 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
370 .state_mem = {
371 .disabled = 1,
372 },
373 },
374};
375
376static struct regulator_init_data lp3974_ldo13_data = {
377 .constraints = {
378 .name = "VHIC_1.2V",
379 .min_uV = 1200000,
380 .max_uV = 1200000,
381 .apply_uV = 1,
382 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
383 .state_mem = {
384 .disabled = 1,
385 },
386 },
387};
388
389static struct regulator_consumer_supply lp3974_ldo14_consumer =
390 REGULATOR_SUPPLY("dig_18", "0-001f");
391
392static struct regulator_init_data lp3974_ldo14_data = {
393 .constraints = {
394 .name = "CAM_I_HOST_1.8V",
395 .min_uV = 1800000,
396 .max_uV = 1800000,
397 .apply_uV = 1,
398 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
399 .state_mem = {
400 .disabled = 1,
401 },
402 },
403 .num_consumer_supplies = 1,
404 .consumer_supplies = &lp3974_ldo14_consumer,
405};
406
407
408static struct regulator_consumer_supply lp3974_ldo15_consumer =
409 REGULATOR_SUPPLY("dig_12", "0-001f");
410
411static struct regulator_init_data lp3974_ldo15_data = {
412 .constraints = {
413 .name = "CAM_S_DIG+FM33_CORE_1.2V",
414 .min_uV = 1200000,
415 .max_uV = 1200000,
416 .apply_uV = 1,
417 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
418 .state_mem = {
419 .disabled = 1,
420 },
421 },
422 .num_consumer_supplies = 1,
423 .consumer_supplies = &lp3974_ldo15_consumer,
424};
425
426static struct regulator_consumer_supply lp3974_ldo16_consumer[] = {
427 REGULATOR_SUPPLY("vdda", "0-003c"),
428 REGULATOR_SUPPLY("a_sensor", "0-001f"),
429};
430
431static struct regulator_init_data lp3974_ldo16_data = {
432 .constraints = {
433 .name = "CAM_S_ANA_2.8V",
434 .min_uV = 2800000,
435 .max_uV = 2800000,
436 .apply_uV = 1,
437 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
438 .state_mem = {
439 .disabled = 1,
440 },
441 },
442 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo16_consumer),
443 .consumer_supplies = lp3974_ldo16_consumer,
444};
445
446static struct regulator_init_data lp3974_ldo17_data = {
447 .constraints = {
448 .name = "VCC_3.0V_LCD",
449 .min_uV = 3000000,
450 .max_uV = 3000000,
451 .apply_uV = 1,
452 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
453 .boot_on = 1,
454 .state_mem = {
455 .disabled = 1,
456 },
457 },
458};
459
460static struct regulator_init_data lp3974_32khz_ap_data = {
461 .constraints = {
462 .name = "32KHz AP",
463 .always_on = 1,
464 .state_mem = {
465 .enabled = 1,
466 },
467 },
468};
469
470static struct regulator_init_data lp3974_32khz_cp_data = {
471 .constraints = {
472 .name = "32KHz CP",
473 .state_mem = {
474 .disabled = 1,
475 },
476 },
477};
478
479static struct regulator_init_data lp3974_vichg_data = {
480 .constraints = {
481 .name = "VICHG",
482 .state_mem = {
483 .disabled = 1,
484 },
485 },
486};
487
488static struct regulator_init_data lp3974_esafeout1_data = {
489 .constraints = {
490 .name = "SAFEOUT1",
491 .min_uV = 4800000,
492 .max_uV = 4800000,
493 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
494 .always_on = 1,
495 .state_mem = {
496 .enabled = 1,
497 },
498 },
499};
500
501static struct regulator_init_data lp3974_esafeout2_data = {
502 .constraints = {
503 .name = "SAFEOUT2",
504 .boot_on = 1,
505 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
506 .state_mem = {
507 .enabled = 1,
508 },
509 },
510};
511
512static struct max8998_regulator_data lp3974_regulators[] = {
513 { MAX8998_LDO2, &lp3974_ldo2_data },
514 { MAX8998_LDO3, &lp3974_ldo3_data },
515 { MAX8998_LDO4, &lp3974_ldo4_data },
516 { MAX8998_LDO5, &lp3974_ldo5_data },
517 { MAX8998_LDO6, &lp3974_ldo6_data },
518 { MAX8998_LDO7, &lp3974_ldo7_data },
519 { MAX8998_LDO8, &lp3974_ldo8_data },
520 { MAX8998_LDO9, &lp3974_ldo9_data },
521 { MAX8998_LDO10, &lp3974_ldo10_data },
522 { MAX8998_LDO11, &lp3974_ldo11_data },
523 { MAX8998_LDO12, &lp3974_ldo12_data },
524 { MAX8998_LDO13, &lp3974_ldo13_data },
525 { MAX8998_LDO14, &lp3974_ldo14_data },
526 { MAX8998_LDO15, &lp3974_ldo15_data },
527 { MAX8998_LDO16, &lp3974_ldo16_data },
528 { MAX8998_LDO17, &lp3974_ldo17_data },
529 { MAX8998_BUCK1, &lp3974_buck1_data },
530 { MAX8998_BUCK2, &lp3974_buck2_data },
531 { MAX8998_BUCK3, &lp3974_buck3_data },
532 { MAX8998_BUCK4, &lp3974_buck4_data },
533 { MAX8998_EN32KHZ_AP, &lp3974_32khz_ap_data },
534 { MAX8998_EN32KHZ_CP, &lp3974_32khz_cp_data },
535 { MAX8998_ENVICHG, &lp3974_vichg_data },
536 { MAX8998_ESAFEOUT1, &lp3974_esafeout1_data },
537 { MAX8998_ESAFEOUT2, &lp3974_esafeout2_data },
538};
539
540static struct max8998_platform_data universal_lp3974_pdata = {
541 .num_regulators = ARRAY_SIZE(lp3974_regulators),
542 .regulators = lp3974_regulators,
543 .buck1_voltage1 = 1100000, /* INT */
544 .buck1_voltage2 = 1000000,
545 .buck1_voltage3 = 1100000,
546 .buck1_voltage4 = 1000000,
547 .buck1_set1 = EXYNOS4_GPX0(5),
548 .buck1_set2 = EXYNOS4_GPX0(6),
549 .buck2_voltage1 = 1200000, /* G3D */
550 .buck2_voltage2 = 1100000,
551 .buck1_default_idx = 0,
552 .buck2_set3 = EXYNOS4_GPE2(0),
553 .buck2_default_idx = 0,
554 .wakeup = true,
555};
556
557
558enum fixed_regulator_id {
559 FIXED_REG_ID_MMC0,
560 FIXED_REG_ID_HDMI_5V,
561 FIXED_REG_ID_CAM_S_IF,
562 FIXED_REG_ID_CAM_I_CORE,
563 FIXED_REG_ID_CAM_VT_DIO,
564};
565
566static struct regulator_consumer_supply hdmi_fixed_consumer =
567 REGULATOR_SUPPLY("hdmi-en", "exynos4-hdmi");
568
569static struct regulator_init_data hdmi_fixed_voltage_init_data = {
570 .constraints = {
571 .name = "HDMI_5V",
572 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
573 },
574 .num_consumer_supplies = 1,
575 .consumer_supplies = &hdmi_fixed_consumer,
576};
577
578static struct fixed_voltage_config hdmi_fixed_voltage_config = {
579 .supply_name = "HDMI_EN1",
580 .microvolts = 5000000,
581 .gpio = EXYNOS4_GPE0(1),
582 .enable_high = true,
583 .init_data = &hdmi_fixed_voltage_init_data,
584};
585
586static struct platform_device hdmi_fixed_voltage = {
587 .name = "reg-fixed-voltage",
588 .id = FIXED_REG_ID_HDMI_5V,
589 .dev = {
590 .platform_data = &hdmi_fixed_voltage_config,
591 },
592};
593
594/* GPIO I2C 5 (PMIC) */
595static struct i2c_board_info i2c5_devs[] __initdata = {
596 {
597 I2C_BOARD_INFO("max8952", 0xC0 >> 1),
598 .platform_data = &universal_max8952_pdata,
599 }, {
600 I2C_BOARD_INFO("lp3974", 0xCC >> 1),
601 .platform_data = &universal_lp3974_pdata,
602 },
603};
604
605/* I2C3 (TSP) */
606static struct mxt_platform_data qt602240_platform_data = {
607 .x_line = 19,
608 .y_line = 11,
609 .x_size = 800,
610 .y_size = 480,
611 .blen = 0x11,
612 .threshold = 0x28,
613 .voltage = 2800000, /* 2.8V */
614 .orient = MXT_DIAGONAL,
615 .irqflags = IRQF_TRIGGER_FALLING,
616};
617
618static struct i2c_board_info i2c3_devs[] __initdata = {
619 {
620 I2C_BOARD_INFO("qt602240_ts", 0x4a),
621 .platform_data = &qt602240_platform_data,
622 },
623};
624
625static void __init universal_tsp_init(void)
626{
627 int gpio;
628
629 /* TSP_LDO_ON: XMDMADDR_11 */
630 gpio = EXYNOS4_GPE2(3);
631 gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON");
632 gpio_export(gpio, 0);
633
634 /* TSP_INT: XMDMADDR_7 */
635 gpio = EXYNOS4_GPE1(7);
636 gpio_request(gpio, "TSP_INT");
637
638 s5p_register_gpio_interrupt(gpio);
639 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
640 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
641 i2c3_devs[0].irq = gpio_to_irq(gpio);
642}
643
644
645/* GPIO I2C 12 (3 Touchkey) */
646static uint32_t touchkey_keymap[] = {
647 /* MCS_KEY_MAP(value, keycode) */
648 MCS_KEY_MAP(0, KEY_MENU), /* KEY_SEND */
649 MCS_KEY_MAP(1, KEY_BACK), /* KEY_END */
650};
651
652static struct mcs_platform_data touchkey_data = {
653 .keymap = touchkey_keymap,
654 .keymap_size = ARRAY_SIZE(touchkey_keymap),
655 .key_maxval = 2,
656};
657
658/* GPIO I2C 3_TOUCH 2.8V */
659#define I2C_GPIO_BUS_12 12
660static struct i2c_gpio_platform_data i2c_gpio12_data = {
661 .sda_pin = EXYNOS4_GPE4(0), /* XMDMDATA_8 */
662 .scl_pin = EXYNOS4_GPE4(1), /* XMDMDATA_9 */
663};
664
665static struct platform_device i2c_gpio12 = {
666 .name = "i2c-gpio",
667 .id = I2C_GPIO_BUS_12,
668 .dev = {
669 .platform_data = &i2c_gpio12_data,
670 },
671};
672
673static struct i2c_board_info i2c_gpio12_devs[] __initdata = {
674 {
675 I2C_BOARD_INFO("mcs5080_touchkey", 0x20),
676 .platform_data = &touchkey_data,
677 },
678};
679
680static void __init universal_touchkey_init(void)
681{
682 int gpio;
683
684 gpio = EXYNOS4_GPE3(7); /* XMDMDATA_7 */
685 gpio_request(gpio, "3_TOUCH_INT");
686 s5p_register_gpio_interrupt(gpio);
687 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
688 i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
689
690 gpio = EXYNOS4_GPE3(3); /* XMDMDATA_3 */
691 gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "3_TOUCH_EN");
692}
693
694static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = {
695 .frequency = 300 * 1000,
696 .sda_delay = 200,
697};
698
699/* GPIO KEYS */
700static struct gpio_keys_button universal_gpio_keys_tables[] = {
701 {
702 .code = KEY_VOLUMEUP,
703 .gpio = EXYNOS4_GPX2(0), /* XEINT16 */
704 .desc = "gpio-keys: KEY_VOLUMEUP",
705 .type = EV_KEY,
706 .active_low = 1,
707 .debounce_interval = 1,
708 }, {
709 .code = KEY_VOLUMEDOWN,
710 .gpio = EXYNOS4_GPX2(1), /* XEINT17 */
711 .desc = "gpio-keys: KEY_VOLUMEDOWN",
712 .type = EV_KEY,
713 .active_low = 1,
714 .debounce_interval = 1,
715 }, {
716 .code = KEY_CONFIG,
717 .gpio = EXYNOS4_GPX2(2), /* XEINT18 */
718 .desc = "gpio-keys: KEY_CONFIG",
719 .type = EV_KEY,
720 .active_low = 1,
721 .debounce_interval = 1,
722 }, {
723 .code = KEY_CAMERA,
724 .gpio = EXYNOS4_GPX2(3), /* XEINT19 */
725 .desc = "gpio-keys: KEY_CAMERA",
726 .type = EV_KEY,
727 .active_low = 1,
728 .debounce_interval = 1,
729 }, {
730 .code = KEY_OK,
731 .gpio = EXYNOS4_GPX3(5), /* XEINT29 */
732 .desc = "gpio-keys: KEY_OK",
733 .type = EV_KEY,
734 .active_low = 1,
735 .debounce_interval = 1,
736 },
737};
738
739static struct gpio_keys_platform_data universal_gpio_keys_data = {
740 .buttons = universal_gpio_keys_tables,
741 .nbuttons = ARRAY_SIZE(universal_gpio_keys_tables),
742};
743
744static struct platform_device universal_gpio_keys = {
745 .name = "gpio-keys",
746 .dev = {
747 .platform_data = &universal_gpio_keys_data,
748 },
749};
750
751/* eMMC */
752static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
753 .max_width = 8,
754 .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
755 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
756 .cd_type = S3C_SDHCI_CD_PERMANENT,
757};
758
759static struct regulator_consumer_supply mmc0_supplies[] = {
760 REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
761};
762
763static struct regulator_init_data mmc0_fixed_voltage_init_data = {
764 .constraints = {
765 .name = "VMEM_VDD_2.8V",
766 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
767 },
768 .num_consumer_supplies = ARRAY_SIZE(mmc0_supplies),
769 .consumer_supplies = mmc0_supplies,
770};
771
772static struct fixed_voltage_config mmc0_fixed_voltage_config = {
773 .supply_name = "MASSMEMORY_EN",
774 .microvolts = 2800000,
775 .gpio = EXYNOS4_GPE1(3),
776 .enable_high = true,
777 .init_data = &mmc0_fixed_voltage_init_data,
778};
779
780static struct platform_device mmc0_fixed_voltage = {
781 .name = "reg-fixed-voltage",
782 .id = FIXED_REG_ID_MMC0,
783 .dev = {
784 .platform_data = &mmc0_fixed_voltage_config,
785 },
786};
787
788/* SD */
789static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
790 .max_width = 4,
791 .host_caps = MMC_CAP_4_BIT_DATA |
792 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
793 .ext_cd_gpio = EXYNOS4_GPX3(4), /* XEINT_28 */
794 .ext_cd_gpio_invert = 1,
795 .cd_type = S3C_SDHCI_CD_GPIO,
796};
797
798/* WiFi */
799static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
800 .max_width = 4,
801 .host_caps = MMC_CAP_4_BIT_DATA |
802 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
803 .cd_type = S3C_SDHCI_CD_EXTERNAL,
804};
805
806static void __init universal_sdhci_init(void)
807{
808 s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
809 s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
810 s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
811}
812
813/* I2C1 */
814static struct i2c_board_info i2c1_devs[] __initdata = {
815 /* Gyro, To be updated */
816};
817
818#ifdef CONFIG_DRM_EXYNOS
819static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
820 .panel = {
821 .timing = {
822 .left_margin = 16,
823 .right_margin = 16,
824 .upper_margin = 2,
825 .lower_margin = 28,
826 .hsync_len = 2,
827 .vsync_len = 1,
828 .xres = 480,
829 .yres = 800,
830 .refresh = 55,
831 },
832 },
833 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
834 VIDCON0_CLKSEL_LCD,
835 .vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
836 | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
837 .default_win = 3,
838 .bpp = 32,
839};
840#else
841/* Frame Buffer */
842static struct s3c_fb_pd_win universal_fb_win0 = {
843 .max_bpp = 32,
844 .default_bpp = 16,
845 .xres = 480,
846 .yres = 800,
847 .virtual_x = 480,
848 .virtual_y = 2 * 800,
849};
850
851static struct fb_videomode universal_lcd_timing = {
852 .left_margin = 16,
853 .right_margin = 16,
854 .upper_margin = 2,
855 .lower_margin = 28,
856 .hsync_len = 2,
857 .vsync_len = 1,
858 .xres = 480,
859 .yres = 800,
860 .refresh = 55,
861};
862
863static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
864 .win[0] = &universal_fb_win0,
865 .vtiming = &universal_lcd_timing,
866 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
867 VIDCON0_CLKSEL_LCD,
868 .vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
869 | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
870 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
871};
872#endif
873
874static struct regulator_consumer_supply cam_vt_dio_supply =
875 REGULATOR_SUPPLY("vdd_core", "0-003c");
876
877static struct regulator_init_data cam_vt_dio_reg_init_data = {
878 .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
879 .num_consumer_supplies = 1,
880 .consumer_supplies = &cam_vt_dio_supply,
881};
882
883static struct fixed_voltage_config cam_vt_dio_fixed_voltage_cfg = {
884 .supply_name = "CAM_VT_D_IO",
885 .microvolts = 2800000,
886 .gpio = EXYNOS4_GPE2(1), /* CAM_PWR_EN2 */
887 .enable_high = 1,
888 .init_data = &cam_vt_dio_reg_init_data,
889};
890
891static struct platform_device cam_vt_dio_fixed_reg_dev = {
892 .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_VT_DIO,
893 .dev = { .platform_data = &cam_vt_dio_fixed_voltage_cfg },
894};
895
896static struct regulator_consumer_supply cam_i_core_supply =
897 REGULATOR_SUPPLY("core", "0-001f");
898
899static struct regulator_init_data cam_i_core_reg_init_data = {
900 .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
901 .num_consumer_supplies = 1,
902 .consumer_supplies = &cam_i_core_supply,
903};
904
905static struct fixed_voltage_config cam_i_core_fixed_voltage_cfg = {
906 .supply_name = "CAM_I_CORE_1.2V",
907 .microvolts = 1200000,
908 .gpio = EXYNOS4_GPE2(2), /* CAM_8M_CORE_EN */
909 .enable_high = 1,
910 .init_data = &cam_i_core_reg_init_data,
911};
912
913static struct platform_device cam_i_core_fixed_reg_dev = {
914 .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_I_CORE,
915 .dev = { .platform_data = &cam_i_core_fixed_voltage_cfg },
916};
917
918static struct regulator_consumer_supply cam_s_if_supply =
919 REGULATOR_SUPPLY("d_sensor", "0-001f");
920
921static struct regulator_init_data cam_s_if_reg_init_data = {
922 .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
923 .num_consumer_supplies = 1,
924 .consumer_supplies = &cam_s_if_supply,
925};
926
927static struct fixed_voltage_config cam_s_if_fixed_voltage_cfg = {
928 .supply_name = "CAM_S_IF_1.8V",
929 .microvolts = 1800000,
930 .gpio = EXYNOS4_GPE3(0), /* CAM_PWR_EN1 */
931 .enable_high = 1,
932 .init_data = &cam_s_if_reg_init_data,
933};
934
935static struct platform_device cam_s_if_fixed_reg_dev = {
936 .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_S_IF,
937 .dev = { .platform_data = &cam_s_if_fixed_voltage_cfg },
938};
939
940static struct s5p_platform_mipi_csis mipi_csis_platdata = {
941 .clk_rate = 166000000UL,
942 .lanes = 2,
943 .hs_settle = 12,
944};
945
946#define GPIO_CAM_LEVEL_EN(n) EXYNOS4_GPE4(n + 3)
947#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPX1(5) /* XEINT_13 */
948#define GPIO_CAM_MEGA_nRST EXYNOS4_GPE2(5)
949#define GPIO_CAM_VGA_NRST EXYNOS4_GPE4(7)
950#define GPIO_CAM_VGA_NSTBY EXYNOS4_GPE4(6)
951
952static int s5k6aa_set_power(int on)
953{
954 gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
955 return 0;
956}
957
958static struct s5k6aa_platform_data s5k6aa_platdata = {
959 .mclk_frequency = 21600000UL,
960 .gpio_reset = { GPIO_CAM_VGA_NRST, 0 },
961 .gpio_stby = { GPIO_CAM_VGA_NSTBY, 0 },
962 .bus_type = V4L2_MBUS_PARALLEL,
963 .horiz_flip = 1,
964 .set_power = s5k6aa_set_power,
965};
966
967static struct i2c_board_info s5k6aa_board_info = {
968 I2C_BOARD_INFO("S5K6AA", 0x3C),
969 .platform_data = &s5k6aa_platdata,
970};
971
972static int m5mols_set_power(struct device *dev, int on)
973{
974 gpio_set_value(GPIO_CAM_LEVEL_EN(1), !on);
975 gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
976 return 0;
977}
978
979static struct m5mols_platform_data m5mols_platdata = {
980 .gpio_reset = GPIO_CAM_MEGA_nRST,
981 .reset_polarity = 0,
982 .set_power = m5mols_set_power,
983};
984
985static struct i2c_board_info m5mols_board_info = {
986 I2C_BOARD_INFO("M5MOLS", 0x1F),
987 .platform_data = &m5mols_platdata,
988};
989
990static struct fimc_source_info universal_camera_sensors[] = {
991 {
992 .mux_id = 0,
993 .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
994 V4L2_MBUS_VSYNC_ACTIVE_LOW,
995 .fimc_bus_type = FIMC_BUS_TYPE_ITU_601,
996 .board_info = &s5k6aa_board_info,
997 .i2c_bus_num = 0,
998 .clk_frequency = 24000000UL,
999 }, {
1000 .mux_id = 0,
1001 .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
1002 V4L2_MBUS_VSYNC_ACTIVE_LOW,
1003 .fimc_bus_type = FIMC_BUS_TYPE_MIPI_CSI2,
1004 .board_info = &m5mols_board_info,
1005 .i2c_bus_num = 0,
1006 .clk_frequency = 24000000UL,
1007 },
1008};
1009
1010static struct s5p_platform_fimc fimc_md_platdata = {
1011 .source_info = universal_camera_sensors,
1012 .num_clients = ARRAY_SIZE(universal_camera_sensors),
1013};
1014
1015static struct gpio universal_camera_gpios[] = {
1016 { GPIO_CAM_LEVEL_EN(1), GPIOF_OUT_INIT_HIGH, "CAM_LVL_EN1" },
1017 { GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW, "CAM_LVL_EN2" },
1018 { GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" },
1019 { GPIO_CAM_MEGA_nRST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
1020 { GPIO_CAM_VGA_NRST, GPIOF_OUT_INIT_LOW, "CAM_VGA_NRST" },
1021 { GPIO_CAM_VGA_NSTBY, GPIOF_OUT_INIT_LOW, "CAM_VGA_NSTBY" },
1022};
1023
1024/* USB OTG */
1025static struct s3c_hsotg_plat universal_hsotg_pdata;
1026
1027static void __init universal_camera_init(void)
1028{
1029 s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
1030 &s5p_device_mipi_csis0);
1031 s3c_set_platdata(&fimc_md_platdata, sizeof(fimc_md_platdata),
1032 &s5p_device_fimc_md);
1033
1034 if (gpio_request_array(universal_camera_gpios,
1035 ARRAY_SIZE(universal_camera_gpios))) {
1036 pr_err("%s: GPIO request failed\n", __func__);
1037 return;
1038 }
1039
1040 if (!s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xf)))
1041 m5mols_board_info.irq = gpio_to_irq(GPIO_CAM_8M_ISP_INT);
1042 else
1043 pr_err("Failed to configure 8M_ISP_INT GPIO\n");
1044
1045 /* Free GPIOs controlled directly by the sensor drivers. */
1046 gpio_free(GPIO_CAM_MEGA_nRST);
1047 gpio_free(GPIO_CAM_8M_ISP_INT);
1048 gpio_free(GPIO_CAM_VGA_NRST);
1049 gpio_free(GPIO_CAM_VGA_NSTBY);
1050
1051 if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A))
1052 pr_err("Camera port A setup failed\n");
1053}
1054
1055static struct platform_device *universal_devices[] __initdata = {
1056 /* Samsung Platform Devices */
1057 &s5p_device_mipi_csis0,
1058 &s5p_device_fimc0,
1059 &s5p_device_fimc1,
1060 &s5p_device_fimc2,
1061 &s5p_device_fimc3,
1062 &s5p_device_g2d,
1063 &mmc0_fixed_voltage,
1064 &s3c_device_hsmmc0,
1065 &s3c_device_hsmmc2,
1066 &s3c_device_hsmmc3,
1067 &s3c_device_i2c0,
1068 &s3c_device_i2c3,
1069 &s3c_device_i2c5,
1070 &s5p_device_i2c_hdmiphy,
1071 &hdmi_fixed_voltage,
1072 &s5p_device_hdmi,
1073 &s5p_device_sdo,
1074 &s5p_device_mixer,
1075
1076 /* Universal Devices */
1077 &i2c_gpio12,
1078 &universal_gpio_keys,
1079 &s5p_device_onenand,
1080 &s5p_device_fimd0,
1081 &s5p_device_jpeg,
1082 &s3c_device_usb_hsotg,
1083 &s5p_device_mfc,
1084 &s5p_device_mfc_l,
1085 &s5p_device_mfc_r,
1086 &cam_vt_dio_fixed_reg_dev,
1087 &cam_i_core_fixed_reg_dev,
1088 &cam_s_if_fixed_reg_dev,
1089 &s5p_device_fimc_md,
1090};
1091
1092static void __init universal_map_io(void)
1093{
1094 exynos_init_io(NULL, 0);
1095 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
1096 exynos_set_timer_source(BIT(2) | BIT(4));
1097 xxti_f = 0;
1098 xusbxti_f = 24000000;
1099}
1100
1101static void s5p_tv_setup(void)
1102{
1103 /* direct HPD to HDMI chip */
1104 gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
1105 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
1106 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
1107}
1108
1109static void __init universal_reserve(void)
1110{
1111 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
1112}
1113
1114static void __init universal_machine_init(void)
1115{
1116 universal_sdhci_init();
1117 s5p_tv_setup();
1118
1119 s3c_i2c0_set_platdata(&universal_i2c0_platdata);
1120 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
1121
1122 universal_tsp_init();
1123 s3c_i2c3_set_platdata(NULL);
1124 i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
1125
1126 s3c_i2c5_set_platdata(NULL);
1127 s5p_i2c_hdmiphy_set_platdata(NULL);
1128 i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
1129
1130#ifdef CONFIG_DRM_EXYNOS
1131 s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
1132 exynos4_fimd0_gpio_setup_24bpp();
1133#else
1134 s5p_fimd0_set_platdata(&universal_lcd_pdata);
1135#endif
1136
1137 universal_touchkey_init();
1138 i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
1139 ARRAY_SIZE(i2c_gpio12_devs));
1140
1141 s3c_hsotg_set_platdata(&universal_hsotg_pdata);
1142 universal_camera_init();
1143
1144 /* Last */
1145 platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
1146}
1147
1148MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
1149 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
1150 .atag_offset = 0x100,
1151 .smp = smp_ops(exynos_smp_ops),
1152 .init_irq = exynos4_init_irq,
1153 .map_io = universal_map_io,
1154 .init_machine = universal_machine_init,
1155 .init_late = exynos_init_late,
1156 .init_time = exynos_init_time,
1157 .reserve = &universal_reserve,
1158 .restart = exynos4_restart,
1159MACHINE_END
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index e3faaa812016..41c20692a13f 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -30,7 +30,6 @@
30#include <plat/regs-srom.h> 30#include <plat/regs-srom.h>
31 31
32#include <mach/regs-irq.h> 32#include <mach/regs-irq.h>
33#include <mach/regs-gpio.h>
34#include <mach/regs-clock.h> 33#include <mach/regs-clock.h>
35#include <mach/regs-pmu.h> 34#include <mach/regs-pmu.h>
36#include <mach/pm-core.h> 35#include <mach/pm-core.h>
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index 9f1351de52f7..1703593e366c 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -74,17 +74,6 @@ static int exynos_pd_power_off(struct generic_pm_domain *domain)
74 return exynos_pd_power(domain, false); 74 return exynos_pd_power(domain, false);
75} 75}
76 76
77#define EXYNOS_GPD(PD, BASE, NAME) \
78static struct exynos_pm_domain PD = { \
79 .base = (void __iomem *)BASE, \
80 .name = NAME, \
81 .pd = { \
82 .power_off = exynos_pd_power_off, \
83 .power_on = exynos_pd_power_on, \
84 }, \
85}
86
87#ifdef CONFIG_OF
88static void exynos_add_device_to_domain(struct exynos_pm_domain *pd, 77static void exynos_add_device_to_domain(struct exynos_pm_domain *pd,
89 struct device *dev) 78 struct device *dev)
90{ 79{
@@ -157,7 +146,7 @@ static struct notifier_block platform_nb = {
157 .notifier_call = exynos_pm_notifier_call, 146 .notifier_call = exynos_pm_notifier_call,
158}; 147};
159 148
160static __init int exynos_pm_dt_parse_domains(void) 149static __init int exynos4_pm_init_power_domain(void)
161{ 150{
162 struct platform_device *pdev; 151 struct platform_device *pdev;
163 struct device_node *np; 152 struct device_node *np;
@@ -193,94 +182,6 @@ static __init int exynos_pm_dt_parse_domains(void)
193 182
194 return 0; 183 return 0;
195} 184}
196#else
197static __init int exynos_pm_dt_parse_domains(void)
198{
199 return 0;
200}
201#endif /* CONFIG_OF */
202
203static __init __maybe_unused void exynos_pm_add_dev_to_genpd(struct platform_device *pdev,
204 struct exynos_pm_domain *pd)
205{
206 if (pdev->dev.bus) {
207 if (!pm_genpd_add_device(&pd->pd, &pdev->dev))
208 pm_genpd_dev_need_restore(&pdev->dev, true);
209 else
210 pr_info("%s: error in adding %s device to %s power"
211 "domain\n", __func__, dev_name(&pdev->dev),
212 pd->name);
213 }
214}
215
216EXYNOS_GPD(exynos4_pd_mfc, S5P_PMU_MFC_CONF, "pd-mfc");
217EXYNOS_GPD(exynos4_pd_g3d, S5P_PMU_G3D_CONF, "pd-g3d");
218EXYNOS_GPD(exynos4_pd_lcd0, S5P_PMU_LCD0_CONF, "pd-lcd0");
219EXYNOS_GPD(exynos4_pd_lcd1, S5P_PMU_LCD1_CONF, "pd-lcd1");
220EXYNOS_GPD(exynos4_pd_tv, S5P_PMU_TV_CONF, "pd-tv");
221EXYNOS_GPD(exynos4_pd_cam, S5P_PMU_CAM_CONF, "pd-cam");
222EXYNOS_GPD(exynos4_pd_gps, S5P_PMU_GPS_CONF, "pd-gps");
223
224static struct exynos_pm_domain *exynos4_pm_domains[] = {
225 &exynos4_pd_mfc,
226 &exynos4_pd_g3d,
227 &exynos4_pd_lcd0,
228 &exynos4_pd_lcd1,
229 &exynos4_pd_tv,
230 &exynos4_pd_cam,
231 &exynos4_pd_gps,
232};
233
234static __init int exynos4_pm_init_power_domain(void)
235{
236 int idx;
237
238 if (of_have_populated_dt())
239 return exynos_pm_dt_parse_domains();
240
241 for (idx = 0; idx < ARRAY_SIZE(exynos4_pm_domains); idx++) {
242 struct exynos_pm_domain *pd = exynos4_pm_domains[idx];
243 int on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN;
244
245 pm_genpd_init(&pd->pd, NULL, !on);
246 }
247
248#ifdef CONFIG_S5P_DEV_FIMD0
249 exynos_pm_add_dev_to_genpd(&s5p_device_fimd0, &exynos4_pd_lcd0);
250#endif
251#ifdef CONFIG_S5P_DEV_TV
252 exynos_pm_add_dev_to_genpd(&s5p_device_hdmi, &exynos4_pd_tv);
253 exynos_pm_add_dev_to_genpd(&s5p_device_mixer, &exynos4_pd_tv);
254#endif
255#ifdef CONFIG_S5P_DEV_MFC
256 exynos_pm_add_dev_to_genpd(&s5p_device_mfc, &exynos4_pd_mfc);
257#endif
258#ifdef CONFIG_S5P_DEV_FIMC0
259 exynos_pm_add_dev_to_genpd(&s5p_device_fimc0, &exynos4_pd_cam);
260#endif
261#ifdef CONFIG_S5P_DEV_FIMC1
262 exynos_pm_add_dev_to_genpd(&s5p_device_fimc1, &exynos4_pd_cam);
263#endif
264#ifdef CONFIG_S5P_DEV_FIMC2
265 exynos_pm_add_dev_to_genpd(&s5p_device_fimc2, &exynos4_pd_cam);
266#endif
267#ifdef CONFIG_S5P_DEV_FIMC3
268 exynos_pm_add_dev_to_genpd(&s5p_device_fimc3, &exynos4_pd_cam);
269#endif
270#ifdef CONFIG_S5P_DEV_CSIS0
271 exynos_pm_add_dev_to_genpd(&s5p_device_mipi_csis0, &exynos4_pd_cam);
272#endif
273#ifdef CONFIG_S5P_DEV_CSIS1
274 exynos_pm_add_dev_to_genpd(&s5p_device_mipi_csis1, &exynos4_pd_cam);
275#endif
276#ifdef CONFIG_S5P_DEV_G2D
277 exynos_pm_add_dev_to_genpd(&s5p_device_g2d, &exynos4_pd_lcd0);
278#endif
279#ifdef CONFIG_S5P_DEV_JPEG
280 exynos_pm_add_dev_to_genpd(&s5p_device_jpeg, &exynos4_pd_cam);
281#endif
282 return 0;
283}
284arch_initcall(exynos4_pm_init_power_domain); 185arch_initcall(exynos4_pm_init_power_domain);
285 186
286int __init exynos_pm_late_initcall(void) 187int __init exynos_pm_late_initcall(void)
diff --git a/arch/arm/mach-exynos/setup-fimc.c b/arch/arm/mach-exynos/setup-fimc.c
deleted file mode 100644
index 6a45078d9d12..000000000000
--- a/arch/arm/mach-exynos/setup-fimc.c
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
3 *
4 * Exynos4 camera interface GPIO configuration.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <plat/gpio-cfg.h>
13#include <plat/camport.h>
14
15int exynos4_fimc_setup_gpio(enum s5p_camport_id id)
16{
17 u32 gpio8, gpio5;
18 u32 sfn;
19 int ret;
20
21 switch (id) {
22 case S5P_CAMPORT_A:
23 gpio8 = EXYNOS4_GPJ0(0); /* PCLK, VSYNC, HREF, DATA[0:4] */
24 gpio5 = EXYNOS4_GPJ1(0); /* DATA[5:7], CLKOUT, FIELD */
25 sfn = S3C_GPIO_SFN(2);
26 break;
27
28 case S5P_CAMPORT_B:
29 gpio8 = EXYNOS4_GPE0(0); /* DATA[0:7] */
30 gpio5 = EXYNOS4_GPE1(0); /* PCLK, VSYNC, HREF, CLKOUT, FIELD */
31 sfn = S3C_GPIO_SFN(3);
32 break;
33
34 default:
35 WARN(1, "Wrong camport id: %d\n", id);
36 return -EINVAL;
37 }
38
39 ret = s3c_gpio_cfgall_range(gpio8, 8, sfn, S3C_GPIO_PULL_UP);
40 if (ret)
41 return ret;
42
43 return s3c_gpio_cfgall_range(gpio5, 5, sfn, S3C_GPIO_PULL_UP);
44}
diff --git a/arch/arm/mach-exynos/setup-fimd0.c b/arch/arm/mach-exynos/setup-fimd0.c
deleted file mode 100644
index 5665bb4e980b..000000000000
--- a/arch/arm/mach-exynos/setup-fimd0.c
+++ /dev/null
@@ -1,43 +0,0 @@
1/* linux/arch/arm/mach-exynos4/setup-fimd0.c
2 *
3 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Base Exynos4 FIMD 0 configuration
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/fb.h>
14#include <linux/gpio.h>
15
16#include <video/samsung_fimd.h>
17#include <plat/gpio-cfg.h>
18
19#include <mach/map.h>
20
21void exynos4_fimd0_gpio_setup_24bpp(void)
22{
23 unsigned int reg;
24
25 s3c_gpio_cfgrange_nopull(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2));
26 s3c_gpio_cfgrange_nopull(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2));
27 s3c_gpio_cfgrange_nopull(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2));
28 s3c_gpio_cfgrange_nopull(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2));
29
30 /*
31 * Set DISPLAY_CONTROL register for Display path selection.
32 *
33 * DISPLAY_CONTROL[1:0]
34 * ---------------------
35 * 00 | MIE
36 * 01 | MDINE
37 * 10 | FIMD : selected
38 * 11 | FIMD
39 */
40 reg = __raw_readl(S3C_VA_SYS + 0x0210);
41 reg |= (1 << 1);
42 __raw_writel(reg, S3C_VA_SYS + 0x0210);
43}
diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c
deleted file mode 100644
index e2d9dfbf102c..000000000000
--- a/arch/arm/mach-exynos/setup-i2c0.c
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * Copyright (c) 2009-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
4 *
5 * I2C0 GPIO configuration.
6 *
7 * Based on plat-s3c64xx/setup-i2c0.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14struct platform_device; /* don't need the contents */
15
16#include <linux/gpio.h>
17#include <linux/platform_data/i2c-s3c2410.h>
18#include <plat/gpio-cfg.h>
19#include <plat/cpu.h>
20
21void s3c_i2c0_cfg_gpio(struct platform_device *dev)
22{
23 if (soc_is_exynos5250() || soc_is_exynos5440())
24 /* will be implemented with gpio function */
25 return;
26
27 s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
28 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
29}
diff --git a/arch/arm/mach-exynos/setup-i2c1.c b/arch/arm/mach-exynos/setup-i2c1.c
deleted file mode 100644
index 8d2279cc85dc..000000000000
--- a/arch/arm/mach-exynos/setup-i2c1.c
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * linux/arch/arm/mach-exynos4/setup-i2c1.c
3 *
4 * Copyright (C) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C1 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <linux/platform_data/i2c-s3c2410.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c1_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(EXYNOS4_GPD1(2), 2,
22 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-exynos/setup-i2c2.c b/arch/arm/mach-exynos/setup-i2c2.c
deleted file mode 100644
index 0ed62fc42a77..000000000000
--- a/arch/arm/mach-exynos/setup-i2c2.c
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * linux/arch/arm/mach-exynos4/setup-i2c2.c
3 *
4 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C2 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <linux/platform_data/i2c-s3c2410.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c2_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(EXYNOS4_GPA0(6), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-exynos/setup-i2c3.c b/arch/arm/mach-exynos/setup-i2c3.c
deleted file mode 100644
index 7787fd26076b..000000000000
--- a/arch/arm/mach-exynos/setup-i2c3.c
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * linux/arch/arm/mach-exynos4/setup-i2c3.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C3 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <linux/platform_data/i2c-s3c2410.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c3_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(EXYNOS4_GPA1(2), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-exynos/setup-i2c4.c b/arch/arm/mach-exynos/setup-i2c4.c
deleted file mode 100644
index edc847f89826..000000000000
--- a/arch/arm/mach-exynos/setup-i2c4.c
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * linux/arch/arm/mach-exynos4/setup-i2c4.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C4 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <linux/platform_data/i2c-s3c2410.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c4_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-exynos/setup-i2c5.c b/arch/arm/mach-exynos/setup-i2c5.c
deleted file mode 100644
index d88af7f75954..000000000000
--- a/arch/arm/mach-exynos/setup-i2c5.c
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * linux/arch/arm/mach-exynos4/setup-i2c5.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C5 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <linux/platform_data/i2c-s3c2410.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c5_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-exynos/setup-i2c6.c b/arch/arm/mach-exynos/setup-i2c6.c
deleted file mode 100644
index c590286c9d3a..000000000000
--- a/arch/arm/mach-exynos/setup-i2c6.c
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * linux/arch/arm/mach-exynos4/setup-i2c6.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C6 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <linux/platform_data/i2c-s3c2410.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c6_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
22 S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-exynos/setup-i2c7.c b/arch/arm/mach-exynos/setup-i2c7.c
deleted file mode 100644
index 1bba75568a5f..000000000000
--- a/arch/arm/mach-exynos/setup-i2c7.c
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * linux/arch/arm/mach-exynos4/setup-i2c7.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C7 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <linux/platform_data/i2c-s3c2410.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c7_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(EXYNOS4_GPD0(2), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-exynos/setup-keypad.c b/arch/arm/mach-exynos/setup-keypad.c
deleted file mode 100644
index 7862bfb5933d..000000000000
--- a/arch/arm/mach-exynos/setup-keypad.c
+++ /dev/null
@@ -1,36 +0,0 @@
1/* linux/arch/arm/mach-exynos4/setup-keypad.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * GPIO configuration for Exynos4 KeyPad device
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/gpio.h>
14#include <plat/gpio-cfg.h>
15
16void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
17{
18 /* Keypads can be of various combinations, Just making sure */
19
20 if (rows > 8) {
21 /* Set all the necessary GPX2 pins: KP_ROW[0~7] */
22 s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3),
23 S3C_GPIO_PULL_UP);
24
25 /* Set all the necessary GPX3 pins: KP_ROW[8~] */
26 s3c_gpio_cfgall_range(EXYNOS4_GPX3(0), (rows - 8),
27 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
28 } else {
29 /* Set all the necessary GPX2 pins: KP_ROW[x] */
30 s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), rows, S3C_GPIO_SFN(3),
31 S3C_GPIO_PULL_UP);
32 }
33
34 /* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */
35 s3c_gpio_cfgrange_nopull(EXYNOS4_GPX1(0), cols, S3C_GPIO_SFN(3));
36}
diff --git a/arch/arm/mach-exynos/setup-sdhci-gpio.c b/arch/arm/mach-exynos/setup-sdhci-gpio.c
deleted file mode 100644
index d5b98c866738..000000000000
--- a/arch/arm/mach-exynos/setup-sdhci-gpio.c
+++ /dev/null
@@ -1,152 +0,0 @@
1/* linux/arch/arm/mach-exynos4/setup-sdhci-gpio.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/gpio.h>
19#include <linux/mmc/host.h>
20#include <linux/mmc/card.h>
21
22#include <mach/gpio.h>
23#include <plat/gpio-cfg.h>
24#include <plat/sdhci.h>
25
26void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
27{
28 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
29 unsigned int gpio;
30
31 /* Set all the necessary GPK0[0:1] pins to special-function 2 */
32 for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2); gpio++) {
33 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
34 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
35 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
36 }
37
38 switch (width) {
39 case 8:
40 for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
41 /* Data pin GPK1[3:6] to special-function 3 */
42 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
43 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
44 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
45 }
46 case 4:
47 for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) {
48 /* Data pin GPK0[3:6] to special-function 2 */
49 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
50 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
51 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
52 }
53 default:
54 break;
55 }
56
57 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
58 s3c_gpio_cfgpin(EXYNOS4_GPK0(2), S3C_GPIO_SFN(2));
59 s3c_gpio_setpull(EXYNOS4_GPK0(2), S3C_GPIO_PULL_UP);
60 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
61 }
62}
63
64void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
65{
66 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
67 unsigned int gpio;
68
69 /* Set all the necessary GPK1[0:1] pins to special-function 2 */
70 for (gpio = EXYNOS4_GPK1(0); gpio < EXYNOS4_GPK1(2); gpio++) {
71 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
72 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
73 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
74 }
75
76 for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
77 /* Data pin GPK1[3:6] to special-function 2 */
78 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
79 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
80 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
81 }
82
83 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
84 s3c_gpio_cfgpin(EXYNOS4_GPK1(2), S3C_GPIO_SFN(2));
85 s3c_gpio_setpull(EXYNOS4_GPK1(2), S3C_GPIO_PULL_UP);
86 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
87 }
88}
89
90void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
91{
92 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
93 unsigned int gpio;
94
95 /* Set all the necessary GPK2[0:1] pins to special-function 2 */
96 for (gpio = EXYNOS4_GPK2(0); gpio < EXYNOS4_GPK2(2); gpio++) {
97 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
98 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
99 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
100 }
101
102 switch (width) {
103 case 8:
104 for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
105 /* Data pin GPK3[3:6] to special-function 3 */
106 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
107 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
108 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
109 }
110 case 4:
111 for (gpio = EXYNOS4_GPK2(3); gpio <= EXYNOS4_GPK2(6); gpio++) {
112 /* Data pin GPK2[3:6] to special-function 2 */
113 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
114 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
115 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
116 }
117 default:
118 break;
119 }
120
121 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
122 s3c_gpio_cfgpin(EXYNOS4_GPK2(2), S3C_GPIO_SFN(2));
123 s3c_gpio_setpull(EXYNOS4_GPK2(2), S3C_GPIO_PULL_UP);
124 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
125 }
126}
127
128void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
129{
130 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
131 unsigned int gpio;
132
133 /* Set all the necessary GPK3[0:1] pins to special-function 2 */
134 for (gpio = EXYNOS4_GPK3(0); gpio < EXYNOS4_GPK3(2); gpio++) {
135 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
136 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
137 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
138 }
139
140 for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
141 /* Data pin GPK3[3:6] to special-function 2 */
142 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
143 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
144 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
145 }
146
147 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
148 s3c_gpio_cfgpin(EXYNOS4_GPK3(2), S3C_GPIO_SFN(2));
149 s3c_gpio_setpull(EXYNOS4_GPK3(2), S3C_GPIO_PULL_UP);
150 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
151 }
152}
diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c
deleted file mode 100644
index 4999829d1c6e..000000000000
--- a/arch/arm/mach-exynos/setup-spi.c
+++ /dev/null
@@ -1,45 +0,0 @@
1/* linux/arch/arm/mach-exynos4/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <plat/gpio-cfg.h>
13
14#ifdef CONFIG_S3C64XX_DEV_SPI0
15int s3c64xx_spi0_cfg_gpio(void)
16{
17 s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));
18 s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP);
19 s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
20 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
21 return 0;
22}
23#endif
24
25#ifdef CONFIG_S3C64XX_DEV_SPI1
26int s3c64xx_spi1_cfg_gpio(void)
27{
28 s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));
29 s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP);
30 s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
31 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
32 return 0;
33}
34#endif
35
36#ifdef CONFIG_S3C64XX_DEV_SPI2
37int s3c64xx_spi2_cfg_gpio(void)
38{
39 s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));
40 s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP);
41 s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
42 S3C_GPIO_SFN(5), S3C_GPIO_PULL_UP);
43 return 0;
44}
45#endif
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
deleted file mode 100644
index 6af40662a449..000000000000
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ /dev/null
@@ -1,223 +0,0 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 */
11
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/platform_device.h>
17#include <mach/regs-pmu.h>
18#include <mach/regs-usb-phy.h>
19#include <plat/cpu.h>
20#include <plat/usb-phy.h>
21
22static atomic_t host_usage;
23
24static int exynos4_usb_host_phy_is_on(void)
25{
26 return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
27}
28
29static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
30{
31 struct clk *xusbxti_clk;
32 u32 phyclk;
33
34 xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
35 if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
36 if (soc_is_exynos4210()) {
37 /* set clock frequency for PLL */
38 phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK;
39
40 switch (clk_get_rate(xusbxti_clk)) {
41 case 12 * MHZ:
42 phyclk |= EXYNOS4210_CLKSEL_12M;
43 break;
44 case 48 * MHZ:
45 phyclk |= EXYNOS4210_CLKSEL_48M;
46 break;
47 default:
48 case 24 * MHZ:
49 phyclk |= EXYNOS4210_CLKSEL_24M;
50 break;
51 }
52 writel(phyclk, EXYNOS4_PHYCLK);
53 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
54 /* set clock frequency for PLL */
55 phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK;
56
57 switch (clk_get_rate(xusbxti_clk)) {
58 case 9600 * KHZ:
59 phyclk |= EXYNOS4X12_CLKSEL_9600K;
60 break;
61 case 10 * MHZ:
62 phyclk |= EXYNOS4X12_CLKSEL_10M;
63 break;
64 case 12 * MHZ:
65 phyclk |= EXYNOS4X12_CLKSEL_12M;
66 break;
67 case 19200 * KHZ:
68 phyclk |= EXYNOS4X12_CLKSEL_19200K;
69 break;
70 case 20 * MHZ:
71 phyclk |= EXYNOS4X12_CLKSEL_20M;
72 break;
73 default:
74 case 24 * MHZ:
75 /* default reference clock */
76 phyclk |= EXYNOS4X12_CLKSEL_24M;
77 break;
78 }
79 writel(phyclk, EXYNOS4_PHYCLK);
80 }
81 clk_put(xusbxti_clk);
82 }
83}
84
85static int exynos4210_usb_phy0_init(struct platform_device *pdev)
86{
87 u32 rstcon;
88
89 writel(readl(S5P_USBDEVICE_PHY_CONTROL) | S5P_USBDEVICE_PHY_ENABLE,
90 S5P_USBDEVICE_PHY_CONTROL);
91
92 exynos4210_usb_phy_clkset(pdev);
93
94 /* set to normal PHY0 */
95 writel((readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK), EXYNOS4_PHYPWR);
96
97 /* reset PHY0 and Link */
98 rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
99 writel(rstcon, EXYNOS4_RSTCON);
100 udelay(10);
101
102 rstcon &= ~PHY0_SWRST_MASK;
103 writel(rstcon, EXYNOS4_RSTCON);
104
105 return 0;
106}
107
108static int exynos4210_usb_phy0_exit(struct platform_device *pdev)
109{
110 writel((readl(EXYNOS4_PHYPWR) | PHY0_ANALOG_POWERDOWN |
111 PHY0_OTG_DISABLE), EXYNOS4_PHYPWR);
112
113 writel(readl(S5P_USBDEVICE_PHY_CONTROL) & ~S5P_USBDEVICE_PHY_ENABLE,
114 S5P_USBDEVICE_PHY_CONTROL);
115
116 return 0;
117}
118
119static int exynos4210_usb_phy1_init(struct platform_device *pdev)
120{
121 struct clk *otg_clk;
122 u32 rstcon;
123 int err;
124
125 atomic_inc(&host_usage);
126
127 otg_clk = clk_get(&pdev->dev, "otg");
128 if (IS_ERR(otg_clk)) {
129 dev_err(&pdev->dev, "Failed to get otg clock\n");
130 return PTR_ERR(otg_clk);
131 }
132
133 err = clk_enable(otg_clk);
134 if (err) {
135 clk_put(otg_clk);
136 return err;
137 }
138
139 if (exynos4_usb_host_phy_is_on())
140 return 0;
141
142 writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE,
143 S5P_USBHOST_PHY_CONTROL);
144
145 exynos4210_usb_phy_clkset(pdev);
146
147 /* floating prevention logic: disable */
148 writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
149
150 /* set to normal HSIC 0 and 1 of PHY1 */
151 writel((readl(EXYNOS4_PHYPWR) & ~PHY1_HSIC_NORMAL_MASK),
152 EXYNOS4_PHYPWR);
153
154 /* set to normal standard USB of PHY1 */
155 writel((readl(EXYNOS4_PHYPWR) & ~PHY1_STD_NORMAL_MASK), EXYNOS4_PHYPWR);
156
157 /* reset all ports of both PHY and Link */
158 rstcon = readl(EXYNOS4_RSTCON) | HOST_LINK_PORT_SWRST_MASK |
159 PHY1_SWRST_MASK;
160 writel(rstcon, EXYNOS4_RSTCON);
161 udelay(10);
162
163 rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK);
164 writel(rstcon, EXYNOS4_RSTCON);
165 udelay(80);
166
167 clk_disable(otg_clk);
168 clk_put(otg_clk);
169
170 return 0;
171}
172
173static int exynos4210_usb_phy1_exit(struct platform_device *pdev)
174{
175 struct clk *otg_clk;
176 int err;
177
178 if (atomic_dec_return(&host_usage) > 0)
179 return 0;
180
181 otg_clk = clk_get(&pdev->dev, "otg");
182 if (IS_ERR(otg_clk)) {
183 dev_err(&pdev->dev, "Failed to get otg clock\n");
184 return PTR_ERR(otg_clk);
185 }
186
187 err = clk_enable(otg_clk);
188 if (err) {
189 clk_put(otg_clk);
190 return err;
191 }
192
193 writel((readl(EXYNOS4_PHYPWR) | PHY1_STD_ANALOG_POWERDOWN),
194 EXYNOS4_PHYPWR);
195
196 writel(readl(S5P_USBHOST_PHY_CONTROL) & ~S5P_USBHOST_PHY_ENABLE,
197 S5P_USBHOST_PHY_CONTROL);
198
199 clk_disable(otg_clk);
200 clk_put(otg_clk);
201
202 return 0;
203}
204
205int s5p_usb_phy_init(struct platform_device *pdev, int type)
206{
207 if (type == USB_PHY_TYPE_DEVICE)
208 return exynos4210_usb_phy0_init(pdev);
209 else if (type == USB_PHY_TYPE_HOST)
210 return exynos4210_usb_phy1_init(pdev);
211
212 return -EINVAL;
213}
214
215int s5p_usb_phy_exit(struct platform_device *pdev, int type)
216{
217 if (type == USB_PHY_TYPE_DEVICE)
218 return exynos4210_usb_phy0_exit(pdev);
219 else if (type == USB_PHY_TYPE_HOST)
220 return exynos4210_usb_phy1_exit(pdev);
221
222 return -EINVAL;
223}
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index f8ed2de0a678..ca27cc9ac4bf 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -6,7 +6,7 @@
6 6
7config PLAT_SAMSUNG 7config PLAT_SAMSUNG
8 bool 8 bool
9 depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P 9 depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P || ARCH_EXYNOS
10 default y 10 default y
11 select GENERIC_IRQ_CHIP 11 select GENERIC_IRQ_CHIP
12 select NO_IOPORT 12 select NO_IOPORT
@@ -15,12 +15,10 @@ config PLAT_SAMSUNG
15 15
16config PLAT_S5P 16config PLAT_S5P
17 bool 17 bool
18 depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS) 18 depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
19 default y 19 default y
20 select ARCH_REQUIRE_GPIOLIB 20 select ARCH_REQUIRE_GPIOLIB
21 select ARM_GIC if ARCH_EXYNOS 21 select ARM_VIC
22 select ARM_VIC if !ARCH_EXYNOS
23 select GIC_NON_BANKED if ARCH_EXYNOS4
24 select NO_IOPORT 22 select NO_IOPORT
25 select PLAT_SAMSUNG 23 select PLAT_SAMSUNG
26 select S3C_GPIO_TRACK 24 select S3C_GPIO_TRACK
@@ -60,6 +58,20 @@ config S3C_LOWLEVEL_UART_PORT
60 this configuration should be between zero and two. The port 58 this configuration should be between zero and two. The port
61 must have been initialised by the boot-loader before use. 59 must have been initialised by the boot-loader before use.
62 60
61config SAMSUNG_ATAGS
62 def_bool n
63 depends on !ARCH_MULTIPLATFORM
64 depends on ATAGS
65 help
66 This option enables ATAGS based boot support code for
67 Samsung platforms, including static platform devices, legacy
68 clock, timer and interrupt initialization, etc.
69
70 Platforms that support only DT based boot need not to select
71 this option.
72
73if SAMSUNG_ATAGS
74
63# timer options 75# timer options
64 76
65config SAMSUNG_HRT 77config SAMSUNG_HRT
@@ -367,11 +379,6 @@ config S5P_DEV_JPEG
367 help 379 help
368 Compile in platform device definitions for JPEG codec 380 Compile in platform device definitions for JPEG codec
369 381
370config S5P_DEV_MFC
371 bool
372 help
373 Compile in setup memory (init) code for MFC
374
375config S5P_DEV_ONENAND 382config S5P_DEV_ONENAND
376 bool 383 bool
377 help 384 help
@@ -412,6 +419,21 @@ config S3C_DMA
412 help 419 help
413 Internal configuration for S3C DMA core 420 Internal configuration for S3C DMA core
414 421
422config S5P_IRQ_PM
423 bool
424 default y if S5P_PM
425 help
426 Legacy IRQ power management for S5P platforms
427
428config SAMSUNG_PM_GPIO
429 bool
430 default y if GPIO_SAMSUNG && PM
431 help
432 Include legacy GPIO power management code for platforms not using
433 pinctrl-samsung driver.
434
435endif
436
415config SAMSUNG_DMADEV 437config SAMSUNG_DMADEV
416 bool 438 bool
417 select ARM_AMBA 439 select ARM_AMBA
@@ -421,6 +443,11 @@ config SAMSUNG_DMADEV
421 help 443 help
422 Use DMA device engine for PL330 DMAC. 444 Use DMA device engine for PL330 DMAC.
423 445
446config S5P_DEV_MFC
447 bool
448 help
449 Compile in setup memory (init) code for MFC
450
424comment "Power management" 451comment "Power management"
425 452
426config SAMSUNG_PM_DEBUG 453config SAMSUNG_PM_DEBUG
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index a23c460299a1..6348ae2e3b46 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -31,10 +31,10 @@ obj-$(CONFIG_S3C_ADC) += adc.o
31 31
32# devices 32# devices
33 33
34obj-y += platformdata.o 34obj-$(CONFIG_SAMSUNG_ATAGS) += platformdata.o
35 35
36obj-y += devs.o 36obj-$(CONFIG_SAMSUNG_ATAGS) += devs.o
37obj-y += dev-uart.o 37obj-$(CONFIG_SAMSUNG_ATAGS) += dev-uart.o
38obj-$(CONFIG_S5P_DEV_MFC) += s5p-dev-mfc.o 38obj-$(CONFIG_S5P_DEV_MFC) += s5p-dev-mfc.o
39obj-$(CONFIG_S5P_DEV_UART) += s5p-dev-uart.o 39obj-$(CONFIG_S5P_DEV_UART) += s5p-dev-uart.o
40 40
@@ -52,10 +52,11 @@ obj-$(CONFIG_SAMSUNG_DMADEV) += dma-ops.o
52# PM support 52# PM support
53 53
54obj-$(CONFIG_PM) += pm.o 54obj-$(CONFIG_PM) += pm.o
55obj-$(CONFIG_PM) += pm-gpio.o 55obj-$(CONFIG_SAMSUNG_PM_GPIO) += pm-gpio.o
56obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o 56obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o
57 57
58obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o 58obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o
59 59
60obj-$(CONFIG_S5P_PM) += s5p-pm.o s5p-irq-pm.o 60obj-$(CONFIG_S5P_PM) += s5p-pm.o
61obj-$(CONFIG_S5P_IRQ_PM) += s5p-irq-pm.o
61obj-$(CONFIG_S5P_SLEEP) += s5p-sleep.o 62obj-$(CONFIG_S5P_SLEEP) += s5p-sleep.o
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index f6fcadeee969..5d47ca35cabd 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -166,6 +166,7 @@ extern void s3c_pm_check_store(void);
166 */ 166 */
167extern void s3c_pm_configure_extint(void); 167extern void s3c_pm_configure_extint(void);
168 168
169#ifdef CONFIG_GPIO_SAMSUNG
169/** 170/**
170 * samsung_pm_restore_gpios() - restore the state of the gpios after sleep. 171 * samsung_pm_restore_gpios() - restore the state of the gpios after sleep.
171 * 172 *
@@ -181,6 +182,10 @@ extern void samsung_pm_restore_gpios(void);
181 * Save the GPIO states for resotration on resume. See samsung_pm_restore_gpios(). 182 * Save the GPIO states for resotration on resume. See samsung_pm_restore_gpios().
182 */ 183 */
183extern void samsung_pm_save_gpios(void); 184extern void samsung_pm_save_gpios(void);
185#else
186static inline void samsung_pm_restore_gpios(void) {}
187static inline void samsung_pm_save_gpios(void) {}
188#endif
184 189
185extern void s3c_pm_save_core(void); 190extern void s3c_pm_save_core(void);
186extern void s3c_pm_restore_core(void); 191extern void s3c_pm_restore_core(void);
diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c
index 79d10fca9090..3e5c4619caa5 100644
--- a/arch/arm/plat-samsung/init.c
+++ b/arch/arm/plat-samsung/init.c
@@ -87,7 +87,7 @@ void __init s3c24xx_init_clocks(int xtal)
87} 87}
88 88
89/* uart management */ 89/* uart management */
90 90#if IS_ENABLED(CONFIG_SAMSUNG_ATAGS)
91static int nr_uarts __initdata = 0; 91static int nr_uarts __initdata = 0;
92 92
93static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS]; 93static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS];
@@ -134,11 +134,12 @@ void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
134 if (cpu == NULL) 134 if (cpu == NULL)
135 return; 135 return;
136 136
137 if (cpu->init_uarts == NULL) { 137 if (cpu->init_uarts == NULL && IS_ENABLED(CONFIG_SAMSUNG_ATAGS)) {
138 printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n"); 138 printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
139 } else 139 } else
140 (cpu->init_uarts)(cfg, no); 140 (cpu->init_uarts)(cfg, no);
141} 141}
142#endif
142 143
143static int __init s3c_arch_init(void) 144static int __init s3c_arch_init(void)
144{ 145{
@@ -152,8 +153,9 @@ static int __init s3c_arch_init(void)
152 ret = (cpu->init)(); 153 ret = (cpu->init)();
153 if (ret != 0) 154 if (ret != 0)
154 return ret; 155 return ret;
155 156#if IS_ENABLED(CONFIG_SAMSUNG_ATAGS)
156 ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts); 157 ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
158#endif
157 return ret; 159 return ret;
158} 160}
159 161
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
index c2ff92c30bdf..a8de3cfe2ee1 100644
--- a/arch/arm/plat-samsung/pm-gpio.c
+++ b/arch/arm/plat-samsung/pm-gpio.c
@@ -192,7 +192,8 @@ struct samsung_gpio_pm samsung_gpio_pm_2bit = {
192 .resume = samsung_gpio_pm_2bit_resume, 192 .resume = samsung_gpio_pm_2bit_resume,
193}; 193};
194 194
195#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P) 195#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P) \
196 || defined(CONFIG_ARCH_EXYNOS)
196static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip) 197static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip)
197{ 198{
198 chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); 199 chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
@@ -302,7 +303,7 @@ struct samsung_gpio_pm samsung_gpio_pm_4bit = {
302 .save = samsung_gpio_pm_4bit_save, 303 .save = samsung_gpio_pm_4bit_save,
303 .resume = samsung_gpio_pm_4bit_resume, 304 .resume = samsung_gpio_pm_4bit_resume,
304}; 305};
305#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */ 306#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P || CONFIG_ARCH_EXYNOS */
306 307
307/** 308/**
308 * samsung_pm_save_gpio() - save gpio chip data for suspend 309 * samsung_pm_save_gpio() - save gpio chip data for suspend
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index bd7124c87fea..ea3613642451 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -22,13 +22,17 @@
22 22
23#include <asm/cacheflush.h> 23#include <asm/cacheflush.h>
24#include <asm/suspend.h> 24#include <asm/suspend.h>
25#include <mach/hardware.h>
26#include <mach/map.h>
27 25
28#include <plat/regs-serial.h> 26#include <plat/regs-serial.h>
27
28#ifdef CONFIG_SAMSUNG_ATAGS
29#include <mach/hardware.h>
30#include <mach/map.h>
29#include <mach/regs-clock.h> 31#include <mach/regs-clock.h>
30#include <mach/regs-irq.h> 32#include <mach/regs-irq.h>
31#include <mach/irqs.h> 33#include <mach/irqs.h>
34#endif
35
32#include <asm/irq.h> 36#include <asm/irq.h>
33 37
34#include <plat/pm.h> 38#include <plat/pm.h>
diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c
index a93fb6fb6606..ad51f85fbd01 100644
--- a/arch/arm/plat-samsung/s5p-dev-mfc.c
+++ b/arch/arm/plat-samsung/s5p-dev-mfc.c
@@ -17,10 +17,12 @@
17#include <linux/of_fdt.h> 17#include <linux/of_fdt.h>
18#include <linux/of.h> 18#include <linux/of.h>
19 19
20#include <plat/mfc.h>
21
22#ifdef CONFIG_SAMSUNG_ATAGS
20#include <mach/map.h> 23#include <mach/map.h>
21#include <mach/irqs.h> 24#include <mach/irqs.h>
22#include <plat/devs.h> 25#include <plat/devs.h>
23#include <plat/mfc.h>
24 26
25static struct resource s5p_mfc_resource[] = { 27static struct resource s5p_mfc_resource[] = {
26 [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K), 28 [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
@@ -61,6 +63,10 @@ struct platform_device s5p_device_mfc_r = {
61 .coherent_dma_mask = DMA_BIT_MASK(32), 63 .coherent_dma_mask = DMA_BIT_MASK(32),
62 }, 64 },
63}; 65};
66#else
67static struct platform_device s5p_device_mfc_l;
68static struct platform_device s5p_device_mfc_r;
69#endif
64 70
65struct s5p_mfc_reserved_mem { 71struct s5p_mfc_reserved_mem {
66 phys_addr_t base; 72 phys_addr_t base;
@@ -70,6 +76,7 @@ struct s5p_mfc_reserved_mem {
70 76
71static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata; 77static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata;
72 78
79
73void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize, 80void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
74 phys_addr_t lbase, unsigned int lsize) 81 phys_addr_t lbase, unsigned int lsize)
75{ 82{
@@ -93,6 +100,7 @@ void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
93 } 100 }
94} 101}
95 102
103#ifdef CONFIG_SAMSUNG_ATAGS
96static int __init s5p_mfc_memory_init(void) 104static int __init s5p_mfc_memory_init(void)
97{ 105{
98 int i; 106 int i;
@@ -111,6 +119,7 @@ static int __init s5p_mfc_memory_init(void)
111 return 0; 119 return 0;
112} 120}
113device_initcall(s5p_mfc_memory_init); 121device_initcall(s5p_mfc_memory_init);
122#endif
114 123
115#ifdef CONFIG_OF 124#ifdef CONFIG_OF
116int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname, 125int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname,
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 23d1d0155bb3..ec1dcdca5b8a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -212,6 +212,13 @@ config GPIO_RCAR
212 help 212 help
213 Say yes here to support GPIO on Renesas R-Car SoCs. 213 Say yes here to support GPIO on Renesas R-Car SoCs.
214 214
215config GPIO_SAMSUNG
216 bool
217 depends on PLAT_SAMSUNG
218 help
219 Legacy GPIO support. Use only for platforms without support for
220 pinctrl.
221
215config GPIO_SPEAR_SPICS 222config GPIO_SPEAR_SPICS
216 bool "ST SPEAr13xx SPI Chip Select as GPIO support" 223 bool "ST SPEAr13xx SPI Chip Select as GPIO support"
217 depends on PLAT_SPEAR 224 depends on PLAT_SPEAR
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 0cb2d656ad16..ef3e983a2f1e 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -59,7 +59,7 @@ obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
59obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o 59obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
60obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o 60obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
61obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o 61obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
62obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o 62obj-$(CONFIG_GPIO_SAMSUNG) += gpio-samsung.o
63obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o 63obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o
64obj-$(CONFIG_GPIO_SCH) += gpio-sch.o 64obj-$(CONFIG_GPIO_SCH) += gpio-sch.o
65obj-$(CONFIG_GPIO_SODAVILLE) += gpio-sodaville.o 65obj-$(CONFIG_GPIO_SODAVILLE) += gpio-sodaville.o
diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index 0494d2769fd7..bce695d42f10 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -159,7 +159,7 @@ config VIDEO_MEM2MEM_DEINTERLACE
159 159
160config VIDEO_SAMSUNG_S5P_G2D 160config VIDEO_SAMSUNG_S5P_G2D
161 tristate "Samsung S5P and EXYNOS4 G2D 2d graphics accelerator driver" 161 tristate "Samsung S5P and EXYNOS4 G2D 2d graphics accelerator driver"
162 depends on VIDEO_DEV && VIDEO_V4L2 && PLAT_S5P 162 depends on VIDEO_DEV && VIDEO_V4L2 && (PLAT_S5P || ARCH_EXYNOS)
163 select VIDEOBUF2_DMA_CONTIG 163 select VIDEOBUF2_DMA_CONTIG
164 select V4L2_MEM2MEM_DEV 164 select V4L2_MEM2MEM_DEV
165 default n 165 default n
@@ -169,7 +169,7 @@ config VIDEO_SAMSUNG_S5P_G2D
169 169
170config VIDEO_SAMSUNG_S5P_JPEG 170config VIDEO_SAMSUNG_S5P_JPEG
171 tristate "Samsung S5P/Exynos4 JPEG codec driver" 171 tristate "Samsung S5P/Exynos4 JPEG codec driver"
172 depends on VIDEO_DEV && VIDEO_V4L2 && PLAT_S5P 172 depends on VIDEO_DEV && VIDEO_V4L2 && (PLAT_S5P || ARCH_EXYNOS)
173 select VIDEOBUF2_DMA_CONTIG 173 select VIDEOBUF2_DMA_CONTIG
174 select V4L2_MEM2MEM_DEV 174 select V4L2_MEM2MEM_DEV
175 ---help--- 175 ---help---
@@ -177,7 +177,7 @@ config VIDEO_SAMSUNG_S5P_JPEG
177 177
178config VIDEO_SAMSUNG_S5P_MFC 178config VIDEO_SAMSUNG_S5P_MFC
179 tristate "Samsung S5P MFC Video Codec" 179 tristate "Samsung S5P MFC Video Codec"
180 depends on VIDEO_DEV && VIDEO_V4L2 && PLAT_S5P 180 depends on VIDEO_DEV && VIDEO_V4L2 && (PLAT_S5P || ARCH_EXYNOS)
181 select VIDEOBUF2_DMA_CONTIG 181 select VIDEOBUF2_DMA_CONTIG
182 default n 182 default n
183 help 183 help
diff --git a/drivers/media/platform/exynos4-is/Kconfig b/drivers/media/platform/exynos4-is/Kconfig
index 6ff99b5849f9..004fd0b4e9df 100644
--- a/drivers/media/platform/exynos4-is/Kconfig
+++ b/drivers/media/platform/exynos4-is/Kconfig
@@ -1,7 +1,8 @@
1 1
2config VIDEO_SAMSUNG_EXYNOS4_IS 2config VIDEO_SAMSUNG_EXYNOS4_IS
3 bool "Samsung S5P/EXYNOS4 SoC series Camera Subsystem driver" 3 bool "Samsung S5P/EXYNOS4 SoC series Camera Subsystem driver"
4 depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && PLAT_S5P && PM_RUNTIME 4 depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && PM_RUNTIME
5 depends on (PLAT_S5P || ARCH_EXYNOS)
5 help 6 help
6 Say Y here to enable camera host interface devices for 7 Say Y here to enable camera host interface devices for
7 Samsung S5P and EXYNOS SoC series. 8 Samsung S5P and EXYNOS SoC series.
diff --git a/drivers/media/platform/s5p-tv/Kconfig b/drivers/media/platform/s5p-tv/Kconfig
index 7b659bd09bfd..369a4c191e18 100644
--- a/drivers/media/platform/s5p-tv/Kconfig
+++ b/drivers/media/platform/s5p-tv/Kconfig
@@ -8,7 +8,7 @@
8 8
9config VIDEO_SAMSUNG_S5P_TV 9config VIDEO_SAMSUNG_S5P_TV
10 bool "Samsung TV driver for S5P platform" 10 bool "Samsung TV driver for S5P platform"
11 depends on PLAT_S5P && PM_RUNTIME 11 depends on (PLAT_S5P || ARCH_EXYNOS) && PM_RUNTIME
12 default n 12 default n
13 ---help--- 13 ---help---
14 Say Y here to enable selecting the TV output devices for 14 Say Y here to enable selecting the TV output devices for
diff --git a/drivers/thermal/exynos_thermal.c b/drivers/thermal/exynos_thermal.c
index 788b1ddcac6c..4cbe3eea6deb 100644
--- a/drivers/thermal/exynos_thermal.c
+++ b/drivers/thermal/exynos_thermal.c
@@ -817,7 +817,8 @@ static struct exynos_tmu_platform_data const exynos4210_default_tmu_data = {
817#define EXYNOS4210_TMU_DRV_DATA (NULL) 817#define EXYNOS4210_TMU_DRV_DATA (NULL)
818#endif 818#endif
819 819
820#if defined(CONFIG_SOC_EXYNOS5250) || defined(CONFIG_SOC_EXYNOS4412) 820#if defined(CONFIG_SOC_EXYNOS5250) || defined(CONFIG_SOC_EXYNOS4412) || \
821 defined(CONFIG_SOC_EXYNOS4212)
821static struct exynos_tmu_platform_data const exynos_default_tmu_data = { 822static struct exynos_tmu_platform_data const exynos_default_tmu_data = {
822 .threshold_falling = 10, 823 .threshold_falling = 10,
823 .trigger_levels[0] = 85, 824 .trigger_levels[0] = 85,
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 92e1dc94ecc8..a3b48b5ea8d3 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -43,6 +43,7 @@ config USB_ARCH_HAS_EHCI
43 default y if ARCH_VT8500 43 default y if ARCH_VT8500
44 default y if PLAT_SPEAR 44 default y if PLAT_SPEAR
45 default y if PLAT_S5P 45 default y if PLAT_S5P
46 default y if ARCH_EXYNOS
46 default y if ARCH_MSM 47 default y if ARCH_MSM
47 default y if MICROBLAZE 48 default y if MICROBLAZE
48 default y if SPARC_LEON 49 default y if SPARC_LEON
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 344d5e2f87d7..922a65d361c8 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -225,7 +225,7 @@ config USB_EHCI_SH
225 225
226config USB_EHCI_S5P 226config USB_EHCI_S5P
227 tristate "EHCI support for Samsung S5P/EXYNOS SoC Series" 227 tristate "EHCI support for Samsung S5P/EXYNOS SoC Series"
228 depends on PLAT_S5P 228 depends on PLAT_S5P || ARCH_EXYNOS
229 help 229 help
230 Enable support for the Samsung S5Pxxxx and Exynos3/4/5 SOC's 230 Enable support for the Samsung S5Pxxxx and Exynos3/4/5 SOC's
231 on-chip EHCI controller. 231 on-chip EHCI controller.
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-22 06:51:25 -0500