58 files changed, 11800 insertions, 503 deletions

diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
new file mode 100644
index 000000000000..63379b04e052
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -0,0 +1,462 @@
+* Samsung Exynos5433 CMU (Clock Management Units)
+
+The Exynos5433 clock controller generates and supplies clock to various
+controllers within the Exynos5433 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "samsung,exynos5433-cmu-top"   - clock controller compatible for CMU_TOP
+    which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
+    domains and bus clocks.
+  - "samsung,exynos5433-cmu-cpif"  - clock controller compatible for CMU_CPIF
+    which generates clocks for LLI (Low Latency Interface) IP.
+  - "samsung,exynos5433-cmu-mif"   - clock controller compatible for CMU_MIF
+    which generates clocks for DRAM Memory Controller domain.
+  - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
+    which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
+  - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
+    which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
+  - "samsung,exynos5433-cmu-fsys"  - clock controller compatible for CMU_FSYS
+    which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
+  - "samsung,exynos5433-cmu-g2d"   - clock controller compatible for CMU_G2D
+    which generates clocks for G2D/MDMA IPs.
+  - "samsung,exynos5433-cmu-disp"  - clock controller compatible for CMU_DISP
+    which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
+  - "samsung,exynos5433-cmu-aud"   - clock controller compatible for CMU_AUD
+    which generates clocks for Cortex-A5/BUS/AUDIO clocks.
+  - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
+    and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
+    which generates global data buses clock and global peripheral buses clock.
+  - "samsung,exynos5433-cmu-g3d"  - clock controller compatible for CMU_G3D
+    which generates clocks for 3D Graphics Engine IP.
+  - "samsung,exynos5433-cmu-gscl"  - clock controller compatible for CMU_GSCL
+    which generates clocks for GSCALER IPs.
+  - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO
+    which generates clocks for Cortex-A53 Quad-core processor.
+  - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS
+    which generates clocks for Cortex-A57 Quad-core processor, CoreSight and
+    L2 cache controller.
+  - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL
+    which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs.
+  - "samsung,exynos5433-cmu-mfc"  - clock controller compatible for CMU_MFC
+    which generates clocks for MFC(Multi-Format Codec) IP.
+  - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC
+    which generates clocks for HEVC(High Efficiency Video Codec) decoder IP.
+  - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP
+    which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
+  - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0
+    which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1}
+    IPs.
+  - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1
+    which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+- clocks: list of the clock controller input clock identifiers,
+        from common clock bindings. Please refer the next section
+        to find the input clocks for a given controller.
+
+- clock-names: list of the clock controller input clock names,
+        as described in clock-bindings.txt.
+
+        Input clocks for top clock controller:
+                - oscclk
+                - sclk_mphy_pll
+                - sclk_mfc_pll
+                - sclk_bus_pll
+
+        Input clocks for cpif clock controller:
+                - oscclk
+
+        Input clocks for mif clock controller:
+                - oscclk
+                - sclk_mphy_pll
+
+        Input clocks for fsys clock controller:
+                - oscclk
+                - sclk_ufs_mphy
+                - div_aclk_fsys_200
+                - sclk_pcie_100_fsys
+                - sclk_ufsunipro_fsys
+                - sclk_mmc2_fsys
+                - sclk_mmc1_fsys
+                - sclk_mmc0_fsys
+                - sclk_usbhost30_fsys
+                - sclk_usbdrd30_fsys
+
+        Input clocks for g2d clock controller:
+                - oscclk
+                - aclk_g2d_266
+                - aclk_g2d_400
+
+        Input clocks for disp clock controller:
+                - oscclk
+                - sclk_dsim1_disp
+                - sclk_dsim0_disp
+                - sclk_dsd_disp
+                - sclk_decon_tv_eclk_disp
+                - sclk_decon_vclk_disp
+                - sclk_decon_eclk_disp
+                - sclk_decon_tv_vclk_disp
+                - aclk_disp_333
+
+        Input clocks for bus0 clock controller:
+                - aclk_bus0_400
+
+        Input clocks for bus1 clock controller:
+                - aclk_bus1_400
+
+        Input clocks for bus2 clock controller:
+                - oscclk
+                - aclk_bus2_400
+
+        Input clocks for g3d clock controller:
+                - oscclk
+                - aclk_g3d_400
+
+        Input clocks for gscl clock controller:
+                - oscclk
+                - aclk_gscl_111
+                - aclk_gscl_333
+
+        Input clocks for apollo clock controller:
+                - oscclk
+                - sclk_bus_pll_apollo
+
+        Input clocks for atlas clock controller:
+                - oscclk
+                - sclk_bus_pll_atlas
+
+        Input clocks for mscl clock controller:
+                - oscclk
+                - sclk_jpeg_mscl
+                - aclk_mscl_400
+
+        Input clocks for mfc clock controller:
+                - oscclk
+                - aclk_mfc_400
+
+        Input clocks for hevc clock controller:
+                - oscclk
+                - aclk_hevc_400
+
+        Input clocks for isp clock controller:
+                - oscclk
+                - aclk_isp_dis_400
+                - aclk_isp_400
+
+        Input clocks for cam0 clock controller:
+                - oscclk
+                - aclk_cam0_333
+                - aclk_cam0_400
+                - aclk_cam0_552
+
+        Input clocks for cam1 clock controller:
+                - oscclk
+                - sclk_isp_uart_cam1
+                - sclk_isp_spi1_cam1
+                - sclk_isp_spi0_cam1
+                - aclk_cam1_333
+                - aclk_cam1_400
+                - aclk_cam1_552
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5433.h header and can be used in device
+tree sources.
+
+Example 1: Examples of 'oscclk' source clock node are listed below.
+
+        xxti: xxti {
+                compatible = "fixed-clock";
+                clock-output-names = "oscclk";
+                #clock-cells = <0>;
+        };
+
+Example 2: Examples of clock controller nodes are listed below.
+
+        cmu_top: clock-controller@10030000 {
+                compatible = "samsung,exynos5433-cmu-top";
+                reg = <0x10030000 0x0c04>;
+                #clock-cells = <1>;
+
+                clock-names = "oscclk",
+                        "sclk_mphy_pll",
+                        "sclk_mfc_pll",
+                        "sclk_bus_pll";
+                clocks = <&xxti>,
+                       <&cmu_cpif CLK_SCLK_MPHY_PLL>,
+                       <&cmu_mif CLK_SCLK_MFC_PLL>,
+                       <&cmu_mif CLK_SCLK_BUS_PLL>;
+        };
+
+        cmu_cpif: clock-controller@10fc0000 {
+                compatible = "samsung,exynos5433-cmu-cpif";
+                reg = <0x10fc0000 0x0c04>;
+                #clock-cells = <1>;
+
+                clock-names = "oscclk";
+                clocks = <&xxti>;
+        };
+
+        cmu_mif: clock-controller@105b0000 {
+                compatible = "samsung,exynos5433-cmu-mif";
+                reg = <0x105b0000 0x100c>;
+                #clock-cells = <1>;
+
+                clock-names = "oscclk",
+                        "sclk_mphy_pll";
+                clocks = <&xxti>,
+                       <&cmu_cpif CLK_SCLK_MPHY_PLL>;
+        };
+
+        cmu_peric: clock-controller@14c80000 {
+                compatible = "samsung,exynos5433-cmu-peric";
+                reg = <0x14c80000 0x0b08>;
+                #clock-cells = <1>;
+        };
+
+        cmu_peris: clock-controller@10040000 {
+                compatible = "samsung,exynos5433-cmu-peris";
+                reg = <0x10040000 0x0b20>;
+                #clock-cells = <1>;
+        };
+
+        cmu_fsys: clock-controller@156e0000 {
+                compatible = "samsung,exynos5433-cmu-fsys";
+                reg = <0x156e0000 0x0b04>;
+                #clock-cells = <1>;
+
+                clock-names = "oscclk",
+                        "sclk_ufs_mphy",
+                        "div_aclk_fsys_200",
+                        "sclk_pcie_100_fsys",
+                        "sclk_ufsunipro_fsys",
+                        "sclk_mmc2_fsys",
+                        "sclk_mmc1_fsys",
+                        "sclk_mmc0_fsys",
+                        "sclk_usbhost30_fsys",
+                        "sclk_usbdrd30_fsys";
+                clocks = <&xxti>,
+                       <&cmu_cpif CLK_SCLK_UFS_MPHY>,
+                       <&cmu_top CLK_DIV_ACLK_FSYS_200>,
+                       <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
+                       <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
+                       <&cmu_top CLK_SCLK_MMC2_FSYS>,
+                       <&cmu_top CLK_SCLK_MMC1_FSYS>,
+                       <&cmu_top CLK_SCLK_MMC0_FSYS>,
+                       <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
+                       <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
+        };
+
+        cmu_g2d: clock-controller@12460000 {
+                compatible = "samsung,exynos5433-cmu-g2d";
+                reg = <0x12460000 0x0b08>;
+                #clock-cells = <1>;
+
+                clock-names = "oscclk",
+                        "aclk_g2d_266",
+                        "aclk_g2d_400";
+                clocks = <&xxti>,
+                       <&cmu_top CLK_ACLK_G2D_266>,
+                       <&cmu_top CLK_ACLK_G2D_400>;
+        };
+
+        cmu_disp: clock-controller@13b90000 {
+                compatible = "samsung,exynos5433-cmu-disp";
+                reg = <0x13b90000 0x0c04>;
+                #clock-cells = <1>;
+
+                clock-names = "oscclk",
+                        "sclk_dsim1_disp",
+                        "sclk_dsim0_disp",
+                        "sclk_dsd_disp",
+                        "sclk_decon_tv_eclk_disp",
+                        "sclk_decon_vclk_disp",
+                        "sclk_decon_eclk_disp",
+                        "sclk_decon_tv_vclk_disp",
+                        "aclk_disp_333";
+                clocks = <&xxti>,
+                       <&cmu_mif CLK_SCLK_DSIM1_DISP>,
+                       <&cmu_mif CLK_SCLK_DSIM0_DISP>,
+                       <&cmu_mif CLK_SCLK_DSD_DISP>,
+                       <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
+                       <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
+                       <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
+                       <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
+                       <&cmu_mif CLK_ACLK_DISP_333>;
+        };
+
+        cmu_aud: clock-controller@114c0000 {
+                compatible = "samsung,exynos5433-cmu-aud";
+                reg = <0x114c0000 0x0b04>;
+                #clock-cells = <1>;
+        };
+
+        cmu_bus0: clock-controller@13600000 {
+                compatible = "samsung,exynos5433-cmu-bus0";
+                reg = <0x13600000 0x0b04>;
+                #clock-cells = <1>;
+
+                clock-names = "aclk_bus0_400";
+                clocks = <&cmu_top CLK_ACLK_BUS0_400>;
+        };
+
+        cmu_bus1: clock-controller@14800000 {
+                compatible = "samsung,exynos5433-cmu-bus1";
+                reg = <0x14800000 0x0b04>;
+                #clock-cells = <1>;
+
+                clock-names = "aclk_bus1_400";
+                clocks = <&cmu_top CLK_ACLK_BUS1_400>;
+        };
+
+        cmu_bus2: clock-controller@13400000 {
+                compatible = "samsung,exynos5433-cmu-bus2";
+                reg = <0x13400000 0x0b04>;
+                #clock-cells = <1>;
+
+                clock-names = "oscclk", "aclk_bus2_400";
+                clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
+        };
+
+        cmu_g3d: clock-controller@14aa0000 {
+                compatible = "samsung,exynos5433-cmu-g3d";
+                reg = <0x14aa0000 0x1000>;
+                #clock-cells = <1>;
+
+                clock-names = "oscclk", "aclk_g3d_400";
+                clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
+        };
+
+        cmu_gscl: clock-controller@13cf0000 {
+                compatible = "samsung,exynos5433-cmu-gscl";
+                reg = <0x13cf0000 0x0b10>;
+                #clock-cells = <1>;
+
+                clock-names = "oscclk",
+                        "aclk_gscl_111",
+                        "aclk_gscl_333";
+                clocks = <&xxti>,
+                        <&cmu_top CLK_ACLK_GSCL_111>,
+                        <&cmu_top CLK_ACLK_GSCL_333>;
+        };
+
+        cmu_apollo: clock-controller@11900000 {
+                compatible = "samsung,exynos5433-cmu-apollo";
+                reg = <0x11900000 0x1088>;
+                #clock-cells = <1>;
+
+                clock-names = "oscclk", "sclk_bus_pll_apollo";
+                clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
+        };
+
+        cmu_atlas: clock-controller@11800000 {
+                compatible = "samsung,exynos5433-cmu-atlas";
+                reg = <0x11800000 0x1088>;
+                #clock-cells = <1>;
+
+                clock-names = "oscclk", "sclk_bus_pll_atlas";
+                clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
+        };
+
+        cmu_mscl: clock-controller@105d0000 {
+                compatible = "samsung,exynos5433-cmu-mscl";
+                reg = <0x105d0000 0x0b10>;
+                #clock-cells = <1>;
+
+                clock-names = "oscclk",
+                        "sclk_jpeg_mscl",
+                        "aclk_mscl_400";
+                clocks = <&xxti>,
+                       <&cmu_top CLK_SCLK_JPEG_MSCL>,
+                       <&cmu_top CLK_ACLK_MSCL_400>;
+        };
+
+        cmu_mfc: clock-controller@15280000 {
+                compatible = "samsung,exynos5433-cmu-mfc";
+                reg = <0x15280000 0x0b08>;
+                #clock-cells = <1>;
+
+                clock-names = "oscclk", "aclk_mfc_400";
+                clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
+        };
+
+        cmu_hevc: clock-controller@14f80000 {
+                compatible = "samsung,exynos5433-cmu-hevc";
+                reg = <0x14f80000 0x0b08>;
+                #clock-cells = <1>;
+
+                clock-names = "oscclk", "aclk_hevc_400";
+                clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
+        };
+
+        cmu_isp: clock-controller@146d0000 {
+                compatible = "samsung,exynos5433-cmu-isp";
+                reg = <0x146d0000 0x0b0c>;
+                #clock-cells = <1>;
+
+                clock-names = "oscclk",
+                        "aclk_isp_dis_400",
+                        "aclk_isp_400";
+                clocks = <&xxti>,
+                       <&cmu_top CLK_ACLK_ISP_DIS_400>,
+                       <&cmu_top CLK_ACLK_ISP_400>;
+        };
+
+        cmu_cam0: clock-controller@120d0000 {
+                compatible = "samsung,exynos5433-cmu-cam0";
+                reg = <0x120d0000 0x0b0c>;
+                #clock-cells = <1>;
+
+                clock-names = "oscclk",
+                        "aclk_cam0_333",
+                        "aclk_cam0_400",
+                        "aclk_cam0_552";
+                clocks = <&xxti>,
+                       <&cmu_top CLK_ACLK_CAM0_333>,
+                       <&cmu_top CLK_ACLK_CAM0_400>,
+                       <&cmu_top CLK_ACLK_CAM0_552>;
+        };
+
+        cmu_cam1: clock-controller@145d0000 {
+                compatible = "samsung,exynos5433-cmu-cam1";
+                reg = <0x145d0000 0x0b08>;
+                #clock-cells = <1>;
+
+                clock-names = "oscclk",
+                        "sclk_isp_uart_cam1",
+                        "sclk_isp_spi1_cam1",
+                        "sclk_isp_spi0_cam1",
+                        "aclk_cam1_333",
+                        "aclk_cam1_400",
+                        "aclk_cam1_552";
+                clocks = <&xxti>,
+                       <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
+                       <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
+                       <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
+                       <&cmu_top CLK_ACLK_CAM1_333>,
+                       <&cmu_top CLK_ACLK_CAM1_400>,
+                       <&cmu_top CLK_ACLK_CAM1_552>;
+        };
+
+Example 3: UART controller node that consumes the clock generated by the clock
+           controller.
+
+        serial_0: serial@14C10000 {
+                compatible = "samsung,exynos5433-uart";
+                reg = <0x14C10000 0x100>;
+                interrupts = <0 421 0>;
+                clocks = <&cmu_peric CLK_PCLK_UART0>,
+                         <&cmu_peric CLK_SCLK_UART0>;
+                clock-names = "uart", "clk_uart_baud0";
+                pinctrl-names = "default";
+                pinctrl-0 = <&uart0_bus>;
+                status = "disabled";
+        };
diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
index dc5ea5b22da9..670c2af3e931 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -23,6 +23,14 @@ The following is a list of provided IDs and clock names on Armada 380/385:
  2 = l2clk   (L2 Cache clock)
  3 = ddrclk  (DDR clock)
 
+The following is a list of provided IDs and clock names on Armada 39x:
+ 0 = tclk    (Internal Bus clock)
+ 1 = cpuclk  (CPU clock)
+ 2 = nbclk   (Coherent Fabric clock)
+ 3 = hclk    (SDRAM Controller Internal Clock)
+ 4 = dclk    (SDRAM Interface Clock)
+ 5 = refclk  (Reference Clock)
+
 The following is a list of provided IDs and clock names on Kirkwood and Dove:
  0 = tclk   (Internal Bus clock)
  1 = cpuclk (CPU0 clock)
@@ -39,6 +47,7 @@ Required properties:
         "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
         "marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
         "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
+        "marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
         "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
         "marvell,dove-core-clock" - for Dove SoC core clocks
         "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
index 76477be742b2..31c7c0c1ce8f 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
@@ -1,6 +1,6 @@
 * Gated Clock bindings for Marvell EBU SoCs
 
-Marvell Armada 370/375/380/385/XP, Dove and Kirkwood allow some
+Marvell Armada 370/375/380/385/39x/XP, Dove and Kirkwood allow some
 peripheral clocks to be gated to save some power. The clock consumer
 should specify the desired clock by having the clock ID in its
 "clocks" phandle cell. The clock ID is directly mapped to the
@@ -77,6 +77,18 @@ ID	Clock		Peripheral
 28      xor1            XOR 1
 30      sata1           SATA 1
 
+The following is a list of provided IDs for Armada 39x:
+ID      Clock           Peripheral
+-----------------------------------
+5       pex1            PCIe 1
+6       pex2            PCIe 2
+7       pex3            PCIe 3
+8       pex0            PCIe 0
+9       usb3h0          USB3 Host 0
+17      sdio            SDIO
+22      xor0            XOR 0
+28      xor1            XOR 1
+
 The following is a list of provided IDs for Armada XP:
 ID      Clock   Peripheral
 -----------------------------------
@@ -152,6 +164,7 @@ Required properties:
         "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
         "marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
         "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
+        "marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
         "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
         "marvell,dove-gating-clock" - for Dove SoC clock gating
         "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index aba3d254e037..54c23f34f194 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -8,6 +8,7 @@ Required properties :
                         "qcom,gcc-apq8084"
                         "qcom,gcc-ipq8064"
                         "qcom,gcc-msm8660"
+                        "qcom,gcc-msm8916"
                         "qcom,gcc-msm8960"
                         "qcom,gcc-msm8974"
                         "qcom,gcc-msm8974pro"
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 4ad6e473cf83..9de3412af406 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -211,8 +211,9 @@ static void __init imx6q_1588_init(void)
          * set bit IOMUXC_GPR1[21].  Or the PTP clock must be from pad
          * (external OSC), and we need to clear the bit.
          */
-        clksel = ptp_clk == enet_ref ? IMX6Q_GPR1_ENET_CLK_SEL_ANATOP :
-                                       IMX6Q_GPR1_ENET_CLK_SEL_PAD;
+        clksel = clk_is_match(ptp_clk, enet_ref) ?
+                                IMX6Q_GPR1_ENET_CLK_SEL_ANATOP :
+                                IMX6Q_GPR1_ENET_CLK_SEL_PAD;
         gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
         if (!IS_ERR(gpr))
                 regmap_update_bits(gpr, IOMUXC_GPR1,
diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c
index aad4796aa3ed..48a65b2b4027 100644
--- a/drivers/clk/clk-conf.c
+++ b/drivers/clk/clk-conf.c
@@ -13,7 +13,6 @@
 #include <linux/device.h>
 #include <linux/of.h>
 #include <linux/printk.h>
-#include "clk.h"
 
 static int __set_clk_parents(struct device_node *node, bool clk_supplier)
 {
@@ -39,7 +38,7 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier)
                 }
                 if (clkspec.np == node && !clk_supplier)
                         return 0;
-                pclk = of_clk_get_by_clkspec(&clkspec);
+                pclk = of_clk_get_from_provider(&clkspec);
                 if (IS_ERR(pclk)) {
                         pr_warn("clk: couldn't get parent clock %d for %s\n",
                                 index, node->full_name);
@@ -54,7 +53,7 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier)
                         rc = 0;
                         goto err;
                 }
-                clk = of_clk_get_by_clkspec(&clkspec);
+                clk = of_clk_get_from_provider(&clkspec);
                 if (IS_ERR(clk)) {
                         pr_warn("clk: couldn't get parent clock %d for %s\n",
                                 index, node->full_name);
@@ -98,7 +97,7 @@ static int __set_clk_rates(struct device_node *node, bool clk_supplier)
                         if (clkspec.np == node && !clk_supplier)
                                 return 0;
 
-                        clk = of_clk_get_by_clkspec(&clkspec);
+                        clk = of_clk_get_from_provider(&clkspec);
                         if (IS_ERR(clk)) {
                                 pr_warn("clk: couldn't get clock %d for %s\n",
                                         index, node->full_name);
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index db7f8bce7467..25006a8bb8e6 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -144,12 +144,6 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
                                    divider->flags);
 }
 
-/*
- * The reverse of DIV_ROUND_UP: The maximum number which
- * divided by m is r
- */
-#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
-
 static bool _is_valid_table_div(const struct clk_div_table *table,
                                                          unsigned int div)
 {
@@ -225,19 +219,24 @@ static int _div_round_closest(const struct clk_div_table *table,
                               unsigned long parent_rate, unsigned long rate,
                               unsigned long flags)
 {
-        int up, down, div;
+        int up, down;
+        unsigned long up_rate, down_rate;
 
-        up = down = div = DIV_ROUND_CLOSEST(parent_rate, rate);
+        up = DIV_ROUND_UP(parent_rate, rate);
+        down = parent_rate / rate;
 
         if (flags & CLK_DIVIDER_POWER_OF_TWO) {
-                up = __roundup_pow_of_two(div);
-                down = __rounddown_pow_of_two(div);
+                up = __roundup_pow_of_two(up);
+                down = __rounddown_pow_of_two(down);
         } else if (table) {
-                up = _round_up_table(table, div);
-                down = _round_down_table(table, div);
+                up = _round_up_table(table, up);
+                down = _round_down_table(table, down);
         }
 
-        return (up - div) <= (div - down) ? up : down;
+        up_rate = DIV_ROUND_UP(parent_rate, up);
+        down_rate = DIV_ROUND_UP(parent_rate, down);
+
+        return (rate - up_rate) <= (down_rate - rate) ? up : down;
 }
 
 static int _div_round(const struct clk_div_table *table,
@@ -313,7 +312,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
                         return i;
                 }
                 parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
-                                MULT_ROUND_UP(rate, i));
+                                               rate * i);
                 now = DIV_ROUND_UP(parent_rate, i);
                 if (_is_best_div(rate, now, best, flags)) {
                         bestdiv = i;
@@ -353,7 +352,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
                 bestdiv = readl(divider->reg) >> divider->shift;
                 bestdiv &= div_mask(divider->width);
                 bestdiv = _get_div(divider->table, bestdiv, divider->flags);
-                return bestdiv;
+                return DIV_ROUND_UP(*prate, bestdiv);
         }
 
         return divider_round_rate(hw, rate, prate, divider->table,
diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index 82a59d0086cc..6aa72d9d79ba 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -36,6 +36,9 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
         m = (val & fd->mmask) >> fd->mshift;
         n = (val & fd->nmask) >> fd->nshift;
 
+        if (!n || !m)
+                return parent_rate;
+
         ret = (u64)parent_rate * m;
         do_div(ret, n);
 
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index eb0152961d3c..fa5a00e5ee41 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -77,13 +77,16 @@ struct clk_core {
         struct kref             ref;
 };
 
+#define CREATE_TRACE_POINTS
+#include <trace/events/clk.h>
+
 struct clk {
         struct clk_core *core;
         const char *dev_id;
         const char *con_id;
         unsigned long min_rate;
         unsigned long max_rate;
-        struct hlist_node child_node;
+        struct hlist_node clks_node;
 };
 
 /***           locking             ***/
@@ -480,6 +483,8 @@ static void clk_unprepare_unused_subtree(struct clk_core *clk)
 {
         struct clk_core *child;
 
+        lockdep_assert_held(&prepare_lock);
+
         hlist_for_each_entry(child, &clk->children, child_node)
                 clk_unprepare_unused_subtree(child);
 
@@ -490,10 +495,12 @@ static void clk_unprepare_unused_subtree(struct clk_core *clk)
                 return;
 
         if (clk_core_is_prepared(clk)) {
+                trace_clk_unprepare(clk);
                 if (clk->ops->unprepare_unused)
                         clk->ops->unprepare_unused(clk->hw);
                 else if (clk->ops->unprepare)
                         clk->ops->unprepare(clk->hw);
+                trace_clk_unprepare_complete(clk);
         }
 }
 
@@ -503,6 +510,8 @@ static void clk_disable_unused_subtree(struct clk_core *clk)
         struct clk_core *child;
         unsigned long flags;
 
+        lockdep_assert_held(&prepare_lock);
+
         hlist_for_each_entry(child, &clk->children, child_node)
                 clk_disable_unused_subtree(child);
 
@@ -520,10 +529,12 @@ static void clk_disable_unused_subtree(struct clk_core *clk)
          * back to .disable
          */
         if (clk_core_is_enabled(clk)) {
+                trace_clk_disable(clk);
                 if (clk->ops->disable_unused)
                         clk->ops->disable_unused(clk->hw);
                 else if (clk->ops->disable)
                         clk->ops->disable(clk->hw);
+                trace_clk_disable_complete(clk);
         }
 
 unlock_out:
@@ -851,10 +862,10 @@ static void clk_core_get_boundaries(struct clk_core *clk,
         *min_rate = 0;
         *max_rate = ULONG_MAX;
 
-        hlist_for_each_entry(clk_user, &clk->clks, child_node)
+        hlist_for_each_entry(clk_user, &clk->clks, clks_node)
                 *min_rate = max(*min_rate, clk_user->min_rate);
 
-        hlist_for_each_entry(clk_user, &clk->clks, child_node)
+        hlist_for_each_entry(clk_user, &clk->clks, clks_node)
                 *max_rate = min(*max_rate, clk_user->max_rate);
 }
 
@@ -903,9 +914,12 @@ static void clk_core_unprepare(struct clk_core *clk)
 
         WARN_ON(clk->enable_count > 0);
 
+        trace_clk_unprepare(clk);
+
         if (clk->ops->unprepare)
                 clk->ops->unprepare(clk->hw);
 
+        trace_clk_unprepare_complete(clk);
         clk_core_unprepare(clk->parent);
 }
 
@@ -943,12 +957,16 @@ static int clk_core_prepare(struct clk_core *clk)
                 if (ret)
                         return ret;
 
-                if (clk->ops->prepare) {
+                trace_clk_prepare(clk);
+
+                if (clk->ops->prepare)
                         ret = clk->ops->prepare(clk->hw);
-                        if (ret) {
-                                clk_core_unprepare(clk->parent);
-                                return ret;
-                        }
+
+                trace_clk_prepare_complete(clk);
+
+                if (ret) {
+                        clk_core_unprepare(clk->parent);
+                        return ret;
                 }
         }
 
@@ -995,9 +1013,13 @@ static void clk_core_disable(struct clk_core *clk)
         if (--clk->enable_count > 0)
                 return;
 
+        trace_clk_disable(clk);
+
         if (clk->ops->disable)
                 clk->ops->disable(clk->hw);
 
+        trace_clk_disable_complete(clk);
+
         clk_core_disable(clk->parent);
 }
 
@@ -1050,12 +1072,16 @@ static int clk_core_enable(struct clk_core *clk)
                 if (ret)
                         return ret;
 
-                if (clk->ops->enable) {
+                trace_clk_enable(clk);
+
+                if (clk->ops->enable)
                         ret = clk->ops->enable(clk->hw);
-                        if (ret) {
-                                clk_core_disable(clk->parent);
-                                return ret;
-                        }
+
+                trace_clk_enable_complete(clk);
+
+                if (ret) {
+                        clk_core_disable(clk->parent);
+                        return ret;
                 }
         }
 
@@ -1106,6 +1132,8 @@ static unsigned long clk_core_round_rate_nolock(struct clk_core *clk,
         struct clk_core *parent;
         struct clk_hw *parent_hw;
 
+        lockdep_assert_held(&prepare_lock);
+
         if (!clk)
                 return 0;
 
@@ -1245,6 +1273,8 @@ static void __clk_recalc_accuracies(struct clk_core *clk)
         unsigned long parent_accuracy = 0;
         struct clk_core *child;
 
+        lockdep_assert_held(&prepare_lock);
+
         if (clk->parent)
                 parent_accuracy = clk->parent->accuracy;
 
@@ -1318,6 +1348,8 @@ static void __clk_recalc_rates(struct clk_core *clk, unsigned long msg)
         unsigned long parent_rate = 0;
         struct clk_core *child;
 
+        lockdep_assert_held(&prepare_lock);
+
         old_rate = clk->rate;
 
         if (clk->parent)
@@ -1350,7 +1382,6 @@ static unsigned long clk_core_get_rate(struct clk_core *clk)
 
         return rate;
 }
-EXPORT_SYMBOL_GPL(clk_core_get_rate);
 
 /**
  * clk_get_rate - return the rate of clk
@@ -1480,10 +1511,14 @@ static int __clk_set_parent(struct clk_core *clk, struct clk_core *parent,
 
         old_parent = __clk_set_parent_before(clk, parent);
 
+        trace_clk_set_parent(clk, parent);
+
         /* change clock input source */
         if (parent && clk->ops->set_parent)
                 ret = clk->ops->set_parent(clk->hw, p_index);
 
+        trace_clk_set_parent_complete(clk, parent);
+
         if (ret) {
                 flags = clk_enable_lock();
                 clk_reparent(clk, old_parent);
@@ -1525,6 +1560,8 @@ static int __clk_speculate_rates(struct clk_core *clk,
         unsigned long new_rate;
         int ret = NOTIFY_DONE;
 
+        lockdep_assert_held(&prepare_lock);
+
         new_rate = clk_recalc(clk, parent_rate);
 
         /* abort rate change if a driver returns NOTIFY_BAD or NOTIFY_STOP */
@@ -1707,6 +1744,7 @@ static void clk_change_rate(struct clk_core *clk)
 
         if (clk->new_parent && clk->new_parent != clk->parent) {
                 old_parent = __clk_set_parent_before(clk, clk->new_parent);
+                trace_clk_set_parent(clk, clk->new_parent);
 
                 if (clk->ops->set_rate_and_parent) {
                         skip_set_rate = true;
@@ -1717,12 +1755,17 @@ static void clk_change_rate(struct clk_core *clk)
                         clk->ops->set_parent(clk->hw, clk->new_parent_index);
                 }
 
+                trace_clk_set_parent_complete(clk, clk->new_parent);
                 __clk_set_parent_after(clk, clk->new_parent, old_parent);
         }
 
+        trace_clk_set_rate(clk, clk->new_rate);
+
         if (!skip_set_rate && clk->ops->set_rate)
                 clk->ops->set_rate(clk->hw, clk->new_rate, best_parent_rate);
 
+        trace_clk_set_rate_complete(clk, clk->new_rate);
+
         clk->rate = clk_recalc(clk, best_parent_rate);
 
         if (clk->notifier_count && old_rate != clk->rate)
@@ -2011,16 +2054,18 @@ static int clk_core_set_parent(struct clk_core *clk, struct clk_core *parent)
         if (!clk)
                 return 0;
 
-        /* verify ops for for multi-parent clks */
-        if ((clk->num_parents > 1) && (!clk->ops->set_parent))
-                return -ENOSYS;
-
         /* prevent racing with updates to the clock topology */
         clk_prepare_lock();
 
         if (clk->parent == parent)
                 goto out;
 
+        /* verify ops for for multi-parent clks */
+        if ((clk->num_parents > 1) && (!clk->ops->set_parent)) {
+                ret = -ENOSYS;
+                goto out;
+        }
+
         /* check that we are allowed to re-parent if the clock is in use */
         if ((clk->flags & CLK_SET_PARENT_GATE) && clk->prepare_count) {
                 ret = -EBUSY;
@@ -2111,10 +2156,10 @@ EXPORT_SYMBOL_GPL(clk_set_parent);
  */
 int clk_set_phase(struct clk *clk, int degrees)
 {
-        int ret = 0;
+        int ret = -EINVAL;
 
         if (!clk)
-                goto out;
+                return 0;
 
         /* sanity check degrees */
         degrees %= 360;
@@ -2123,18 +2168,18 @@ int clk_set_phase(struct clk *clk, int degrees)
 
         clk_prepare_lock();
 
-        if (!clk->core->ops->set_phase)
-                goto out_unlock;
+        trace_clk_set_phase(clk->core, degrees);
 
-        ret = clk->core->ops->set_phase(clk->core->hw, degrees);
+        if (clk->core->ops->set_phase)
+                ret = clk->core->ops->set_phase(clk->core->hw, degrees);
+
+        trace_clk_set_phase_complete(clk->core, degrees);
 
         if (!ret)
                 clk->core->phase = degrees;
 
-out_unlock:
         clk_prepare_unlock();
 
-out:
         return ret;
 }
 EXPORT_SYMBOL_GPL(clk_set_phase);
@@ -2171,6 +2216,32 @@ int clk_get_phase(struct clk *clk)
 }
 
 /**
+ * clk_is_match - check if two clk's point to the same hardware clock
+ * @p: clk compared against q
+ * @q: clk compared against p
+ *
+ * Returns true if the two struct clk pointers both point to the same hardware
+ * clock node. Put differently, returns true if struct clk *p and struct clk *q
+ * share the same struct clk_core object.
+ *
+ * Returns false otherwise. Note that two NULL clks are treated as matching.
+ */
+bool clk_is_match(const struct clk *p, const struct clk *q)
+{
+        /* trivial case: identical struct clk's or both NULL */
+        if (p == q)
+                return true;
+
+        /* true if clk->core pointers match. Avoid derefing garbage */
+        if (!IS_ERR_OR_NULL(p) && !IS_ERR_OR_NULL(q))
+                if (p->core == q->core)
+                        return true;
+
+        return false;
+}
+EXPORT_SYMBOL_GPL(clk_is_match);
+
+/**
  * __clk_init - initialize the data structures in a struct clk
  * @dev:        device initializing this clk, placeholder for now
  * @clk:        clk being initialized
@@ -2376,7 +2447,7 @@ struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
         clk->max_rate = ULONG_MAX;
 
         clk_prepare_lock();
-        hlist_add_head(&clk->child_node, &hw->core->clks);
+        hlist_add_head(&clk->clks_node, &hw->core->clks);
         clk_prepare_unlock();
 
         return clk;
@@ -2385,7 +2456,7 @@ struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
 void __clk_free_clk(struct clk *clk)
 {
         clk_prepare_lock();
-        hlist_del(&clk->child_node);
+        hlist_del(&clk->clks_node);
         clk_prepare_unlock();
 
         kfree(clk);
@@ -2488,6 +2559,8 @@ static void __clk_release(struct kref *ref)
         struct clk_core *clk = container_of(ref, struct clk_core, ref);
         int i = clk->num_parents;
 
+        lockdep_assert_held(&prepare_lock);
+
         kfree(clk->parents);
         while (--i >= 0)
                 kfree_const(clk->parent_names[i]);
@@ -2663,7 +2736,7 @@ void __clk_put(struct clk *clk)
 
         clk_prepare_lock();
 
-        hlist_del(&clk->child_node);
+        hlist_del(&clk->clks_node);
         if (clk->min_rate > clk->core->req_rate ||
             clk->max_rate < clk->core->req_rate)
                 clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
@@ -2809,17 +2882,6 @@ static const struct of_device_id __clk_of_table_sentinel
 static LIST_HEAD(of_clk_providers);
 static DEFINE_MUTEX(of_clk_mutex);
 
-/* of_clk_provider list locking helpers */
-void of_clk_lock(void)
-{
-        mutex_lock(&of_clk_mutex);
-}
-
-void of_clk_unlock(void)
-{
-        mutex_unlock(&of_clk_mutex);
-}
-
 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
                                      void *data)
 {
@@ -2903,7 +2965,11 @@ struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
         struct of_clk_provider *provider;
         struct clk *clk = ERR_PTR(-EPROBE_DEFER);
 
+        if (!clkspec)
+                return ERR_PTR(-EINVAL);
+
         /* Check if we have such a provider in our array */
+        mutex_lock(&of_clk_mutex);
         list_for_each_entry(provider, &of_clk_providers, link) {
                 if (provider->node == clkspec->np)
                         clk = provider->get(clkspec, provider->data);
@@ -2919,19 +2985,22 @@ struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
                         break;
                 }
         }
+        mutex_unlock(&of_clk_mutex);
 
         return clk;
 }
 
+/**
+ * of_clk_get_from_provider() - Lookup a clock from a clock provider
+ * @clkspec: pointer to a clock specifier data structure
+ *
+ * This function looks up a struct clk from the registered list of clock
+ * providers, an input is a clock specifier data structure as returned
+ * from the of_parse_phandle_with_args() function call.
+ */
 struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec)
 {
-        struct clk *clk;
-
-        mutex_lock(&of_clk_mutex);
-        clk = __of_clk_get_from_provider(clkspec, NULL, __func__);
-        mutex_unlock(&of_clk_mutex);
-
-        return clk;
+        return __of_clk_get_from_provider(clkspec, NULL, __func__);
 }
 
 int of_clk_get_parent_count(struct device_node *np)
diff --git a/drivers/clk/clk.h b/drivers/clk/clk.h
index ba845408cc3e..00b35a13cdf3 100644
--- a/drivers/clk/clk.h
+++ b/drivers/clk/clk.h
@@ -12,11 +12,8 @@
 struct clk_hw;
 
 #if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK)
-struct clk *of_clk_get_by_clkspec(struct of_phandle_args *clkspec);
 struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
                                        const char *dev_id, const char *con_id);
-void of_clk_lock(void);
-void of_clk_unlock(void);
 #endif
 
 #ifdef CONFIG_COMMON_CLK
diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index 043fd3633373..1fcb6ef2cdac 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -28,34 +28,6 @@ static LIST_HEAD(clocks);
 static DEFINE_MUTEX(clocks_mutex);
 
 #if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK)
-
-static struct clk *__of_clk_get_by_clkspec(struct of_phandle_args *clkspec,
-                                         const char *dev_id, const char *con_id)
-{
-        struct clk *clk;
-
-        if (!clkspec)
-                return ERR_PTR(-EINVAL);
-
-        of_clk_lock();
-        clk = __of_clk_get_from_provider(clkspec, dev_id, con_id);
-        of_clk_unlock();
-        return clk;
-}
-
-/**
- * of_clk_get_by_clkspec() - Lookup a clock form a clock provider
- * @clkspec: pointer to a clock specifier data structure
- *
- * This function looks up a struct clk from the registered list of clock
- * providers, an input is a clock specifier data structure as returned
- * from the of_parse_phandle_with_args() function call.
- */
-struct clk *of_clk_get_by_clkspec(struct of_phandle_args *clkspec)
-{
-        return __of_clk_get_by_clkspec(clkspec, NULL, __func__);
-}
-
 static struct clk *__of_clk_get(struct device_node *np, int index,
                                const char *dev_id, const char *con_id)
 {
@@ -71,7 +43,7 @@ static struct clk *__of_clk_get(struct device_node *np, int index,
         if (rc)
                 return ERR_PTR(rc);
 
-        clk = __of_clk_get_by_clkspec(&clkspec, dev_id, con_id);
+        clk = __of_clk_get_from_provider(&clkspec, dev_id, con_id);
         of_node_put(clkspec.np);
 
         return clk;
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 3b34dba9178d..27696255486d 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -21,6 +21,10 @@ config ARMADA_38X_CLK
         bool
         select MVEBU_CLK_COMMON
 
+config ARMADA_39X_CLK
+        bool
+        select MVEBU_CLK_COMMON
+
 config ARMADA_XP_CLK
         bool
         select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index a9a56fc01901..645ac7ea3565 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_MVEBU_CLK_COREDIV)	+= clk-corediv.o
 obj-$(CONFIG_ARMADA_370_CLK)    += armada-370.o
 obj-$(CONFIG_ARMADA_375_CLK)    += armada-375.o
 obj-$(CONFIG_ARMADA_38X_CLK)    += armada-38x.o
+obj-$(CONFIG_ARMADA_39X_CLK)    += armada-39x.o
 obj-$(CONFIG_ARMADA_XP_CLK)     += armada-xp.o
 obj-$(CONFIG_DOVE_CLK)          += dove.o
 obj-$(CONFIG_KIRKWOOD_CLK)      += kirkwood.o
diff --git a/drivers/clk/mvebu/armada-39x.c b/drivers/clk/mvebu/armada-39x.c
new file mode 100644
index 000000000000..efb974df9822
--- /dev/null
+++ b/drivers/clk/mvebu/armada-39x.c
@@ -0,0 +1,156 @@
+/*
+ * Marvell Armada 39x SoC clocks
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * SARL[14:10] : Ratios between CPU, NBCLK, HCLK and DCLK.
+ *
+ * SARL[15]    : TCLK frequency
+ *               0 = 250 MHz
+ *               1 = 200 MHz
+ *
+ * SARH[0]     : Reference clock frequency
+ *               0 = 25 Mhz
+ *               1 = 40 Mhz
+ */
+
+#define SARL                                    0
+#define  SARL_A390_TCLK_FREQ_OPT                15
+#define  SARL_A390_TCLK_FREQ_OPT_MASK           0x1
+#define  SARL_A390_CPU_DDR_L2_FREQ_OPT          10
+#define  SARL_A390_CPU_DDR_L2_FREQ_OPT_MASK     0x1F
+#define SARH                                    4
+#define  SARH_A390_REFCLK_FREQ                  BIT(0)
+
+static const u32 armada_39x_tclk_frequencies[] __initconst = {
+        250000000,
+        200000000,
+};
+
+static u32 __init armada_39x_get_tclk_freq(void __iomem *sar)
+{
+        u8 tclk_freq_select;
+
+        tclk_freq_select = ((readl(sar + SARL) >> SARL_A390_TCLK_FREQ_OPT) &
+                            SARL_A390_TCLK_FREQ_OPT_MASK);
+        return armada_39x_tclk_frequencies[tclk_freq_select];
+}
+
+static const u32 armada_39x_cpu_frequencies[] __initconst = {
+        [0x0] = 666 * 1000 * 1000,
+        [0x2] = 800 * 1000 * 1000,
+        [0x3] = 800 * 1000 * 1000,
+        [0x4] = 1066 * 1000 * 1000,
+        [0x5] = 1066 * 1000 * 1000,
+        [0x6] = 1200 * 1000 * 1000,
+        [0x8] = 1332 * 1000 * 1000,
+        [0xB] = 1600 * 1000 * 1000,
+        [0xC] = 1600 * 1000 * 1000,
+        [0x12] = 1800 * 1000 * 1000,
+        [0x1E] = 1800 * 1000 * 1000,
+};
+
+static u32 __init armada_39x_get_cpu_freq(void __iomem *sar)
+{
+        u8 cpu_freq_select;
+
+        cpu_freq_select = ((readl(sar + SARL) >> SARL_A390_CPU_DDR_L2_FREQ_OPT) &
+                           SARL_A390_CPU_DDR_L2_FREQ_OPT_MASK);
+        if (cpu_freq_select >= ARRAY_SIZE(armada_39x_cpu_frequencies)) {
+                pr_err("Selected CPU frequency (%d) unsupported\n",
+                        cpu_freq_select);
+                return 0;
+        }
+
+        return armada_39x_cpu_frequencies[cpu_freq_select];
+}
+
+enum { A390_CPU_TO_NBCLK, A390_CPU_TO_HCLK, A390_CPU_TO_DCLK };
+
+static const struct coreclk_ratio armada_39x_coreclk_ratios[] __initconst = {
+        { .id = A390_CPU_TO_NBCLK, .name = "nbclk" },
+        { .id = A390_CPU_TO_HCLK, .name = "hclk" },
+        { .id = A390_CPU_TO_DCLK, .name = "dclk" },
+};
+
+static void __init armada_39x_get_clk_ratio(
+        void __iomem *sar, int id, int *mult, int *div)
+{
+        switch (id) {
+        case A390_CPU_TO_NBCLK:
+                *mult = 1;
+                *div = 2;
+                break;
+        case A390_CPU_TO_HCLK:
+                *mult = 1;
+                *div = 4;
+                break;
+        case A390_CPU_TO_DCLK:
+                *mult = 1;
+                *div = 2;
+                break;
+        }
+}
+
+static u32 __init armada_39x_refclk_ratio(void __iomem *sar)
+{
+        if (readl(sar + SARH) & SARH_A390_REFCLK_FREQ)
+                return 40 * 1000 * 1000;
+        else
+                return 25 * 1000 * 1000;
+}
+
+static const struct coreclk_soc_desc armada_39x_coreclks = {
+        .get_tclk_freq = armada_39x_get_tclk_freq,
+        .get_cpu_freq = armada_39x_get_cpu_freq,
+        .get_clk_ratio = armada_39x_get_clk_ratio,
+        .get_refclk_freq = armada_39x_refclk_ratio,
+        .ratios = armada_39x_coreclk_ratios,
+        .num_ratios = ARRAY_SIZE(armada_39x_coreclk_ratios),
+};
+
+static void __init armada_39x_coreclk_init(struct device_node *np)
+{
+        mvebu_coreclk_setup(np, &armada_39x_coreclks);
+}
+CLK_OF_DECLARE(armada_39x_core_clk, "marvell,armada-390-core-clock",
+               armada_39x_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+static const struct clk_gating_soc_desc armada_39x_gating_desc[] __initconst = {
+        { "pex1", NULL, 5 },
+        { "pex2", NULL, 6 },
+        { "pex3", NULL, 7 },
+        { "pex0", NULL, 8 },
+        { "usb3h0", NULL, 9 },
+        { "sdio", NULL, 17 },
+        { "xor0", NULL, 22 },
+        { "xor1", NULL, 28 },
+        { }
+};
+
+static void __init armada_39x_clk_gating_init(struct device_node *np)
+{
+        mvebu_clk_gating_setup(np, armada_39x_gating_desc);
+}
+CLK_OF_DECLARE(armada_39x_clk_gating, "marvell,armada-390-gating-clock",
+               armada_39x_clk_gating_init);
diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
index 0d4d1216f2dd..15b370ff3748 100644
--- a/drivers/clk/mvebu/common.c
+++ b/drivers/clk/mvebu/common.c
@@ -121,6 +121,11 @@ void __init mvebu_coreclk_setup(struct device_node *np,
 
         /* Allocate struct for TCLK, cpu clk, and core ratio clocks */
         clk_data.clk_num = 2 + desc->num_ratios;
+
+        /* One more clock for the optional refclk */
+        if (desc->get_refclk_freq)
+                clk_data.clk_num += 1;
+
         clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
                                 GFP_KERNEL);
         if (WARN_ON(!clk_data.clks)) {
@@ -162,6 +167,18 @@ void __init mvebu_coreclk_setup(struct device_node *np,
                 WARN_ON(IS_ERR(clk_data.clks[2+n]));
         };
 
+        /* Register optional refclk */
+        if (desc->get_refclk_freq) {
+                const char *name = "refclk";
+                of_property_read_string_index(np, "clock-output-names",
+                                              2 + desc->num_ratios, &name);
+                rate = desc->get_refclk_freq(base);
+                clk_data.clks[2 + desc->num_ratios] =
+                        clk_register_fixed_rate(NULL, name, NULL,
+                                                CLK_IS_ROOT, rate);
+                WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios]));
+        }
+
         /* SAR register isn't needed anymore */
         iounmap(base);
 
diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h
index 783b5631a453..f0de6c8a494a 100644
--- a/drivers/clk/mvebu/common.h
+++ b/drivers/clk/mvebu/common.h
@@ -30,6 +30,7 @@ struct coreclk_soc_desc {
         u32 (*get_tclk_freq)(void __iomem *sar);
         u32 (*get_cpu_freq)(void __iomem *sar);
         void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
+        u32 (*get_refclk_freq)(void __iomem *sar);
         bool (*is_sscg_enabled)(void __iomem *sar);
         u32 (*fix_sscg_deviation)(u32 system_clk);
         const struct coreclk_ratio *ratios;
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 0d7ab52b7ab0..48d51512d009 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -46,6 +46,14 @@ config MSM_GCC_8660
           Say Y if you want to use peripheral devices such as UART, SPI,
           i2c, USB, SD/eMMC, etc.
 
+config MSM_GCC_8916
+        tristate "MSM8916 Global Clock Controller"
+        depends on COMMON_CLK_QCOM
+        help
+          Support for the global clock controller on msm8916 devices.
+          Say Y if you want to use devices such as UART, SPI i2c, USB,
+          SD/eMMC, display, graphics, camera etc.
+
 config MSM_GCC_8960
         tristate "APQ8064/MSM8960 Global Clock Controller"
         depends on COMMON_CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 617826469595..50b337a24a87 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
 obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
 obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
 obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
+obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o
 obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
 obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
 obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c
index 0039bd7d3965..8f2f48071a7a 100644
--- a/drivers/clk/qcom/clk-rcg.c
+++ b/drivers/clk/qcom/clk-rcg.c
@@ -47,15 +47,20 @@ static u8 clk_rcg_get_parent(struct clk_hw *hw)
         struct clk_rcg *rcg = to_clk_rcg(hw);
         int num_parents = __clk_get_num_parents(hw->clk);
         u32 ns;
-        int i;
+        int i, ret;
 
-        regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
+        ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
+        if (ret)
+                goto err;
         ns = ns_to_src(&rcg->s, ns);
         for (i = 0; i < num_parents; i++)
-                if (ns == rcg->s.parent_map[i])
+                if (ns == rcg->s.parent_map[i].cfg)
                         return i;
 
-        return -EINVAL;
+err:
+        pr_debug("%s: Clock %s has invalid parent, using default.\n",
+                 __func__, __clk_get_name(hw->clk));
+        return 0;
 }
 
 static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank)
@@ -70,21 +75,28 @@ static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
         int num_parents = __clk_get_num_parents(hw->clk);
         u32 ns, reg;
         int bank;
-        int i;
+        int i, ret;
         struct src_sel *s;
 
-        regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
+        ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
+        if (ret)
+                goto err;
         bank = reg_to_bank(rcg, reg);
         s = &rcg->s[bank];
 
-        regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
+        ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
+        if (ret)
+                goto err;
         ns = ns_to_src(s, ns);
 
         for (i = 0; i < num_parents; i++)
-                if (ns == s->parent_map[i])
+                if (ns == s->parent_map[i].cfg)
                         return i;
 
-        return -EINVAL;
+err:
+        pr_debug("%s: Clock %s has invalid parent, using default.\n",
+                 __func__, __clk_get_name(hw->clk));
+        return 0;
 }
 
 static int clk_rcg_set_parent(struct clk_hw *hw, u8 index)
@@ -93,7 +105,7 @@ static int clk_rcg_set_parent(struct clk_hw *hw, u8 index)
         u32 ns;
 
         regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
-        ns = src_to_ns(&rcg->s, rcg->s.parent_map[index], ns);
+        ns = src_to_ns(&rcg->s, rcg->s.parent_map[index].cfg, ns);
         regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
 
         return 0;
@@ -191,10 +203,10 @@ static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)
         return val;
 }
 
-static void configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
+static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
 {
         u32 ns, md, reg;
-        int bank, new_bank;
+        int bank, new_bank, ret, index;
         struct mn *mn;
         struct pre_div *p;
         struct src_sel *s;
@@ -206,38 +218,56 @@ static void configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
 
         enabled = __clk_is_enabled(hw->clk);
 
-        regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
+        ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
+        if (ret)
+                return ret;
         bank = reg_to_bank(rcg, reg);
         new_bank = enabled ? !bank : bank;
 
         ns_reg = rcg->ns_reg[new_bank];
-        regmap_read(rcg->clkr.regmap, ns_reg, &ns);
+        ret = regmap_read(rcg->clkr.regmap, ns_reg, &ns);
+        if (ret)
+                return ret;
 
         if (banked_mn) {
                 mn = &rcg->mn[new_bank];
                 md_reg = rcg->md_reg[new_bank];
 
                 ns |= BIT(mn->mnctr_reset_bit);
-                regmap_write(rcg->clkr.regmap, ns_reg, ns);
+                ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
+                if (ret)
+                        return ret;
 
-                regmap_read(rcg->clkr.regmap, md_reg, &md);
+                ret = regmap_read(rcg->clkr.regmap, md_reg, &md);
+                if (ret)
+                        return ret;
                 md = mn_to_md(mn, f->m, f->n, md);
-                regmap_write(rcg->clkr.regmap, md_reg, md);
-
+                ret = regmap_write(rcg->clkr.regmap, md_reg, md);
+                if (ret)
+                        return ret;
                 ns = mn_to_ns(mn, f->m, f->n, ns);
-                regmap_write(rcg->clkr.regmap, ns_reg, ns);
+                ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
+                if (ret)
+                        return ret;
 
                 /* Two NS registers means mode control is in NS register */
                 if (rcg->ns_reg[0] != rcg->ns_reg[1]) {
                         ns = mn_to_reg(mn, f->m, f->n, ns);
-                        regmap_write(rcg->clkr.regmap, ns_reg, ns);
+                        ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
+                        if (ret)
+                                return ret;
                 } else {
                         reg = mn_to_reg(mn, f->m, f->n, reg);
-                        regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
+                        ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg,
+                                           reg);
+                        if (ret)
+                                return ret;
                 }
 
                 ns &= ~BIT(mn->mnctr_reset_bit);
-                regmap_write(rcg->clkr.regmap, ns_reg, ns);
+                ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
+                if (ret)
+                        return ret;
         }
 
         if (banked_p) {
@@ -246,14 +276,24 @@ static void configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
         }
 
         s = &rcg->s[new_bank];
-        ns = src_to_ns(s, s->parent_map[f->src], ns);
-        regmap_write(rcg->clkr.regmap, ns_reg, ns);
+        index = qcom_find_src_index(hw, s->parent_map, f->src);
+        if (index < 0)
+                return index;
+        ns = src_to_ns(s, s->parent_map[index].cfg, ns);
+        ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
+        if (ret)
+                return ret;
 
         if (enabled) {
-                regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
+                ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
+                if (ret)
+                        return ret;
                 reg ^= BIT(rcg->mux_sel_bit);
-                regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
+                ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
+                if (ret)
+                        return ret;
         }
+        return 0;
 }
 
 static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)
@@ -280,9 +320,7 @@ static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)
                 f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;
 
         f.src = index;
-        configure_bank(rcg, &f);
-
-        return 0;
+        return configure_bank(rcg, &f);
 }
 
 /*
@@ -495,6 +533,57 @@ static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate,
         return __clk_rcg_set_rate(rcg, rcg->freq_tbl);
 }
 
+/*
+ * This type of clock has a glitch-free mux that switches between the output of
+ * the M/N counter and an always on clock source (XO). When clk_set_rate() is
+ * called we need to make sure that we don't switch to the M/N counter if it
+ * isn't clocking because the mux will get stuck and the clock will stop
+ * outputting a clock. This can happen if the framework isn't aware that this
+ * clock is on and so clk_set_rate() doesn't turn on the new parent. To fix
+ * this we switch the mux in the enable/disable ops and reprogram the M/N
+ * counter in the set_rate op. We also make sure to switch away from the M/N
+ * counter in set_rate if software thinks the clock is off.
+ */
+static int clk_rcg_lcc_set_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate)
+{
+        struct clk_rcg *rcg = to_clk_rcg(hw);
+        const struct freq_tbl *f;
+        int ret;
+        u32 gfm = BIT(10);
+
+        f = qcom_find_freq(rcg->freq_tbl, rate);
+        if (!f)
+                return -EINVAL;
+
+        /* Switch to XO to avoid glitches */
+        regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);
+        ret = __clk_rcg_set_rate(rcg, f);
+        /* Switch back to M/N if it's clocking */
+        if (__clk_is_enabled(hw->clk))
+                regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);
+
+        return ret;
+}
+
+static int clk_rcg_lcc_enable(struct clk_hw *hw)
+{
+        struct clk_rcg *rcg = to_clk_rcg(hw);
+        u32 gfm = BIT(10);
+
+        /* Use M/N */
+        return regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);
+}
+
+static void clk_rcg_lcc_disable(struct clk_hw *hw)
+{
+        struct clk_rcg *rcg = to_clk_rcg(hw);
+        u32 gfm = BIT(10);
+
+        /* Use XO */
+        regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);
+}
+
 static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate)
 {
         struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
@@ -504,9 +593,7 @@ static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate)
         if (!f)
                 return -EINVAL;
 
-        configure_bank(rcg, f);
-
-        return 0;
+        return configure_bank(rcg, f);
 }
 
 static int clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -543,6 +630,17 @@ const struct clk_ops clk_rcg_bypass_ops = {
 };
 EXPORT_SYMBOL_GPL(clk_rcg_bypass_ops);
 
+const struct clk_ops clk_rcg_lcc_ops = {
+        .enable = clk_rcg_lcc_enable,
+        .disable = clk_rcg_lcc_disable,
+        .get_parent = clk_rcg_get_parent,
+        .set_parent = clk_rcg_set_parent,
+        .recalc_rate = clk_rcg_recalc_rate,
+        .determine_rate = clk_rcg_determine_rate,
+        .set_rate = clk_rcg_lcc_set_rate,
+};
+EXPORT_SYMBOL_GPL(clk_rcg_lcc_ops);
+
 const struct clk_ops clk_dyn_rcg_ops = {
         .enable = clk_enable_regmap,
         .is_enabled = clk_is_enabled_regmap,
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index 687e41f91d7c..56028bb31d87 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -26,6 +26,16 @@ struct freq_tbl {
 };
 
 /**
+ * struct parent_map - map table for PLL source select configuration values
+ * @src: source PLL
+ * @cfg: configuration value
+ */
+struct parent_map {
+        u8 src;
+        u8 cfg;
+};
+
+/**
  * struct mn - M/N:D counter
  * @mnctr_en_bit: bit to enable mn counter
  * @mnctr_reset_bit: bit to assert mn counter reset
@@ -65,7 +75,7 @@ struct pre_div {
 struct src_sel {
         u8              src_sel_shift;
 #define SRC_SEL_MASK    0x7
-        const u8        *parent_map;
+        const struct parent_map *parent_map;
 };
 
 /**
@@ -96,6 +106,7 @@ struct clk_rcg {
 
 extern const struct clk_ops clk_rcg_ops;
 extern const struct clk_ops clk_rcg_bypass_ops;
+extern const struct clk_ops clk_rcg_lcc_ops;
 
 #define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr)
 
@@ -150,7 +161,7 @@ struct clk_rcg2 {
         u32                     cmd_rcgr;
         u8                      mnd_width;
         u8                      hid_width;
-        const u8                *parent_map;
+        const struct parent_map *parent_map;
         const struct freq_tbl   *freq_tbl;
         struct clk_regmap       clkr;
 };
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 742acfa18d63..416becce4170 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -69,16 +69,19 @@ static u8 clk_rcg2_get_parent(struct clk_hw *hw)
 
         ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
         if (ret)
-                return ret;
+                goto err;
 
         cfg &= CFG_SRC_SEL_MASK;
         cfg >>= CFG_SRC_SEL_SHIFT;
 
         for (i = 0; i < num_parents; i++)
-                if (cfg == rcg->parent_map[i])
+                if (cfg == rcg->parent_map[i].cfg)
                         return i;
 
-        return -EINVAL;
+err:
+        pr_debug("%s: Clock %s has invalid parent, using default.\n",
+                 __func__, __clk_get_name(hw->clk));
+        return 0;
 }
 
 static int update_config(struct clk_rcg2 *rcg)
@@ -111,10 +114,10 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
 {
         struct clk_rcg2 *rcg = to_clk_rcg2(hw);
         int ret;
+        u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
 
         ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
-                                 CFG_SRC_SEL_MASK,
-                                 rcg->parent_map[index] << CFG_SRC_SEL_SHIFT);
+                                 CFG_SRC_SEL_MASK, cfg);
         if (ret)
                 return ret;
 
@@ -219,7 +222,11 @@ static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
 static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
 {
         u32 cfg, mask;
-        int ret;
+        struct clk_hw *hw = &rcg->clkr.hw;
+        int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
+
+        if (index < 0)
+                return index;
 
         if (rcg->mnd_width && f->n) {
                 mask = BIT(rcg->mnd_width) - 1;
@@ -242,8 +249,8 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
         mask = BIT(rcg->hid_width) - 1;
         mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
         cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
-        cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT;
-        if (rcg->mnd_width && f->n)
+        cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
+        if (rcg->mnd_width && f->n && (f->m != f->n))
                 cfg |= CFG_MODE_DUAL_EDGE;
         ret = regmap_update_bits(rcg->clkr.regmap,
                         rcg->cmd_rcgr + CFG_REG, mask, cfg);
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index e20d947db3e5..f7101e330b1d 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -43,6 +43,18 @@ struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
 }
 EXPORT_SYMBOL_GPL(qcom_find_freq);
 
+int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src)
+{
+        int i, num_parents = __clk_get_num_parents(hw->clk);
+
+        for (i = 0; i < num_parents; i++)
+                if (src == map[i].src)
+                        return i;
+
+        return -ENOENT;
+}
+EXPORT_SYMBOL_GPL(qcom_find_src_index);
+
 struct regmap *
 qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc)
 {
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index f519322acdf3..7a0e73713063 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -19,6 +19,8 @@ struct clk_regmap;
 struct qcom_reset_map;
 struct regmap;
 struct freq_tbl;
+struct clk_hw;
+struct parent_map;
 
 struct qcom_cc_desc {
         const struct regmap_config *config;
@@ -30,6 +32,8 @@ struct qcom_cc_desc {
 
 extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
                                              unsigned long rate);
+extern int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map,
+                               u8 src);
 
 extern struct regmap *qcom_cc_map(struct platform_device *pdev,
                                   const struct qcom_cc_desc *desc);
diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
index e3ef90264214..54a756b90a37 100644
--- a/drivers/clk/qcom/gcc-apq8084.c
+++ b/drivers/clk/qcom/gcc-apq8084.c
@@ -32,18 +32,20 @@
 #include "clk-branch.h"
 #include "reset.h"
 
-#define P_XO    0
-#define P_GPLL0 1
-#define P_GPLL1 1
-#define P_GPLL4 2
-#define P_PCIE_0_1_PIPE_CLK 1
-#define P_SATA_ASIC0_CLK 1
-#define P_SATA_RX_CLK 1
-#define P_SLEEP_CLK 1
+enum {
+        P_XO,
+        P_GPLL0,
+        P_GPLL1,
+        P_GPLL4,
+        P_PCIE_0_1_PIPE_CLK,
+        P_SATA_ASIC0_CLK,
+        P_SATA_RX_CLK,
+        P_SLEEP_CLK,
+};
 
-static const u8 gcc_xo_gpll0_map[] = {
-        [P_XO]          = 0,
-        [P_GPLL0]       = 1,
+static const struct parent_map gcc_xo_gpll0_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0, 1 }
 };
 
 static const char *gcc_xo_gpll0[] = {
@@ -51,10 +53,10 @@ static const char *gcc_xo_gpll0[] = {
         "gpll0_vote",
 };
 
-static const u8 gcc_xo_gpll0_gpll4_map[] = {
-        [P_XO]          = 0,
-        [P_GPLL0]       = 1,
-        [P_GPLL4]       = 5,
+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0, 1 },
+        { P_GPLL4, 5 }
 };
 
 static const char *gcc_xo_gpll0_gpll4[] = {
@@ -63,9 +65,9 @@ static const char *gcc_xo_gpll0_gpll4[] = {
         "gpll4_vote",
 };
 
-static const u8 gcc_xo_sata_asic0_map[] = {
-        [P_XO]                  = 0,
-        [P_SATA_ASIC0_CLK]      = 2,
+static const struct parent_map gcc_xo_sata_asic0_map[] = {
+        { P_XO, 0 },
+        { P_SATA_ASIC0_CLK, 2 }
 };
 
 static const char *gcc_xo_sata_asic0[] = {
@@ -73,9 +75,9 @@ static const char *gcc_xo_sata_asic0[] = {
         "sata_asic0_clk",
 };
 
-static const u8 gcc_xo_sata_rx_map[] = {
-        [P_XO]                  = 0,
-        [P_SATA_RX_CLK]         = 2,
+static const struct parent_map gcc_xo_sata_rx_map[] = {
+        { P_XO, 0 },
+        { P_SATA_RX_CLK, 2}
 };
 
 static const char *gcc_xo_sata_rx[] = {
@@ -83,9 +85,9 @@ static const char *gcc_xo_sata_rx[] = {
         "sata_rx_clk",
 };
 
-static const u8 gcc_xo_pcie_map[] = {
-        [P_XO]                  = 0,
-        [P_PCIE_0_1_PIPE_CLK]   = 2,
+static const struct parent_map gcc_xo_pcie_map[] = {
+        { P_XO, 0 },
+        { P_PCIE_0_1_PIPE_CLK, 2 }
 };
 
 static const char *gcc_xo_pcie[] = {
@@ -93,9 +95,9 @@ static const char *gcc_xo_pcie[] = {
         "pcie_pipe",
 };
 
-static const u8 gcc_xo_pcie_sleep_map[] = {
-        [P_XO]                  = 0,
-        [P_SLEEP_CLK]           = 6,
+static const struct parent_map gcc_xo_pcie_sleep_map[] = {
+        { P_XO, 0 },
+        { P_SLEEP_CLK, 6 }
 };
 
 static const char *gcc_xo_pcie_sleep[] = {
@@ -1263,9 +1265,9 @@ static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
         { }
 };
 
-static u8 usb_hsic_clk_src_map[] = {
-        [P_XO]          = 0,
-        [P_GPLL1]       = 4,
+static const struct parent_map usb_hsic_clk_src_map[] = {
+        { P_XO, 0 },
+        { P_GPLL1, 4 }
 };
 
 static struct clk_rcg2 usb_hsic_clk_src = {
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index cbdc31dea7f4..ee73cc7f6e55 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -140,15 +140,17 @@ static struct clk_regmap pll14_vote = {
         },
 };
 
-#define P_PXO   0
-#define P_PLL8  1
-#define P_PLL3  1
-#define P_PLL0  2
-#define P_CXO   2
+enum {
+        P_PXO,
+        P_PLL8,
+        P_PLL3,
+        P_PLL0,
+        P_CXO,
+};
 
-static const u8 gcc_pxo_pll8_map[] = {
-        [P_PXO]         = 0,
-        [P_PLL8]        = 3,
+static const struct parent_map gcc_pxo_pll8_map[] = {
+        { P_PXO, 0 },
+        { P_PLL8, 3 }
 };
 
 static const char *gcc_pxo_pll8[] = {
@@ -156,10 +158,10 @@ static const char *gcc_pxo_pll8[] = {
         "pll8_vote",
 };
 
-static const u8 gcc_pxo_pll8_cxo_map[] = {
-        [P_PXO]         = 0,
-        [P_PLL8]        = 3,
-        [P_CXO]         = 5,
+static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
+        { P_PXO, 0 },
+        { P_PLL8, 3 },
+        { P_CXO, 5 }
 };
 
 static const char *gcc_pxo_pll8_cxo[] = {
@@ -168,14 +170,14 @@ static const char *gcc_pxo_pll8_cxo[] = {
         "cxo",
 };
 
-static const u8 gcc_pxo_pll3_map[] = {
-        [P_PXO]         = 0,
-        [P_PLL3]        = 1,
+static const struct parent_map gcc_pxo_pll3_map[] = {
+        { P_PXO, 0 },
+        { P_PLL3, 1 }
 };
 
-static const u8 gcc_pxo_pll3_sata_map[] = {
-        [P_PXO]         = 0,
-        [P_PLL3]        = 6,
+static const struct parent_map gcc_pxo_pll3_sata_map[] = {
+        { P_PXO, 0 },
+        { P_PLL3, 6 }
 };
 
 static const char *gcc_pxo_pll3[] = {
@@ -183,10 +185,10 @@ static const char *gcc_pxo_pll3[] = {
         "pll3",
 };
 
-static const u8 gcc_pxo_pll8_pll0[] = {
-        [P_PXO]         = 0,
-        [P_PLL8]        = 3,
-        [P_PLL0]        = 2,
+static const struct parent_map gcc_pxo_pll8_pll0[] = {
+        { P_PXO, 0 },
+        { P_PLL8, 3 },
+        { P_PLL0, 2 }
 };
 
 static const char *gcc_pxo_pll8_pll0_map[] = {
@@ -525,8 +527,8 @@ static struct freq_tbl clk_tbl_gsbi_qup[] = {
         { 10800000, P_PXO,  1, 2,  5 },
         { 15060000, P_PLL8, 1, 2, 51 },
         { 24000000, P_PLL8, 4, 1,  4 },
+        { 25000000, P_PXO,  1, 0,  0 },
         { 25600000, P_PLL8, 1, 1, 15 },
-        { 27000000, P_PXO,  1, 0,  0 },
         { 48000000, P_PLL8, 4, 1,  2 },
         { 51200000, P_PLL8, 1, 2, 15 },
         { }
diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm8660.c
index f366e68f7316..fc6b12da5b30 100644
--- a/drivers/clk/qcom/gcc-msm8660.c
+++ b/drivers/clk/qcom/gcc-msm8660.c
@@ -59,13 +59,15 @@ static struct clk_regmap pll8_vote = {
         },
 };
 
-#define P_PXO   0
-#define P_PLL8  1
-#define P_CXO   2
+enum {
+        P_PXO,
+        P_PLL8,
+        P_CXO,
+};
 
-static const u8 gcc_pxo_pll8_map[] = {
-        [P_PXO]         = 0,
-        [P_PLL8]        = 3,
+static const struct parent_map gcc_pxo_pll8_map[] = {
+        { P_PXO, 0 },
+        { P_PLL8, 3 }
 };
 
 static const char *gcc_pxo_pll8[] = {
@@ -73,10 +75,10 @@ static const char *gcc_pxo_pll8[] = {
         "pll8_vote",
 };
 
-static const u8 gcc_pxo_pll8_cxo_map[] = {
-        [P_PXO]         = 0,
-        [P_PLL8]        = 3,
-        [P_CXO]         = 5,
+static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
+        { P_PXO, 0 },
+        { P_PLL8, 3 },
+        { P_CXO, 5 }
 };
 
 static const char *gcc_pxo_pll8_cxo[] = {
diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
new file mode 100644
index 000000000000..d3458474eb3a
--- /dev/null
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -0,0 +1,2868 @@
+/*
+ * Copyright 2015 Linaro Limited
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/clock/qcom,gcc-msm8916.h>
+#include <dt-bindings/reset/qcom,gcc-msm8916.h>
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "reset.h"
+
+enum {
+        P_XO,
+        P_GPLL0,
+        P_GPLL0_AUX,
+        P_BIMC,
+        P_GPLL1,
+        P_GPLL1_AUX,
+        P_GPLL2,
+        P_GPLL2_AUX,
+        P_SLEEP_CLK,
+        P_DSI0_PHYPLL_BYTE,
+        P_DSI0_PHYPLL_DSI,
+};
+
+static const struct parent_map gcc_xo_gpll0_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0, 1 },
+};
+
+static const char *gcc_xo_gpll0[] = {
+        "xo",
+        "gpll0_vote",
+};
+
+static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0, 1 },
+        { P_BIMC, 2 },
+};
+
+static const char *gcc_xo_gpll0_bimc[] = {
+        "xo",
+        "gpll0_vote",
+        "bimc_pll_vote",
+};
+
+static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0_AUX, 3 },
+        { P_GPLL2_AUX, 2 },
+        { P_GPLL1, 1 },
+};
+
+static const char *gcc_xo_gpll0a_gpll1_gpll2a[] = {
+        "xo",
+        "gpll0_vote",
+        "gpll1_vote",
+        "gpll2_vote",
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0, 1 },
+        { P_GPLL2, 2 },
+};
+
+static const char *gcc_xo_gpll0_gpll2[] = {
+        "xo",
+        "gpll0_vote",
+        "gpll2_vote",
+};
+
+static const struct parent_map gcc_xo_gpll0a_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0_AUX, 2 },
+};
+
+static const char *gcc_xo_gpll0a[] = {
+        "xo",
+        "gpll0_vote",
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0, 1 },
+        { P_GPLL1_AUX, 2 },
+        { P_SLEEP_CLK, 6 },
+};
+
+static const char *gcc_xo_gpll0_gpll1a_sleep[] = {
+        "xo",
+        "gpll0_vote",
+        "gpll1_vote",
+        "sleep_clk",
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0, 1 },
+        { P_GPLL1_AUX, 2 },
+};
+
+static const char *gcc_xo_gpll0_gpll1a[] = {
+        "xo",
+        "gpll0_vote",
+        "gpll1_vote",
+};
+
+static const struct parent_map gcc_xo_dsibyte_map[] = {
+        { P_XO, 0, },
+        { P_DSI0_PHYPLL_BYTE, 2 },
+};
+
+static const char *gcc_xo_dsibyte[] = {
+        "xo",
+        "dsi0pllbyte",
+};
+
+static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0_AUX, 2 },
+        { P_DSI0_PHYPLL_BYTE, 1 },
+};
+
+static const char *gcc_xo_gpll0a_dsibyte[] = {
+        "xo",
+        "gpll0_vote",
+        "dsi0pllbyte",
+};
+
+static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0, 1 },
+        { P_DSI0_PHYPLL_DSI, 2 },
+};
+
+static const char *gcc_xo_gpll0_dsiphy[] = {
+        "xo",
+        "gpll0_vote",
+        "dsi0pll",
+};
+
+static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0_AUX, 2 },
+        { P_DSI0_PHYPLL_DSI, 1 },
+};
+
+static const char *gcc_xo_gpll0a_dsiphy[] = {
+        "xo",
+        "gpll0_vote",
+        "dsi0pll",
+};
+
+static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0_AUX, 1 },
+        { P_GPLL1, 3 },
+        { P_GPLL2, 2 },
+};
+
+static const char *gcc_xo_gpll0a_gpll1_gpll2[] = {
+        "xo",
+        "gpll0_vote",
+        "gpll1_vote",
+        "gpll2_vote",
+};
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+static struct clk_pll gpll0 = {
+        .l_reg = 0x21004,
+        .m_reg = 0x21008,
+        .n_reg = 0x2100c,
+        .config_reg = 0x21014,
+        .mode_reg = 0x21000,
+        .status_reg = 0x2101c,
+        .status_bit = 17,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll0",
+                .parent_names = (const char *[]){ "xo" },
+                .num_parents = 1,
+                .ops = &clk_pll_ops,
+        },
+};
+
+static struct clk_regmap gpll0_vote = {
+        .enable_reg = 0x45000,
+        .enable_mask = BIT(0),
+        .hw.init = &(struct clk_init_data){
+                .name = "gpll0_vote",
+                .parent_names = (const char *[]){ "gpll0" },
+                .num_parents = 1,
+                .ops = &clk_pll_vote_ops,
+        },
+};
+
+static struct clk_pll gpll1 = {
+        .l_reg = 0x20004,
+        .m_reg = 0x20008,
+        .n_reg = 0x2000c,
+        .config_reg = 0x20014,
+        .mode_reg = 0x20000,
+        .status_reg = 0x2001c,
+        .status_bit = 17,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll1",
+                .parent_names = (const char *[]){ "xo" },
+                .num_parents = 1,
+                .ops = &clk_pll_ops,
+        },
+};
+
+static struct clk_regmap gpll1_vote = {
+        .enable_reg = 0x45000,
+        .enable_mask = BIT(1),
+        .hw.init = &(struct clk_init_data){
+                .name = "gpll1_vote",
+                .parent_names = (const char *[]){ "gpll1" },
+                .num_parents = 1,
+                .ops = &clk_pll_vote_ops,
+        },
+};
+
+static struct clk_pll gpll2 = {
+        .l_reg = 0x4a004,
+        .m_reg = 0x4a008,
+        .n_reg = 0x4a00c,
+        .config_reg = 0x4a014,
+        .mode_reg = 0x4a000,
+        .status_reg = 0x4a01c,
+        .status_bit = 17,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll2",
+                .parent_names = (const char *[]){ "xo" },
+                .num_parents = 1,
+                .ops = &clk_pll_ops,
+        },
+};
+
+static struct clk_regmap gpll2_vote = {
+        .enable_reg = 0x45000,
+        .enable_mask = BIT(2),
+        .hw.init = &(struct clk_init_data){
+                .name = "gpll2_vote",
+                .parent_names = (const char *[]){ "gpll2" },
+                .num_parents = 1,
+                .ops = &clk_pll_vote_ops,
+        },
+};
+
+static struct clk_pll bimc_pll = {
+        .l_reg = 0x23004,
+        .m_reg = 0x23008,
+        .n_reg = 0x2300c,
+        .config_reg = 0x23014,
+        .mode_reg = 0x23000,
+        .status_reg = 0x2301c,
+        .status_bit = 17,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "bimc_pll",
+                .parent_names = (const char *[]){ "xo" },
+                .num_parents = 1,
+                .ops = &clk_pll_ops,
+        },
+};
+
+static struct clk_regmap bimc_pll_vote = {
+        .enable_reg = 0x45000,
+        .enable_mask = BIT(3),
+        .hw.init = &(struct clk_init_data){
+                .name = "bimc_pll_vote",
+                .parent_names = (const char *[]){ "bimc_pll" },
+                .num_parents = 1,
+                .ops = &clk_pll_vote_ops,
+        },
+};
+
+static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
+        .cmd_rcgr = 0x27000,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_bimc_map,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "pcnoc_bfdcd_clk_src",
+                .parent_names = gcc_xo_gpll0_bimc,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 system_noc_bfdcd_clk_src = {
+        .cmd_rcgr = 0x26004,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_bimc_map,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "system_noc_bfdcd_clk_src",
+                .parent_names = gcc_xo_gpll0_bimc,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
+        F(40000000, P_GPLL0, 10, 1, 2),
+        F(80000000, P_GPLL0, 10, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 camss_ahb_clk_src = {
+        .cmd_rcgr = 0x5a000,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_camss_ahb_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "camss_ahb_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_apss_ahb_clk[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        F(50000000, P_GPLL0, 16, 0, 0),
+        F(100000000, P_GPLL0, 8, 0, 0),
+        F(133330000, P_GPLL0, 6, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 apss_ahb_clk_src = {
+        .cmd_rcgr = 0x46000,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_apss_ahb_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "apss_ahb_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
+        F(100000000, P_GPLL0, 8, 0,     0),
+        F(200000000, P_GPLL0, 4, 0,     0),
+        { }
+};
+
+static struct clk_rcg2 csi0_clk_src = {
+        .cmd_rcgr = 0x4e020,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "csi0_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 csi1_clk_src = {
+        .cmd_rcgr = 0x4f020,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "csi1_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        F(50000000, P_GPLL0_AUX, 16, 0, 0),
+        F(80000000, P_GPLL0_AUX, 10, 0, 0),
+        F(100000000, P_GPLL0_AUX, 8, 0, 0),
+        F(160000000, P_GPLL0_AUX, 5, 0, 0),
+        F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
+        F(200000000, P_GPLL0_AUX, 4, 0, 0),
+        F(266670000, P_GPLL0_AUX, 3, 0, 0),
+        F(294912000, P_GPLL1, 3, 0, 0),
+        F(310000000, P_GPLL2, 3, 0, 0),
+        F(400000000, P_GPLL0_AUX, 2, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gfx3d_clk_src = {
+        .cmd_rcgr = 0x59000,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0a_gpll1_gpll2a_map,
+        .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gfx3d_clk_src",
+                .parent_names = gcc_xo_gpll0a_gpll1_gpll2a,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
+        F(50000000, P_GPLL0, 16, 0, 0),
+        F(80000000, P_GPLL0, 10, 0, 0),
+        F(100000000, P_GPLL0, 8, 0, 0),
+        F(160000000, P_GPLL0, 5, 0, 0),
+        F(177780000, P_GPLL0, 4.5, 0, 0),
+        F(200000000, P_GPLL0, 4, 0, 0),
+        F(266670000, P_GPLL0, 3, 0, 0),
+        F(320000000, P_GPLL0, 2.5, 0, 0),
+        F(400000000, P_GPLL0, 2, 0, 0),
+        F(465000000, P_GPLL2, 2, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 vfe0_clk_src = {
+        .cmd_rcgr = 0x58000,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_gpll2_map,
+        .freq_tbl = ftbl_gcc_camss_vfe0_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "vfe0_clk_src",
+                .parent_names = gcc_xo_gpll0_gpll2,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        F(50000000, P_GPLL0, 16, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x0200c,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup1_i2c_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
+        F(960000, P_XO, 10, 1, 2),
+        F(4800000, P_XO, 4, 0, 0),
+        F(9600000, P_XO, 2, 0, 0),
+        F(16000000, P_GPLL0, 10, 1, 5),
+        F(19200000, P_XO, 1, 0, 0),
+        F(25000000, P_GPLL0, 16, 1, 2),
+        F(50000000, P_GPLL0, 16, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
+        .cmd_rcgr = 0x02024,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup1_spi_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x03000,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup2_i2c_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
+        .cmd_rcgr = 0x03014,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup2_spi_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x04000,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup3_i2c_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
+        .cmd_rcgr = 0x04024,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup3_spi_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x05000,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup4_i2c_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
+        .cmd_rcgr = 0x05024,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup4_spi_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x06000,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup5_i2c_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
+        .cmd_rcgr = 0x06024,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup5_spi_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x07000,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup6_i2c_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
+        .cmd_rcgr = 0x07024,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup6_spi_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
+        F(3686400, P_GPLL0, 1, 72, 15625),
+        F(7372800, P_GPLL0, 1, 144, 15625),
+        F(14745600, P_GPLL0, 1, 288, 15625),
+        F(16000000, P_GPLL0, 10, 1, 5),
+        F(19200000, P_XO, 1, 0, 0),
+        F(24000000, P_GPLL0, 1, 3, 100),
+        F(25000000, P_GPLL0, 16, 1, 2),
+        F(32000000, P_GPLL0, 1, 1, 25),
+        F(40000000, P_GPLL0, 1, 1, 20),
+        F(46400000, P_GPLL0, 1, 29, 500),
+        F(48000000, P_GPLL0, 1, 3, 50),
+        F(51200000, P_GPLL0, 1, 8, 125),
+        F(56000000, P_GPLL0, 1, 7, 100),
+        F(58982400, P_GPLL0, 1, 1152, 15625),
+        F(60000000, P_GPLL0, 1, 3, 40),
+        { }
+};
+
+static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
+        .cmd_rcgr = 0x02044,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_uart1_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
+        .cmd_rcgr = 0x03034,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_uart2_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
+        F(19200000,     P_XO, 1, 0,     0),
+        { }
+};
+
+static struct clk_rcg2 cci_clk_src = {
+        .cmd_rcgr = 0x51000,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0a_map,
+        .freq_tbl = ftbl_gcc_camss_cci_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "cci_clk_src",
+                .parent_names = gcc_xo_gpll0a,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
+        F(100000000, P_GPLL0, 8, 0, 0),
+        F(200000000, P_GPLL0, 4, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 camss_gp0_clk_src = {
+        .cmd_rcgr = 0x54000,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
+        .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "camss_gp0_clk_src",
+                .parent_names = gcc_xo_gpll0_gpll1a_sleep,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 camss_gp1_clk_src = {
+        .cmd_rcgr = 0x55000,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
+        .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "camss_gp1_clk_src",
+                .parent_names = gcc_xo_gpll0_gpll1a_sleep,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
+        F(133330000, P_GPLL0, 6, 0,     0),
+        F(266670000, P_GPLL0, 3, 0,     0),
+        F(320000000, P_GPLL0, 2.5, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 jpeg0_clk_src = {
+        .cmd_rcgr = 0x57000,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "jpeg0_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
+        F(9600000, P_XO, 2, 0, 0),
+        F(23880000, P_GPLL0, 1, 2, 67),
+        F(66670000, P_GPLL0, 12, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 mclk0_clk_src = {
+        .cmd_rcgr = 0x52000,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
+        .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mclk0_clk_src",
+                .parent_names = gcc_xo_gpll0_gpll1a_sleep,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 mclk1_clk_src = {
+        .cmd_rcgr = 0x53000,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
+        .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mclk1_clk_src",
+                .parent_names = gcc_xo_gpll0_gpll1a_sleep,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
+        F(100000000, P_GPLL0, 8, 0,     0),
+        F(200000000, P_GPLL0, 4, 0,     0),
+        { }
+};
+
+static struct clk_rcg2 csi0phytimer_clk_src = {
+        .cmd_rcgr = 0x4e000,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_gpll1a_map,
+        .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "csi0phytimer_clk_src",
+                .parent_names = gcc_xo_gpll0_gpll1a,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 csi1phytimer_clk_src = {
+        .cmd_rcgr = 0x4f000,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_gpll1a_map,
+        .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "csi1phytimer_clk_src",
+                .parent_names = gcc_xo_gpll0_gpll1a,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
+        F(160000000, P_GPLL0, 5, 0, 0),
+        F(320000000, P_GPLL0, 2.5, 0, 0),
+        F(465000000, P_GPLL2, 2, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 cpp_clk_src = {
+        .cmd_rcgr = 0x58018,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_gpll2_map,
+        .freq_tbl = ftbl_gcc_camss_cpp_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "cpp_clk_src",
+                .parent_names = gcc_xo_gpll0_gpll2,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
+        F(50000000, P_GPLL0, 16, 0, 0),
+        F(80000000, P_GPLL0, 10, 0, 0),
+        F(100000000, P_GPLL0, 8, 0, 0),
+        F(160000000, P_GPLL0, 5, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 crypto_clk_src = {
+        .cmd_rcgr = 0x16004,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_crypto_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "crypto_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gp1_clk_src = {
+        .cmd_rcgr = 0x08004,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
+        .freq_tbl = ftbl_gcc_gp1_3_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gp1_clk_src",
+                .parent_names = gcc_xo_gpll0_gpll1a_sleep,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gp2_clk_src = {
+        .cmd_rcgr = 0x09004,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
+        .freq_tbl = ftbl_gcc_gp1_3_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gp2_clk_src",
+                .parent_names = gcc_xo_gpll0_gpll1a_sleep,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gp3_clk_src = {
+        .cmd_rcgr = 0x0a004,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
+        .freq_tbl = ftbl_gcc_gp1_3_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gp3_clk_src",
+                .parent_names = gcc_xo_gpll0_gpll1a_sleep,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct freq_tbl ftbl_gcc_mdss_byte0_clk[] = {
+        { .src = P_DSI0_PHYPLL_BYTE },
+        { }
+};
+
+static struct clk_rcg2 byte0_clk_src = {
+        .cmd_rcgr = 0x4d044,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0a_dsibyte_map,
+        .freq_tbl = ftbl_gcc_mdss_byte0_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "byte0_clk_src",
+                .parent_names = gcc_xo_gpll0a_dsibyte,
+                .num_parents = 3,
+                .ops = &clk_byte_ops,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_mdss_esc0_clk[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 esc0_clk_src = {
+        .cmd_rcgr = 0x4d05c,
+        .hid_width = 5,
+        .parent_map = gcc_xo_dsibyte_map,
+        .freq_tbl = ftbl_gcc_mdss_esc0_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "esc0_clk_src",
+                .parent_names = gcc_xo_dsibyte,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
+        F(50000000, P_GPLL0, 16, 0, 0),
+        F(80000000, P_GPLL0, 10, 0, 0),
+        F(100000000, P_GPLL0, 8, 0, 0),
+        F(160000000, P_GPLL0, 5, 0, 0),
+        F(177780000, P_GPLL0, 4.5, 0, 0),
+        F(200000000, P_GPLL0, 4, 0, 0),
+        F(266670000, P_GPLL0, 3, 0, 0),
+        F(320000000, P_GPLL0, 2.5, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 mdp_clk_src = {
+        .cmd_rcgr = 0x4d014,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_dsiphy_map,
+        .freq_tbl = ftbl_gcc_mdss_mdp_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mdp_clk_src",
+                .parent_names = gcc_xo_gpll0_dsiphy,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct freq_tbl ftbl_gcc_mdss_pclk[] = {
+        { .src = P_DSI0_PHYPLL_DSI },
+        { }
+};
+
+static struct clk_rcg2 pclk0_clk_src = {
+        .cmd_rcgr = 0x4d000,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0a_dsiphy_map,
+        .freq_tbl = ftbl_gcc_mdss_pclk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "pclk0_clk_src",
+                .parent_names = gcc_xo_gpll0a_dsiphy,
+                .num_parents = 3,
+                .ops = &clk_pixel_ops,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 vsync_clk_src = {
+        .cmd_rcgr = 0x4d02c,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0a_map,
+        .freq_tbl = ftbl_gcc_mdss_vsync_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "vsync_clk_src",
+                .parent_names = gcc_xo_gpll0a,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
+        F(64000000, P_GPLL0, 12.5, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 pdm2_clk_src = {
+        .cmd_rcgr = 0x44010,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_pdm2_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "pdm2_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
+        F(144000, P_XO, 16, 3, 25),
+        F(400000, P_XO, 12, 1, 4),
+        F(20000000, P_GPLL0, 10, 1, 4),
+        F(25000000, P_GPLL0, 16, 1, 2),
+        F(50000000, P_GPLL0, 16, 0, 0),
+        F(100000000, P_GPLL0, 8, 0, 0),
+        F(177770000, P_GPLL0, 4.5, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 sdcc1_apps_clk_src = {
+        .cmd_rcgr = 0x42004,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "sdcc1_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk[] = {
+        F(144000, P_XO, 16, 3, 25),
+        F(400000, P_XO, 12, 1, 4),
+        F(20000000, P_GPLL0, 10, 1, 4),
+        F(25000000, P_GPLL0, 16, 1, 2),
+        F(50000000, P_GPLL0, 16, 0, 0),
+        F(100000000, P_GPLL0, 8, 0, 0),
+        F(200000000, P_GPLL0, 4, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 sdcc2_apps_clk_src = {
+        .cmd_rcgr = 0x43004,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_sdcc2_apps_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "sdcc2_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
+        F(155000000, P_GPLL2, 6, 0, 0),
+        F(310000000, P_GPLL2, 3, 0, 0),
+        F(400000000, P_GPLL0, 2, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 apss_tcu_clk_src = {
+        .cmd_rcgr = 0x1207c,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0a_gpll1_gpll2_map,
+        .freq_tbl = ftbl_gcc_apss_tcu_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "apss_tcu_clk_src",
+                .parent_names = gcc_xo_gpll0a_gpll1_gpll2,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
+        F(80000000, P_GPLL0, 10, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 usb_hs_system_clk_src = {
+        .cmd_rcgr = 0x41010,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_usb_hs_system_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "usb_hs_system_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
+        F(100000000, P_GPLL0, 8, 0, 0),
+        F(160000000, P_GPLL0, 5, 0, 0),
+        F(228570000, P_GPLL0, 5, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 vcodec0_clk_src = {
+        .cmd_rcgr = 0x4C000,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "vcodec0_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_branch gcc_blsp1_ahb_clk = {
+        .halt_reg = 0x01008,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x45004,
+                .enable_mask = BIT(10),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "pcnoc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_sleep_clk = {
+        .halt_reg = 0x01004,
+        .clkr = {
+                .enable_reg = 0x01004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_sleep_clk",
+                        .parent_names = (const char *[]){
+                                "sleep_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
+        .halt_reg = 0x02008,
+        .clkr = {
+                .enable_reg = 0x02008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup1_i2c_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup1_i2c_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
+        .halt_reg = 0x02004,
+        .clkr = {
+                .enable_reg = 0x02004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup1_spi_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup1_spi_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
+        .halt_reg = 0x03010,
+        .clkr = {
+                .enable_reg = 0x03010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup2_i2c_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup2_i2c_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
+        .halt_reg = 0x0300c,
+        .clkr = {
+                .enable_reg = 0x0300c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup2_spi_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup2_spi_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
+        .halt_reg = 0x04020,
+        .clkr = {
+                .enable_reg = 0x04020,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup3_i2c_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup3_i2c_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
+        .halt_reg = 0x0401c,
+        .clkr = {
+                .enable_reg = 0x0401c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup3_spi_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup3_spi_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
+        .halt_reg = 0x05020,
+        .clkr = {
+                .enable_reg = 0x05020,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup4_i2c_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup4_i2c_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
+        .halt_reg = 0x0501c,
+        .clkr = {
+                .enable_reg = 0x0501c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup4_spi_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup4_spi_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
+        .halt_reg = 0x06020,
+        .clkr = {
+                .enable_reg = 0x06020,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup5_i2c_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup5_i2c_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
+        .halt_reg = 0x0601c,
+        .clkr = {
+                .enable_reg = 0x0601c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup5_spi_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup5_spi_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
+        .halt_reg = 0x07020,
+        .clkr = {
+                .enable_reg = 0x07020,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup6_i2c_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup6_i2c_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
+        .halt_reg = 0x0701c,
+        .clkr = {
+                .enable_reg = 0x0701c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup6_spi_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup6_spi_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_uart1_apps_clk = {
+        .halt_reg = 0x0203c,
+        .clkr = {
+                .enable_reg = 0x0203c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_uart1_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_uart1_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_uart2_apps_clk = {
+        .halt_reg = 0x0302c,
+        .clkr = {
+                .enable_reg = 0x0302c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_uart2_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_uart2_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_boot_rom_ahb_clk = {
+        .halt_reg = 0x1300c,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x45004,
+                .enable_mask = BIT(7),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_boot_rom_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "pcnoc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_cci_ahb_clk = {
+        .halt_reg = 0x5101c,
+        .clkr = {
+                .enable_reg = 0x5101c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_cci_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "camss_ahb_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_cci_clk = {
+        .halt_reg = 0x51018,
+        .clkr = {
+                .enable_reg = 0x51018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_cci_clk",
+                        .parent_names = (const char *[]){
+                                "cci_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_csi0_ahb_clk = {
+        .halt_reg = 0x4e040,
+        .clkr = {
+                .enable_reg = 0x4e040,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_csi0_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "camss_ahb_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_csi0_clk = {
+        .halt_reg = 0x4e03c,
+        .clkr = {
+                .enable_reg = 0x4e03c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_csi0_clk",
+                        .parent_names = (const char *[]){
+                                "csi0_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_csi0phy_clk = {
+        .halt_reg = 0x4e048,
+        .clkr = {
+                .enable_reg = 0x4e048,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_csi0phy_clk",
+                        .parent_names = (const char *[]){
+                                "csi0_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_csi0pix_clk = {
+        .halt_reg = 0x4e058,
+        .clkr = {
+                .enable_reg = 0x4e058,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_csi0pix_clk",
+                        .parent_names = (const char *[]){
+                                "csi0_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_csi0rdi_clk = {
+        .halt_reg = 0x4e050,
+        .clkr = {
+                .enable_reg = 0x4e050,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_csi0rdi_clk",
+                        .parent_names = (const char *[]){
+                                "csi0_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_csi1_ahb_clk = {
+        .halt_reg = 0x4f040,
+        .clkr = {
+                .enable_reg = 0x4f040,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_csi1_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "camss_ahb_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_csi1_clk = {
+        .halt_reg = 0x4f03c,
+        .clkr = {
+                .enable_reg = 0x4f03c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_csi1_clk",
+                        .parent_names = (const char *[]){
+                                "csi1_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_csi1phy_clk = {
+        .halt_reg = 0x4f048,
+        .clkr = {
+                .enable_reg = 0x4f048,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_csi1phy_clk",
+                        .parent_names = (const char *[]){
+                                "csi1_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_csi1pix_clk = {
+        .halt_reg = 0x4f058,
+        .clkr = {
+                .enable_reg = 0x4f058,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_csi1pix_clk",
+                        .parent_names = (const char *[]){
+                                "csi1_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_csi1rdi_clk = {
+        .halt_reg = 0x4f050,
+        .clkr = {
+                .enable_reg = 0x4f050,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_csi1rdi_clk",
+                        .parent_names = (const char *[]){
+                                "csi1_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_csi_vfe0_clk = {
+        .halt_reg = 0x58050,
+        .clkr = {
+                .enable_reg = 0x58050,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_csi_vfe0_clk",
+                        .parent_names = (const char *[]){
+                                "vfe0_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_gp0_clk = {
+        .halt_reg = 0x54018,
+        .clkr = {
+                .enable_reg = 0x54018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_gp0_clk",
+                        .parent_names = (const char *[]){
+                                "camss_gp0_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_gp1_clk = {
+        .halt_reg = 0x55018,
+        .clkr = {
+                .enable_reg = 0x55018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_gp1_clk",
+                        .parent_names = (const char *[]){
+                                "camss_gp1_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_ispif_ahb_clk = {
+        .halt_reg = 0x50004,
+        .clkr = {
+                .enable_reg = 0x50004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_ispif_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "camss_ahb_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_jpeg0_clk = {
+        .halt_reg = 0x57020,
+        .clkr = {
+                .enable_reg = 0x57020,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_jpeg0_clk",
+                        .parent_names = (const char *[]){
+                                "jpeg0_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_jpeg_ahb_clk = {
+        .halt_reg = 0x57024,
+        .clkr = {
+                .enable_reg = 0x57024,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_jpeg_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "camss_ahb_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_jpeg_axi_clk = {
+        .halt_reg = 0x57028,
+        .clkr = {
+                .enable_reg = 0x57028,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_jpeg_axi_clk",
+                        .parent_names = (const char *[]){
+                                "system_noc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_mclk0_clk = {
+        .halt_reg = 0x52018,
+        .clkr = {
+                .enable_reg = 0x52018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_mclk0_clk",
+                        .parent_names = (const char *[]){
+                                "mclk0_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_mclk1_clk = {
+        .halt_reg = 0x53018,
+        .clkr = {
+                .enable_reg = 0x53018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_mclk1_clk",
+                        .parent_names = (const char *[]){
+                                "mclk1_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_micro_ahb_clk = {
+        .halt_reg = 0x5600c,
+        .clkr = {
+                .enable_reg = 0x5600c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_micro_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "camss_ahb_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_csi0phytimer_clk = {
+        .halt_reg = 0x4e01c,
+        .clkr = {
+                .enable_reg = 0x4e01c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_csi0phytimer_clk",
+                        .parent_names = (const char *[]){
+                                "csi0phytimer_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_csi1phytimer_clk = {
+        .halt_reg = 0x4f01c,
+        .clkr = {
+                .enable_reg = 0x4f01c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_csi1phytimer_clk",
+                        .parent_names = (const char *[]){
+                                "csi1phytimer_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_ahb_clk = {
+        .halt_reg = 0x5a014,
+        .clkr = {
+                .enable_reg = 0x5a014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "camss_ahb_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_top_ahb_clk = {
+        .halt_reg = 0x56004,
+        .clkr = {
+                .enable_reg = 0x56004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_top_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "pcnoc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_cpp_ahb_clk = {
+        .halt_reg = 0x58040,
+        .clkr = {
+                .enable_reg = 0x58040,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_cpp_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "camss_ahb_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_cpp_clk = {
+        .halt_reg = 0x5803c,
+        .clkr = {
+                .enable_reg = 0x5803c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_cpp_clk",
+                        .parent_names = (const char *[]){
+                                "cpp_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_vfe0_clk = {
+        .halt_reg = 0x58038,
+        .clkr = {
+                .enable_reg = 0x58038,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_vfe0_clk",
+                        .parent_names = (const char *[]){
+                                "vfe0_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_vfe_ahb_clk = {
+        .halt_reg = 0x58044,
+        .clkr = {
+                .enable_reg = 0x58044,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_vfe_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "camss_ahb_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camss_vfe_axi_clk = {
+        .halt_reg = 0x58048,
+        .clkr = {
+                .enable_reg = 0x58048,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camss_vfe_axi_clk",
+                        .parent_names = (const char *[]){
+                                "system_noc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_crypto_ahb_clk = {
+        .halt_reg = 0x16024,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x45004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_crypto_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "pcnoc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_crypto_axi_clk = {
+        .halt_reg = 0x16020,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x45004,
+                .enable_mask = BIT(1),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_crypto_axi_clk",
+                        .parent_names = (const char *[]){
+                                "pcnoc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_crypto_clk = {
+        .halt_reg = 0x1601c,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x45004,
+                .enable_mask = BIT(2),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_crypto_clk",
+                        .parent_names = (const char *[]){
+                                "crypto_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_oxili_gmem_clk = {
+        .halt_reg = 0x59024,
+        .clkr = {
+                .enable_reg = 0x59024,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_oxili_gmem_clk",
+                        .parent_names = (const char *[]){
+                                "gfx3d_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gp1_clk = {
+        .halt_reg = 0x08000,
+        .clkr = {
+                .enable_reg = 0x08000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gp1_clk",
+                        .parent_names = (const char *[]){
+                                "gp1_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gp2_clk = {
+        .halt_reg = 0x09000,
+        .clkr = {
+                .enable_reg = 0x09000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gp2_clk",
+                        .parent_names = (const char *[]){
+                                "gp2_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gp3_clk = {
+        .halt_reg = 0x0a000,
+        .clkr = {
+                .enable_reg = 0x0a000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gp3_clk",
+                        .parent_names = (const char *[]){
+                                "gp3_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mdss_ahb_clk = {
+        .halt_reg = 0x4d07c,
+        .clkr = {
+                .enable_reg = 0x4d07c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mdss_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "pcnoc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mdss_axi_clk = {
+        .halt_reg = 0x4d080,
+        .clkr = {
+                .enable_reg = 0x4d080,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mdss_axi_clk",
+                        .parent_names = (const char *[]){
+                                "system_noc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mdss_byte0_clk = {
+        .halt_reg = 0x4d094,
+        .clkr = {
+                .enable_reg = 0x4d094,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mdss_byte0_clk",
+                        .parent_names = (const char *[]){
+                                "byte0_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mdss_esc0_clk = {
+        .halt_reg = 0x4d098,
+        .clkr = {
+                .enable_reg = 0x4d098,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mdss_esc0_clk",
+                        .parent_names = (const char *[]){
+                                "esc0_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mdss_mdp_clk = {
+        .halt_reg = 0x4D088,
+        .clkr = {
+                .enable_reg = 0x4D088,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mdss_mdp_clk",
+                        .parent_names = (const char *[]){
+                                "mdp_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mdss_pclk0_clk = {
+        .halt_reg = 0x4d084,
+        .clkr = {
+                .enable_reg = 0x4d084,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mdss_pclk0_clk",
+                        .parent_names = (const char *[]){
+                                "pclk0_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mdss_vsync_clk = {
+        .halt_reg = 0x4d090,
+        .clkr = {
+                .enable_reg = 0x4d090,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mdss_vsync_clk",
+                        .parent_names = (const char *[]){
+                                "vsync_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mss_cfg_ahb_clk = {
+        .halt_reg = 0x49000,
+        .clkr = {
+                .enable_reg = 0x49000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mss_cfg_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "pcnoc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_oxili_ahb_clk = {
+        .halt_reg = 0x59028,
+        .clkr = {
+                .enable_reg = 0x59028,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_oxili_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "pcnoc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_oxili_gfx3d_clk = {
+        .halt_reg = 0x59020,
+        .clkr = {
+                .enable_reg = 0x59020,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_oxili_gfx3d_clk",
+                        .parent_names = (const char *[]){
+                                "gfx3d_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pdm2_clk = {
+        .halt_reg = 0x4400c,
+        .clkr = {
+                .enable_reg = 0x4400c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pdm2_clk",
+                        .parent_names = (const char *[]){
+                                "pdm2_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pdm_ahb_clk = {
+        .halt_reg = 0x44004,
+        .clkr = {
+                .enable_reg = 0x44004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pdm_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "pcnoc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_prng_ahb_clk = {
+        .halt_reg = 0x13004,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x45004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_prng_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "pcnoc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc1_ahb_clk = {
+        .halt_reg = 0x4201c,
+        .clkr = {
+                .enable_reg = 0x4201c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc1_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "pcnoc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc1_apps_clk = {
+        .halt_reg = 0x42018,
+        .clkr = {
+                .enable_reg = 0x42018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc1_apps_clk",
+                        .parent_names = (const char *[]){
+                                "sdcc1_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc2_ahb_clk = {
+        .halt_reg = 0x4301c,
+        .clkr = {
+                .enable_reg = 0x4301c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc2_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "pcnoc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc2_apps_clk = {
+        .halt_reg = 0x43018,
+        .clkr = {
+                .enable_reg = 0x43018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc2_apps_clk",
+                        .parent_names = (const char *[]){
+                                "sdcc2_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gtcu_ahb_clk = {
+        .halt_reg = 0x12044,
+        .clkr = {
+                .enable_reg = 0x4500c,
+                .enable_mask = BIT(13),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gtcu_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "pcnoc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_jpeg_tbu_clk = {
+        .halt_reg = 0x12034,
+        .clkr = {
+                .enable_reg = 0x4500c,
+                .enable_mask = BIT(10),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_jpeg_tbu_clk",
+                        .parent_names = (const char *[]){
+                                "system_noc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mdp_tbu_clk = {
+        .halt_reg = 0x1201c,
+        .clkr = {
+                .enable_reg = 0x4500c,
+                .enable_mask = BIT(4),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mdp_tbu_clk",
+                        .parent_names = (const char *[]){
+                                "system_noc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_smmu_cfg_clk = {
+        .halt_reg = 0x12038,
+        .clkr = {
+                .enable_reg = 0x4500c,
+                .enable_mask = BIT(12),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_smmu_cfg_clk",
+                        .parent_names = (const char *[]){
+                                "pcnoc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_venus_tbu_clk = {
+        .halt_reg = 0x12014,
+        .clkr = {
+                .enable_reg = 0x4500c,
+                .enable_mask = BIT(5),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_venus_tbu_clk",
+                        .parent_names = (const char *[]){
+                                "system_noc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_vfe_tbu_clk = {
+        .halt_reg = 0x1203c,
+        .clkr = {
+                .enable_reg = 0x4500c,
+                .enable_mask = BIT(9),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_vfe_tbu_clk",
+                        .parent_names = (const char *[]){
+                                "system_noc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb2a_phy_sleep_clk = {
+        .halt_reg = 0x4102c,
+        .clkr = {
+                .enable_reg = 0x4102c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb2a_phy_sleep_clk",
+                        .parent_names = (const char *[]){
+                                "sleep_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb_hs_ahb_clk = {
+        .halt_reg = 0x41008,
+        .clkr = {
+                .enable_reg = 0x41008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb_hs_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "pcnoc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb_hs_system_clk = {
+        .halt_reg = 0x41004,
+        .clkr = {
+                .enable_reg = 0x41004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb_hs_system_clk",
+                        .parent_names = (const char *[]){
+                                "usb_hs_system_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_venus0_ahb_clk = {
+        .halt_reg = 0x4c020,
+        .clkr = {
+                .enable_reg = 0x4c020,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_venus0_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "pcnoc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_venus0_axi_clk = {
+        .halt_reg = 0x4c024,
+        .clkr = {
+                .enable_reg = 0x4c024,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_venus0_axi_clk",
+                        .parent_names = (const char *[]){
+                                "system_noc_bfdcd_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_venus0_vcodec0_clk = {
+        .halt_reg = 0x4c01c,
+        .clkr = {
+                .enable_reg = 0x4c01c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_venus0_vcodec0_clk",
+                        .parent_names = (const char *[]){
+                                "vcodec0_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_regmap *gcc_msm8916_clocks[] = {
+        [GPLL0] = &gpll0.clkr,
+        [GPLL0_VOTE] = &gpll0_vote,
+        [BIMC_PLL] = &bimc_pll.clkr,
+        [BIMC_PLL_VOTE] = &bimc_pll_vote,
+        [GPLL1] = &gpll1.clkr,
+        [GPLL1_VOTE] = &gpll1_vote,
+        [GPLL2] = &gpll2.clkr,
+        [GPLL2_VOTE] = &gpll2_vote,
+        [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
+        [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
+        [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
+        [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
+        [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
+        [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
+        [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
+        [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
+        [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
+        [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
+        [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
+        [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
+        [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
+        [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
+        [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
+        [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
+        [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
+        [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
+        [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
+        [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
+        [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
+        [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
+        [CCI_CLK_SRC] = &cci_clk_src.clkr,
+        [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
+        [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
+        [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
+        [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
+        [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
+        [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
+        [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
+        [CPP_CLK_SRC] = &cpp_clk_src.clkr,
+        [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
+        [GP1_CLK_SRC] = &gp1_clk_src.clkr,
+        [GP2_CLK_SRC] = &gp2_clk_src.clkr,
+        [GP3_CLK_SRC] = &gp3_clk_src.clkr,
+        [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
+        [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
+        [MDP_CLK_SRC] = &mdp_clk_src.clkr,
+        [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
+        [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
+        [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
+        [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
+        [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
+        [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
+        [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
+        [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
+        [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
+        [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
+        [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
+        [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
+        [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
+        [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
+        [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
+        [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
+        [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
+        [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
+        [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
+        [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
+        [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
+        [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
+        [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
+        [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
+        [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
+        [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
+        [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
+        [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
+        [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
+        [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
+        [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
+        [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
+        [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
+        [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
+        [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
+        [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
+        [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
+        [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
+        [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
+        [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
+        [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
+        [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
+        [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
+        [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
+        [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
+        [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
+        [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
+        [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
+        [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
+        [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
+        [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
+        [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
+        [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
+        [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
+        [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
+        [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
+        [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
+        [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
+        [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
+        [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
+        [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+        [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+        [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
+        [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
+        [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
+        [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
+        [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
+        [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
+        [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
+        [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
+        [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
+        [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
+        [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
+        [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
+        [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
+        [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+        [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
+        [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
+        [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
+        [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
+        [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
+        [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
+        [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
+        [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
+        [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
+        [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
+        [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
+        [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
+        [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
+        [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
+        [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
+        [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
+};
+
+static const struct qcom_reset_map gcc_msm8916_resets[] = {
+        [GCC_BLSP1_BCR] = { 0x01000 },
+        [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
+        [GCC_BLSP1_UART1_BCR] = { 0x02038 },
+        [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
+        [GCC_BLSP1_UART2_BCR] = { 0x03028 },
+        [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
+        [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
+        [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
+        [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
+        [GCC_IMEM_BCR] = { 0x0e000 },
+        [GCC_SMMU_BCR] = { 0x12000 },
+        [GCC_APSS_TCU_BCR] = { 0x12050 },
+        [GCC_SMMU_XPU_BCR] = { 0x12054 },
+        [GCC_PCNOC_TBU_BCR] = { 0x12058 },
+        [GCC_PRNG_BCR] = { 0x13000 },
+        [GCC_BOOT_ROM_BCR] = { 0x13008 },
+        [GCC_CRYPTO_BCR] = { 0x16000 },
+        [GCC_SEC_CTRL_BCR] = { 0x1a000 },
+        [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
+        [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
+        [GCC_DEHR_BCR] = { 0x1f000 },
+        [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
+        [GCC_PCNOC_BCR] = { 0x27018 },
+        [GCC_TCSR_BCR] = { 0x28000 },
+        [GCC_QDSS_BCR] = { 0x29000 },
+        [GCC_DCD_BCR] = { 0x2a000 },
+        [GCC_MSG_RAM_BCR] = { 0x2b000 },
+        [GCC_MPM_BCR] = { 0x2c000 },
+        [GCC_SPMI_BCR] = { 0x2e000 },
+        [GCC_SPDM_BCR] = { 0x2f000 },
+        [GCC_MM_SPDM_BCR] = { 0x2f024 },
+        [GCC_BIMC_BCR] = { 0x31000 },
+        [GCC_RBCPR_BCR] = { 0x33000 },
+        [GCC_TLMM_BCR] = { 0x34000 },
+        [GCC_USB_HS_BCR] = { 0x41000 },
+        [GCC_USB2A_PHY_BCR] = { 0x41028 },
+        [GCC_SDCC1_BCR] = { 0x42000 },
+        [GCC_SDCC2_BCR] = { 0x43000 },
+        [GCC_PDM_BCR] = { 0x44000 },
+        [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
+        [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
+        [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
+        [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
+        [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
+        [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
+        [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
+        [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
+        [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
+        [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
+        [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
+        [GCC_MMSS_BCR] = { 0x4b000 },
+        [GCC_VENUS0_BCR] = { 0x4c014 },
+        [GCC_MDSS_BCR] = { 0x4d074 },
+        [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
+        [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
+        [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
+        [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
+        [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
+        [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
+        [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
+        [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
+        [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
+        [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
+        [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
+        [GCC_CAMSS_CCI_BCR] = { 0x51014 },
+        [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
+        [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
+        [GCC_CAMSS_GP0_BCR] = { 0x54014 },
+        [GCC_CAMSS_GP1_BCR] = { 0x55014 },
+        [GCC_CAMSS_TOP_BCR] = { 0x56000 },
+        [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
+        [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
+        [GCC_CAMSS_VFE_BCR] = { 0x58030 },
+        [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
+        [GCC_OXILI_BCR] = { 0x59018 },
+        [GCC_GMEM_BCR] = { 0x5902c },
+        [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
+        [GCC_MDP_TBU_BCR] = { 0x62000 },
+        [GCC_GFX_TBU_BCR] = { 0x63000 },
+        [GCC_GFX_TCU_BCR] = { 0x64000 },
+        [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
+        [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
+        [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
+        [GCC_GTCU_AHB_BCR] = { 0x68000 },
+        [GCC_SMMU_CFG_BCR] = { 0x69000 },
+        [GCC_VFE_TBU_BCR] = { 0x6a000 },
+        [GCC_VENUS_TBU_BCR] = { 0x6b000 },
+        [GCC_JPEG_TBU_BCR] = { 0x6c000 },
+        [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
+        [GCC_SMMU_CATS_BCR] = { 0x7c000 },
+};
+
+static const struct regmap_config gcc_msm8916_regmap_config = {
+        .reg_bits       = 32,
+        .reg_stride     = 4,
+        .val_bits       = 32,
+        .max_register   = 0x80000,
+        .fast_io        = true,
+};
+
+static const struct qcom_cc_desc gcc_msm8916_desc = {
+        .config = &gcc_msm8916_regmap_config,
+        .clks = gcc_msm8916_clocks,
+        .num_clks = ARRAY_SIZE(gcc_msm8916_clocks),
+        .resets = gcc_msm8916_resets,
+        .num_resets = ARRAY_SIZE(gcc_msm8916_resets),
+};
+
+static const struct of_device_id gcc_msm8916_match_table[] = {
+        { .compatible = "qcom,gcc-msm8916" },
+        { }
+};
+MODULE_DEVICE_TABLE(of, gcc_msm8916_match_table);
+
+static int gcc_msm8916_probe(struct platform_device *pdev)
+{
+        struct clk *clk;
+        struct device *dev = &pdev->dev;
+
+        /* Temporary until RPM clocks supported */
+        clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000);
+        if (IS_ERR(clk))
+                return PTR_ERR(clk);
+
+        clk = clk_register_fixed_rate(dev, "sleep_clk_src", NULL,
+                                      CLK_IS_ROOT, 32768);
+        if (IS_ERR(clk))
+                return PTR_ERR(clk);
+
+        return qcom_cc_probe(pdev, &gcc_msm8916_desc);
+}
+
+static int gcc_msm8916_remove(struct platform_device *pdev)
+{
+        qcom_cc_remove(pdev);
+        return 0;
+}
+
+static struct platform_driver gcc_msm8916_driver = {
+        .probe          = gcc_msm8916_probe,
+        .remove         = gcc_msm8916_remove,
+        .driver         = {
+                .name   = "gcc-msm8916",
+                .of_match_table = gcc_msm8916_match_table,
+        },
+};
+
+static int __init gcc_msm8916_init(void)
+{
+        return platform_driver_register(&gcc_msm8916_driver);
+}
+core_initcall(gcc_msm8916_init);
+
+static void __exit gcc_msm8916_exit(void)
+{
+        platform_driver_unregister(&gcc_msm8916_driver);
+}
+module_exit(gcc_msm8916_exit);
+
+MODULE_DESCRIPTION("Qualcomm GCC MSM8916 Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:gcc-msm8916");
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index b0b562b9ce0e..eb6a4f9fa107 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -48,6 +48,17 @@ static struct clk_pll pll3 = {
         },
 };
 
+static struct clk_regmap pll4_vote = {
+        .enable_reg = 0x34c0,
+        .enable_mask = BIT(4),
+        .hw.init = &(struct clk_init_data){
+                .name = "pll4_vote",
+                .parent_names = (const char *[]){ "pll4" },
+                .num_parents = 1,
+                .ops = &clk_pll_vote_ops,
+        },
+};
+
 static struct clk_pll pll8 = {
         .l_reg = 0x3144,
         .m_reg = 0x3148,
@@ -102,14 +113,16 @@ static struct clk_regmap pll14_vote = {
         },
 };
 
-#define P_PXO   0
-#define P_PLL8  1
-#define P_PLL3  2
-#define P_CXO   2
+enum {
+        P_PXO,
+        P_PLL8,
+        P_PLL3,
+        P_CXO,
+};
 
-static const u8 gcc_pxo_pll8_map[] = {
-        [P_PXO]         = 0,
-        [P_PLL8]        = 3,
+static const struct parent_map gcc_pxo_pll8_map[] = {
+        { P_PXO, 0 },
+        { P_PLL8, 3 }
 };
 
 static const char *gcc_pxo_pll8[] = {
@@ -117,10 +130,10 @@ static const char *gcc_pxo_pll8[] = {
         "pll8_vote",
 };
 
-static const u8 gcc_pxo_pll8_cxo_map[] = {
-        [P_PXO]         = 0,
-        [P_PLL8]        = 3,
-        [P_CXO]         = 5,
+static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
+        { P_PXO, 0 },
+        { P_PLL8, 3 },
+        { P_CXO, 5 }
 };
 
 static const char *gcc_pxo_pll8_cxo[] = {
@@ -129,10 +142,10 @@ static const char *gcc_pxo_pll8_cxo[] = {
         "cxo",
 };
 
-static const u8 gcc_pxo_pll8_pll3_map[] = {
-        [P_PXO]         = 0,
-        [P_PLL8]        = 3,
-        [P_PLL3]        = 6,
+static const struct parent_map gcc_pxo_pll8_pll3_map[] = {
+        { P_PXO, 0 },
+        { P_PLL8, 3 },
+        { P_PLL3, 6 }
 };
 
 static const char *gcc_pxo_pll8_pll3[] = {
@@ -3023,6 +3036,7 @@ static struct clk_branch rpm_msg_ram_h_clk = {
 
 static struct clk_regmap *gcc_msm8960_clks[] = {
         [PLL3] = &pll3.clkr,
+        [PLL4_VOTE] = &pll4_vote,
         [PLL8] = &pll8.clkr,
         [PLL8_VOTE] = &pll8_vote,
         [PLL14] = &pll14.clkr,
@@ -3247,6 +3261,7 @@ static const struct qcom_reset_map gcc_msm8960_resets[] = {
 
 static struct clk_regmap *gcc_apq8064_clks[] = {
         [PLL3] = &pll3.clkr,
+        [PLL4_VOTE] = &pll4_vote,
         [PLL8] = &pll8.clkr,
         [PLL8_VOTE] = &pll8_vote,
         [PLL14] = &pll14.clkr,
diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
index a6937fe78d8a..c39d09874e74 100644
--- a/drivers/clk/qcom/gcc-msm8974.c
+++ b/drivers/clk/qcom/gcc-msm8974.c
@@ -32,14 +32,16 @@
 #include "clk-branch.h"
 #include "reset.h"
 
-#define P_XO    0
-#define P_GPLL0 1
-#define P_GPLL1 1
-#define P_GPLL4 2
+enum {
+        P_XO,
+        P_GPLL0,
+        P_GPLL1,
+        P_GPLL4,
+};
 
-static const u8 gcc_xo_gpll0_map[] = {
-        [P_XO]          = 0,
-        [P_GPLL0]       = 1,
+static const struct parent_map gcc_xo_gpll0_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0, 1 }
 };
 
 static const char *gcc_xo_gpll0[] = {
@@ -47,10 +49,10 @@ static const char *gcc_xo_gpll0[] = {
         "gpll0_vote",
 };
 
-static const u8 gcc_xo_gpll0_gpll4_map[] = {
-        [P_XO]          = 0,
-        [P_GPLL0]       = 1,
-        [P_GPLL4]       = 5,
+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0, 1 },
+        { P_GPLL4, 5 }
 };
 
 static const char *gcc_xo_gpll0_gpll4[] = {
@@ -984,9 +986,9 @@ static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
         { }
 };
 
-static u8 usb_hsic_clk_src_map[] = {
-        [P_XO]          = 0,
-        [P_GPLL1]       = 4,
+static const struct parent_map usb_hsic_clk_src_map[] = {
+        { P_XO, 0 },
+        { P_GPLL1, 4 }
 };
 
 static struct clk_rcg2 usb_hsic_clk_src = {
diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c
index 121ffde25dc3..e4ac699666d5 100644
--- a/drivers/clk/qcom/lcc-ipq806x.c
+++ b/drivers/clk/qcom/lcc-ipq806x.c
@@ -61,12 +61,14 @@ static const struct pll_config pll4_config = {
         .main_output_mask = BIT(23),
 };
 
-#define P_PXO   0
-#define P_PLL4  1
+enum {
+        P_PXO,
+        P_PLL4,
+};
 
-static const u8 lcc_pxo_pll4_map[] = {
-        [P_PXO]         = 0,
-        [P_PLL4]        = 2,
+static const struct parent_map lcc_pxo_pll4_map[] = {
+        { P_PXO, 0 },
+        { P_PLL4, 2 }
 };
 
 static const char *lcc_pxo_pll4[] = {
@@ -386,13 +388,12 @@ static struct clk_rcg ahbix_clk = {
         .freq_tbl = clk_tbl_ahbix,
         .clkr = {
                 .enable_reg = 0x38,
-                .enable_mask = BIT(10), /* toggle the gfmux to select mn/pxo */
+                .enable_mask = BIT(11),
                 .hw.init = &(struct clk_init_data){
                         .name = "ahbix",
                         .parent_names = lcc_pxo_pll4,
                         .num_parents = 2,
-                        .ops = &clk_rcg_ops,
-                        .flags = CLK_SET_RATE_GATE,
+                        .ops = &clk_rcg_lcc_ops,
                 },
         },
 };
@@ -462,7 +463,6 @@ static struct platform_driver lcc_ipq806x_driver = {
         .remove         = lcc_ipq806x_remove,
         .driver         = {
                 .name   = "lcc-ipq806x",
-                .owner  = THIS_MODULE,
                 .of_match_table = lcc_ipq806x_match_table,
         },
 };
diff --git a/drivers/clk/qcom/lcc-msm8960.c b/drivers/clk/qcom/lcc-msm8960.c
index a75a408cfccd..d0df9d5fc3af 100644
--- a/drivers/clk/qcom/lcc-msm8960.c
+++ b/drivers/clk/qcom/lcc-msm8960.c
@@ -47,12 +47,14 @@ static struct clk_pll pll4 = {
         },
 };
 
-#define P_PXO   0
-#define P_PLL4  1
+enum {
+        P_PXO,
+        P_PLL4,
+};
 
-static const u8 lcc_pxo_pll4_map[] = {
-        [P_PXO]         = 0,
-        [P_PLL4]        = 2,
+static const struct parent_map lcc_pxo_pll4_map[] = {
+        { P_PXO, 0 },
+        { P_PLL4, 2 }
 };
 
 static const char *lcc_pxo_pll4[] = {
@@ -417,8 +419,8 @@ static struct clk_rcg slimbus_src = {
                 .mnctr_en_bit = 8,
                 .mnctr_reset_bit = 7,
                 .mnctr_mode_shift = 5,
-                .n_val_shift = 16,
-                .m_val_shift = 16,
+                .n_val_shift = 24,
+                .m_val_shift = 8,
                 .width = 8,
         },
         .p = {
@@ -547,7 +549,7 @@ static int lcc_msm8960_probe(struct platform_device *pdev)
                 return PTR_ERR(regmap);
 
         /* Use the correct frequency plan depending on speed of PLL4 */
-        val = regmap_read(regmap, 0x4, &val);
+        regmap_read(regmap, 0x4, &val);
         if (val == 0x12) {
                 slimbus_src.freq_tbl = clk_tbl_aif_osr_492;
                 mi2s_osr_src.freq_tbl = clk_tbl_aif_osr_492;
@@ -574,7 +576,6 @@ static struct platform_driver lcc_msm8960_driver = {
         .remove         = lcc_msm8960_remove,
         .driver         = {
                 .name   = "lcc-msm8960",
-                .owner  = THIS_MODULE,
                 .of_match_table = lcc_msm8960_match_table,
         },
 };
diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
index 157139a5c1ca..1b17df2cb0af 100644
--- a/drivers/clk/qcom/mmcc-apq8084.c
+++ b/drivers/clk/qcom/mmcc-apq8084.c
@@ -27,28 +27,30 @@
 #include "clk-branch.h"
 #include "reset.h"
 
-#define P_XO            0
-#define P_MMPLL0        1
-#define P_EDPLINK       1
-#define P_MMPLL1        2
-#define P_HDMIPLL       2
-#define P_GPLL0         3
-#define P_EDPVCO        3
-#define P_MMPLL4        4
-#define P_DSI0PLL       4
-#define P_DSI0PLL_BYTE  4
-#define P_MMPLL2        4
-#define P_MMPLL3        4
-#define P_GPLL1         5
-#define P_DSI1PLL       5
-#define P_DSI1PLL_BYTE  5
-#define P_MMSLEEP       6
-
-static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
-        [P_XO]          = 0,
-        [P_MMPLL0]      = 1,
-        [P_MMPLL1]      = 2,
-        [P_GPLL0]       = 5,
+enum {
+        P_XO,
+        P_MMPLL0,
+        P_EDPLINK,
+        P_MMPLL1,
+        P_HDMIPLL,
+        P_GPLL0,
+        P_EDPVCO,
+        P_MMPLL4,
+        P_DSI0PLL,
+        P_DSI0PLL_BYTE,
+        P_MMPLL2,
+        P_MMPLL3,
+        P_GPLL1,
+        P_DSI1PLL,
+        P_DSI1PLL_BYTE,
+        P_MMSLEEP,
+};
+
+static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
+        { P_XO, 0 },
+        { P_MMPLL0, 1 },
+        { P_MMPLL1, 2 },
+        { P_GPLL0, 5 }
 };
 
 static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
@@ -58,13 +60,13 @@ static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
         "mmss_gpll0_vote",
 };
 
-static const u8 mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
-        [P_XO]          = 0,
-        [P_MMPLL0]      = 1,
-        [P_HDMIPLL]     = 4,
-        [P_GPLL0]       = 5,
-        [P_DSI0PLL]     = 2,
-        [P_DSI1PLL]     = 3,
+static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
+        { P_XO, 0 },
+        { P_MMPLL0, 1 },
+        { P_HDMIPLL, 4 },
+        { P_GPLL0, 5 },
+        { P_DSI0PLL, 2 },
+        { P_DSI1PLL, 3 }
 };
 
 static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
@@ -76,12 +78,12 @@ static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
         "dsi1pll",
 };
 
-static const u8 mmcc_xo_mmpll0_1_2_gpll0_map[] = {
-        [P_XO]          = 0,
-        [P_MMPLL0]      = 1,
-        [P_MMPLL1]      = 2,
-        [P_GPLL0]       = 5,
-        [P_MMPLL2]      = 3,
+static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
+        { P_XO, 0 },
+        { P_MMPLL0, 1 },
+        { P_MMPLL1, 2 },
+        { P_GPLL0, 5 },
+        { P_MMPLL2, 3 }
 };
 
 static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
@@ -92,12 +94,12 @@ static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
         "mmpll2",
 };
 
-static const u8 mmcc_xo_mmpll0_1_3_gpll0_map[] = {
-        [P_XO]          = 0,
-        [P_MMPLL0]      = 1,
-        [P_MMPLL1]      = 2,
-        [P_GPLL0]       = 5,
-        [P_MMPLL3]      = 3,
+static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
+        { P_XO, 0 },
+        { P_MMPLL0, 1 },
+        { P_MMPLL1, 2 },
+        { P_GPLL0, 5 },
+        { P_MMPLL3, 3 }
 };
 
 static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
@@ -108,13 +110,13 @@ static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
         "mmpll3",
 };
 
-static const u8 mmcc_xo_dsi_hdmi_edp_map[] = {
-        [P_XO]          = 0,
-        [P_EDPLINK]     = 4,
-        [P_HDMIPLL]     = 3,
-        [P_EDPVCO]      = 5,
-        [P_DSI0PLL]     = 1,
-        [P_DSI1PLL]     = 2,
+static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
+        { P_XO, 0 },
+        { P_EDPLINK, 4 },
+        { P_HDMIPLL, 3 },
+        { P_EDPVCO, 5 },
+        { P_DSI0PLL, 1 },
+        { P_DSI1PLL, 2 }
 };
 
 static const char *mmcc_xo_dsi_hdmi_edp[] = {
@@ -126,13 +128,13 @@ static const char *mmcc_xo_dsi_hdmi_edp[] = {
         "dsi1pll",
 };
 
-static const u8 mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
-        [P_XO]          = 0,
-        [P_EDPLINK]     = 4,
-        [P_HDMIPLL]     = 3,
-        [P_GPLL0]       = 5,
-        [P_DSI0PLL]     = 1,
-        [P_DSI1PLL]     = 2,
+static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
+        { P_XO, 0 },
+        { P_EDPLINK, 4 },
+        { P_HDMIPLL, 3 },
+        { P_GPLL0, 5 },
+        { P_DSI0PLL, 1 },
+        { P_DSI1PLL, 2 }
 };
 
 static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
@@ -144,13 +146,13 @@ static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
         "dsi1pll",
 };
 
-static const u8 mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
-        [P_XO]                  = 0,
-        [P_EDPLINK]             = 4,
-        [P_HDMIPLL]             = 3,
-        [P_GPLL0]               = 5,
-        [P_DSI0PLL_BYTE]        = 1,
-        [P_DSI1PLL_BYTE]        = 2,
+static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
+        { P_XO, 0 },
+        { P_EDPLINK, 4 },
+        { P_HDMIPLL, 3 },
+        { P_GPLL0, 5 },
+        { P_DSI0PLL_BYTE, 1 },
+        { P_DSI1PLL_BYTE, 2 }
 };
 
 static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
@@ -162,12 +164,12 @@ static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
         "dsi1pllbyte",
 };
 
-static const u8 mmcc_xo_mmpll0_1_4_gpll0_map[] = {
-        [P_XO]          = 0,
-        [P_MMPLL0]      = 1,
-        [P_MMPLL1]      = 2,
-        [P_GPLL0]       = 5,
-        [P_MMPLL4]      = 3,
+static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = {
+        { P_XO, 0 },
+        { P_MMPLL0, 1 },
+        { P_MMPLL1, 2 },
+        { P_GPLL0, 5 },
+        { P_MMPLL4, 3 }
 };
 
 static const char *mmcc_xo_mmpll0_1_4_gpll0[] = {
@@ -178,13 +180,13 @@ static const char *mmcc_xo_mmpll0_1_4_gpll0[] = {
         "gpll0",
 };
 
-static const u8 mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
-        [P_XO]          = 0,
-        [P_MMPLL0]      = 1,
-        [P_MMPLL1]      = 2,
-        [P_MMPLL4]      = 3,
-        [P_GPLL0]       = 5,
-        [P_GPLL1]       = 4,
+static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
+        { P_XO, 0 },
+        { P_MMPLL0, 1 },
+        { P_MMPLL1, 2 },
+        { P_MMPLL4, 3 },
+        { P_GPLL0, 5 },
+        { P_GPLL1, 4 }
 };
 
 static const char *mmcc_xo_mmpll0_1_4_gpll1_0[] = {
@@ -196,14 +198,14 @@ static const char *mmcc_xo_mmpll0_1_4_gpll1_0[] = {
         "gpll0",
 };
 
-static const u8 mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
-        [P_XO]          = 0,
-        [P_MMPLL0]      = 1,
-        [P_MMPLL1]      = 2,
-        [P_MMPLL4]      = 3,
-        [P_GPLL0]       = 5,
-        [P_GPLL1]       = 4,
-        [P_MMSLEEP]     = 6,
+static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
+        { P_XO, 0 },
+        { P_MMPLL0, 1 },
+        { P_MMPLL1, 2 },
+        { P_MMPLL4, 3 },
+        { P_GPLL0, 5 },
+        { P_GPLL1, 4 },
+        { P_MMSLEEP, 6 }
 };
 
 static const char *mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c
index e8b33bbc362f..9711bca9cc06 100644
--- a/drivers/clk/qcom/mmcc-msm8960.c
+++ b/drivers/clk/qcom/mmcc-msm8960.c
@@ -33,18 +33,21 @@
 #include "clk-branch.h"
 #include "reset.h"
 
-#define P_PXO   0
-#define P_PLL8  1
-#define P_PLL2  2
-#define P_PLL3  3
-#define P_PLL15 3
+enum {
+        P_PXO,
+        P_PLL8,
+        P_PLL2,
+        P_PLL3,
+        P_PLL15,
+        P_HDMI_PLL,
+};
 
 #define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
 
-static u8 mmcc_pxo_pll8_pll2_map[] = {
-        [P_PXO]         = 0,
-        [P_PLL8]        = 2,
-        [P_PLL2]        = 1,
+static const struct parent_map mmcc_pxo_pll8_pll2_map[] = {
+        { P_PXO, 0 },
+        { P_PLL8, 2 },
+        { P_PLL2, 1 }
 };
 
 static const char *mmcc_pxo_pll8_pll2[] = {
@@ -53,11 +56,11 @@ static const char *mmcc_pxo_pll8_pll2[] = {
         "pll2",
 };
 
-static u8 mmcc_pxo_pll8_pll2_pll3_map[] = {
-        [P_PXO]         = 0,
-        [P_PLL8]        = 2,
-        [P_PLL2]        = 1,
-        [P_PLL3]        = 3,
+static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = {
+        { P_PXO, 0 },
+        { P_PLL8, 2 },
+        { P_PLL2, 1 },
+        { P_PLL3, 3 }
 };
 
 static const char *mmcc_pxo_pll8_pll2_pll15[] = {
@@ -67,11 +70,11 @@ static const char *mmcc_pxo_pll8_pll2_pll15[] = {
         "pll15",
 };
 
-static u8 mmcc_pxo_pll8_pll2_pll15_map[] = {
-        [P_PXO]         = 0,
-        [P_PLL8]        = 2,
-        [P_PLL2]        = 1,
-        [P_PLL15]       = 3,
+static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = {
+        { P_PXO, 0 },
+        { P_PLL8, 2 },
+        { P_PLL2, 1 },
+        { P_PLL15, 3 }
 };
 
 static const char *mmcc_pxo_pll8_pll2_pll3[] = {
@@ -1377,11 +1380,9 @@ static struct clk_branch rot_clk = {
         },
 };
 
-#define P_HDMI_PLL 1
-
-static u8 mmcc_pxo_hdmi_map[] = {
-        [P_PXO]         = 0,
-        [P_HDMI_PLL]    = 3,
+static const struct parent_map mmcc_pxo_hdmi_map[] = {
+        { P_PXO, 0 },
+        { P_HDMI_PLL, 3 }
 };
 
 static const char *mmcc_pxo_hdmi[] = {
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index be94c54a9a4f..07f4cc159ad3 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -32,26 +32,28 @@
 #include "clk-branch.h"
 #include "reset.h"
 
-#define P_XO            0
-#define P_MMPLL0        1
-#define P_EDPLINK       1
-#define P_MMPLL1        2
-#define P_HDMIPLL       2
-#define P_GPLL0         3
-#define P_EDPVCO        3
-#define P_GPLL1         4
-#define P_DSI0PLL       4
-#define P_DSI0PLL_BYTE  4
-#define P_MMPLL2        4
-#define P_MMPLL3        4
-#define P_DSI1PLL       5
-#define P_DSI1PLL_BYTE  5
-
-static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
-        [P_XO]          = 0,
-        [P_MMPLL0]      = 1,
-        [P_MMPLL1]      = 2,
-        [P_GPLL0]       = 5,
+enum {
+        P_XO,
+        P_MMPLL0,
+        P_EDPLINK,
+        P_MMPLL1,
+        P_HDMIPLL,
+        P_GPLL0,
+        P_EDPVCO,
+        P_GPLL1,
+        P_DSI0PLL,
+        P_DSI0PLL_BYTE,
+        P_MMPLL2,
+        P_MMPLL3,
+        P_DSI1PLL,
+        P_DSI1PLL_BYTE,
+};
+
+static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
+        { P_XO, 0 },
+        { P_MMPLL0, 1 },
+        { P_MMPLL1, 2 },
+        { P_GPLL0, 5 }
 };
 
 static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
@@ -61,13 +63,13 @@ static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
         "mmss_gpll0_vote",
 };
 
-static const u8 mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
-        [P_XO]          = 0,
-        [P_MMPLL0]      = 1,
-        [P_HDMIPLL]     = 4,
-        [P_GPLL0]       = 5,
-        [P_DSI0PLL]     = 2,
-        [P_DSI1PLL]     = 3,
+static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
+        { P_XO, 0 },
+        { P_MMPLL0, 1 },
+        { P_HDMIPLL, 4 },
+        { P_GPLL0, 5 },
+        { P_DSI0PLL, 2 },
+        { P_DSI1PLL, 3 }
 };
 
 static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
@@ -79,12 +81,12 @@ static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
         "dsi1pll",
 };
 
-static const u8 mmcc_xo_mmpll0_1_2_gpll0_map[] = {
-        [P_XO]          = 0,
-        [P_MMPLL0]      = 1,
-        [P_MMPLL1]      = 2,
-        [P_GPLL0]       = 5,
-        [P_MMPLL2]      = 3,
+static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
+        { P_XO, 0 },
+        { P_MMPLL0, 1 },
+        { P_MMPLL1, 2 },
+        { P_GPLL0, 5 },
+        { P_MMPLL2, 3 }
 };
 
 static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
@@ -95,12 +97,12 @@ static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
         "mmpll2",
 };
 
-static const u8 mmcc_xo_mmpll0_1_3_gpll0_map[] = {
-        [P_XO]          = 0,
-        [P_MMPLL0]      = 1,
-        [P_MMPLL1]      = 2,
-        [P_GPLL0]       = 5,
-        [P_MMPLL3]      = 3,
+static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
+        { P_XO, 0 },
+        { P_MMPLL0, 1 },
+        { P_MMPLL1, 2 },
+        { P_GPLL0, 5 },
+        { P_MMPLL3, 3 }
 };
 
 static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
@@ -111,12 +113,12 @@ static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
         "mmpll3",
 };
 
-static const u8 mmcc_xo_mmpll0_1_gpll1_0_map[] = {
-        [P_XO]          = 0,
-        [P_MMPLL0]      = 1,
-        [P_MMPLL1]      = 2,
-        [P_GPLL0]       = 5,
-        [P_GPLL1]       = 4,
+static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
+        { P_XO, 0 },
+        { P_MMPLL0, 1 },
+        { P_MMPLL1, 2 },
+        { P_GPLL0, 5 },
+        { P_GPLL1, 4 }
 };
 
 static const char *mmcc_xo_mmpll0_1_gpll1_0[] = {
@@ -127,13 +129,13 @@ static const char *mmcc_xo_mmpll0_1_gpll1_0[] = {
         "gpll1_vote",
 };
 
-static const u8 mmcc_xo_dsi_hdmi_edp_map[] = {
-        [P_XO]          = 0,
-        [P_EDPLINK]     = 4,
-        [P_HDMIPLL]     = 3,
-        [P_EDPVCO]      = 5,
-        [P_DSI0PLL]     = 1,
-        [P_DSI1PLL]     = 2,
+static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
+        { P_XO, 0 },
+        { P_EDPLINK, 4 },
+        { P_HDMIPLL, 3 },
+        { P_EDPVCO, 5 },
+        { P_DSI0PLL, 1 },
+        { P_DSI1PLL, 2 }
 };
 
 static const char *mmcc_xo_dsi_hdmi_edp[] = {
@@ -145,13 +147,13 @@ static const char *mmcc_xo_dsi_hdmi_edp[] = {
         "dsi1pll",
 };
 
-static const u8 mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
-        [P_XO]          = 0,
-        [P_EDPLINK]     = 4,
-        [P_HDMIPLL]     = 3,
-        [P_GPLL0]       = 5,
-        [P_DSI0PLL]     = 1,
-        [P_DSI1PLL]     = 2,
+static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
+        { P_XO, 0 },
+        { P_EDPLINK, 4 },
+        { P_HDMIPLL, 3 },
+        { P_GPLL0, 5 },
+        { P_DSI0PLL, 1 },
+        { P_DSI1PLL, 2 }
 };
 
 static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
@@ -163,13 +165,13 @@ static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
         "dsi1pll",
 };
 
-static const u8 mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
-        [P_XO]                  = 0,
-        [P_EDPLINK]             = 4,
-        [P_HDMIPLL]             = 3,
-        [P_GPLL0]               = 5,
-        [P_DSI0PLL_BYTE]        = 1,
-        [P_DSI1PLL_BYTE]        = 2,
+static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
+        { P_XO, 0 },
+        { P_EDPLINK, 4 },
+        { P_HDMIPLL, 3 },
+        { P_GPLL0, 5 },
+        { P_DSI0PLL_BYTE, 1 },
+        { P_DSI1PLL_BYTE, 2 }
 };
 
 static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 006c6f294310..17e9af7fe81f 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5250.o
 obj-$(CONFIG_SOC_EXYNOS5260)    += clk-exynos5260.o
 obj-$(CONFIG_SOC_EXYNOS5410)    += clk-exynos5410.o
 obj-$(CONFIG_SOC_EXYNOS5420)    += clk-exynos5420.o
+obj-$(CONFIG_ARCH_EXYNOS5433)   += clk-exynos5433.o
 obj-$(CONFIG_SOC_EXYNOS5440)    += clk-exynos5440.o
 obj-$(CONFIG_ARCH_EXYNOS)       += clk-exynos-audss.o
 obj-$(CONFIG_ARCH_EXYNOS)       += clk-exynos-clkout.o
diff --git a/drivers/clk/samsung/clk-exynos-clkout.c b/drivers/clk/samsung/clk-exynos-clkout.c
index 3a7cb2506731..1eb16b868421 100644
--- a/drivers/clk/samsung/clk-exynos-clkout.c
+++ b/drivers/clk/samsung/clk-exynos-clkout.c
@@ -151,3 +151,5 @@ CLK_OF_DECLARE(exynos5250_clkout, "samsung,exynos5250-pmu",
                 exynos5_clkout_init);
 CLK_OF_DECLARE(exynos5420_clkout, "samsung,exynos5420-pmu",
                 exynos5_clkout_init);
+CLK_OF_DECLARE(exynos5433_clkout, "samsung,exynos5433-pmu",
+                exynos5_clkout_init);
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
new file mode 100644
index 000000000000..387e3e39e635
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -0,0 +1,5423 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Chanwoo Choi <cw00.choi@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5443 SoC.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+
+#include <dt-bindings/clock/exynos5433.h>
+
+#include "clk.h"
+#include "clk-pll.h"
+
+/*
+ * Register offset definitions for CMU_TOP
+ */
+#define ISP_PLL_LOCK                    0x0000
+#define AUD_PLL_LOCK                    0x0004
+#define ISP_PLL_CON0                    0x0100
+#define ISP_PLL_CON1                    0x0104
+#define ISP_PLL_FREQ_DET                0x0108
+#define AUD_PLL_CON0                    0x0110
+#define AUD_PLL_CON1                    0x0114
+#define AUD_PLL_CON2                    0x0118
+#define AUD_PLL_FREQ_DET                0x011c
+#define MUX_SEL_TOP0                    0x0200
+#define MUX_SEL_TOP1                    0x0204
+#define MUX_SEL_TOP2                    0x0208
+#define MUX_SEL_TOP3                    0x020c
+#define MUX_SEL_TOP4                    0x0210
+#define MUX_SEL_TOP_MSCL                0x0220
+#define MUX_SEL_TOP_CAM1                0x0224
+#define MUX_SEL_TOP_DISP                0x0228
+#define MUX_SEL_TOP_FSYS0               0x0230
+#define MUX_SEL_TOP_FSYS1               0x0234
+#define MUX_SEL_TOP_PERIC0              0x0238
+#define MUX_SEL_TOP_PERIC1              0x023c
+#define MUX_ENABLE_TOP0                 0x0300
+#define MUX_ENABLE_TOP1                 0x0304
+#define MUX_ENABLE_TOP2                 0x0308
+#define MUX_ENABLE_TOP3                 0x030c
+#define MUX_ENABLE_TOP4                 0x0310
+#define MUX_ENABLE_TOP_MSCL             0x0320
+#define MUX_ENABLE_TOP_CAM1             0x0324
+#define MUX_ENABLE_TOP_DISP             0x0328
+#define MUX_ENABLE_TOP_FSYS0            0x0330
+#define MUX_ENABLE_TOP_FSYS1            0x0334
+#define MUX_ENABLE_TOP_PERIC0           0x0338
+#define MUX_ENABLE_TOP_PERIC1           0x033c
+#define MUX_STAT_TOP0                   0x0400
+#define MUX_STAT_TOP1                   0x0404
+#define MUX_STAT_TOP2                   0x0408
+#define MUX_STAT_TOP3                   0x040c
+#define MUX_STAT_TOP4                   0x0410
+#define MUX_STAT_TOP_MSCL               0x0420
+#define MUX_STAT_TOP_CAM1               0x0424
+#define MUX_STAT_TOP_FSYS0              0x0430
+#define MUX_STAT_TOP_FSYS1              0x0434
+#define MUX_STAT_TOP_PERIC0             0x0438
+#define MUX_STAT_TOP_PERIC1             0x043c
+#define DIV_TOP0                        0x0600
+#define DIV_TOP1                        0x0604
+#define DIV_TOP2                        0x0608
+#define DIV_TOP3                        0x060c
+#define DIV_TOP4                        0x0610
+#define DIV_TOP_MSCL                    0x0618
+#define DIV_TOP_CAM10                   0x061c
+#define DIV_TOP_CAM11                   0x0620
+#define DIV_TOP_FSYS0                   0x062c
+#define DIV_TOP_FSYS1                   0x0630
+#define DIV_TOP_FSYS2                   0x0634
+#define DIV_TOP_PERIC0                  0x0638
+#define DIV_TOP_PERIC1                  0x063c
+#define DIV_TOP_PERIC2                  0x0640
+#define DIV_TOP_PERIC3                  0x0644
+#define DIV_TOP_PERIC4                  0x0648
+#define DIV_TOP_PLL_FREQ_DET            0x064c
+#define DIV_STAT_TOP0                   0x0700
+#define DIV_STAT_TOP1                   0x0704
+#define DIV_STAT_TOP2                   0x0708
+#define DIV_STAT_TOP3                   0x070c
+#define DIV_STAT_TOP4                   0x0710
+#define DIV_STAT_TOP_MSCL               0x0718
+#define DIV_STAT_TOP_CAM10              0x071c
+#define DIV_STAT_TOP_CAM11              0x0720
+#define DIV_STAT_TOP_FSYS0              0x072c
+#define DIV_STAT_TOP_FSYS1              0x0730
+#define DIV_STAT_TOP_FSYS2              0x0734
+#define DIV_STAT_TOP_PERIC0             0x0738
+#define DIV_STAT_TOP_PERIC1             0x073c
+#define DIV_STAT_TOP_PERIC2             0x0740
+#define DIV_STAT_TOP_PERIC3             0x0744
+#define DIV_STAT_TOP_PLL_FREQ_DET       0x074c
+#define ENABLE_ACLK_TOP                 0x0800
+#define ENABLE_SCLK_TOP                 0x0a00
+#define ENABLE_SCLK_TOP_MSCL            0x0a04
+#define ENABLE_SCLK_TOP_CAM1            0x0a08
+#define ENABLE_SCLK_TOP_DISP            0x0a0c
+#define ENABLE_SCLK_TOP_FSYS            0x0a10
+#define ENABLE_SCLK_TOP_PERIC           0x0a14
+#define ENABLE_IP_TOP                   0x0b00
+#define ENABLE_CMU_TOP                  0x0c00
+#define ENABLE_CMU_TOP_DIV_STAT         0x0c04
+
+static unsigned long top_clk_regs[] __initdata = {
+        ISP_PLL_LOCK,
+        AUD_PLL_LOCK,
+        ISP_PLL_CON0,
+        ISP_PLL_CON1,
+        ISP_PLL_FREQ_DET,
+        AUD_PLL_CON0,
+        AUD_PLL_CON1,
+        AUD_PLL_CON2,
+        AUD_PLL_FREQ_DET,
+        MUX_SEL_TOP0,
+        MUX_SEL_TOP1,
+        MUX_SEL_TOP2,
+        MUX_SEL_TOP3,
+        MUX_SEL_TOP4,
+        MUX_SEL_TOP_MSCL,
+        MUX_SEL_TOP_CAM1,
+        MUX_SEL_TOP_DISP,
+        MUX_SEL_TOP_FSYS0,
+        MUX_SEL_TOP_FSYS1,
+        MUX_SEL_TOP_PERIC0,
+        MUX_SEL_TOP_PERIC1,
+        MUX_ENABLE_TOP0,
+        MUX_ENABLE_TOP1,
+        MUX_ENABLE_TOP2,
+        MUX_ENABLE_TOP3,
+        MUX_ENABLE_TOP4,
+        MUX_ENABLE_TOP_MSCL,
+        MUX_ENABLE_TOP_CAM1,
+        MUX_ENABLE_TOP_DISP,
+        MUX_ENABLE_TOP_FSYS0,
+        MUX_ENABLE_TOP_FSYS1,
+        MUX_ENABLE_TOP_PERIC0,
+        MUX_ENABLE_TOP_PERIC1,
+        MUX_STAT_TOP0,
+        MUX_STAT_TOP1,
+        MUX_STAT_TOP2,
+        MUX_STAT_TOP3,
+        MUX_STAT_TOP4,
+        MUX_STAT_TOP_MSCL,
+        MUX_STAT_TOP_CAM1,
+        MUX_STAT_TOP_FSYS0,
+        MUX_STAT_TOP_FSYS1,
+        MUX_STAT_TOP_PERIC0,
+        MUX_STAT_TOP_PERIC1,
+        DIV_TOP0,
+        DIV_TOP1,
+        DIV_TOP2,
+        DIV_TOP3,
+        DIV_TOP4,
+        DIV_TOP_MSCL,
+        DIV_TOP_CAM10,
+        DIV_TOP_CAM11,
+        DIV_TOP_FSYS0,
+        DIV_TOP_FSYS1,
+        DIV_TOP_FSYS2,
+        DIV_TOP_PERIC0,
+        DIV_TOP_PERIC1,
+        DIV_TOP_PERIC2,
+        DIV_TOP_PERIC3,
+        DIV_TOP_PERIC4,
+        DIV_TOP_PLL_FREQ_DET,
+        DIV_STAT_TOP0,
+        DIV_STAT_TOP1,
+        DIV_STAT_TOP2,
+        DIV_STAT_TOP3,
+        DIV_STAT_TOP4,
+        DIV_STAT_TOP_MSCL,
+        DIV_STAT_TOP_CAM10,
+        DIV_STAT_TOP_CAM11,
+        DIV_STAT_TOP_FSYS0,
+        DIV_STAT_TOP_FSYS1,
+        DIV_STAT_TOP_FSYS2,
+        DIV_STAT_TOP_PERIC0,
+        DIV_STAT_TOP_PERIC1,
+        DIV_STAT_TOP_PERIC2,
+        DIV_STAT_TOP_PERIC3,
+        DIV_STAT_TOP_PLL_FREQ_DET,
+        ENABLE_ACLK_TOP,
+        ENABLE_SCLK_TOP,
+        ENABLE_SCLK_TOP_MSCL,
+        ENABLE_SCLK_TOP_CAM1,
+        ENABLE_SCLK_TOP_DISP,
+        ENABLE_SCLK_TOP_FSYS,
+        ENABLE_SCLK_TOP_PERIC,
+        ENABLE_IP_TOP,
+        ENABLE_CMU_TOP,
+        ENABLE_CMU_TOP_DIV_STAT,
+};
+
+/* list of all parent clock list */
+PNAME(mout_aud_pll_p)           = { "oscclk", "fout_aud_pll", };
+PNAME(mout_isp_pll_p)           = { "oscclk", "fout_isp_pll", };
+PNAME(mout_aud_pll_user_p)      = { "oscclk", "mout_aud_pll", };
+PNAME(mout_mphy_pll_user_p)     = { "oscclk", "sclk_mphy_pll", };
+PNAME(mout_mfc_pll_user_p)      = { "oscclk", "sclk_mfc_pll", };
+PNAME(mout_bus_pll_user_p)      = { "oscclk", "sclk_bus_pll", };
+PNAME(mout_bus_pll_user_t_p)    = { "oscclk", "mout_bus_pll_user", };
+PNAME(mout_mphy_pll_user_t_p)   = { "oscclk", "mout_mphy_pll_user", };
+
+PNAME(mout_bus_mfc_pll_user_p)  = { "mout_bus_pll_user", "mout_mfc_pll_user",};
+PNAME(mout_mfc_bus_pll_user_p)  = { "mout_mfc_pll_user", "mout_bus_pll_user",};
+PNAME(mout_aclk_cam1_552_b_p)   = { "mout_aclk_cam1_552_a",
+                                    "mout_mfc_pll_user", };
+PNAME(mout_aclk_cam1_552_a_p)   = { "mout_isp_pll", "mout_bus_pll_user", };
+
+PNAME(mout_aclk_mfc_400_c_p)    = { "mout_aclk_mfc_400_b",
+                                    "mout_mphy_pll_user", };
+PNAME(mout_aclk_mfc_400_b_p)    = { "mout_aclk_mfc_400_a",
+                                    "mout_bus_pll_user", };
+PNAME(mout_aclk_mfc_400_a_p)    = { "mout_mfc_pll_user", "mout_isp_pll", };
+
+PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
+                                    "mout_mphy_pll_user", };
+PNAME(mout_aclk_mscl_b_p)       = { "mout_aclk_mscl_400_a",
+                                    "mout_mphy_pll_user", };
+PNAME(mout_aclk_g2d_400_b_p)    = { "mout_aclk_g2d_400_a",
+                                    "mout_mphy_pll_user", };
+
+PNAME(mout_sclk_jpeg_c_p)       = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
+PNAME(mout_sclk_jpeg_b_p)       = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
+
+PNAME(mout_sclk_mmc2_b_p)       = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
+PNAME(mout_sclk_mmc1_b_p)       = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
+PNAME(mout_sclk_mmc0_d_p)       = { "mout_sclk_mmc0_c", "mout_isp_pll", };
+PNAME(mout_sclk_mmc0_c_p)       = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
+PNAME(mout_sclk_mmc0_b_p)       = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
+
+PNAME(mout_sclk_spdif_p)        = { "sclk_audio0", "sclk_audio1",
+                                    "oscclk", "ioclk_spdif_extclk", };
+PNAME(mout_sclk_audio1_p)       = { "ioclk_audiocdclk1", "oscclk",
+                                    "mout_aud_pll_user_t",};
+PNAME(mout_sclk_audio0_p)       = { "ioclk_audiocdclk0", "oscclk",
+                                    "mout_aud_pll_user_t",};
+
+PNAME(mout_sclk_hdmi_spdif_p)   = { "sclk_audio1", "ioclk_spdif_extclk", };
+
+static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
+        FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
+};
+
+static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
+        /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
+        FRATE(0, "ioclk_audiocdclk1", NULL, CLK_IS_ROOT, 100000000),
+        FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000),
+        /* Xi2s1SDI input clock for SPDIF */
+        FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 100000000),
+        /* XspiCLK[4:0] input clock for SPI */
+        FRATE(0, "ioclk_spi4_clk_in", NULL, CLK_IS_ROOT, 50000000),
+        FRATE(0, "ioclk_spi3_clk_in", NULL, CLK_IS_ROOT, 50000000),
+        FRATE(0, "ioclk_spi2_clk_in", NULL, CLK_IS_ROOT, 50000000),
+        FRATE(0, "ioclk_spi1_clk_in", NULL, CLK_IS_ROOT, 50000000),
+        FRATE(0, "ioclk_spi0_clk_in", NULL, CLK_IS_ROOT, 50000000),
+        /* Xi2s1SCLK input clock for I2S1_BCLK */
+        FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000),
+};
+
+static struct samsung_mux_clock top_mux_clks[] __initdata = {
+        /* MUX_SEL_TOP0 */
+        MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
+                        4, 1),
+        MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
+                        0, 1),
+
+        /* MUX_SEL_TOP1 */
+        MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
+                        mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
+        MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
+                        MUX_SEL_TOP1, 8, 1),
+        MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
+                        MUX_SEL_TOP1, 4, 1),
+        MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
+                        MUX_SEL_TOP1, 0, 1),
+
+        /* MUX_SEL_TOP2 */
+        MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
+                        mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
+        MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
+                        mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
+        MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
+                        mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
+        MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
+                        mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
+        MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
+                        mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
+        MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
+                        mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
+
+        /* MUX_SEL_TOP3 */
+        MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
+                        mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
+        MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
+                        mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
+        MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
+                        mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
+        MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
+                        mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
+        MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
+                        mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
+        MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
+                        mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
+
+        /* MUX_SEL_TOP4 */
+        MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
+                        mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
+        MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
+                        mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
+        MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
+                        mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
+
+        /* MUX_SEL_TOP_MSCL */
+        MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
+                        MUX_SEL_TOP_MSCL, 8, 1),
+        MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
+                        MUX_SEL_TOP_MSCL, 4, 1),
+        MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
+                        MUX_SEL_TOP_MSCL, 0, 1),
+
+        /* MUX_SEL_TOP_CAM1 */
+        MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
+                        mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
+        MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
+                        mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
+        MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
+                        mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
+        MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
+                        mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
+        MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
+                        mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
+        MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
+                        mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
+
+        /* MUX_SEL_TOP_FSYS0 */
+        MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
+                        MUX_SEL_TOP_FSYS0, 28, 1),
+        MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
+                        MUX_SEL_TOP_FSYS0, 24, 1),
+        MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
+                        MUX_SEL_TOP_FSYS0, 20, 1),
+        MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
+                        MUX_SEL_TOP_FSYS0, 16, 1),
+        MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
+                        MUX_SEL_TOP_FSYS0, 12, 1),
+        MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
+                        MUX_SEL_TOP_FSYS0, 8, 1),
+        MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
+                        MUX_SEL_TOP_FSYS0, 4, 1),
+        MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
+                        MUX_SEL_TOP_FSYS0, 0, 1),
+
+        /* MUX_SEL_TOP_FSYS1 */
+        MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
+                        MUX_SEL_TOP_FSYS1, 12, 1),
+        MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
+                        mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
+        MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
+                        mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
+        MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
+                        mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
+
+        /* MUX_SEL_TOP_PERIC0 */
+        MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
+                        MUX_SEL_TOP_PERIC0, 28, 1),
+        MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
+                        MUX_SEL_TOP_PERIC0, 24, 1),
+        MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
+                        MUX_SEL_TOP_PERIC0, 20, 1),
+        MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
+                        MUX_SEL_TOP_PERIC0, 16, 1),
+        MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
+                        MUX_SEL_TOP_PERIC0, 12, 1),
+        MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
+                        MUX_SEL_TOP_PERIC0, 8, 1),
+        MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
+                        MUX_SEL_TOP_PERIC0, 4, 1),
+        MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
+                        MUX_SEL_TOP_PERIC0, 0, 1),
+
+        /* MUX_SEL_TOP_PERIC1 */
+        MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
+                        MUX_SEL_TOP_PERIC1, 16, 1),
+        MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
+                        MUX_SEL_TOP_PERIC1, 12, 2),
+        MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
+                        MUX_SEL_TOP_PERIC1, 4, 2),
+        MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
+                        MUX_SEL_TOP_PERIC1, 0, 2),
+
+        /* MUX_SEL_TOP_DISP */
+        MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
+                        mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
+};
+
+static struct samsung_div_clock top_div_clks[] __initdata = {
+        /* DIV_TOP0 */
+        DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333",
+                        DIV_TOP0, 28, 3),
+        DIV(CLK_DIV_ACLK_CAM1_400, "div_aclk_cam1_400", "mout_bus_pll_user",
+                        DIV_TOP0, 24, 3),
+        DIV(CLK_DIV_ACLK_CAM1_552, "div_aclk_cam1_552", "mout_aclk_cam1_552_b",
+                        DIV_TOP0, 20, 3),
+        DIV(CLK_DIV_ACLK_CAM0_333, "div_aclk_cam0_333", "mout_mfc_pll_user",
+                        DIV_TOP0, 16, 3),
+        DIV(CLK_DIV_ACLK_CAM0_400, "div_aclk_cam0_400", "mout_bus_pll_user",
+                        DIV_TOP0, 12, 3),
+        DIV(CLK_DIV_ACLK_CAM0_552, "div_aclk_cam0_552", "mout_isp_pll",
+                        DIV_TOP0, 8, 3),
+        DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400",
+                        "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4),
+        DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400",
+                        "mout_aclk_isp_400", DIV_TOP0, 0, 4),
+
+        /* DIV_TOP1 */
+        DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
+                        DIV_TOP1, 28, 3),
+        DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
+                        DIV_TOP1, 24, 3),
+        DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400",
+                        DIV_TOP1, 20, 3),
+        DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
+                        DIV_TOP1, 12, 3),
+        DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user",
+                        DIV_TOP1, 8, 3),
+        DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
+                        DIV_TOP1, 0, 3),
+
+        /* DIV_TOP2 */
+        DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b",
+                        DIV_TOP2, 4, 3),
+        DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
+                        DIV_TOP2, 0, 3),
+
+        /* DIV_TOP3 */
+        DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
+                        "mout_bus_pll_user", DIV_TOP3, 24, 3),
+        DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
+                        "mout_bus_pll_user", DIV_TOP3, 20, 3),
+        DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
+                        "mout_bus_pll_user", DIV_TOP3, 16, 3),
+        DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
+                        "div_aclk_peric_66_a", DIV_TOP3, 12, 3),
+        DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
+                        "mout_bus_pll_user", DIV_TOP3, 8, 3),
+        DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
+                        "div_aclk_peris_66_a", DIV_TOP3, 4, 3),
+        DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
+                        "mout_bus_pll_user", DIV_TOP3, 0, 3),
+
+        /* DIV_TOP4 */
+        DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
+                        DIV_TOP4, 8, 3),
+        DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
+                        DIV_TOP4, 4, 3),
+        DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
+                        DIV_TOP4, 0, 3),
+
+        /* DIV_TOP_MSCL */
+        DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c",
+                        DIV_TOP_MSCL, 0, 4),
+
+        /* DIV_TOP_CAM10 */
+        DIV(CLK_DIV_SCLK_ISP_UART, "div_sclk_isp_uart", "mout_sclk_isp_uart",
+                        DIV_TOP_CAM10, 24, 5),
+        DIV(CLK_DIV_SCLK_ISP_SPI1_B, "div_sclk_isp_spi1_b",
+                        "div_sclk_isp_spi1_a", DIV_TOP_CAM10, 16, 8),
+        DIV(CLK_DIV_SCLK_ISP_SPI1_A, "div_sclk_isp_spi1_a",
+                        "mout_sclk_isp_spi1", DIV_TOP_CAM10, 12, 4),
+        DIV(CLK_DIV_SCLK_ISP_SPI0_B, "div_sclk_isp_spi0_b",
+                        "div_sclk_isp_spi0_a", DIV_TOP_CAM10, 4, 8),
+        DIV(CLK_DIV_SCLK_ISP_SPI0_A, "div_sclk_isp_spi0_a",
+                        "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4),
+
+        /* DIV_TOP_CAM11 */
+        DIV(CLK_DIV_SCLK_ISP_SENSOR2_B, "div_sclk_isp_sensor2_b",
+                        "div_sclk_isp_sensor2_a", DIV_TOP_CAM11, 20, 4),
+        DIV(CLK_DIV_SCLK_ISP_SENSOR2_A, "div_sclk_isp_sensor2_a",
+                        "mout_sclk_isp_sensor2", DIV_TOP_CAM11, 16, 4),
+        DIV(CLK_DIV_SCLK_ISP_SENSOR1_B, "div_sclk_isp_sensor1_b",
+                        "div_sclk_isp_sensor1_a", DIV_TOP_CAM11, 12, 4),
+        DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a",
+                        "mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4),
+        DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b",
+                        "div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 12, 4),
+        DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a",
+                        "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 8, 4),
+
+        /* DIV_TOP_FSYS0 */
+        DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
+                        DIV_TOP_FSYS0, 16, 8),
+        DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
+                        DIV_TOP_FSYS0, 12, 4),
+        DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
+                        DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
+        DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
+                        DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
+
+        /* DIV_TOP_FSYS1 */
+        DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
+                        DIV_TOP_FSYS1, 4, 8),
+        DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
+                        DIV_TOP_FSYS1, 0, 4),
+
+        /* DIV_TOP_FSYS2 */
+        DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
+                        DIV_TOP_FSYS2, 12, 3),
+        DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
+                        "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
+        DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
+                        "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
+        DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
+                        DIV_TOP_FSYS2, 0, 4),
+
+        /* DIV_TOP_PERIC0 */
+        DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
+                        DIV_TOP_PERIC0, 16, 8),
+        DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
+                        DIV_TOP_PERIC0, 12, 4),
+        DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
+                        DIV_TOP_PERIC0, 4, 8),
+        DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
+                        DIV_TOP_PERIC0, 0, 4),
+
+        /* DIV_TOP_PERIC1 */
+        DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
+                        DIV_TOP_PERIC1, 4, 8),
+        DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
+                        DIV_TOP_PERIC1, 0, 4),
+
+        /* DIV_TOP_PERIC2 */
+        DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
+                        DIV_TOP_PERIC2, 8, 4),
+        DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
+                        DIV_TOP_PERIC2, 4, 4),
+        DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
+                        DIV_TOP_PERIC2, 0, 4),
+
+        /* DIV_TOP_PERIC3 */
+        DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
+                        DIV_TOP_PERIC3, 16, 6),
+        DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
+                        DIV_TOP_PERIC3, 8, 8),
+        DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
+                        DIV_TOP_PERIC3, 4, 4),
+        DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
+                        DIV_TOP_PERIC3, 0, 4),
+
+        /* DIV_TOP_PERIC4 */
+        DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
+                        DIV_TOP_PERIC4, 16, 8),
+        DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
+                        DIV_TOP_PERIC4, 12, 4),
+        DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
+                        DIV_TOP_PERIC4, 4, 8),
+        DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
+                        DIV_TOP_PERIC4, 0, 4),
+};
+
+static struct samsung_gate_clock top_gate_clks[] __initdata = {
+        /* ENABLE_ACLK_TOP */
+        GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
+                        ENABLE_ACLK_TOP, 30, 0, 0),
+        GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266",
+                        "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
+                        29, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
+                        ENABLE_ACLK_TOP, 26,
+                        CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
+                        ENABLE_ACLK_TOP, 25,
+                        CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",
+                        ENABLE_ACLK_TOP, 24,
+                        CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200",
+                        ENABLE_ACLK_TOP, 23,
+                        CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
+                        ENABLE_ACLK_TOP, 22,
+                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
+                        ENABLE_ACLK_TOP, 21,
+                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
+                        ENABLE_ACLK_TOP, 19,
+                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
+                        ENABLE_ACLK_TOP, 18,
+                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
+                        ENABLE_ACLK_TOP, 15,
+                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
+                        ENABLE_ACLK_TOP, 14,
+                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333",
+                        ENABLE_ACLK_TOP, 13,
+                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400",
+                        ENABLE_ACLK_TOP, 12,
+                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552",
+                        ENABLE_ACLK_TOP, 11,
+                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333",
+                        ENABLE_ACLK_TOP, 10,
+                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400",
+                        ENABLE_ACLK_TOP, 9,
+                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552",
+                        ENABLE_ACLK_TOP, 8,
+                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
+                        ENABLE_ACLK_TOP, 7,
+                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
+                        ENABLE_ACLK_TOP, 6,
+                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
+                        ENABLE_ACLK_TOP, 5,
+                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
+                        ENABLE_ACLK_TOP, 3,
+                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
+                        ENABLE_ACLK_TOP, 2,
+                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
+                        ENABLE_ACLK_TOP, 0,
+                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_SCLK_TOP_MSCL */
+        GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg",
+                        ENABLE_SCLK_TOP_MSCL, 0, 0, 0),
+
+        /* ENABLE_SCLK_TOP_CAM1 */
+        GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
+                        ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
+        GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b",
+                        ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
+        GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b",
+                        ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
+        GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk",
+                        ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
+        GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart",
+                        ENABLE_SCLK_TOP_CAM1, 2, 0, 0),
+        GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b",
+                        ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
+        GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b",
+                        ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
+
+        /* ENABLE_SCLK_TOP_DISP */
+        GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
+                        "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
+                        CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_SCLK_TOP_FSYS */
+        GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
+                        ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
+        GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
+                        ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
+                        ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
+                        ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
+                        "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
+                        3, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
+                        "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
+                        1, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
+                        "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS,
+                        0, CLK_SET_RATE_PARENT, 0),
+
+        /* ENABLE_SCLK_TOP_PERIC */
+        GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
+                        ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
+                        ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
+                        ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
+                        ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
+                        ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
+                        ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
+                        ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
+                        ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
+                        ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
+                        ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
+                        ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
+
+        /* MUX_ENABLE_TOP_PERIC1 */
+        GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
+                        MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
+        GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
+                        MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
+        GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
+                        MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
+};
+
+/*
+ * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
+ * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
+ */
+static struct samsung_pll_rate_table exynos5443_pll_rates[] = {
+        PLL_35XX_RATE(2500000000U, 625, 6,  0),
+        PLL_35XX_RATE(2400000000U, 500, 5,  0),
+        PLL_35XX_RATE(2300000000U, 575, 6,  0),
+        PLL_35XX_RATE(2200000000U, 550, 6,  0),
+        PLL_35XX_RATE(2100000000U, 350, 4,  0),
+        PLL_35XX_RATE(2000000000U, 500, 6,  0),
+        PLL_35XX_RATE(1900000000U, 475, 6,  0),
+        PLL_35XX_RATE(1800000000U, 375, 5,  0),
+        PLL_35XX_RATE(1700000000U, 425, 6,  0),
+        PLL_35XX_RATE(1600000000U, 400, 6,  0),
+        PLL_35XX_RATE(1500000000U, 250, 4,  0),
+        PLL_35XX_RATE(1400000000U, 350, 6,  0),
+        PLL_35XX_RATE(1332000000U, 222, 4,  0),
+        PLL_35XX_RATE(1300000000U, 325, 6,  0),
+        PLL_35XX_RATE(1200000000U, 500, 5,  1),
+        PLL_35XX_RATE(1100000000U, 550, 6,  1),
+        PLL_35XX_RATE(1086000000U, 362, 4,  1),
+        PLL_35XX_RATE(1066000000U, 533, 6,  1),
+        PLL_35XX_RATE(1000000000U, 500, 6,  1),
+        PLL_35XX_RATE(933000000U,  311, 4,  1),
+        PLL_35XX_RATE(921000000U,  307, 4,  1),
+        PLL_35XX_RATE(900000000U,  375, 5,  1),
+        PLL_35XX_RATE(825000000U,  275, 4,  1),
+        PLL_35XX_RATE(800000000U,  400, 6,  1),
+        PLL_35XX_RATE(733000000U,  733, 12, 1),
+        PLL_35XX_RATE(700000000U,  360, 6,  1),
+        PLL_35XX_RATE(667000000U,  222, 4,  1),
+        PLL_35XX_RATE(633000000U,  211, 4,  1),
+        PLL_35XX_RATE(600000000U,  500, 5,  2),
+        PLL_35XX_RATE(552000000U,  460, 5,  2),
+        PLL_35XX_RATE(550000000U,  550, 6,  2),
+        PLL_35XX_RATE(543000000U,  362, 4,  2),
+        PLL_35XX_RATE(533000000U,  533, 6,  2),
+        PLL_35XX_RATE(500000000U,  500, 6,  2),
+        PLL_35XX_RATE(444000000U,  370, 5,  2),
+        PLL_35XX_RATE(420000000U,  350, 5,  2),
+        PLL_35XX_RATE(400000000U,  400, 6,  2),
+        PLL_35XX_RATE(350000000U,  360, 6,  2),
+        PLL_35XX_RATE(333000000U,  222, 4,  2),
+        PLL_35XX_RATE(300000000U,  500, 5,  3),
+        PLL_35XX_RATE(266000000U,  532, 6,  3),
+        PLL_35XX_RATE(200000000U,  400, 6,  3),
+        PLL_35XX_RATE(166000000U,  332, 6,  3),
+        PLL_35XX_RATE(160000000U,  320, 6,  3),
+        PLL_35XX_RATE(133000000U,  552, 6,  4),
+        PLL_35XX_RATE(100000000U,  400, 6,  4),
+        { /* sentinel */ }
+};
+
+/* AUD_PLL */
+static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = {
+        PLL_36XX_RATE(400000000U, 200, 3, 2,      0),
+        PLL_36XX_RATE(393216000U, 197, 3, 2, -25690),
+        PLL_36XX_RATE(384000000U, 128, 2, 2,      0),
+        PLL_36XX_RATE(368640000U, 246, 4, 2, -15729),
+        PLL_36XX_RATE(361507200U, 181, 3, 2, -16148),
+        PLL_36XX_RATE(338688000U, 113, 2, 2,  -6816),
+        PLL_36XX_RATE(294912000U,  98, 1, 3,  19923),
+        PLL_36XX_RATE(288000000U,  96, 1, 3,      0),
+        PLL_36XX_RATE(252000000U,  84, 1, 3,      0),
+        { /* sentinel */ }
+};
+
+static struct samsung_pll_clock top_pll_clks[] __initdata = {
+        PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
+                ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates),
+        PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
+                AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates),
+};
+
+static struct samsung_cmu_info top_cmu_info __initdata = {
+        .pll_clks               = top_pll_clks,
+        .nr_pll_clks            = ARRAY_SIZE(top_pll_clks),
+        .mux_clks               = top_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(top_mux_clks),
+        .div_clks               = top_div_clks,
+        .nr_div_clks            = ARRAY_SIZE(top_div_clks),
+        .gate_clks              = top_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(top_gate_clks),
+        .fixed_clks             = top_fixed_clks,
+        .nr_fixed_clks          = ARRAY_SIZE(top_fixed_clks),
+        .fixed_factor_clks      = top_fixed_factor_clks,
+        .nr_fixed_factor_clks   = ARRAY_SIZE(top_fixed_factor_clks),
+        .nr_clk_ids             = TOP_NR_CLK,
+        .clk_regs               = top_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(top_clk_regs),
+};
+
+static void __init exynos5433_cmu_top_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &top_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
+                exynos5433_cmu_top_init);
+
+/*
+ * Register offset definitions for CMU_CPIF
+ */
+#define MPHY_PLL_LOCK           0x0000
+#define MPHY_PLL_CON0           0x0100
+#define MPHY_PLL_CON1           0x0104
+#define MPHY_PLL_FREQ_DET       0x010c
+#define MUX_SEL_CPIF0           0x0200
+#define DIV_CPIF                0x0600
+#define ENABLE_SCLK_CPIF        0x0a00
+
+static unsigned long cpif_clk_regs[] __initdata = {
+        MPHY_PLL_LOCK,
+        MPHY_PLL_CON0,
+        MPHY_PLL_CON1,
+        MPHY_PLL_FREQ_DET,
+        MUX_SEL_CPIF0,
+        ENABLE_SCLK_CPIF,
+};
+
+/* list of all parent clock list */
+PNAME(mout_mphy_pll_p)          = { "oscclk", "fout_mphy_pll", };
+
+static struct samsung_pll_clock cpif_pll_clks[] __initdata = {
+        PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
+                MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates),
+};
+
+static struct samsung_mux_clock cpif_mux_clks[] __initdata = {
+        /* MUX_SEL_CPIF0 */
+        MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
+                        0, 1),
+};
+
+static struct samsung_div_clock cpif_div_clks[] __initdata = {
+        /* DIV_CPIF */
+        DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
+                        0, 6),
+};
+
+static struct samsung_gate_clock cpif_gate_clks[] __initdata = {
+        /* ENABLE_SCLK_CPIF */
+        GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
+                        ENABLE_SCLK_CPIF, 9, 0, 0),
+        GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
+                        ENABLE_SCLK_CPIF, 4, 0, 0),
+};
+
+static struct samsung_cmu_info cpif_cmu_info __initdata = {
+        .pll_clks               = cpif_pll_clks,
+        .nr_pll_clks            = ARRAY_SIZE(cpif_pll_clks),
+        .mux_clks               = cpif_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(cpif_mux_clks),
+        .div_clks               = cpif_div_clks,
+        .nr_div_clks            = ARRAY_SIZE(cpif_div_clks),
+        .gate_clks              = cpif_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(cpif_gate_clks),
+        .nr_clk_ids             = CPIF_NR_CLK,
+        .clk_regs               = cpif_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(cpif_clk_regs),
+};
+
+static void __init exynos5433_cmu_cpif_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &cpif_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
+                exynos5433_cmu_cpif_init);
+
+/*
+ * Register offset definitions for CMU_MIF
+ */
+#define MEM0_PLL_LOCK                   0x0000
+#define MEM1_PLL_LOCK                   0x0004
+#define BUS_PLL_LOCK                    0x0008
+#define MFC_PLL_LOCK                    0x000c
+#define MEM0_PLL_CON0                   0x0100
+#define MEM0_PLL_CON1                   0x0104
+#define MEM0_PLL_FREQ_DET               0x010c
+#define MEM1_PLL_CON0                   0x0110
+#define MEM1_PLL_CON1                   0x0114
+#define MEM1_PLL_FREQ_DET               0x011c
+#define BUS_PLL_CON0                    0x0120
+#define BUS_PLL_CON1                    0x0124
+#define BUS_PLL_FREQ_DET                0x012c
+#define MFC_PLL_CON0                    0x0130
+#define MFC_PLL_CON1                    0x0134
+#define MFC_PLL_FREQ_DET                0x013c
+#define MUX_SEL_MIF0                    0x0200
+#define MUX_SEL_MIF1                    0x0204
+#define MUX_SEL_MIF2                    0x0208
+#define MUX_SEL_MIF3                    0x020c
+#define MUX_SEL_MIF4                    0x0210
+#define MUX_SEL_MIF5                    0x0214
+#define MUX_SEL_MIF6                    0x0218
+#define MUX_SEL_MIF7                    0x021c
+#define MUX_ENABLE_MIF0                 0x0300
+#define MUX_ENABLE_MIF1                 0x0304
+#define MUX_ENABLE_MIF2                 0x0308
+#define MUX_ENABLE_MIF3                 0x030c
+#define MUX_ENABLE_MIF4                 0x0310
+#define MUX_ENABLE_MIF5                 0x0314
+#define MUX_ENABLE_MIF6                 0x0318
+#define MUX_ENABLE_MIF7                 0x031c
+#define MUX_STAT_MIF0                   0x0400
+#define MUX_STAT_MIF1                   0x0404
+#define MUX_STAT_MIF2                   0x0408
+#define MUX_STAT_MIF3                   0x040c
+#define MUX_STAT_MIF4                   0x0410
+#define MUX_STAT_MIF5                   0x0414
+#define MUX_STAT_MIF6                   0x0418
+#define MUX_STAT_MIF7                   0x041c
+#define DIV_MIF1                        0x0604
+#define DIV_MIF2                        0x0608
+#define DIV_MIF3                        0x060c
+#define DIV_MIF4                        0x0610
+#define DIV_MIF5                        0x0614
+#define DIV_MIF_PLL_FREQ_DET            0x0618
+#define DIV_STAT_MIF1                   0x0704
+#define DIV_STAT_MIF2                   0x0708
+#define DIV_STAT_MIF3                   0x070c
+#define DIV_STAT_MIF4                   0x0710
+#define DIV_STAT_MIF5                   0x0714
+#define DIV_STAT_MIF_PLL_FREQ_DET       0x0718
+#define ENABLE_ACLK_MIF0                0x0800
+#define ENABLE_ACLK_MIF1                0x0804
+#define ENABLE_ACLK_MIF2                0x0808
+#define ENABLE_ACLK_MIF3                0x080c
+#define ENABLE_PCLK_MIF                 0x0900
+#define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
+#define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
+#define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT    0x090c
+#define ENABLE_PCLK_MIF_SECURE_RTC      0x0910
+#define ENABLE_SCLK_MIF                 0x0a00
+#define ENABLE_IP_MIF0                  0x0b00
+#define ENABLE_IP_MIF1                  0x0b04
+#define ENABLE_IP_MIF2                  0x0b08
+#define ENABLE_IP_MIF3                  0x0b0c
+#define ENABLE_IP_MIF_SECURE_DREX0_TZ   0x0b10
+#define ENABLE_IP_MIF_SECURE_DREX1_TZ   0x0b14
+#define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT      0x0b18
+#define ENABLE_IP_MIF_SECURE_RTC        0x0b1c
+#define CLKOUT_CMU_MIF                  0x0c00
+#define CLKOUT_CMU_MIF_DIV_STAT         0x0c04
+#define DREX_FREQ_CTRL0                 0x1000
+#define DREX_FREQ_CTRL1                 0x1004
+#define PAUSE                           0x1008
+#define DDRPHY_LOCK_CTRL                0x100c
+
+static unsigned long mif_clk_regs[] __initdata = {
+        MEM0_PLL_LOCK,
+        MEM1_PLL_LOCK,
+        BUS_PLL_LOCK,
+        MFC_PLL_LOCK,
+        MEM0_PLL_CON0,
+        MEM0_PLL_CON1,
+        MEM0_PLL_FREQ_DET,
+        MEM1_PLL_CON0,
+        MEM1_PLL_CON1,
+        MEM1_PLL_FREQ_DET,
+        BUS_PLL_CON0,
+        BUS_PLL_CON1,
+        BUS_PLL_FREQ_DET,
+        MFC_PLL_CON0,
+        MFC_PLL_CON1,
+        MFC_PLL_FREQ_DET,
+        MUX_SEL_MIF0,
+        MUX_SEL_MIF1,
+        MUX_SEL_MIF2,
+        MUX_SEL_MIF3,
+        MUX_SEL_MIF4,
+        MUX_SEL_MIF5,
+        MUX_SEL_MIF6,
+        MUX_SEL_MIF7,
+        MUX_ENABLE_MIF0,
+        MUX_ENABLE_MIF1,
+        MUX_ENABLE_MIF2,
+        MUX_ENABLE_MIF3,
+        MUX_ENABLE_MIF4,
+        MUX_ENABLE_MIF5,
+        MUX_ENABLE_MIF6,
+        MUX_ENABLE_MIF7,
+        MUX_STAT_MIF0,
+        MUX_STAT_MIF1,
+        MUX_STAT_MIF2,
+        MUX_STAT_MIF3,
+        MUX_STAT_MIF4,
+        MUX_STAT_MIF5,
+        MUX_STAT_MIF6,
+        MUX_STAT_MIF7,
+        DIV_MIF1,
+        DIV_MIF2,
+        DIV_MIF3,
+        DIV_MIF4,
+        DIV_MIF5,
+        DIV_MIF_PLL_FREQ_DET,
+        DIV_STAT_MIF1,
+        DIV_STAT_MIF2,
+        DIV_STAT_MIF3,
+        DIV_STAT_MIF4,
+        DIV_STAT_MIF5,
+        DIV_STAT_MIF_PLL_FREQ_DET,
+        ENABLE_ACLK_MIF0,
+        ENABLE_ACLK_MIF1,
+        ENABLE_ACLK_MIF2,
+        ENABLE_ACLK_MIF3,
+        ENABLE_PCLK_MIF,
+        ENABLE_PCLK_MIF_SECURE_DREX0_TZ,
+        ENABLE_PCLK_MIF_SECURE_DREX1_TZ,
+        ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT,
+        ENABLE_PCLK_MIF_SECURE_RTC,
+        ENABLE_SCLK_MIF,
+        ENABLE_IP_MIF0,
+        ENABLE_IP_MIF1,
+        ENABLE_IP_MIF2,
+        ENABLE_IP_MIF3,
+        ENABLE_IP_MIF_SECURE_DREX0_TZ,
+        ENABLE_IP_MIF_SECURE_DREX1_TZ,
+        ENABLE_IP_MIF_SECURE_MONOTONIC_CNT,
+        ENABLE_IP_MIF_SECURE_RTC,
+        CLKOUT_CMU_MIF,
+        CLKOUT_CMU_MIF_DIV_STAT,
+        DREX_FREQ_CTRL0,
+        DREX_FREQ_CTRL1,
+        PAUSE,
+        DDRPHY_LOCK_CTRL,
+};
+
+static struct samsung_pll_clock mif_pll_clks[] __initdata = {
+        PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
+                MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates),
+        PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
+                MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5443_pll_rates),
+        PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
+                BUS_PLL_LOCK, BUS_PLL_CON0, exynos5443_pll_rates),
+        PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
+                MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates),
+};
+
+/* list of all parent clock list */
+PNAME(mout_mfc_pll_div2_p)      = { "mout_mfc_pll", "dout_mfc_pll", };
+PNAME(mout_bus_pll_div2_p)      = { "mout_bus_pll", "dout_bus_pll", };
+PNAME(mout_mem1_pll_div2_p)     = { "mout_mem1_pll", "dout_mem1_pll", };
+PNAME(mout_mem0_pll_div2_p)     = { "mout_mem0_pll", "dout_mem0_pll", };
+PNAME(mout_mfc_pll_p)           = { "oscclk", "fout_mfc_pll", };
+PNAME(mout_bus_pll_p)           = { "oscclk", "fout_bus_pll", };
+PNAME(mout_mem1_pll_p)          = { "oscclk", "fout_mem1_pll", };
+PNAME(mout_mem0_pll_p)          = { "oscclk", "fout_mem0_pll", };
+
+PNAME(mout_clk2x_phy_c_p)       = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
+PNAME(mout_clk2x_phy_b_p)       = { "mout_bus_pll_div2", "mout_clkm_phy_a", };
+PNAME(mout_clk2x_phy_a_p)       = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
+PNAME(mout_clkm_phy_b_p)        = { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
+
+PNAME(mout_aclk_mifnm_200_p)    = { "mout_mem0_pll_div2", "div_mif_pre", };
+PNAME(mout_aclk_mifnm_400_p)    = { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
+
+PNAME(mout_aclk_disp_333_b_p)   = { "mout_aclk_disp_333_a",
+                                    "mout_bus_pll_div2", };
+PNAME(mout_aclk_disp_333_a_p)   = { "mout_mfc_pll_div2", "sclk_mphy_pll", };
+
+PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b",
+                                    "sclk_mphy_pll", };
+PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a",
+                                    "mout_mfc_pll_div2", };
+PNAME(mout_sclk_decon_p)        = { "oscclk", "mout_bus_pll_div2", };
+PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b",
+                                    "sclk_mphy_pll", };
+PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a",
+                                    "mout_mfc_pll_div2", };
+
+PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b",
+                                       "sclk_mphy_pll", };
+PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a",
+                                       "mout_mfc_pll_div2", };
+PNAME(mout_sclk_dsd_c_p)        = { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
+PNAME(mout_sclk_dsd_b_p)        = { "mout_sclk_dsd_a", "sclk_mphy_pll", };
+PNAME(mout_sclk_dsd_a_p)        = { "oscclk", "mout_mfc_pll_div2", };
+
+PNAME(mout_sclk_dsim0_c_p)      = { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
+PNAME(mout_sclk_dsim0_b_p)      = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
+
+PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b",
+                                       "sclk_mphy_pll", };
+PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
+                                       "mout_mfc_pll_div2", };
+PNAME(mout_sclk_dsim1_c_p)      = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
+PNAME(mout_sclk_dsim1_b_p)      = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
+
+static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = {
+        /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
+        FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
+        FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
+        FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
+        FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
+};
+
+static struct samsung_mux_clock mif_mux_clks[] __initdata = {
+        /* MUX_SEL_MIF0 */
+        MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
+                        MUX_SEL_MIF0, 28, 1),
+        MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p,
+                        MUX_SEL_MIF0, 24, 1),
+        MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p,
+                        MUX_SEL_MIF0, 20, 1),
+        MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p,
+                        MUX_SEL_MIF0, 16, 1),
+        MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0,
+                        12, 1),
+        MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0,
+                        8, 1),
+        MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0,
+                        4, 1),
+        MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0,
+                        0, 1),
+
+        /* MUX_SEL_MIF1 */
+        MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p,
+                        MUX_SEL_MIF1, 24, 1),
+        MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p,
+                        MUX_SEL_MIF1, 20, 1),
+        MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p,
+                        MUX_SEL_MIF1, 16, 1),
+        MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p,
+                        MUX_SEL_MIF1, 12, 1),
+        MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p,
+                        MUX_SEL_MIF1, 8, 1),
+        MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p,
+                        MUX_SEL_MIF1, 4, 1),
+
+        /* MUX_SEL_MIF2 */
+        MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200",
+                        mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1),
+        MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400",
+                        mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
+
+        /* MUX_SEL_MIF3 */
+        MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b",
+                        mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1),
+        MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a",
+                        mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
+
+        /* MUX_SEL_MIF4 */
+        MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c",
+                        mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1),
+        MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b",
+                        mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1),
+        MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a",
+                        mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1),
+        MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c",
+                        mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1),
+        MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b",
+                        mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1),
+        MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a",
+                        mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
+
+        /* MUX_SEL_MIF5 */
+        MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c",
+                        mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1),
+        MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b",
+                        mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1),
+        MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a",
+                        mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1),
+        MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p,
+                        MUX_SEL_MIF5, 8, 1),
+        MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p,
+                        MUX_SEL_MIF5, 4, 1),
+        MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p,
+                        MUX_SEL_MIF5, 0, 1),
+
+        /* MUX_SEL_MIF6 */
+        MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p,
+                        MUX_SEL_MIF6, 8, 1),
+        MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p,
+                        MUX_SEL_MIF6, 4, 1),
+        MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p,
+                        MUX_SEL_MIF6, 0, 1),
+
+        /* MUX_SEL_MIF7 */
+        MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c",
+                        mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1),
+        MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b",
+                        mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1),
+        MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a",
+                        mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1),
+        MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p,
+                        MUX_SEL_MIF7, 8, 1),
+        MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p,
+                        MUX_SEL_MIF7, 4, 1),
+        MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p,
+                        MUX_SEL_MIF7, 0, 1),
+};
+
+static struct samsung_div_clock mif_div_clks[] __initdata = {
+        /* DIV_MIF1 */
+        DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
+                        DIV_MIF1, 16, 2),
+        DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1,
+                        12, 2),
+        DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1,
+                        8, 2),
+        DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1,
+                        4, 4),
+
+        /* DIV_MIF2 */
+        DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2",
+                        DIV_MIF2, 20, 3),
+        DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre",
+                        DIV_MIF2, 16, 4),
+        DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre",
+                        DIV_MIF2, 12, 4),
+        DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200",
+                        "mout_aclk_mifnm_200", DIV_MIF2, 8, 3),
+        DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400",
+                        DIV_MIF2, 4, 2),
+        DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400",
+                        DIV_MIF2, 0, 3),
+
+        /* DIV_MIF3 */
+        DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre",
+                        DIV_MIF3, 16, 4),
+        DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b",
+                        DIV_MIF3, 4, 3),
+        DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
+                        DIV_MIF3, 0, 3),
+
+        /* DIV_MIF4 */
+        DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c",
+                        DIV_MIF4, 24, 4),
+        DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk",
+                        "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4),
+        DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c",
+                        DIV_MIF4, 16, 4),
+        DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c",
+                        DIV_MIF4, 12, 4),
+        DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk",
+                        "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4),
+        DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk",
+                        "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4),
+        DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk",
+                        "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
+
+        /* DIV_MIF5 */
+        DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5,
+                        0, 3),
+};
+
+static struct samsung_gate_clock mif_gate_clks[] __initdata = {
+        /* ENABLE_ACLK_MIF0 */
+        GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
+                        19, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0,
+                        18, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
+                        17, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
+                        16, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0,
+                        15, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0,
+                        14, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1",
+                        ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0",
+                        ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1",
+                        ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0",
+                        ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1",
+                        ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0",
+                        ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1",
+                        ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0",
+                        ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1",
+                        ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0",
+                        ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1",
+                        ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0",
+                        ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1",
+                        ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0",
+                        ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_ACLK_MIF1 */
+        GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem",
+                        "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci",
+                        "div_aclk_mif_200", ENABLE_ACLK_MIF1,
+                        27, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci",
+                        "div_aclk_mif_133", ENABLE_ACLK_MIF1,
+                        26, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1",
+                        "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
+                        25, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1",
+                        "div_aclk_drex1", ENABLE_ACLK_MIF1,
+                        24, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0",
+                        "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
+                        23, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0",
+                        "div_aclk_drex0", ENABLE_ACLK_MIF1,
+                        22, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3",
+                        "div_aclk_mif_133", ENABLE_ACLK_MIF1,
+                        21, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3",
+                        "div_aclk_drex1", ENABLE_ACLK_MIF1,
+                        20, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1",
+                        "div_aclk_mif_133", ENABLE_ACLK_MIF1,
+                        19, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1",
+                        "div_aclk_drex1", ENABLE_ACLK_MIF1,
+                        18, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0",
+                        "div_aclk_mif_133", ENABLE_ACLK_MIF1,
+                        17, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0",
+                        "div_aclk_drex1", ENABLE_ACLK_MIF1,
+                        16, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3",
+                        "div_aclk_mif_133", ENABLE_ACLK_MIF1,
+                        15, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3",
+                        "div_aclk_drex0", ENABLE_ACLK_MIF1,
+                        14, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1",
+                        "div_aclk_mif_133", ENABLE_ACLK_MIF1,
+                        13, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1",
+                        "div_aclk_drex0", ENABLE_ACLK_MIF1,
+                        12, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0",
+                        "div_aclk_mif_133", ENABLE_ACLK_MIF1,
+                        11, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0",
+                        "div_aclk_drex0", ENABLE_ACLK_MIF1,
+                        10, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
+                        ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
+                        ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
+                        ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400",
+                        ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
+                        ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133",
+                        ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200",
+                        ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133",
+                        ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400",
+                        ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1,
+                        0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_ACLK_MIF2 */
+        GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266",
+                        ENABLE_ACLK_MIF2, 20, 0, 0),
+        GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1",
+                        ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1",
+                        ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1",
+                        ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0",
+                        ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0",
+                        ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0",
+                        ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx",
+                        "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci",
+                        "div_aclk_mif_400", ENABLE_ACLK_MIF2,
+                        5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400",
+                        ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d",
+                        "div_aclk_mif_200", ENABLE_ACLK_MIF2,
+                        3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys",
+                        "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
+
+        /* ENABLE_ACLK_MIF3 */
+        GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
+                        ENABLE_ACLK_MIF3, 4,
+                        CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
+                        ENABLE_ACLK_MIF3, 1,
+                        CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
+                        ENABLE_ACLK_MIF3, 0,
+                        CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+
+        /* ENABLE_PCLK_MIF */
+        GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1",
+                        ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1",
+                        ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1",
+                        ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0",
+                        ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0",
+                        ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0",
+                        ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci",
+                        "div_aclk_mif_133", ENABLE_PCLK_MIF, 21,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
+                        ENABLE_PCLK_MIF, 19, 0, 0),
+        GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
+                        ENABLE_PCLK_MIF, 18, 0, 0),
+        GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3",
+                        "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
+        GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1",
+                        "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
+        GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0",
+                        "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
+        GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3",
+                        "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
+        GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1",
+                        "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
+        GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0",
+                        "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
+        GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133",
+                        ENABLE_PCLK_MIF, 11, 0, 0),
+        GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133",
+                        ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133",
+                        ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133",
+                        ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133",
+                        ENABLE_PCLK_MIF, 7, 0, 0),
+        GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133",
+                        ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133",
+                        ENABLE_PCLK_MIF, 5, 0, 0),
+        GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133",
+                        ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",
+                        ENABLE_PCLK_MIF, 2, 0, 0),
+        GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133",
+                        ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
+        GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
+                        ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 0, 0),
+
+        /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
+        GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
+                        ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 0, 0),
+
+        /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
+        GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
+                        ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
+
+        /* ENABLE_PCLK_MIF_SECURE_RTC */
+        GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
+                        ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
+
+        /* ENABLE_SCLK_MIF */
+        GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
+                        ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
+                        "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
+                        14, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
+                        ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
+                        ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
+                        "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
+                        7, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
+                        "div_sclk_decon_vclk", ENABLE_SCLK_MIF,
+                        6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
+                        "div_sclk_decon_eclk", ENABLE_SCLK_MIF,
+                        5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
+                        ENABLE_SCLK_MIF, 4,
+                        CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
+                        ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
+                        ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
+                        ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
+                        ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
+};
+
+static struct samsung_cmu_info mif_cmu_info __initdata = {
+        .pll_clks               = mif_pll_clks,
+        .nr_pll_clks            = ARRAY_SIZE(mif_pll_clks),
+        .mux_clks               = mif_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(mif_mux_clks),
+        .div_clks               = mif_div_clks,
+        .nr_div_clks            = ARRAY_SIZE(mif_div_clks),
+        .gate_clks              = mif_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(mif_gate_clks),
+        .fixed_factor_clks      = mif_fixed_factor_clks,
+        .nr_fixed_factor_clks   = ARRAY_SIZE(mif_fixed_factor_clks),
+        .nr_clk_ids             = MIF_NR_CLK,
+        .clk_regs               = mif_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(mif_clk_regs),
+};
+
+static void __init exynos5433_cmu_mif_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &mif_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
+                exynos5433_cmu_mif_init);
+
+/*
+ * Register offset definitions for CMU_PERIC
+ */
+#define DIV_PERIC                       0x0600
+#define DIV_STAT_PERIC                  0x0700
+#define ENABLE_ACLK_PERIC               0x0800
+#define ENABLE_PCLK_PERIC0              0x0900
+#define ENABLE_PCLK_PERIC1              0x0904
+#define ENABLE_SCLK_PERIC               0x0A00
+#define ENABLE_IP_PERIC0                0x0B00
+#define ENABLE_IP_PERIC1                0x0B04
+#define ENABLE_IP_PERIC2                0x0B08
+
+static unsigned long peric_clk_regs[] __initdata = {
+        DIV_PERIC,
+        DIV_STAT_PERIC,
+        ENABLE_ACLK_PERIC,
+        ENABLE_PCLK_PERIC0,
+        ENABLE_PCLK_PERIC1,
+        ENABLE_SCLK_PERIC,
+        ENABLE_IP_PERIC0,
+        ENABLE_IP_PERIC1,
+        ENABLE_IP_PERIC2,
+};
+
+static struct samsung_div_clock peric_div_clks[] __initdata = {
+        /* DIV_PERIC */
+        DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
+        DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
+};
+
+static struct samsung_gate_clock peric_gate_clks[] __initdata = {
+        /* ENABLE_ACLK_PERIC */
+        GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
+                        ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
+                        ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
+                        ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
+                        ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_PCLK_PERIC0 */
+        GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+                        31, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
+                        ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
+                        ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+                        28, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+                        26, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+                        25, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+                        24, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+                        23, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+                        22, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+                        21, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+                        20, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
+                        ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
+                        ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
+                        ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
+                        ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
+                        ENABLE_PCLK_PERIC0, 15,
+                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+                        14, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+                        13, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+                        12, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
+                        ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
+                        ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
+                        ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
+                        ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+                        7, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+                        6, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+                        5, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+                        4, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+                        3, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+                        2, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+                        1, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+                        0, CLK_SET_RATE_PARENT, 0),
+
+        /* ENABLE_PCLK_PERIC1 */
+        GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
+                        9, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
+                        8, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
+                        ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
+                        ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
+                        ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
+                        ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
+                        ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
+                        ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
+                        ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
+                        ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
+
+        /* ENABLE_SCLK_PERIC */
+        GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
+                        ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
+                        ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
+                        19, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
+                        18, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
+                        17, 0, 0),
+        GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
+                        16, 0, 0),
+        GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
+        GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
+                        ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
+                        ENABLE_SCLK_PERIC, 12,
+                        CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
+                        ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
+                        "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
+                        CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
+                        ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
+                        ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
+                        ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
+                        5, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
+                        4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
+                        3, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
+                        ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
+                        ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
+                        ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
+};
+
+static struct samsung_cmu_info peric_cmu_info __initdata = {
+        .div_clks               = peric_div_clks,
+        .nr_div_clks            = ARRAY_SIZE(peric_div_clks),
+        .gate_clks              = peric_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(peric_gate_clks),
+        .nr_clk_ids             = PERIC_NR_CLK,
+        .clk_regs               = peric_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(peric_clk_regs),
+};
+
+static void __init exynos5433_cmu_peric_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &peric_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
+                exynos5433_cmu_peric_init);
+
+/*
+ * Register offset definitions for CMU_PERIS
+ */
+#define ENABLE_ACLK_PERIS                               0x0800
+#define ENABLE_PCLK_PERIS                               0x0900
+#define ENABLE_PCLK_PERIS_SECURE_TZPC                   0x0904
+#define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF           0x0908
+#define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF           0x090c
+#define ENABLE_PCLK_PERIS_SECURE_TOPRTC                 0x0910
+#define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF     0x0914
+#define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF      0x0918
+#define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF          0x091c
+#define ENABLE_SCLK_PERIS                               0x0a00
+#define ENABLE_SCLK_PERIS_SECURE_SECKEY                 0x0a04
+#define ENABLE_SCLK_PERIS_SECURE_CHIPID                 0x0a08
+#define ENABLE_SCLK_PERIS_SECURE_TOPRTC                 0x0a0c
+#define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE           0x0a10
+#define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT            0x0a14
+#define ENABLE_SCLK_PERIS_SECURE_OTP_CON                0x0a18
+#define ENABLE_IP_PERIS0                                0x0b00
+#define ENABLE_IP_PERIS1                                0x0b04
+#define ENABLE_IP_PERIS_SECURE_TZPC                     0x0b08
+#define ENABLE_IP_PERIS_SECURE_SECKEY                   0x0b0c
+#define ENABLE_IP_PERIS_SECURE_CHIPID                   0x0b10
+#define ENABLE_IP_PERIS_SECURE_TOPRTC                   0x0b14
+#define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE             0x0b18
+#define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT              0x0b1c
+#define ENABLE_IP_PERIS_SECURE_OTP_CON                  0x0b20
+
+static unsigned long peris_clk_regs[] __initdata = {
+        ENABLE_ACLK_PERIS,
+        ENABLE_PCLK_PERIS,
+        ENABLE_PCLK_PERIS_SECURE_TZPC,
+        ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
+        ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
+        ENABLE_PCLK_PERIS_SECURE_TOPRTC,
+        ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
+        ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
+        ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
+        ENABLE_SCLK_PERIS,
+        ENABLE_SCLK_PERIS_SECURE_SECKEY,
+        ENABLE_SCLK_PERIS_SECURE_CHIPID,
+        ENABLE_SCLK_PERIS_SECURE_TOPRTC,
+        ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
+        ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
+        ENABLE_SCLK_PERIS_SECURE_OTP_CON,
+        ENABLE_IP_PERIS0,
+        ENABLE_IP_PERIS1,
+        ENABLE_IP_PERIS_SECURE_TZPC,
+        ENABLE_IP_PERIS_SECURE_SECKEY,
+        ENABLE_IP_PERIS_SECURE_CHIPID,
+        ENABLE_IP_PERIS_SECURE_TOPRTC,
+        ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
+        ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
+        ENABLE_IP_PERIS_SECURE_OTP_CON,
+};
+
+static struct samsung_gate_clock peris_gate_clks[] __initdata = {
+        /* ENABLE_ACLK_PERIS */
+        GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
+                        ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
+                        ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
+                        ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_PCLK_PERIS */
+        GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_PCLK_PERIS_SECURE_TZPC */
+        GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS_SECURE_TZPC, 12, 0, 0),
+        GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS_SECURE_TZPC, 11, 0, 0),
+        GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS_SECURE_TZPC, 10, 0, 0),
+        GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS_SECURE_TZPC, 9, 0, 0),
+        GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS_SECURE_TZPC, 8, 0, 0),
+        GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS_SECURE_TZPC, 7, 0, 0),
+        GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS_SECURE_TZPC, 6, 0, 0),
+        GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS_SECURE_TZPC, 5, 0, 0),
+        GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS_SECURE_TZPC, 4, 0, 0),
+        GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS_SECURE_TZPC, 3, 0, 0),
+        GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS_SECURE_TZPC, 2, 0, 0),
+        GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS_SECURE_TZPC, 1, 0, 0),
+        GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS_SECURE_TZPC, 0, 0, 0),
+
+        /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
+        GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, 0, 0),
+
+        /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
+        GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, 0, 0),
+
+        /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
+        GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66",
+                        ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
+
+        /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
+        GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif",
+                        "aclk_peris_66",
+                        ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
+
+        /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
+        GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif",
+                        "aclk_peris_66",
+                        ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
+
+        /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
+        GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif",
+                        "aclk_peris_66",
+                        ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
+
+        /* ENABLE_SCLK_PERIS */
+        GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common",
+                        ENABLE_SCLK_PERIS, 10, 0, 0),
+        GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common",
+                        ENABLE_SCLK_PERIS, 4, 0, 0),
+        GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common",
+                        ENABLE_SCLK_PERIS, 3, 0, 0),
+
+        /* ENABLE_SCLK_PERIS_SECURE_SECKEY */
+        GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common",
+                        ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, 0, 0),
+
+        /* ENABLE_SCLK_PERIS_SECURE_CHIPID */
+        GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common",
+                        ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
+
+        /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
+        GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common",
+                        ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
+
+        /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
+        GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common",
+                        ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
+
+        /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
+        GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common",
+                        ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
+
+        /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
+        GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common",
+                        ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
+};
+
+static struct samsung_cmu_info peris_cmu_info __initdata = {
+        .gate_clks              = peris_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(peris_gate_clks),
+        .nr_clk_ids             = PERIS_NR_CLK,
+        .clk_regs               = peris_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(peris_clk_regs),
+};
+
+static void __init exynos5433_cmu_peris_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &peris_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
+                exynos5433_cmu_peris_init);
+
+/*
+ * Register offset definitions for CMU_FSYS
+ */
+#define MUX_SEL_FSYS0                   0x0200
+#define MUX_SEL_FSYS1                   0x0204
+#define MUX_SEL_FSYS2                   0x0208
+#define MUX_SEL_FSYS3                   0x020c
+#define MUX_SEL_FSYS4                   0x0210
+#define MUX_ENABLE_FSYS0                0x0300
+#define MUX_ENABLE_FSYS1                0x0304
+#define MUX_ENABLE_FSYS2                0x0308
+#define MUX_ENABLE_FSYS3                0x030c
+#define MUX_ENABLE_FSYS4                0x0310
+#define MUX_STAT_FSYS0                  0x0400
+#define MUX_STAT_FSYS1                  0x0404
+#define MUX_STAT_FSYS2                  0x0408
+#define MUX_STAT_FSYS3                  0x040c
+#define MUX_STAT_FSYS4                  0x0410
+#define MUX_IGNORE_FSYS2                0x0508
+#define MUX_IGNORE_FSYS3                0x050c
+#define ENABLE_ACLK_FSYS0               0x0800
+#define ENABLE_ACLK_FSYS1               0x0804
+#define ENABLE_PCLK_FSYS                0x0900
+#define ENABLE_SCLK_FSYS                0x0a00
+#define ENABLE_IP_FSYS0                 0x0b00
+#define ENABLE_IP_FSYS1                 0x0b04
+
+/* list of all parent clock list */
+PNAME(mout_sclk_ufs_mphy_user_p)        = { "oscclk", "sclk_ufs_mphy", };
+PNAME(mout_aclk_fsys_200_user_p)        = { "oscclk", "div_aclk_fsys_200", };
+PNAME(mout_sclk_pcie_100_user_p)        = { "oscclk", "sclk_pcie_100_fsys",};
+PNAME(mout_sclk_ufsunipro_user_p)       = { "oscclk", "sclk_ufsunipro_fsys",};
+PNAME(mout_sclk_mmc2_user_p)            = { "oscclk", "sclk_mmc2_fsys", };
+PNAME(mout_sclk_mmc1_user_p)            = { "oscclk", "sclk_mmc1_fsys", };
+PNAME(mout_sclk_mmc0_user_p)            = { "oscclk", "sclk_mmc0_fsys", };
+PNAME(mout_sclk_usbhost30_user_p)       = { "oscclk", "sclk_usbhost30_fsys",};
+PNAME(mout_sclk_usbdrd30_user_p)        = { "oscclk", "sclk_usbdrd30_fsys", };
+
+PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
+                = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
+PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
+                = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", };
+PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
+                = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", };
+PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
+                = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", };
+PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
+                = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", };
+PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
+                = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", };
+PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
+                = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", };
+PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
+                = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", };
+PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
+                = { "oscclk", "phyclk_ufs_rx1_symbol_phy", };
+PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
+                = { "oscclk", "phyclk_ufs_rx0_symbol_phy", };
+PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
+                = { "oscclk", "phyclk_ufs_tx1_symbol_phy", };
+PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
+                = { "oscclk", "phyclk_ufs_tx0_symbol_phy", };
+PNAME(mout_phyclk_lli_mphy_to_ufs_user_p)
+                = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", };
+PNAME(mout_sclk_mphy_p)
+                = { "mout_sclk_ufs_mphy_user",
+                            "mout_phyclk_lli_mphy_to_ufs_user", };
+
+static unsigned long fsys_clk_regs[] __initdata = {
+        MUX_SEL_FSYS0,
+        MUX_SEL_FSYS1,
+        MUX_SEL_FSYS2,
+        MUX_SEL_FSYS3,
+        MUX_SEL_FSYS4,
+        MUX_ENABLE_FSYS0,
+        MUX_ENABLE_FSYS1,
+        MUX_ENABLE_FSYS2,
+        MUX_ENABLE_FSYS3,
+        MUX_ENABLE_FSYS4,
+        MUX_STAT_FSYS0,
+        MUX_STAT_FSYS1,
+        MUX_STAT_FSYS2,
+        MUX_STAT_FSYS3,
+        MUX_STAT_FSYS4,
+        MUX_IGNORE_FSYS2,
+        MUX_IGNORE_FSYS3,
+        ENABLE_ACLK_FSYS0,
+        ENABLE_ACLK_FSYS1,
+        ENABLE_PCLK_FSYS,
+        ENABLE_SCLK_FSYS,
+        ENABLE_IP_FSYS0,
+        ENABLE_IP_FSYS1,
+};
+
+static struct samsung_fixed_rate_clock fsys_fixed_clks[] __initdata = {
+        /* PHY clocks from USBDRD30_PHY */
+        FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
+                        "phyclk_usbdrd30_udrd30_phyclock_phy", NULL,
+                        CLK_IS_ROOT, 60000000),
+        FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY,
+                        "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL,
+                        CLK_IS_ROOT, 125000000),
+        /* PHY clocks from USBHOST30_PHY */
+        FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY,
+                        "phyclk_usbhost30_uhost30_phyclock_phy", NULL,
+                        CLK_IS_ROOT, 60000000),
+        FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY,
+                        "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL,
+                        CLK_IS_ROOT, 125000000),
+        /* PHY clocks from USBHOST20_PHY */
+        FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY,
+                        "phyclk_usbhost20_phy_freeclk_phy", NULL, CLK_IS_ROOT,
+                        60000000),
+        FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY,
+                        "phyclk_usbhost20_phy_phyclock_phy", NULL, CLK_IS_ROOT,
+                        60000000),
+        FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY,
+                        "phyclk_usbhost20_phy_clk48mohci_phy", NULL,
+                        CLK_IS_ROOT, 48000000),
+        FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY,
+                        "phyclk_usbhost20_phy_hsic1_phy", NULL, CLK_IS_ROOT,
+                        60000000),
+        /* PHY clocks from UFS_PHY */
+        FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy",
+                        NULL, CLK_IS_ROOT, 300000000),
+        FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy",
+                        NULL, CLK_IS_ROOT, 300000000),
+        FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy",
+                        NULL, CLK_IS_ROOT, 300000000),
+        FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy",
+                        NULL, CLK_IS_ROOT, 300000000),
+        /* PHY clocks from LLI_PHY */
+        FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy",
+                        NULL, CLK_IS_ROOT, 26000000),
+};
+
+static struct samsung_mux_clock fsys_mux_clks[] __initdata = {
+        /* MUX_SEL_FSYS0 */
+        MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
+                        mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
+        MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
+                        mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
+
+        /* MUX_SEL_FSYS1 */
+        MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user",
+                        mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1),
+        MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user",
+                        mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1),
+        MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
+                        mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
+        MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
+                        mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
+        MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
+                        mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
+        MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user",
+                        mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1),
+        MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user",
+                        mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
+
+        /* MUX_SEL_FSYS2 */
+        MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER,
+                        "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
+                        mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p,
+                        MUX_SEL_FSYS2, 28, 1),
+        MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER,
+                        "mout_phyclk_usbhost30_uhost30_phyclock_user",
+                        mout_phyclk_usbhost30_uhost30_phyclock_user_p,
+                        MUX_SEL_FSYS2, 24, 1),
+        MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER,
+                        "mout_phyclk_usbhost20_phy_hsic1",
+                        mout_phyclk_usbhost20_phy_hsic1_p,
+                        MUX_SEL_FSYS2, 20, 1),
+        MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER,
+                        "mout_phyclk_usbhost20_phy_clk48mohci_user",
+                        mout_phyclk_usbhost20_phy_clk48mohci_user_p,
+                        MUX_SEL_FSYS2, 16, 1),
+        MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER,
+                        "mout_phyclk_usbhost20_phy_phyclock_user",
+                        mout_phyclk_usbhost20_phy_phyclock_user_p,
+                        MUX_SEL_FSYS2, 12, 1),
+        MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER,
+                        "mout_phyclk_usbhost20_phy_freeclk_user",
+                        mout_phyclk_usbhost20_phy_freeclk_user_p,
+                        MUX_SEL_FSYS2, 8, 1),
+        MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
+                        "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
+                        mout_phyclk_usbdrd30_udrd30_pipe_pclk_p,
+                        MUX_SEL_FSYS2, 4, 1),
+        MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
+                        "mout_phyclk_usbdrd30_udrd30_phyclock_user",
+                        mout_phyclk_usbdrd30_udrd30_phyclock_user_p,
+                        MUX_SEL_FSYS2, 0, 1),
+
+        /* MUX_SEL_FSYS3 */
+        MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
+                        "mout_phyclk_ufs_rx1_symbol_user",
+                        mout_phyclk_ufs_rx1_symbol_user_p,
+                        MUX_SEL_FSYS3, 16, 1),
+        MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
+                        "mout_phyclk_ufs_rx0_symbol_user",
+                        mout_phyclk_ufs_rx0_symbol_user_p,
+                        MUX_SEL_FSYS3, 12, 1),
+        MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
+                        "mout_phyclk_ufs_tx1_symbol_user",
+                        mout_phyclk_ufs_tx1_symbol_user_p,
+                        MUX_SEL_FSYS3, 8, 1),
+        MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
+                        "mout_phyclk_ufs_tx0_symbol_user",
+                        mout_phyclk_ufs_tx0_symbol_user_p,
+                        MUX_SEL_FSYS3, 4, 1),
+        MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
+                        "mout_phyclk_lli_mphy_to_ufs_user",
+                        mout_phyclk_lli_mphy_to_ufs_user_p,
+                        MUX_SEL_FSYS3, 0, 1),
+
+        /* MUX_SEL_FSYS4 */
+        MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p,
+                        MUX_SEL_FSYS4, 0, 1),
+};
+
+static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
+        /* ENABLE_ACLK_FSYS0 */
+        GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
+                        ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
+                        ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
+                        ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
+                        ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
+                        ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
+                        ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
+                        ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
+                        ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
+                        ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
+                        ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
+                        ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_ACLK_FSYS1 */
+        GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user",
+                        ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1",
+                        "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+                        26, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
+                        ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
+                        ENABLE_ACLK_FSYS1, 24, 0, 0),
+        GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
+                        "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+                        22, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user",
+                        ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user",
+                        ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30",
+                        "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+                        13, 0, 0),
+        GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30",
+                        "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+                        12, 0, 0),
+        GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0",
+                        "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+                        11, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs",
+                        "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+                        10, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx",
+                        "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+                        9, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp",
+                        "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+                        8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs",
+                        "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+                        7, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0",
+                        "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+                        6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user",
+                        ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user",
+                        ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user",
+                        ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user",
+                        ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user",
+                        ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user",
+                        ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_PCLK_FSYS */
+        GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
+                        ENABLE_PCLK_FSYS, 17, 0, 0),
+        GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
+                        ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
+                        ENABLE_PCLK_FSYS, 14, 0, 0),
+        GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
+                        ENABLE_PCLK_FSYS, 13, 0, 0),
+        GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
+                        ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
+                        ENABLE_PCLK_FSYS, 5, 0, 0),
+        GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30",
+                        "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
+        GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30",
+                        "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
+        GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user",
+                        ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user",
+                        ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys",
+                        "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS,
+                        0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_SCLK_FSYS */
+        GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user",
+                        ENABLE_SCLK_FSYS, 21, 0, 0),
+        GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
+                        "phyclk_usbhost30_uhost30_pipe_pclk",
+                        "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
+                        ENABLE_SCLK_FSYS, 18, 0, 0),
+        GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
+                        "phyclk_usbhost30_uhost30_phyclock",
+                        "mout_phyclk_usbhost30_uhost30_phyclock_user",
+                        ENABLE_SCLK_FSYS, 17, 0, 0),
+        GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol",
+                        "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS,
+                        16, 0, 0),
+        GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol",
+                        "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS,
+                        15, 0, 0),
+        GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol",
+                        "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS,
+                        14, 0, 0),
+        GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol",
+                        "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS,
+                        13, 0, 0),
+        GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1",
+                        "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS,
+                        12, 0, 0),
+        GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
+                        "phyclk_usbhost20_phy_clk48mohci",
+                        "mout_phyclk_usbhost20_phy_clk48mohci_user",
+                        ENABLE_SCLK_FSYS, 11, 0, 0),
+        GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
+                        "phyclk_usbhost20_phy_phyclock",
+                        "mout_phyclk_usbhost20_phy_phyclock_user",
+                        ENABLE_SCLK_FSYS, 10, 0, 0),
+        GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
+                        "phyclk_usbhost20_phy_freeclk",
+                        "mout_phyclk_usbhost20_phy_freeclk_user",
+                        ENABLE_SCLK_FSYS, 9, 0, 0),
+        GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
+                        "phyclk_usbdrd30_udrd30_pipe_pclk",
+                        "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
+                        ENABLE_SCLK_FSYS, 8, 0, 0),
+        GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
+                        "phyclk_usbdrd30_udrd30_phyclock",
+                        "mout_phyclk_usbdrd30_udrd30_phyclock_user",
+                        ENABLE_SCLK_FSYS, 7, 0, 0),
+        GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy",
+                        ENABLE_SCLK_FSYS, 6, 0, 0),
+        GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user",
+                        ENABLE_SCLK_FSYS, 5, 0, 0),
+        GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
+                        ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
+                        ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
+                        ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user",
+                        ENABLE_SCLK_FSYS, 1, 0, 0),
+        GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user",
+                        ENABLE_SCLK_FSYS, 0, 0, 0),
+
+        /* ENABLE_IP_FSYS0 */
+        GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
+        GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
+};
+
+static struct samsung_cmu_info fsys_cmu_info __initdata = {
+        .mux_clks               = fsys_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(fsys_mux_clks),
+        .gate_clks              = fsys_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(fsys_gate_clks),
+        .fixed_clks             = fsys_fixed_clks,
+        .nr_fixed_clks          = ARRAY_SIZE(fsys_fixed_clks),
+        .nr_clk_ids             = FSYS_NR_CLK,
+        .clk_regs               = fsys_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(fsys_clk_regs),
+};
+
+static void __init exynos5433_cmu_fsys_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &fsys_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys",
+                exynos5433_cmu_fsys_init);
+
+/*
+ * Register offset definitions for CMU_G2D
+ */
+#define MUX_SEL_G2D0                            0x0200
+#define MUX_SEL_ENABLE_G2D0                     0x0300
+#define MUX_SEL_STAT_G2D0                       0x0400
+#define DIV_G2D                                 0x0600
+#define DIV_STAT_G2D                            0x0700
+#define DIV_ENABLE_ACLK_G2D                     0x0800
+#define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D     0x0804
+#define DIV_ENABLE_PCLK_G2D                     0x0900
+#define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D     0x0904
+#define DIV_ENABLE_IP_G2D0                      0x0b00
+#define DIV_ENABLE_IP_G2D1                      0x0b04
+#define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D       0x0b08
+
+static unsigned long g2d_clk_regs[] __initdata = {
+        MUX_SEL_G2D0,
+        MUX_SEL_ENABLE_G2D0,
+        MUX_SEL_STAT_G2D0,
+        DIV_G2D,
+        DIV_STAT_G2D,
+        DIV_ENABLE_ACLK_G2D,
+        DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
+        DIV_ENABLE_PCLK_G2D,
+        DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D,
+        DIV_ENABLE_IP_G2D0,
+        DIV_ENABLE_IP_G2D1,
+        DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D,
+};
+
+/* list of all parent clock list */
+PNAME(mout_aclk_g2d_266_user_p)         = { "oscclk", "aclk_g2d_266", };
+PNAME(mout_aclk_g2d_400_user_p)         = { "oscclk", "aclk_g2d_400", };
+
+static struct samsung_mux_clock g2d_mux_clks[] __initdata = {
+        /* MUX_SEL_G2D0 */
+        MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
+                        mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
+        MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user",
+                        mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
+};
+
+static struct samsung_div_clock g2d_div_clks[] __initdata = {
+        /* DIV_G2D */
+        DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
+                        DIV_G2D, 0, 2),
+};
+
+static struct samsung_gate_clock g2d_gate_clks[] __initdata = {
+        /* DIV_ENABLE_ACLK_G2D */
+        GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
+                        DIV_ENABLE_ACLK_G2D, 12, 0, 0),
+        GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user",
+                        DIV_ENABLE_ACLK_G2D, 11, 0, 0),
+        GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user",
+                        DIV_ENABLE_ACLK_G2D, 10, 0, 0),
+        GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user",
+                        DIV_ENABLE_ACLK_G2D, 9, 0, 0),
+        GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user",
+                        DIV_ENABLE_ACLK_G2D, 8, 0, 0),
+        GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx",
+                        "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D,
+                        7, 0, 0),
+        GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d",
+                        DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d",
+                        DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user",
+                        DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d",
+                        DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user",
+                        DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user",
+                        DIV_ENABLE_ACLK_G2D, 1, 0, 0),
+        GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user",
+                        DIV_ENABLE_ACLK_G2D, 0, 0, 0),
+
+        /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */
+        GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user",
+                DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
+
+        /* DIV_ENABLE_PCLK_G2D */
+        GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d",
+                        DIV_ENABLE_PCLK_G2D, 7, 0, 0),
+        GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d",
+                        DIV_ENABLE_PCLK_G2D, 6, 0, 0),
+        GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d",
+                        DIV_ENABLE_PCLK_G2D, 5, 0, 0),
+        GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d",
+                        DIV_ENABLE_PCLK_G2D, 4, 0, 0),
+        GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d",
+                        DIV_ENABLE_PCLK_G2D, 3, 0, 0),
+        GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d",
+                        DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d",
+                        DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D,
+                        0, 0, 0),
+
+        /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */
+        GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d",
+                DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
+};
+
+static struct samsung_cmu_info g2d_cmu_info __initdata = {
+        .mux_clks               = g2d_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(g2d_mux_clks),
+        .div_clks               = g2d_div_clks,
+        .nr_div_clks            = ARRAY_SIZE(g2d_div_clks),
+        .gate_clks              = g2d_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(g2d_gate_clks),
+        .nr_clk_ids             = G2D_NR_CLK,
+        .clk_regs               = g2d_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(g2d_clk_regs),
+};
+
+static void __init exynos5433_cmu_g2d_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &g2d_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d",
+                exynos5433_cmu_g2d_init);
+
+/*
+ * Register offset definitions for CMU_DISP
+ */
+#define DISP_PLL_LOCK                   0x0000
+#define DISP_PLL_CON0                   0x0100
+#define DISP_PLL_CON1                   0x0104
+#define DISP_PLL_FREQ_DET               0x0108
+#define MUX_SEL_DISP0                   0x0200
+#define MUX_SEL_DISP1                   0x0204
+#define MUX_SEL_DISP2                   0x0208
+#define MUX_SEL_DISP3                   0x020c
+#define MUX_SEL_DISP4                   0x0210
+#define MUX_ENABLE_DISP0                0x0300
+#define MUX_ENABLE_DISP1                0x0304
+#define MUX_ENABLE_DISP2                0x0308
+#define MUX_ENABLE_DISP3                0x030c
+#define MUX_ENABLE_DISP4                0x0310
+#define MUX_STAT_DISP0                  0x0400
+#define MUX_STAT_DISP1                  0x0404
+#define MUX_STAT_DISP2                  0x0408
+#define MUX_STAT_DISP3                  0x040c
+#define MUX_STAT_DISP4                  0x0410
+#define MUX_IGNORE_DISP2                0x0508
+#define DIV_DISP                        0x0600
+#define DIV_DISP_PLL_FREQ_DET           0x0604
+#define DIV_STAT_DISP                   0x0700
+#define DIV_STAT_DISP_PLL_FREQ_DET      0x0704
+#define ENABLE_ACLK_DISP0               0x0800
+#define ENABLE_ACLK_DISP1               0x0804
+#define ENABLE_PCLK_DISP                0x0900
+#define ENABLE_SCLK_DISP                0x0a00
+#define ENABLE_IP_DISP0                 0x0b00
+#define ENABLE_IP_DISP1                 0x0b04
+#define CLKOUT_CMU_DISP                 0x0c00
+#define CLKOUT_CMU_DISP_DIV_STAT        0x0c04
+
+static unsigned long disp_clk_regs[] __initdata = {
+        DISP_PLL_LOCK,
+        DISP_PLL_CON0,
+        DISP_PLL_CON1,
+        DISP_PLL_FREQ_DET,
+        MUX_SEL_DISP0,
+        MUX_SEL_DISP1,
+        MUX_SEL_DISP2,
+        MUX_SEL_DISP3,
+        MUX_SEL_DISP4,
+        MUX_ENABLE_DISP0,
+        MUX_ENABLE_DISP1,
+        MUX_ENABLE_DISP2,
+        MUX_ENABLE_DISP3,
+        MUX_ENABLE_DISP4,
+        MUX_STAT_DISP0,
+        MUX_STAT_DISP1,
+        MUX_STAT_DISP2,
+        MUX_STAT_DISP3,
+        MUX_STAT_DISP4,
+        MUX_IGNORE_DISP2,
+        DIV_DISP,
+        DIV_DISP_PLL_FREQ_DET,
+        DIV_STAT_DISP,
+        DIV_STAT_DISP_PLL_FREQ_DET,
+        ENABLE_ACLK_DISP0,
+        ENABLE_ACLK_DISP1,
+        ENABLE_PCLK_DISP,
+        ENABLE_SCLK_DISP,
+        ENABLE_IP_DISP0,
+        ENABLE_IP_DISP1,
+        CLKOUT_CMU_DISP,
+        CLKOUT_CMU_DISP_DIV_STAT,
+};
+
+/* list of all parent clock list */
+PNAME(mout_disp_pll_p)                  = { "oscclk", "fout_disp_pll", };
+PNAME(mout_sclk_dsim1_user_p)           = { "oscclk", "sclk_dsim1_disp", };
+PNAME(mout_sclk_dsim0_user_p)           = { "oscclk", "sclk_dsim0_disp", };
+PNAME(mout_sclk_dsd_user_p)             = { "oscclk", "sclk_dsd_disp", };
+PNAME(mout_sclk_decon_tv_eclk_user_p)   = { "oscclk",
+                                            "sclk_decon_tv_eclk_disp", };
+PNAME(mout_sclk_decon_vclk_user_p)      = { "oscclk",
+                                            "sclk_decon_vclk_disp", };
+PNAME(mout_sclk_decon_eclk_user_p)      = { "oscclk",
+                                            "sclk_decon_eclk_disp", };
+PNAME(mout_sclk_decon_tv_vlkc_user_p)   = { "oscclk",
+                                            "sclk_decon_tv_vclk_disp", };
+PNAME(mout_aclk_disp_333_user_p)        = { "oscclk", "aclk_disp_333", };
+
+PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p)  = { "oscclk",
+                                        "phyclk_mipidphy1_bitclkdiv8_phy", };
+PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p)   = { "oscclk",
+                                        "phyclk_mipidphy1_rxclkesc0_phy", };
+PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p)  = { "oscclk",
+                                        "phyclk_mipidphy0_bitclkdiv8_phy", };
+PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p)   = { "oscclk",
+                                        "phyclk_mipidphy0_rxclkesc0_phy", };
+PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p)     = { "oscclk",
+                                        "phyclk_hdmiphy_tmds_clko_phy", };
+PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p)    = { "oscclk",
+                                        "phyclk_hdmiphy_pixel_clko_phy", };
+
+PNAME(mout_sclk_dsim0_p)                = { "mout_disp_pll",
+                                            "mout_sclk_dsim0_user", };
+PNAME(mout_sclk_decon_tv_eclk_p)        = { "mout_disp_pll",
+                                            "mout_sclk_decon_tv_eclk_user", };
+PNAME(mout_sclk_decon_vclk_p)           = { "mout_disp_pll",
+                                            "mout_sclk_decon_vclk_user", };
+PNAME(mout_sclk_decon_eclk_p)           = { "mout_disp_pll",
+                                            "mout_sclk_decon_eclk_user", };
+
+PNAME(mout_sclk_dsim1_b_disp_p)         = { "mout_sclk_dsim1_a_disp",
+                                            "mout_sclk_dsim1_user", };
+PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
+                                "mout_phyclk_hdmiphy_pixel_clko_user",
+                                "mout_sclk_decon_tv_vclk_b_disp", };
+PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
+                                            "mout_sclk_decon_tv_vclk_user", };
+
+static struct samsung_pll_clock disp_pll_clks[] __initdata = {
+        PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
+                DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates),
+};
+
+static struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initdata = {
+        /*
+         * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
+         * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
+         * and sclk_decon_{vclk|tv_vclk}.
+         */
+        FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk",
+                        1, 2, 0),
+        FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
+                        1, 2, 0),
+};
+
+static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = {
+        /* PHY clocks from MIPI_DPHY1 */
+        FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, CLK_IS_ROOT,
+                        188000000),
+        FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, CLK_IS_ROOT,
+                        100000000),
+        /* PHY clocks from MIPI_DPHY0 */
+        FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, CLK_IS_ROOT,
+                        188000000),
+        FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT,
+                        100000000),
+        /* PHY clocks from HDMI_PHY */
+        FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 300000000),
+        FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 166000000),
+};
+
+static struct samsung_mux_clock disp_mux_clks[] __initdata = {
+        /* MUX_SEL_DISP0 */
+        MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
+                        0, 1),
+
+        /* MUX_SEL_DISP1 */
+        MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user",
+                        mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
+        MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user",
+                        mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
+        MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p,
+                        MUX_SEL_DISP1, 20, 1),
+        MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user",
+                        mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
+        MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user",
+                        mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
+        MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user",
+                        mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
+        MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user",
+                        mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
+        MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
+                        mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
+
+        /* MUX_SEL_DISP2 */
+        MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER,
+                        "mout_phyclk_mipidphy1_bitclkdiv8_user",
+                        mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2,
+                        20, 1),
+        MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER,
+                        "mout_phyclk_mipidphy1_rxclkesc0_user",
+                        mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2,
+                        16, 1),
+        MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER,
+                        "mout_phyclk_mipidphy0_bitclkdiv8_user",
+                        mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2,
+                        12, 1),
+        MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER,
+                        "mout_phyclk_mipidphy0_rxclkesc0_user",
+                        mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2,
+                        8, 1),
+        MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER,
+                        "mout_phyclk_hdmiphy_tmds_clko_user",
+                        mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2,
+                        4, 1),
+        MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER,
+                        "mout_phyclk_hdmiphy_pixel_clko_user",
+                        mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2,
+                        0, 1),
+
+        /* MUX_SEL_DISP3 */
+        MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p,
+                        MUX_SEL_DISP3, 12, 1),
+        MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk",
+                        mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1),
+        MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk",
+                        mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1),
+        MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk",
+                        mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
+
+        /* MUX_SEL_DISP4 */
+        MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp",
+                        mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1),
+        MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp",
+                        mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1),
+        MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP,
+                        "mout_sclk_decon_tv_vclk_c_disp",
+                        mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1),
+        MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP,
+                        "mout_sclk_decon_tv_vclk_b_disp",
+                        mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1),
+        MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP,
+                        "mout_sclk_decon_tv_vclk_a_disp",
+                        mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
+};
+
+static struct samsung_div_clock disp_div_clks[] __initdata = {
+        /* DIV_DISP */
+        DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
+                        "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
+        DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp",
+                        "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3),
+        DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0",
+                        DIV_DISP, 16, 3),
+        DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp",
+                        "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3),
+        DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp",
+                        "mout_sclk_decon_vclk", DIV_DISP, 8, 3),
+        DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp",
+                        "mout_sclk_decon_eclk", DIV_DISP, 4, 3),
+        DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user",
+                        DIV_DISP, 0, 2),
+};
+
+static struct samsung_gate_clock disp_gate_clks[] __initdata = {
+        /* ENABLE_ACLK_DISP0 */
+        GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
+                        ENABLE_ACLK_DISP0, 2, 0, 0),
+        GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user",
+                        ENABLE_ACLK_DISP0, 0, 0, 0),
+
+        /* ENABLE_ACLK_DISP1 */
+        GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user",
+                        ENABLE_ACLK_DISP1, 25, 0, 0),
+        GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user",
+                        ENABLE_ACLK_DISP1, 24, 0, 0),
+        GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x",
+                        "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
+        GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x",
+                        "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
+        GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3",
+                        "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
+        GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2",
+                        "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
+        GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1",
+                        "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
+        GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0",
+                        "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
+        GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4",
+                        "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
+        GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3",
+                        "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
+        GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2",
+                        "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
+        GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1",
+                        "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
+        GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0",
+                        "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
+        GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p",
+                        "div_pclk_disp", ENABLE_ACLK_DISP1,
+                        12, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p",
+                        "div_pclk_disp", ENABLE_ACLK_DISP1,
+                        11, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p",
+                        "div_pclk_disp", ENABLE_ACLK_DISP1,
+                        10, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp",
+                        ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user",
+                        ENABLE_ACLK_DISP1, 7, 0, 0),
+        GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user",
+                        ENABLE_ACLK_DISP1, 6, 0, 0),
+        GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x",
+                        "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
+        GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x",
+                        "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
+        GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user",
+                        ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp",
+                        ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333",
+                        "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333",
+                        "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1,
+                        0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_PCLK_DISP */
+        GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp",
+                        ENABLE_PCLK_DISP, 23, 0, 0),
+        GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp",
+                        ENABLE_PCLK_DISP, 22, 0, 0),
+        GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp",
+                        ENABLE_PCLK_DISP, 21, 0, 0),
+        GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp",
+                        ENABLE_PCLK_DISP, 20, 0, 0),
+        GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp",
+                        ENABLE_PCLK_DISP, 19, 0, 0),
+        GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp",
+                        ENABLE_PCLK_DISP, 18, 0, 0),
+        GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp",
+                        ENABLE_PCLK_DISP, 17, 0, 0),
+        GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp",
+                        ENABLE_PCLK_DISP, 16, 0, 0),
+        GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp",
+                        ENABLE_PCLK_DISP, 15, 0, 0),
+        GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp",
+                        ENABLE_PCLK_DISP, 14, 0, 0),
+        GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp",
+                        ENABLE_PCLK_DISP, 13, 0, 0),
+        GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp",
+                        ENABLE_PCLK_DISP, 12, 0, 0),
+        GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp",
+                        ENABLE_PCLK_DISP, 11, 0, 0),
+        GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp",
+                        ENABLE_PCLK_DISP, 10, 0, 0),
+        GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp",
+                        ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp",
+                        ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp",
+                        ENABLE_PCLK_DISP, 7, 0, 0),
+        GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp",
+                        ENABLE_PCLK_DISP, 6, 0, 0),
+        GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp",
+                        ENABLE_PCLK_DISP, 5, 0, 0),
+        GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp",
+                        ENABLE_PCLK_DISP, 3, 0, 0),
+        GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp",
+                        ENABLE_PCLK_DISP, 2, 0, 0),
+        GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
+                        ENABLE_PCLK_DISP, 1, 0, 0),
+
+        /* ENABLE_SCLK_DISP */
+        GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
+                        "mout_phyclk_mipidphy1_bitclkdiv8_user",
+                        ENABLE_SCLK_DISP, 26, 0, 0),
+        GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0",
+                        "mout_phyclk_mipidphy1_rxclkesc0_user",
+                        ENABLE_SCLK_DISP, 25, 0, 0),
+        GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1",
+                        "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
+        GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1",
+                        "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
+        GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp",
+                        ENABLE_SCLK_DISP, 22, 0, 0),
+        GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk",
+                        "div_sclk_decon_tv_vclk_disp",
+                        ENABLE_SCLK_DISP, 21, 0, 0),
+        GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8",
+                        "mout_phyclk_mipidphy0_bitclkdiv8_user",
+                        ENABLE_SCLK_DISP, 15, 0, 0),
+        GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0",
+                        "mout_phyclk_mipidphy0_rxclkesc0_user",
+                        ENABLE_SCLK_DISP, 14, 0, 0),
+        GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko",
+                        "mout_phyclk_hdmiphy_tmds_clko_user",
+                        ENABLE_SCLK_DISP, 13, 0, 0),
+        GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel",
+                        "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
+        GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies",
+                        "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
+        GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0",
+                        "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
+        GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0",
+                        "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
+        GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user",
+                        ENABLE_SCLK_DISP, 7, 0, 0),
+        GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp",
+                        ENABLE_SCLK_DISP, 6, 0, 0),
+        GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp",
+                        ENABLE_SCLK_DISP, 5, 0, 0),
+        GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk",
+                        "div_sclk_decon_tv_eclk_disp",
+                        ENABLE_SCLK_DISP, 4, 0, 0),
+        GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk",
+                        "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
+        GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk",
+                        "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
+};
+
+static struct samsung_cmu_info disp_cmu_info __initdata = {
+        .pll_clks               = disp_pll_clks,
+        .nr_pll_clks            = ARRAY_SIZE(disp_pll_clks),
+        .mux_clks               = disp_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(disp_mux_clks),
+        .div_clks               = disp_div_clks,
+        .nr_div_clks            = ARRAY_SIZE(disp_div_clks),
+        .gate_clks              = disp_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(disp_gate_clks),
+        .fixed_clks             = disp_fixed_clks,
+        .nr_fixed_clks          = ARRAY_SIZE(disp_fixed_clks),
+        .fixed_factor_clks      = disp_fixed_factor_clks,
+        .nr_fixed_factor_clks   = ARRAY_SIZE(disp_fixed_factor_clks),
+        .nr_clk_ids             = DISP_NR_CLK,
+        .clk_regs               = disp_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(disp_clk_regs),
+};
+
+static void __init exynos5433_cmu_disp_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &disp_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp",
+                exynos5433_cmu_disp_init);
+
+/*
+ * Register offset definitions for CMU_AUD
+ */
+#define MUX_SEL_AUD0                    0x0200
+#define MUX_SEL_AUD1                    0x0204
+#define MUX_ENABLE_AUD0                 0x0300
+#define MUX_ENABLE_AUD1                 0x0304
+#define MUX_STAT_AUD0                   0x0400
+#define DIV_AUD0                        0x0600
+#define DIV_AUD1                        0x0604
+#define DIV_STAT_AUD0                   0x0700
+#define DIV_STAT_AUD1                   0x0704
+#define ENABLE_ACLK_AUD                 0x0800
+#define ENABLE_PCLK_AUD                 0x0900
+#define ENABLE_SCLK_AUD0                0x0a00
+#define ENABLE_SCLK_AUD1                0x0a04
+#define ENABLE_IP_AUD0                  0x0b00
+#define ENABLE_IP_AUD1                  0x0b04
+
+static unsigned long aud_clk_regs[] __initdata = {
+        MUX_SEL_AUD0,
+        MUX_SEL_AUD1,
+        MUX_ENABLE_AUD0,
+        MUX_ENABLE_AUD1,
+        MUX_STAT_AUD0,
+        DIV_AUD0,
+        DIV_AUD1,
+        DIV_STAT_AUD0,
+        DIV_STAT_AUD1,
+        ENABLE_ACLK_AUD,
+        ENABLE_PCLK_AUD,
+        ENABLE_SCLK_AUD0,
+        ENABLE_SCLK_AUD1,
+        ENABLE_IP_AUD0,
+        ENABLE_IP_AUD1,
+};
+
+/* list of all parent clock list */
+PNAME(mout_aud_pll_user_aud_p)  = { "oscclk", "fout_aud_pll", };
+PNAME(mout_sclk_aud_pcm_p)      = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
+
+static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = {
+        FRATE(0, "ioclk_jtag_tclk", NULL, CLK_IS_ROOT, 33000000),
+        FRATE(0, "ioclk_slimbus_clk", NULL, CLK_IS_ROOT, 25000000),
+        FRATE(0, "ioclk_i2s_bclk", NULL, CLK_IS_ROOT, 50000000),
+};
+
+static struct samsung_mux_clock aud_mux_clks[] __initdata = {
+        /* MUX_SEL_AUD0 */
+        MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
+                        mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
+
+        /* MUX_SEL_AUD1 */
+        MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
+                        MUX_SEL_AUD1, 8, 1),
+        MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p,
+                        MUX_SEL_AUD1, 0, 1),
+};
+
+static struct samsung_div_clock aud_div_clks[] __initdata = {
+        /* DIV_AUD0 */
+        DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
+                        12, 4),
+        DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
+                        8, 4),
+        DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
+                        4, 4),
+        DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
+                        0, 4),
+
+        /* DIV_AUD1 */
+        DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
+                        "mout_aud_pll_user", DIV_AUD1, 16, 5),
+        DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user",
+                        DIV_AUD1, 12, 4),
+        DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
+                        DIV_AUD1, 4, 8),
+        DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s",  "mout_sclk_aud_i2s",
+                        DIV_AUD1, 0, 4),
+};
+
+static struct samsung_gate_clock aud_gate_clks[] __initdata = {
+        /* ENABLE_ACLK_AUD */
+        GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
+                        ENABLE_ACLK_AUD, 12, 0, 0),
+        GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud",
+                        ENABLE_ACLK_AUD, 7, 0, 0),
+        GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud",
+                        ENABLE_ACLK_AUD, 0, 4, 0),
+        GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud",
+                        ENABLE_ACLK_AUD, 0, 3, 0),
+        GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud",
+                        ENABLE_ACLK_AUD, 0, 2, 0),
+        GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD,
+                        0, 1, 0),
+        GATE(CLK_ACLK_DMAC, "aclk_dmac",  "div_aclk_aud", ENABLE_ACLK_AUD,
+                        0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_PCLK_AUD */
+        GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
+                        13, 0, 0),
+        GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
+                        12, 0, 0),
+        GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
+                        11, 0, 0),
+        GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud",
+                        ENABLE_PCLK_AUD, 10, 0, 0),
+        GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud",
+                        ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud",
+                        ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud",
+                        ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
+                        ENABLE_PCLK_AUD, 6, 0, 0),
+        GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
+                        ENABLE_PCLK_AUD, 5, 0, 0),
+        GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
+                        ENABLE_PCLK_AUD, 4, 0, 0),
+        GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
+                        ENABLE_PCLK_AUD, 3, 0, 0),
+        GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
+                        2, 0, 0),
+        GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud",
+                        ENABLE_PCLK_AUD, 0, 0, 0),
+
+        /* ENABLE_SCLK_AUD0 */
+        GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
+                        2, 0, 0),
+        GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
+                        ENABLE_SCLK_AUD0, 1, 0, 0),
+        GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
+                        0, 0, 0),
+
+        /* ENABLE_SCLK_AUD1 */
+        GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk",
+                        ENABLE_SCLK_AUD1, 6, 0, 0),
+        GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
+                        ENABLE_SCLK_AUD1, 5, 0, 0),
+        GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
+                        ENABLE_SCLK_AUD1, 4, 0, 0),
+        GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
+                        ENABLE_SCLK_AUD1, 3, 0, 0),
+        GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
+                        ENABLE_SCLK_AUD1, 2, 0, 0),
+        GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
+                        ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s",
+                        ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
+};
+
+static struct samsung_cmu_info aud_cmu_info __initdata = {
+        .mux_clks               = aud_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(aud_mux_clks),
+        .div_clks               = aud_div_clks,
+        .nr_div_clks            = ARRAY_SIZE(aud_div_clks),
+        .gate_clks              = aud_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(aud_gate_clks),
+        .fixed_clks             = aud_fixed_clks,
+        .nr_fixed_clks          = ARRAY_SIZE(aud_fixed_clks),
+        .nr_clk_ids             = AUD_NR_CLK,
+        .clk_regs               = aud_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(aud_clk_regs),
+};
+
+static void __init exynos5433_cmu_aud_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &aud_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_aud, "samsung,exynos5433-cmu-aud",
+                exynos5433_cmu_aud_init);
+
+
+/*
+ * Register offset definitions for CMU_BUS{0|1|2}
+ */
+#define DIV_BUS                         0x0600
+#define DIV_STAT_BUS                    0x0700
+#define ENABLE_ACLK_BUS                 0x0800
+#define ENABLE_PCLK_BUS                 0x0900
+#define ENABLE_IP_BUS0                  0x0b00
+#define ENABLE_IP_BUS1                  0x0b04
+
+#define MUX_SEL_BUS2                    0x0200  /* Only for CMU_BUS2 */
+#define MUX_ENABLE_BUS2                 0x0300  /* Only for CMU_BUS2 */
+#define MUX_STAT_BUS2                   0x0400  /* Only for CMU_BUS2 */
+
+/* list of all parent clock list */
+PNAME(mout_aclk_bus2_400_p)     = { "oscclk", "aclk_bus2_400", };
+
+#define CMU_BUS_COMMON_CLK_REGS \
+        DIV_BUS,                \
+        DIV_STAT_BUS,           \
+        ENABLE_ACLK_BUS,        \
+        ENABLE_PCLK_BUS,        \
+        ENABLE_IP_BUS0,         \
+        ENABLE_IP_BUS1
+
+static unsigned long bus01_clk_regs[] __initdata = {
+        CMU_BUS_COMMON_CLK_REGS,
+};
+
+static unsigned long bus2_clk_regs[] __initdata = {
+        MUX_SEL_BUS2,
+        MUX_ENABLE_BUS2,
+        MUX_STAT_BUS2,
+        CMU_BUS_COMMON_CLK_REGS,
+};
+
+static struct samsung_div_clock bus0_div_clks[] __initdata = {
+        /* DIV_BUS0 */
+        DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400",
+                        DIV_BUS, 0, 3),
+};
+
+/* CMU_BUS0 clocks */
+static struct samsung_gate_clock bus0_gate_clks[] __initdata = {
+        /* ENABLE_ACLK_BUS0 */
+        GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
+                        ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133",
+                        ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400",
+                        ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_PCLK_BUS0 */
+        GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133",
+                        ENABLE_PCLK_BUS, 2, 0, 0),
+        GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133",
+                        ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133",
+                        ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
+};
+
+/* CMU_BUS1 clocks */
+static struct samsung_div_clock bus1_div_clks[] __initdata = {
+        /* DIV_BUS1 */
+        DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400",
+                        DIV_BUS, 0, 3),
+};
+
+static struct samsung_gate_clock bus1_gate_clks[] __initdata = {
+        /* ENABLE_ACLK_BUS1 */
+        GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
+                        ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133",
+                        ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400",
+                        ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_PCLK_BUS1 */
+        GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133",
+                        ENABLE_PCLK_BUS, 2, 0, 0),
+        GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133",
+                        ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133",
+                        ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
+};
+
+/* CMU_BUS2 clocks */
+static struct samsung_mux_clock bus2_mux_clks[] __initdata = {
+        /* MUX_SEL_BUS2 */
+        MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
+                        mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
+};
+
+static struct samsung_div_clock bus2_div_clks[] __initdata = {
+        /* DIV_BUS2 */
+        DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133",
+                        "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
+};
+
+static struct samsung_gate_clock bus2_gate_clks[] __initdata = {
+        /* ENABLE_ACLK_BUS2 */
+        GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
+                        ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133",
+                        ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400",
+                        "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
+                        1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400",
+                        "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
+                        0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_PCLK_BUS2 */
+        GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133",
+                        ENABLE_PCLK_BUS, 2, 0, 0),
+        GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133",
+                        ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133",
+                        ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
+};
+
+#define CMU_BUS_INFO_CLKS(id)                                           \
+        .div_clks               = bus##id##_div_clks,                   \
+        .nr_div_clks            = ARRAY_SIZE(bus##id##_div_clks),       \
+        .gate_clks              = bus##id##_gate_clks,                  \
+        .nr_gate_clks           = ARRAY_SIZE(bus##id##_gate_clks),      \
+        .nr_clk_ids             = BUSx_NR_CLK
+
+static struct samsung_cmu_info bus0_cmu_info __initdata = {
+        CMU_BUS_INFO_CLKS(0),
+        .clk_regs               = bus01_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(bus01_clk_regs),
+};
+
+static struct samsung_cmu_info bus1_cmu_info __initdata = {
+        CMU_BUS_INFO_CLKS(1),
+        .clk_regs               = bus01_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(bus01_clk_regs),
+};
+
+static struct samsung_cmu_info bus2_cmu_info __initdata = {
+        CMU_BUS_INFO_CLKS(2),
+        .mux_clks               = bus2_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(bus2_mux_clks),
+        .clk_regs               = bus2_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(bus2_clk_regs),
+};
+
+#define exynos5433_cmu_bus_init(id)                                     \
+static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\
+{                                                                       \
+        samsung_cmu_register_one(np, &bus##id##_cmu_info);              \
+}                                                                       \
+CLK_OF_DECLARE(exynos5433_cmu_bus##id,                                  \
+                "samsung,exynos5433-cmu-bus"#id,                        \
+                exynos5433_cmu_bus##id##_init)
+
+exynos5433_cmu_bus_init(0);
+exynos5433_cmu_bus_init(1);
+exynos5433_cmu_bus_init(2);
+
+/*
+ * Register offset definitions for CMU_G3D
+ */
+#define G3D_PLL_LOCK                    0x0000
+#define G3D_PLL_CON0                    0x0100
+#define G3D_PLL_CON1                    0x0104
+#define G3D_PLL_FREQ_DET                0x010c
+#define MUX_SEL_G3D                     0x0200
+#define MUX_ENABLE_G3D                  0x0300
+#define MUX_STAT_G3D                    0x0400
+#define DIV_G3D                         0x0600
+#define DIV_G3D_PLL_FREQ_DET            0x0604
+#define DIV_STAT_G3D                    0x0700
+#define DIV_STAT_G3D_PLL_FREQ_DET       0x0704
+#define ENABLE_ACLK_G3D                 0x0800
+#define ENABLE_PCLK_G3D                 0x0900
+#define ENABLE_SCLK_G3D                 0x0a00
+#define ENABLE_IP_G3D0                  0x0b00
+#define ENABLE_IP_G3D1                  0x0b04
+#define CLKOUT_CMU_G3D                  0x0c00
+#define CLKOUT_CMU_G3D_DIV_STAT         0x0c04
+#define CLK_STOPCTRL                    0x1000
+
+static unsigned long g3d_clk_regs[] __initdata = {
+        G3D_PLL_LOCK,
+        G3D_PLL_CON0,
+        G3D_PLL_CON1,
+        G3D_PLL_FREQ_DET,
+        MUX_SEL_G3D,
+        MUX_ENABLE_G3D,
+        MUX_STAT_G3D,
+        DIV_G3D,
+        DIV_G3D_PLL_FREQ_DET,
+        DIV_STAT_G3D,
+        DIV_STAT_G3D_PLL_FREQ_DET,
+        ENABLE_ACLK_G3D,
+        ENABLE_PCLK_G3D,
+        ENABLE_SCLK_G3D,
+        ENABLE_IP_G3D0,
+        ENABLE_IP_G3D1,
+        CLKOUT_CMU_G3D,
+        CLKOUT_CMU_G3D_DIV_STAT,
+        CLK_STOPCTRL,
+};
+
+/* list of all parent clock list */
+PNAME(mout_aclk_g3d_400_p)      = { "mout_g3d_pll", "aclk_g3d_400", };
+PNAME(mout_g3d_pll_p)           = { "oscclk", "fout_g3d_pll", };
+
+static struct samsung_pll_clock g3d_pll_clks[] __initdata = {
+        PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
+                G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates),
+};
+
+static struct samsung_mux_clock g3d_mux_clks[] __initdata = {
+        /* MUX_SEL_G3D */
+        MUX(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
+                        MUX_SEL_G3D, 8, 1),
+        MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
+                        MUX_SEL_G3D, 0, 1),
+};
+
+static struct samsung_div_clock g3d_div_clks[] __initdata = {
+        /* DIV_G3D */
+        DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
+                        8, 2),
+        DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
+                        4, 3),
+        DIV(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
+                        0, 3),
+};
+
+static struct samsung_gate_clock g3d_gate_clks[] __initdata = {
+        /* ENABLE_ACLK_G3D */
+        GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
+                        ENABLE_ACLK_G3D, 7, 0, 0),
+        GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d",
+                        ENABLE_ACLK_G3D, 6, 0, 0),
+        GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d",
+                        ENABLE_ACLK_G3D, 5, 0, 0),
+        GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d",
+                        ENABLE_ACLK_G3D, 4, 0, 0),
+        GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
+                        ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d",
+                        ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d",
+                        ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d",
+                        ENABLE_ACLK_G3D, 0, 0, 0),
+
+        /* ENABLE_PCLK_G3D */
+        GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d",
+                        ENABLE_PCLK_G3D, 3, 0, 0),
+        GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d",
+                        ENABLE_PCLK_G3D, 2, 0, 0),
+        GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d",
+                        ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d",
+                        ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_SCLK_G3D */
+        GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
+                        ENABLE_SCLK_G3D, 0, 0, 0),
+};
+
+static struct samsung_cmu_info g3d_cmu_info __initdata = {
+        .pll_clks               = g3d_pll_clks,
+        .nr_pll_clks            = ARRAY_SIZE(g3d_pll_clks),
+        .mux_clks               = g3d_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(g3d_mux_clks),
+        .div_clks               = g3d_div_clks,
+        .nr_div_clks            = ARRAY_SIZE(g3d_div_clks),
+        .gate_clks              = g3d_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(g3d_gate_clks),
+        .nr_clk_ids             = G3D_NR_CLK,
+        .clk_regs               = g3d_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(g3d_clk_regs),
+};
+
+static void __init exynos5433_cmu_g3d_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &g3d_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
+                exynos5433_cmu_g3d_init);
+
+/*
+ * Register offset definitions for CMU_GSCL
+ */
+#define MUX_SEL_GSCL                            0x0200
+#define MUX_ENABLE_GSCL                         0x0300
+#define MUX_STAT_GSCL                           0x0400
+#define ENABLE_ACLK_GSCL                        0x0800
+#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0      0x0804
+#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1      0x0808
+#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2      0x080c
+#define ENABLE_PCLK_GSCL                        0x0900
+#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0      0x0904
+#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1      0x0908
+#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2      0x090c
+#define ENABLE_IP_GSCL0                         0x0b00
+#define ENABLE_IP_GSCL1                         0x0b04
+#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0        0x0b08
+#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1        0x0b0c
+#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2        0x0b10
+
+static unsigned long gscl_clk_regs[] __initdata = {
+        MUX_SEL_GSCL,
+        MUX_ENABLE_GSCL,
+        MUX_STAT_GSCL,
+        ENABLE_ACLK_GSCL,
+        ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
+        ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
+        ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
+        ENABLE_PCLK_GSCL,
+        ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
+        ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
+        ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
+        ENABLE_IP_GSCL0,
+        ENABLE_IP_GSCL1,
+        ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
+        ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
+        ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
+};
+
+/* list of all parent clock list */
+PNAME(aclk_gscl_111_user_p)     = { "oscclk", "aclk_gscl_111", };
+PNAME(aclk_gscl_333_user_p)     = { "oscclk", "aclk_gscl_333", };
+
+static struct samsung_mux_clock gscl_mux_clks[] __initdata = {
+        /* MUX_SEL_GSCL */
+        MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
+                        aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
+        MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
+                        aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
+};
+
+static struct samsung_gate_clock gscl_gate_clks[] __initdata = {
+        /* ENABLE_ACLK_GSCL */
+        GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
+                        ENABLE_ACLK_GSCL, 11, 0, 0),
+        GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user",
+                        ENABLE_ACLK_GSCL, 10, 0, 0),
+        GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user",
+                        ENABLE_ACLK_GSCL, 9, 0, 0),
+        GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp",
+                        "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL,
+                        8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user",
+                        ENABLE_ACLK_GSCL, 7, 0, 0),
+        GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
+                        ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
+                        "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 0, 0),
+        GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
+                        "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 0, 0),
+        GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
+                        ENABLE_ACLK_GSCL, 3, 0, 0),
+        GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
+                        ENABLE_ACLK_GSCL, 2, 0, 0),
+        GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user",
+                        ENABLE_ACLK_GSCL, 1, 0, 0),
+        GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user",
+                        ENABLE_ACLK_GSCL, 0, 0, 0),
+
+        /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */
+        GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user",
+                        ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
+
+        /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */
+        GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user",
+                        ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
+
+        /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */
+        GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user",
+                        ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
+
+        /* ENABLE_PCLK_GSCL */
+        GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user",
+                        ENABLE_PCLK_GSCL, 7, 0, 0),
+        GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user",
+                        ENABLE_PCLK_GSCL, 6, 0, 0),
+        GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user",
+                        ENABLE_PCLK_GSCL, 5, 0, 0),
+        GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user",
+                        ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl",
+                        "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL,
+                        3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user",
+                        ENABLE_PCLK_GSCL, 2, 0, 0),
+        GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user",
+                        ENABLE_PCLK_GSCL, 1, 0, 0),
+        GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user",
+                        ENABLE_PCLK_GSCL, 0, 0, 0),
+
+        /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */
+        GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user",
+                ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
+
+        /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
+        GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
+                ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
+
+        /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
+        GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
+                ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
+};
+
+static struct samsung_cmu_info gscl_cmu_info __initdata = {
+        .mux_clks               = gscl_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(gscl_mux_clks),
+        .gate_clks              = gscl_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(gscl_gate_clks),
+        .nr_clk_ids             = GSCL_NR_CLK,
+        .clk_regs               = gscl_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(gscl_clk_regs),
+};
+
+static void __init exynos5433_cmu_gscl_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &gscl_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_gscl, "samsung,exynos5433-cmu-gscl",
+                exynos5433_cmu_gscl_init);
+
+/*
+ * Register offset definitions for CMU_APOLLO
+ */
+#define APOLLO_PLL_LOCK                         0x0000
+#define APOLLO_PLL_CON0                         0x0100
+#define APOLLO_PLL_CON1                         0x0104
+#define APOLLO_PLL_FREQ_DET                     0x010c
+#define MUX_SEL_APOLLO0                         0x0200
+#define MUX_SEL_APOLLO1                         0x0204
+#define MUX_SEL_APOLLO2                         0x0208
+#define MUX_ENABLE_APOLLO0                      0x0300
+#define MUX_ENABLE_APOLLO1                      0x0304
+#define MUX_ENABLE_APOLLO2                      0x0308
+#define MUX_STAT_APOLLO0                        0x0400
+#define MUX_STAT_APOLLO1                        0x0404
+#define MUX_STAT_APOLLO2                        0x0408
+#define DIV_APOLLO0                             0x0600
+#define DIV_APOLLO1                             0x0604
+#define DIV_APOLLO_PLL_FREQ_DET                 0x0608
+#define DIV_STAT_APOLLO0                        0x0700
+#define DIV_STAT_APOLLO1                        0x0704
+#define DIV_STAT_APOLLO_PLL_FREQ_DET            0x0708
+#define ENABLE_ACLK_APOLLO                      0x0800
+#define ENABLE_PCLK_APOLLO                      0x0900
+#define ENABLE_SCLK_APOLLO                      0x0a00
+#define ENABLE_IP_APOLLO0                       0x0b00
+#define ENABLE_IP_APOLLO1                       0x0b04
+#define CLKOUT_CMU_APOLLO                       0x0c00
+#define CLKOUT_CMU_APOLLO_DIV_STAT              0x0c04
+#define ARMCLK_STOPCTRL                         0x1000
+#define APOLLO_PWR_CTRL                         0x1020
+#define APOLLO_PWR_CTRL2                        0x1024
+#define APOLLO_INTR_SPREAD_ENABLE               0x1080
+#define APOLLO_INTR_SPREAD_USE_STANDBYWFI       0x1084
+#define APOLLO_INTR_SPREAD_BLOCKING_DURATION    0x1088
+
+static unsigned long apollo_clk_regs[] __initdata = {
+        APOLLO_PLL_LOCK,
+        APOLLO_PLL_CON0,
+        APOLLO_PLL_CON1,
+        APOLLO_PLL_FREQ_DET,
+        MUX_SEL_APOLLO0,
+        MUX_SEL_APOLLO1,
+        MUX_SEL_APOLLO2,
+        MUX_ENABLE_APOLLO0,
+        MUX_ENABLE_APOLLO1,
+        MUX_ENABLE_APOLLO2,
+        MUX_STAT_APOLLO0,
+        MUX_STAT_APOLLO1,
+        MUX_STAT_APOLLO2,
+        DIV_APOLLO0,
+        DIV_APOLLO1,
+        DIV_APOLLO_PLL_FREQ_DET,
+        DIV_STAT_APOLLO0,
+        DIV_STAT_APOLLO1,
+        DIV_STAT_APOLLO_PLL_FREQ_DET,
+        ENABLE_ACLK_APOLLO,
+        ENABLE_PCLK_APOLLO,
+        ENABLE_SCLK_APOLLO,
+        ENABLE_IP_APOLLO0,
+        ENABLE_IP_APOLLO1,
+        CLKOUT_CMU_APOLLO,
+        CLKOUT_CMU_APOLLO_DIV_STAT,
+        ARMCLK_STOPCTRL,
+        APOLLO_PWR_CTRL,
+        APOLLO_PWR_CTRL2,
+        APOLLO_INTR_SPREAD_ENABLE,
+        APOLLO_INTR_SPREAD_USE_STANDBYWFI,
+        APOLLO_INTR_SPREAD_BLOCKING_DURATION,
+};
+
+/* list of all parent clock list */
+PNAME(mout_apollo_pll_p)                = { "oscclk", "fout_apollo_pll", };
+PNAME(mout_bus_pll_apollo_user_p)       = { "oscclk", "sclk_bus_pll_apollo", };
+PNAME(mout_apollo_p)                    = { "mout_apollo_pll",
+                                            "mout_bus_pll_apollo_user", };
+
+static struct samsung_pll_clock apollo_pll_clks[] __initdata = {
+        PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
+                APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5443_pll_rates),
+};
+
+static struct samsung_mux_clock apollo_mux_clks[] __initdata = {
+        /* MUX_SEL_APOLLO0 */
+        MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
+                        MUX_SEL_APOLLO0, 0, 1, 0, CLK_MUX_READ_ONLY),
+
+        /* MUX_SEL_APOLLO1 */
+        MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user",
+                        mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
+
+        /* MUX_SEL_APOLLO2 */
+        MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2,
+                        0, 1, 0, CLK_MUX_READ_ONLY),
+};
+
+static struct samsung_div_clock apollo_div_clks[] __initdata = {
+        /* DIV_APOLLO0 */
+        DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
+                        DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE,
+                        CLK_DIVIDER_READ_ONLY),
+        DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2",
+                        DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE,
+                        CLK_DIVIDER_READ_ONLY),
+        DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2",
+                        DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE,
+                        CLK_DIVIDER_READ_ONLY),
+        DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2",
+                        DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE,
+                        CLK_DIVIDER_READ_ONLY),
+        DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2",
+                        DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE,
+                        CLK_DIVIDER_READ_ONLY),
+        DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1",
+                        DIV_APOLLO0, 4, 3, CLK_GET_RATE_NOCACHE,
+                        CLK_DIVIDER_READ_ONLY),
+        DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo",
+                        DIV_APOLLO0, 0, 3, CLK_GET_RATE_NOCACHE,
+                        CLK_DIVIDER_READ_ONLY),
+
+        /* DIV_APOLLO1 */
+        DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo",
+                        DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE,
+                        CLK_DIVIDER_READ_ONLY),
+        DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo",
+                        DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
+                        CLK_DIVIDER_READ_ONLY),
+};
+
+static struct samsung_gate_clock apollo_gate_clks[] __initdata = {
+        /* ENABLE_ACLK_APOLLO */
+        GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys",
+                        "div_atclk_apollo", ENABLE_ACLK_APOLLO,
+                        6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys",
+                        "div_atclk_apollo", ENABLE_ACLK_APOLLO,
+                        5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys",
+                        "div_atclk_apollo", ENABLE_ACLK_APOLLO,
+                        4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys",
+                        "div_atclk_apollo", ENABLE_ACLK_APOLLO,
+                        3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci",
+                        "div_aclk_apollo", ENABLE_ACLK_APOLLO,
+                        2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop",
+                        "div_pclk_apollo", ENABLE_ACLK_APOLLO,
+                        1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200",
+                        "div_pclk_apollo", ENABLE_ACLK_APOLLO,
+                        0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_PCLK_APOLLO */
+        GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo",
+                        "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO,
+                        2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo",
+                        ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo",
+                        "div_pclk_apollo", ENABLE_PCLK_APOLLO,
+                        0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_SCLK_APOLLO */
+        GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo",
+                        ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
+                        ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo_pll",
+                        ENABLE_SCLK_APOLLO, 0, CLK_IGNORE_UNUSED, 0),
+};
+
+static struct samsung_cmu_info apollo_cmu_info __initdata = {
+        .pll_clks               = apollo_pll_clks,
+        .nr_pll_clks            = ARRAY_SIZE(apollo_pll_clks),
+        .mux_clks               = apollo_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(apollo_mux_clks),
+        .div_clks               = apollo_div_clks,
+        .nr_div_clks            = ARRAY_SIZE(apollo_div_clks),
+        .gate_clks              = apollo_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(apollo_gate_clks),
+        .nr_clk_ids             = APOLLO_NR_CLK,
+        .clk_regs               = apollo_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(apollo_clk_regs),
+};
+
+static void __init exynos5433_cmu_apollo_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &apollo_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
+                exynos5433_cmu_apollo_init);
+
+/*
+ * Register offset definitions for CMU_ATLAS
+ */
+#define ATLAS_PLL_LOCK                          0x0000
+#define ATLAS_PLL_CON0                          0x0100
+#define ATLAS_PLL_CON1                          0x0104
+#define ATLAS_PLL_FREQ_DET                      0x010c
+#define MUX_SEL_ATLAS0                          0x0200
+#define MUX_SEL_ATLAS1                          0x0204
+#define MUX_SEL_ATLAS2                          0x0208
+#define MUX_ENABLE_ATLAS0                       0x0300
+#define MUX_ENABLE_ATLAS1                       0x0304
+#define MUX_ENABLE_ATLAS2                       0x0308
+#define MUX_STAT_ATLAS0                         0x0400
+#define MUX_STAT_ATLAS1                         0x0404
+#define MUX_STAT_ATLAS2                         0x0408
+#define DIV_ATLAS0                              0x0600
+#define DIV_ATLAS1                              0x0604
+#define DIV_ATLAS_PLL_FREQ_DET                  0x0608
+#define DIV_STAT_ATLAS0                         0x0700
+#define DIV_STAT_ATLAS1                         0x0704
+#define DIV_STAT_ATLAS_PLL_FREQ_DET             0x0708
+#define ENABLE_ACLK_ATLAS                       0x0800
+#define ENABLE_PCLK_ATLAS                       0x0900
+#define ENABLE_SCLK_ATLAS                       0x0a00
+#define ENABLE_IP_ATLAS0                        0x0b00
+#define ENABLE_IP_ATLAS1                        0x0b04
+#define CLKOUT_CMU_ATLAS                        0x0c00
+#define CLKOUT_CMU_ATLAS_DIV_STAT               0x0c04
+#define ARMCLK_STOPCTRL                         0x1000
+#define ATLAS_PWR_CTRL                          0x1020
+#define ATLAS_PWR_CTRL2                         0x1024
+#define ATLAS_INTR_SPREAD_ENABLE                0x1080
+#define ATLAS_INTR_SPREAD_USE_STANDBYWFI        0x1084
+#define ATLAS_INTR_SPREAD_BLOCKING_DURATION     0x1088
+
+static unsigned long atlas_clk_regs[] __initdata = {
+        ATLAS_PLL_LOCK,
+        ATLAS_PLL_CON0,
+        ATLAS_PLL_CON1,
+        ATLAS_PLL_FREQ_DET,
+        MUX_SEL_ATLAS0,
+        MUX_SEL_ATLAS1,
+        MUX_SEL_ATLAS2,
+        MUX_ENABLE_ATLAS0,
+        MUX_ENABLE_ATLAS1,
+        MUX_ENABLE_ATLAS2,
+        MUX_STAT_ATLAS0,
+        MUX_STAT_ATLAS1,
+        MUX_STAT_ATLAS2,
+        DIV_ATLAS0,
+        DIV_ATLAS1,
+        DIV_ATLAS_PLL_FREQ_DET,
+        DIV_STAT_ATLAS0,
+        DIV_STAT_ATLAS1,
+        DIV_STAT_ATLAS_PLL_FREQ_DET,
+        ENABLE_ACLK_ATLAS,
+        ENABLE_PCLK_ATLAS,
+        ENABLE_SCLK_ATLAS,
+        ENABLE_IP_ATLAS0,
+        ENABLE_IP_ATLAS1,
+        CLKOUT_CMU_ATLAS,
+        CLKOUT_CMU_ATLAS_DIV_STAT,
+        ARMCLK_STOPCTRL,
+        ATLAS_PWR_CTRL,
+        ATLAS_PWR_CTRL2,
+        ATLAS_INTR_SPREAD_ENABLE,
+        ATLAS_INTR_SPREAD_USE_STANDBYWFI,
+        ATLAS_INTR_SPREAD_BLOCKING_DURATION,
+};
+
+/* list of all parent clock list */
+PNAME(mout_atlas_pll_p)                 = { "oscclk", "fout_atlas_pll", };
+PNAME(mout_bus_pll_atlas_user_p)        = { "oscclk", "sclk_bus_pll_atlas", };
+PNAME(mout_atlas_p)                     = { "mout_atlas_pll",
+                                            "mout_bus_pll_atlas_user", };
+
+static struct samsung_pll_clock atlas_pll_clks[] __initdata = {
+        PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk",
+                ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5443_pll_rates),
+};
+
+static struct samsung_mux_clock atlas_mux_clks[] __initdata = {
+        /* MUX_SEL_ATLAS0 */
+        MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
+                        MUX_SEL_ATLAS0, 0, 1, 0, CLK_MUX_READ_ONLY),
+
+        /* MUX_SEL_ATLAS1 */
+        MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user",
+                        mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
+
+        /* MUX_SEL_ATLAS2 */
+        MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2,
+                        0, 1, 0, CLK_MUX_READ_ONLY),
+};
+
+static struct samsung_div_clock atlas_div_clks[] __initdata = {
+        /* DIV_ATLAS0 */
+        DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2",
+                        DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE,
+                        CLK_DIVIDER_READ_ONLY),
+        DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas",
+                        DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE,
+                        CLK_DIVIDER_READ_ONLY),
+        DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2",
+                        DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE,
+                        CLK_DIVIDER_READ_ONLY),
+        DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2",
+                        DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE,
+                        CLK_DIVIDER_READ_ONLY),
+        DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2",
+                        DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE,
+                        CLK_DIVIDER_READ_ONLY),
+        DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1",
+                        DIV_ATLAS0, 4, 3, CLK_GET_RATE_NOCACHE,
+                        CLK_DIVIDER_READ_ONLY),
+        DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas",
+                        DIV_ATLAS0, 0, 3, CLK_GET_RATE_NOCACHE,
+                        CLK_DIVIDER_READ_ONLY),
+
+        /* DIV_ATLAS1 */
+        DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas",
+                        DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE,
+                        CLK_DIVIDER_READ_ONLY),
+        DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas",
+                        DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
+                        CLK_DIVIDER_READ_ONLY),
+};
+
+static struct samsung_gate_clock atlas_gate_clks[] __initdata = {
+        /* ENABLE_ACLK_ATLAS */
+        GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys",
+                        "div_atclk_atlas", ENABLE_ACLK_ATLAS,
+                        9, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys",
+                        "div_atclk_atlas", ENABLE_ACLK_ATLAS,
+                        8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys",
+                        "div_atclk_atlas", ENABLE_ACLK_ATLAS,
+                        7, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys",
+                        "div_atclk_atlas", ENABLE_ACLK_ATLAS,
+                        6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys",
+                        "div_atclk_atlas", ENABLE_ACLK_ATLAS,
+                        5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss",
+                        "div_atclk_atlas", ENABLE_ACLK_ATLAS,
+                        4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix",
+                        "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS,
+                        3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci",
+                        "div_aclk_atlas", ENABLE_ACLK_ATLAS,
+                        2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas",
+                        ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas",
+                        ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_PCLK_ATLAS */
+        GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys",
+                        "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
+                        5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys",
+                        "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
+                        4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys",
+                        "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
+                        3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas",
+                        ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas",
+                        ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas",
+                        ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_SCLK_ATLAS */
+        GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas",
+                        ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas",
+                        ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas",
+                        ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas",
+                        ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas",
+                        ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas",
+                        ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas",
+                        ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
+                        ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_ATLAS, "sclk_atlas", "div_atlas2",
+                        ENABLE_SCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
+};
+
+static struct samsung_cmu_info atlas_cmu_info __initdata = {
+        .pll_clks               = atlas_pll_clks,
+        .nr_pll_clks            = ARRAY_SIZE(atlas_pll_clks),
+        .mux_clks               = atlas_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(atlas_mux_clks),
+        .div_clks               = atlas_div_clks,
+        .nr_div_clks            = ARRAY_SIZE(atlas_div_clks),
+        .gate_clks              = atlas_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(atlas_gate_clks),
+        .nr_clk_ids             = ATLAS_NR_CLK,
+        .clk_regs               = atlas_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(atlas_clk_regs),
+};
+
+static void __init exynos5433_cmu_atlas_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &atlas_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
+                exynos5433_cmu_atlas_init);
+
+/*
+ * Register offset definitions for CMU_MSCL
+ */
+#define MUX_SEL_MSCL0                                   0x0200
+#define MUX_SEL_MSCL1                                   0x0204
+#define MUX_ENABLE_MSCL0                                0x0300
+#define MUX_ENABLE_MSCL1                                0x0304
+#define MUX_STAT_MSCL0                                  0x0400
+#define MUX_STAT_MSCL1                                  0x0404
+#define DIV_MSCL                                        0x0600
+#define DIV_STAT_MSCL                                   0x0700
+#define ENABLE_ACLK_MSCL                                0x0800
+#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0         0x0804
+#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1         0x0808
+#define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG               0x080c
+#define ENABLE_PCLK_MSCL                                0x0900
+#define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0         0x0904
+#define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1         0x0908
+#define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG               0x000c
+#define ENABLE_SCLK_MSCL                                0x0a00
+#define ENABLE_IP_MSCL0                                 0x0b00
+#define ENABLE_IP_MSCL1                                 0x0b04
+#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0           0x0b08
+#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1           0x0b0c
+#define ENABLE_IP_MSCL_SECURE_SMMU_JPEG                 0x0b10
+
+static unsigned long mscl_clk_regs[] __initdata = {
+        MUX_SEL_MSCL0,
+        MUX_SEL_MSCL1,
+        MUX_ENABLE_MSCL0,
+        MUX_ENABLE_MSCL1,
+        MUX_STAT_MSCL0,
+        MUX_STAT_MSCL1,
+        DIV_MSCL,
+        DIV_STAT_MSCL,
+        ENABLE_ACLK_MSCL,
+        ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
+        ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
+        ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
+        ENABLE_PCLK_MSCL,
+        ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
+        ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
+        ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
+        ENABLE_SCLK_MSCL,
+        ENABLE_IP_MSCL0,
+        ENABLE_IP_MSCL1,
+        ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0,
+        ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1,
+        ENABLE_IP_MSCL_SECURE_SMMU_JPEG,
+};
+
+/* list of all parent clock list */
+PNAME(mout_sclk_jpeg_user_p)            = { "oscclk", "sclk_jpeg_mscl", };
+PNAME(mout_aclk_mscl_400_user_p)        = { "oscclk", "aclk_mscl_400", };
+PNAME(mout_sclk_jpeg_p)                 = { "mout_sclk_jpeg_user",
+                                        "mout_aclk_mscl_400_user", };
+
+static struct samsung_mux_clock mscl_mux_clks[] __initdata = {
+        /* MUX_SEL_MSCL0 */
+        MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user",
+                        mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1),
+        MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user",
+                        mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
+
+        /* MUX_SEL_MSCL1 */
+        MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p,
+                        MUX_SEL_MSCL1, 0, 1),
+};
+
+static struct samsung_div_clock mscl_div_clks[] __initdata = {
+        /* DIV_MSCL */
+        DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user",
+                        DIV_MSCL, 0, 3),
+};
+
+static struct samsung_gate_clock mscl_gate_clks[] __initdata = {
+        /* ENABLE_ACLK_MSCL */
+        GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
+                        ENABLE_ACLK_MSCL, 9, 0, 0),
+        GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1",
+                        "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
+        GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0",
+                        "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
+        GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl",
+                        ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user",
+                        ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl",
+                        ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user",
+                        ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user",
+                        ENABLE_ACLK_MSCL, 2, 0, 0),
+        GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user",
+                        ENABLE_ACLK_MSCL, 1, 0, 0),
+        GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user",
+                        ENABLE_ACLK_MSCL, 0, 0, 0),
+
+        /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */
+        GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0",
+                        "mout_aclk_mscl_400_user",
+                        ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
+                        0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */
+        GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1",
+                        "mout_aclk_mscl_400_user",
+                        ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
+                        0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */
+        GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user",
+                        ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
+                        0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_PCLK_MSCL */
+        GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl",
+                        ENABLE_PCLK_MSCL, 7, 0, 0),
+        GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl",
+                        ENABLE_PCLK_MSCL, 6, 0, 0),
+        GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl",
+                        ENABLE_PCLK_MSCL, 5, 0, 0),
+        GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl",
+                        ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl",
+                        ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl",
+                        ENABLE_PCLK_MSCL, 2, 0, 0),
+        GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl",
+                        ENABLE_PCLK_MSCL, 1, 0, 0),
+        GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl",
+                        ENABLE_PCLK_MSCL, 0, 0, 0),
+
+        /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */
+        GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl",
+                        ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
+                        0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */
+        GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl",
+                        ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
+                        0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */
+        GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl",
+                        ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
+                        0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_SCLK_MSCL */
+        GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
+                        CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+};
+
+static struct samsung_cmu_info mscl_cmu_info __initdata = {
+        .mux_clks               = mscl_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(mscl_mux_clks),
+        .div_clks               = mscl_div_clks,
+        .nr_div_clks            = ARRAY_SIZE(mscl_div_clks),
+        .gate_clks              = mscl_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(mscl_gate_clks),
+        .nr_clk_ids             = MSCL_NR_CLK,
+        .clk_regs               = mscl_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(mscl_clk_regs),
+};
+
+static void __init exynos5433_cmu_mscl_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &mscl_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_mscl, "samsung,exynos5433-cmu-mscl",
+                exynos5433_cmu_mscl_init);
+
+/*
+ * Register offset definitions for CMU_MFC
+ */
+#define MUX_SEL_MFC                             0x0200
+#define MUX_ENABLE_MFC                          0x0300
+#define MUX_STAT_MFC                            0x0400
+#define DIV_MFC                                 0x0600
+#define DIV_STAT_MFC                            0x0700
+#define ENABLE_ACLK_MFC                         0x0800
+#define ENABLE_ACLK_MFC_SECURE_SMMU_MFC         0x0804
+#define ENABLE_PCLK_MFC                         0x0900
+#define ENABLE_PCLK_MFC_SECURE_SMMU_MFC         0x0904
+#define ENABLE_IP_MFC0                          0x0b00
+#define ENABLE_IP_MFC1                          0x0b04
+#define ENABLE_IP_MFC_SECURE_SMMU_MFC           0x0b08
+
+static unsigned long mfc_clk_regs[] __initdata = {
+        MUX_SEL_MFC,
+        MUX_ENABLE_MFC,
+        MUX_STAT_MFC,
+        DIV_MFC,
+        DIV_STAT_MFC,
+        ENABLE_ACLK_MFC,
+        ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
+        ENABLE_PCLK_MFC,
+        ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
+        ENABLE_IP_MFC0,
+        ENABLE_IP_MFC1,
+        ENABLE_IP_MFC_SECURE_SMMU_MFC,
+};
+
+PNAME(mout_aclk_mfc_400_user_p)         = { "oscclk", "aclk_mfc_400", };
+
+static struct samsung_mux_clock mfc_mux_clks[] __initdata = {
+        /* MUX_SEL_MFC */
+        MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user",
+                        mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
+};
+
+static struct samsung_div_clock mfc_div_clks[] __initdata = {
+        /* DIV_MFC */
+        DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user",
+                        DIV_MFC, 0, 2),
+};
+
+static struct samsung_gate_clock mfc_gate_clks[] __initdata = {
+        /* ENABLE_ACLK_MFC */
+        GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
+                        ENABLE_ACLK_MFC, 6, 0, 0),
+        GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user",
+                        ENABLE_ACLK_MFC, 5, 0, 0),
+        GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc",
+                        ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user",
+                        ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc",
+                        ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user",
+                        ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user",
+                        ENABLE_ACLK_MFC, 0, 0, 0),
+
+        /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */
+        GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user",
+                        ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
+                        1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user",
+                        ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
+                        0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_PCLK_MFC */
+        GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc",
+                        ENABLE_PCLK_MFC, 4, 0, 0),
+        GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc",
+                        ENABLE_PCLK_MFC, 3, 0, 0),
+        GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc",
+                        ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc",
+                        ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc",
+                        ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */
+        GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc",
+                        ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
+                        1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc",
+                        ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
+                        0, CLK_IGNORE_UNUSED, 0),
+};
+
+static struct samsung_cmu_info mfc_cmu_info __initdata = {
+        .mux_clks               = mfc_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(mfc_mux_clks),
+        .div_clks               = mfc_div_clks,
+        .nr_div_clks            = ARRAY_SIZE(mfc_div_clks),
+        .gate_clks              = mfc_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(mfc_gate_clks),
+        .nr_clk_ids             = MFC_NR_CLK,
+        .clk_regs               = mfc_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(mfc_clk_regs),
+};
+
+static void __init exynos5433_cmu_mfc_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &mfc_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc",
+                exynos5433_cmu_mfc_init);
+
+/*
+ * Register offset definitions for CMU_HEVC
+ */
+#define MUX_SEL_HEVC                            0x0200
+#define MUX_ENABLE_HEVC                         0x0300
+#define MUX_STAT_HEVC                           0x0400
+#define DIV_HEVC                                0x0600
+#define DIV_STAT_HEVC                           0x0700
+#define ENABLE_ACLK_HEVC                        0x0800
+#define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC       0x0804
+#define ENABLE_PCLK_HEVC                        0x0900
+#define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC       0x0904
+#define ENABLE_IP_HEVC0                         0x0b00
+#define ENABLE_IP_HEVC1                         0x0b04
+#define ENABLE_IP_HEVC_SECURE_SMMU_HEVC         0x0b08
+
+static unsigned long hevc_clk_regs[] __initdata = {
+        MUX_SEL_HEVC,
+        MUX_ENABLE_HEVC,
+        MUX_STAT_HEVC,
+        DIV_HEVC,
+        DIV_STAT_HEVC,
+        ENABLE_ACLK_HEVC,
+        ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
+        ENABLE_PCLK_HEVC,
+        ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
+        ENABLE_IP_HEVC0,
+        ENABLE_IP_HEVC1,
+        ENABLE_IP_HEVC_SECURE_SMMU_HEVC,
+};
+
+PNAME(mout_aclk_hevc_400_user_p)        = { "oscclk", "aclk_hevc_400", };
+
+static struct samsung_mux_clock hevc_mux_clks[] __initdata = {
+        /* MUX_SEL_HEVC */
+        MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user",
+                        mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
+};
+
+static struct samsung_div_clock hevc_div_clks[] __initdata = {
+        /* DIV_HEVC */
+        DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user",
+                        DIV_HEVC, 0, 2),
+};
+
+static struct samsung_gate_clock hevc_gate_clks[] __initdata = {
+        /* ENABLE_ACLK_HEVC */
+        GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
+                        ENABLE_ACLK_HEVC, 6, 0, 0),
+        GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user",
+                        ENABLE_ACLK_HEVC, 5, 0, 0),
+        GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc",
+                        ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user",
+                        ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc",
+                        ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user",
+                        ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user",
+                        ENABLE_ACLK_HEVC, 0, 0, 0),
+
+        /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */
+        GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1",
+                        "mout_aclk_hevc_400_user",
+                        ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
+                        1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0",
+                        "mout_aclk_hevc_400_user",
+                        ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
+                        0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_PCLK_HEVC */
+        GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc",
+                        ENABLE_PCLK_HEVC, 4, 0, 0),
+        GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc",
+                        ENABLE_PCLK_HEVC, 3, 0, 0),
+        GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc",
+                        ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc",
+                        ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc",
+                        ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */
+        GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc",
+                        ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
+                        1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc",
+                        ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
+                        0, CLK_IGNORE_UNUSED, 0),
+};
+
+static struct samsung_cmu_info hevc_cmu_info __initdata = {
+        .mux_clks               = hevc_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(hevc_mux_clks),
+        .div_clks               = hevc_div_clks,
+        .nr_div_clks            = ARRAY_SIZE(hevc_div_clks),
+        .gate_clks              = hevc_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(hevc_gate_clks),
+        .nr_clk_ids             = HEVC_NR_CLK,
+        .clk_regs               = hevc_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(hevc_clk_regs),
+};
+
+static void __init exynos5433_cmu_hevc_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &hevc_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc",
+                exynos5433_cmu_hevc_init);
+
+/*
+ * Register offset definitions for CMU_ISP
+ */
+#define MUX_SEL_ISP                     0x0200
+#define MUX_ENABLE_ISP                  0x0300
+#define MUX_STAT_ISP                    0x0400
+#define DIV_ISP                         0x0600
+#define DIV_STAT_ISP                    0x0700
+#define ENABLE_ACLK_ISP0                0x0800
+#define ENABLE_ACLK_ISP1                0x0804
+#define ENABLE_ACLK_ISP2                0x0808
+#define ENABLE_PCLK_ISP                 0x0900
+#define ENABLE_SCLK_ISP                 0x0a00
+#define ENABLE_IP_ISP0                  0x0b00
+#define ENABLE_IP_ISP1                  0x0b04
+#define ENABLE_IP_ISP2                  0x0b08
+#define ENABLE_IP_ISP3                  0x0b0c
+
+static unsigned long isp_clk_regs[] __initdata = {
+        MUX_SEL_ISP,
+        MUX_ENABLE_ISP,
+        MUX_STAT_ISP,
+        DIV_ISP,
+        DIV_STAT_ISP,
+        ENABLE_ACLK_ISP0,
+        ENABLE_ACLK_ISP1,
+        ENABLE_ACLK_ISP2,
+        ENABLE_PCLK_ISP,
+        ENABLE_SCLK_ISP,
+        ENABLE_IP_ISP0,
+        ENABLE_IP_ISP1,
+        ENABLE_IP_ISP2,
+        ENABLE_IP_ISP3,
+};
+
+PNAME(mout_aclk_isp_dis_400_user_p)     = { "oscclk", "aclk_isp_dis_400", };
+PNAME(mout_aclk_isp_400_user_p)         = { "oscclk", "aclk_isp_400", };
+
+static struct samsung_mux_clock isp_mux_clks[] __initdata = {
+        /* MUX_SEL_ISP */
+        MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user",
+                        mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
+        MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user",
+                        mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
+};
+
+static struct samsung_div_clock isp_div_clks[] __initdata = {
+        /* DIV_ISP */
+        DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis",
+                        "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3),
+        DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user",
+                        DIV_ISP, 8, 3),
+        DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200",
+                        "mout_aclk_isp_400_user", DIV_ISP, 4, 3),
+        DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200",
+                        "mout_aclk_isp_400_user", DIV_ISP, 0, 3),
+};
+
+static struct samsung_gate_clock isp_gate_clks[] __initdata = {
+        /* ENABLE_ACLK_ISP0 */
+        GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP0, 5, 0, 0),
+        GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP0, 4, 0, 0),
+        GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user",
+                        ENABLE_ACLK_ISP0, 3, 0, 0),
+        GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP0, 2, 0, 0),
+        GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP0, 1, 0, 0),
+        GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP0, 0, 0, 0),
+
+        /* ENABLE_ACLK_ISP1 */
+        GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp",
+                        "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
+                        17, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc",
+                        "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
+                        16, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc",
+                        "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
+                        15, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p",
+                        "div_pclk_isp", ENABLE_ACLK_ISP1,
+                        14, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p",
+                        "div_pclk_isp", ENABLE_ACLK_ISP1,
+                        13, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1",
+                        "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
+                        12, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0",
+                        "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
+                        11, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1",
+                        "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
+                        10, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0",
+                        "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
+                        9, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p",
+                        "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
+                        8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p",
+                        "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
+                        7, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp",
+                        ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp",
+                        ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p",
+                        "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
+                        4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p",
+                        "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
+                        3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_ACLK_ISP2 */
+        GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp",
+                        "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
+                        13, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc",
+                        "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
+                        9, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp",
+                        "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
+                        6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc",
+                        "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
+                        2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_PCLK_ISP */
+        GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200",
+                        ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200",
+                        ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200",
+                        ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200",
+                        ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200",
+                        ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200",
+                        ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200",
+                        ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp",
+                        ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp",
+                        ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp",
+                        ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp",
+                        ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp",
+                        ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp",
+                        ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp",
+                        ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp",
+                        ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp",
+                        ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp",
+                        ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp",
+                        ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local",
+                        "div_aclk_isp_c_200", ENABLE_PCLK_ISP,
+                        7, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200",
+                        ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200",
+                        ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis",
+                        ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200",
+                        ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200",
+                        ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200",
+                        ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200",
+                        ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_SCLK_ISP */
+        GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis",
+                        "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
+                        5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis",
+                        "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
+                        4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp",
+                        "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
+                        3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd",
+                        "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
+                        2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc",
+                        "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
+                        1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc",
+                        "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
+                        0, CLK_IGNORE_UNUSED, 0),
+};
+
+static struct samsung_cmu_info isp_cmu_info __initdata = {
+        .mux_clks               = isp_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(isp_mux_clks),
+        .div_clks               = isp_div_clks,
+        .nr_div_clks            = ARRAY_SIZE(isp_div_clks),
+        .gate_clks              = isp_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(isp_gate_clks),
+        .nr_clk_ids             = ISP_NR_CLK,
+        .clk_regs               = isp_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(isp_clk_regs),
+};
+
+static void __init exynos5433_cmu_isp_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &isp_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_isp, "samsung,exynos5433-cmu-isp",
+                exynos5433_cmu_isp_init);
+
+/*
+ * Register offset definitions for CMU_CAM0
+ */
+#define MUX_SEL_CAM00                   0x0200
+#define MUX_SEL_CAM01                   0x0204
+#define MUX_SEL_CAM02                   0x0208
+#define MUX_SEL_CAM03                   0x020c
+#define MUX_SEL_CAM04                   0x0210
+#define MUX_ENABLE_CAM00                0x0300
+#define MUX_ENABLE_CAM01                0x0304
+#define MUX_ENABLE_CAM02                0x0308
+#define MUX_ENABLE_CAM03                0x030c
+#define MUX_ENABLE_CAM04                0x0310
+#define MUX_STAT_CAM00                  0x0400
+#define MUX_STAT_CAM01                  0x0404
+#define MUX_STAT_CAM02                  0x0408
+#define MUX_STAT_CAM03                  0x040c
+#define MUX_STAT_CAM04                  0x0410
+#define MUX_IGNORE_CAM01                0x0504
+#define DIV_CAM00                       0x0600
+#define DIV_CAM01                       0x0604
+#define DIV_CAM02                       0x0608
+#define DIV_CAM03                       0x060c
+#define DIV_STAT_CAM00                  0x0700
+#define DIV_STAT_CAM01                  0x0704
+#define DIV_STAT_CAM02                  0x0708
+#define DIV_STAT_CAM03                  0x070c
+#define ENABLE_ACLK_CAM00               0X0800
+#define ENABLE_ACLK_CAM01               0X0804
+#define ENABLE_ACLK_CAM02               0X0808
+#define ENABLE_PCLK_CAM0                0X0900
+#define ENABLE_SCLK_CAM0                0X0a00
+#define ENABLE_IP_CAM00                 0X0b00
+#define ENABLE_IP_CAM01                 0X0b04
+#define ENABLE_IP_CAM02                 0X0b08
+#define ENABLE_IP_CAM03                 0X0b0C
+
+static unsigned long cam0_clk_regs[] __initdata = {
+        MUX_SEL_CAM00,
+        MUX_SEL_CAM01,
+        MUX_SEL_CAM02,
+        MUX_SEL_CAM03,
+        MUX_SEL_CAM04,
+        MUX_ENABLE_CAM00,
+        MUX_ENABLE_CAM01,
+        MUX_ENABLE_CAM02,
+        MUX_ENABLE_CAM03,
+        MUX_ENABLE_CAM04,
+        MUX_STAT_CAM00,
+        MUX_STAT_CAM01,
+        MUX_STAT_CAM02,
+        MUX_STAT_CAM03,
+        MUX_STAT_CAM04,
+        MUX_IGNORE_CAM01,
+        DIV_CAM00,
+        DIV_CAM01,
+        DIV_CAM02,
+        DIV_CAM03,
+        DIV_STAT_CAM00,
+        DIV_STAT_CAM01,
+        DIV_STAT_CAM02,
+        DIV_STAT_CAM03,
+        ENABLE_ACLK_CAM00,
+        ENABLE_ACLK_CAM01,
+        ENABLE_ACLK_CAM02,
+        ENABLE_PCLK_CAM0,
+        ENABLE_SCLK_CAM0,
+        ENABLE_IP_CAM00,
+        ENABLE_IP_CAM01,
+        ENABLE_IP_CAM02,
+        ENABLE_IP_CAM03,
+};
+PNAME(mout_aclk_cam0_333_user_p)        = { "oscclk", "aclk_cam0_333", };
+PNAME(mout_aclk_cam0_400_user_p)        = { "oscclk", "aclk_cam0_400", };
+PNAME(mout_aclk_cam0_552_user_p)        = { "oscclk", "aclk_cam0_552", };
+
+PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = { "oscclk",
+                                              "phyclk_rxbyteclkhs0_s4_phy", };
+PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = { "oscclk",
+                                               "phyclk_rxbyteclkhs0_s2a_phy", };
+
+PNAME(mout_aclk_lite_d_b_p)             = { "mout_aclk_lite_d_a",
+                                            "mout_aclk_cam0_333_user", };
+PNAME(mout_aclk_lite_d_a_p)             = { "mout_aclk_cam0_552_user",
+                                            "mout_aclk_cam0_400_user", };
+PNAME(mout_aclk_lite_b_b_p)             = { "mout_aclk_lite_b_a",
+                                            "mout_aclk_cam0_333_user", };
+PNAME(mout_aclk_lite_b_a_p)             = { "mout_aclk_cam0_552_user",
+                                            "mout_aclk_cam0_400_user", };
+PNAME(mout_aclk_lite_a_b_p)             = { "mout_aclk_lite_a_a",
+                                            "mout_aclk_cam0_333_user", };
+PNAME(mout_aclk_lite_a_a_p)             = { "mout_aclk_cam0_552_user",
+                                            "mout_aclk_cam0_400_user", };
+PNAME(mout_aclk_cam0_400_p)             = { "mout_aclk_cam0_400_user",
+                                            "mout_aclk_cam0_333_user", };
+
+PNAME(mout_aclk_csis1_b_p)              = { "mout_aclk_csis1_a",
+                                            "mout_aclk_cam0_333_user" };
+PNAME(mout_aclk_csis1_a_p)              = { "mout_aclk_cam0_552_user",
+                                            "mout_aclk_cam0_400_user", };
+PNAME(mout_aclk_csis0_b_p)              = { "mout_aclk_csis0_a",
+                                            "mout_aclk_cam0_333_user", };
+PNAME(mout_aclk_csis0_a_p)              = { "mout_aclk_cam0_552_user",
+                                            "mout_aclk-cam0_400_user", };
+PNAME(mout_aclk_3aa1_b_p)               = { "mout_aclk_3aa1_a",
+                                            "mout_aclk_cam0_333_user", };
+PNAME(mout_aclk_3aa1_a_p)               = { "mout_aclk_cam0_552_user",
+                                            "mout_aclk_cam0_400_user", };
+PNAME(mout_aclk_3aa0_b_p)               = { "mout_aclk_3aa0_a",
+                                            "mout_aclk_cam0_333_user", };
+PNAME(mout_aclk_3aa0_a_p)               = { "mout_aclk_cam0_552_user",
+                                            "mout_aclk_cam0_400_user", };
+
+PNAME(mout_sclk_lite_freecnt_c_p)       = { "mout_sclk_lite_freecnt_b",
+                                            "div_pclk_lite_d", };
+PNAME(mout_sclk_lite_freecnt_b_p)       = { "mout_sclk_lite_freecnt_a",
+                                            "div_pclk_pixelasync_lite_c", };
+PNAME(mout_sclk_lite_freecnt_a_p)       = { "div_pclk_lite_a",
+                                            "div_pclk_lite_b", };
+PNAME(mout_sclk_pixelasync_lite_c_b_p)  = { "mout_sclk_pixelasync_lite_c_a",
+                                            "mout_aclk_cam0_333_user", };
+PNAME(mout_sclk_pixelasync_lite_c_a_p)  = { "mout_aclk_cam0_552_user",
+                                            "mout_aclk_cam0_400_user", };
+PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = {
+                                        "mout_sclk_pixelasync_lite_c_init_a",
+                                        "mout_aclk_cam0_400_user", };
+PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = {
+                                        "mout_aclk_cam0_552_user",
+                                        "mout_aclk_cam0_400_user", };
+
+static struct samsung_fixed_rate_clock cam0_fixed_clks[] __initdata = {
+        FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy",
+                        NULL, CLK_IS_ROOT, 100000000),
+        FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy",
+                        NULL, CLK_IS_ROOT, 100000000),
+};
+
+static struct samsung_mux_clock cam0_mux_clks[] __initdata = {
+        /* MUX_SEL_CAM00 */
+        MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user",
+                        mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1),
+        MUX(CLK_MOUT_ACLK_CAM0_400_USER, "mout_aclk_cam0_400_user",
+                        mout_aclk_cam0_400_user_p, MUX_SEL_CAM00, 4, 1),
+        MUX(CLK_MOUT_ACLK_CAM0_552_USER, "mout_aclk_cam0_552_user",
+                        mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1),
+
+        /* MUX_SEL_CAM01 */
+        MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER,
+                        "mout_phyclk_rxbyteclkhs0_s4_user",
+                        mout_phyclk_rxbyteclkhs0_s4_user_p,
+                        MUX_SEL_CAM01, 4, 1),
+        MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER,
+                        "mout_phyclk_rxbyteclkhs0_s2a_user",
+                        mout_phyclk_rxbyteclkhs0_s2a_user_p,
+                        MUX_SEL_CAM01, 0, 1),
+
+        /* MUX_SEL_CAM02 */
+        MUX(CLK_MOUT_ACLK_LITE_D_B, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p,
+                        MUX_SEL_CAM02, 24, 1),
+        MUX(CLK_MOUT_ACLK_LITE_D_A, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p,
+                        MUX_SEL_CAM02, 20, 1),
+        MUX(CLK_MOUT_ACLK_LITE_B_B, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p,
+                        MUX_SEL_CAM02, 16, 1),
+        MUX(CLK_MOUT_ACLK_LITE_B_A, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p,
+                        MUX_SEL_CAM02, 12, 1),
+        MUX(CLK_MOUT_ACLK_LITE_A_B, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p,
+                        MUX_SEL_CAM02, 8, 1),
+        MUX(CLK_MOUT_ACLK_LITE_A_A, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p,
+                        MUX_SEL_CAM02, 4, 1),
+        MUX(CLK_MOUT_ACLK_CAM0_400, "mout_aclk_cam0_400", mout_aclk_cam0_400_p,
+                        MUX_SEL_CAM02, 0, 1),
+
+        /* MUX_SEL_CAM03 */
+        MUX(CLK_MOUT_ACLK_CSIS1_B, "mout_aclk_csis1_b", mout_aclk_csis1_b_p,
+                        MUX_SEL_CAM03, 28, 1),
+        MUX(CLK_MOUT_ACLK_CSIS1_A, "mout_aclk_csis1_a", mout_aclk_csis1_a_p,
+                        MUX_SEL_CAM03, 24, 1),
+        MUX(CLK_MOUT_ACLK_CSIS0_B, "mout_aclk_csis0_b", mout_aclk_csis0_b_p,
+                        MUX_SEL_CAM03, 20, 1),
+        MUX(CLK_MOUT_ACLK_CSIS0_A, "mout_aclk_csis0_a", mout_aclk_csis0_a_p,
+                        MUX_SEL_CAM03, 16, 1),
+        MUX(CLK_MOUT_ACLK_3AA1_B, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p,
+                        MUX_SEL_CAM03, 12, 1),
+        MUX(CLK_MOUT_ACLK_3AA1_A, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p,
+                        MUX_SEL_CAM03, 8, 1),
+        MUX(CLK_MOUT_ACLK_3AA0_B, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p,
+                        MUX_SEL_CAM03, 4, 1),
+        MUX(CLK_MOUT_ACLK_3AA0_A, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p,
+                        MUX_SEL_CAM03, 0, 1),
+
+        /* MUX_SEL_CAM04 */
+        MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c",
+                        mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1),
+        MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b",
+                        mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 24, 1),
+        MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a",
+                        mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 24, 1),
+        MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b",
+                        mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 24, 1),
+        MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a",
+                        mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 24, 1),
+        MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B,
+                        "mout_sclk_pixelasync_lite_c_init_b",
+                        mout_sclk_pixelasync_lite_c_init_b_p,
+                        MUX_SEL_CAM04, 24, 1),
+        MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A,
+                        "mout_sclk_pixelasync_lite_c_init_a",
+                        mout_sclk_pixelasync_lite_c_init_a_p,
+                        MUX_SEL_CAM04, 24, 1),
+};
+
+static struct samsung_div_clock cam0_div_clks[] __initdata = {
+        /* DIV_CAM00 */
+        DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200",
+                        DIV_CAM00, 8, 2),
+        DIV(CLK_DIV_ACLK_CAM0_200, "div_aclk_cam0_200", "mout_aclk_cam0_400",
+                        DIV_CAM00, 4, 3),
+        DIV(CLK_DIV_ACLK_CAM0_BUS_400, "div_aclk_cam0_bus_400",
+                        "mout_aclk_cam0_400", DIV_CAM00, 0, 3),
+
+        /* DIV_CAM01 */
+        DIV(CLK_DIV_PCLK_LITE_D, "div_pclk_lite_d", "div_aclk_lite_d",
+                        DIV_CAM01, 20, 2),
+        DIV(CLK_DIV_ACLK_LITE_D, "div_aclk_lite_d", "mout_aclk_lite_d_b",
+                        DIV_CAM01, 16, 3),
+        DIV(CLK_DIV_PCLK_LITE_B, "div_pclk_lite_b", "div_aclk_lite_b",
+                        DIV_CAM01, 12, 2),
+        DIV(CLK_DIV_ACLK_LITE_B, "div_aclk_lite_b", "mout_aclk_lite_b_b",
+                        DIV_CAM01, 8, 3),
+        DIV(CLK_DIV_PCLK_LITE_A, "div_pclk_lite_a", "div_aclk_lite_a",
+                        DIV_CAM01, 4, 2),
+        DIV(CLK_DIV_ACLK_LITE_A, "div_aclk_lite_a", "mout_aclk_lite_a_b",
+                        DIV_CAM01, 0, 3),
+
+        /* DIV_CAM02 */
+        DIV(CLK_DIV_ACLK_CSIS1, "div_aclk_csis1", "mout_aclk_csis1_b",
+                        DIV_CAM02, 20, 3),
+        DIV(CLK_DIV_ACLK_CSIS0, "div_aclk_csis0", "mout_aclk_csis0_b",
+                        DIV_CAM02, 16, 3),
+        DIV(CLK_DIV_PCLK_3AA1, "div_pclk_3aa1", "div_aclk_3aa1",
+                        DIV_CAM02, 12, 2),
+        DIV(CLK_DIV_ACLK_3AA1, "div_aclk_3aa1", "mout_aclk_3aa1_b",
+                        DIV_CAM02, 8, 3),
+        DIV(CLK_DIV_PCLK_3AA0, "div_pclk_3aa0", "div_aclk_3aa0",
+                        DIV_CAM02, 4, 2),
+        DIV(CLK_DIV_ACLK_3AA0, "div_aclk_3aa0", "mout_aclk_3aa0_b",
+                        DIV_CAM02, 0, 3),
+
+        /* DIV_CAM03 */
+        DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C, "div_sclk_pixelasync_lite_c",
+                        "mout_sclk_pixelasync_lite_c_b", DIV_CAM03, 8, 3),
+        DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C, "div_pclk_pixelasync_lite_c",
+                        "div_sclk_pixelasync_lite_c_init", DIV_CAM03, 4, 2),
+        DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT,
+                        "div_sclk_pixelasync_lite_c_init",
+                        "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3),
+};
+
+static struct samsung_gate_clock cam0_gate_clks[] __initdata = {
+        /* ENABLE_ACLK_CAM00 */
+        GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00,
+                        6, 0, 0),
+        GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00,
+                        5, 0, 0),
+        GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00,
+                        4, 0, 0),
+        GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00,
+                        3, 0, 0),
+        GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d",
+                        ENABLE_ACLK_CAM00, 2, 0, 0),
+        GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b",
+                        ENABLE_ACLK_CAM00, 1, 0, 0),
+        GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a",
+                        ENABLE_ACLK_CAM00, 0, 0, 0),
+
+        /* ENABLE_ACLK_CAM01 */
+        GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200",
+                        ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXIUS_LITE_D, "aclk_axius_lite_d", "div_aclk_cam0_bus_400",
+                        ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXIUS_LITE_B, "aclk_axius_lite_b", "div_aclk_cam0_bus_400",
+                        ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXIUS_LITE_A, "aclk_axius_lite_a", "div_aclk_cam0_bus_400",
+                        ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAPBM_3AA1, "aclk_asyncapbm_3aa1", "div_pclk_3aa1",
+                        ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAPBS_3AA1, "aclk_asyncapbs_3aa1", "div_aclk_3aa1",
+                        ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAPBM_3AA0, "aclk_asyncapbm_3aa0", "div_pclk_3aa0",
+                        ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAPBS_3AA0, "aclk_asyncapbs_3aa0", "div_aclk_3aa0",
+                        ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAPBM_LITE_D, "aclk_asyncapbm_lite_d",
+                        "div_pclk_lite_d", ENABLE_ACLK_CAM01,
+                        23, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAPBS_LITE_D, "aclk_asyncapbs_lite_d",
+                        "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
+                        22, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAPBM_LITE_B, "aclk_asyncapbm_lite_b",
+                        "div_pclk_lite_b", ENABLE_ACLK_CAM01,
+                        21, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAPBS_LITE_B, "aclk_asyncapbs_lite_b",
+                        "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
+                        20, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAPBM_LITE_A, "aclk_asyncapbm_lite_a",
+                        "div_pclk_lite_a", ENABLE_ACLK_CAM01,
+                        19, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAPBS_LITE_A, "aclk_asyncapbs_lite_a",
+                        "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
+                        18, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_ISP0P, "aclk_asyncaxim_isp0p",
+                        "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
+                        17, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_3AA1, "aclk_asyncaxim_3aa1",
+                        "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
+                        16, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_3AA1, "aclk_asyncaxis_3aa1",
+                        "div_aclk_3aa1", ENABLE_ACLK_CAM01,
+                        15, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_3AA0, "aclk_asyncaxim_3aa0",
+                        "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
+                        14, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_3AA0, "aclk_asyncaxis_3aa0",
+                        "div_aclk_3aa0", ENABLE_ACLK_CAM01,
+                        13, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_LITE_D, "aclk_asyncaxim_lite_d",
+                        "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
+                        12, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d",
+                        "div_aclk_lite_d", ENABLE_ACLK_CAM01,
+                        11, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_LITE_B, "aclk_asyncaxim_lite_b",
+                        "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
+                        10, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_LITE_B, "aclk_asyncaxis_lite_b",
+                        "div_aclk_lite_b", ENABLE_ACLK_CAM01,
+                        9, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_LITE_A, "aclk_asyncaxim_lite_a",
+                        "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
+                        8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_LITE_A, "aclk_asyncaxis_lite_a",
+                        "div_aclk_lite_a", ENABLE_ACLK_CAM01,
+                        7, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB2APB_ISPSFRP, "aclk_ahb2apb_ispsfrp",
+                        "div_pclk_cam0_50", ENABLE_ACLK_CAM01,
+                        6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXI2APB_ISP0P, "aclk_axi2apb_isp0p", "div_aclk_cam0_200",
+                        ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXI2AHB_ISP0P, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200",
+                        ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_XIU_IS0X, "aclk_xiu_is0x", "div_aclk_cam0_200",
+                        ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_XIU_ISP0EX, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400",
+                        ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_CAM0NP_276, "aclk_cam0np_276", "div_aclk_cam0_200",
+                        ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_CAM0ND_400, "aclk_cam0nd_400", "div_aclk_cam0_bus_400",
+                        ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_ACLK_CAM02 */
+        GATE(CLK_ACLK_SMMU_3AA1, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400",
+                        ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SMMU_3AA0, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400",
+                        ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SMMU_LITE_D, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400",
+                        ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SMMU_LITE_B, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400",
+                        ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SMMU_LITE_A, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400",
+                        ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_3AA1, "aclk_bts_3aa1", "div_aclk_cam0_bus_400",
+                        ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_3AA0, "aclk_bts_3aa0", "div_aclk_cam0_bus_400",
+                        ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_LITE_D, "aclk_bts_lite_d", "div_aclk_cam0_bus_400",
+                        ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_LITE_B, "aclk_bts_lite_b", "div_aclk_cam0_bus_400",
+                        ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_LITE_A, "aclk_bts_lite_a", "div_aclk_cam0_bus_400",
+                        ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_PCLK_CAM0 */
+        GATE(CLK_PCLK_SMMU_3AA1, "pclk_smmu_3aa1", "div_aclk_cam0_200",
+                        ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SMMU_3AA0, "pclk_smmu_3aa0", "div_aclk_cam0_200",
+                        ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SMMU_LITE_D, "pclk_smmu_lite_d", "div_aclk_cam0_200",
+                        ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SMMU_LITE_B, "pclk_smmu_lite_b", "div_aclk_cam0_200",
+                        ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SMMU_LITE_A, "pclk_smmu_lite_a", "div_aclk_cam0_200",
+                        ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_3AA1, "pclk_bts_3aa1", "div_pclk_cam0_50",
+                        ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_3AA0, "pclk_bts_3aa0", "div_pclk_cam0_50",
+                        ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_LITE_D, "pclk_bts_lite_d", "div_pclk_cam0_50",
+                        ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_LITE_B, "pclk_bts_lite_b", "div_pclk_cam0_50",
+                        ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_LITE_A, "pclk_bts_lite_a", "div_pclk_cam0_50",
+                        ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ASYNCAXI_CAM1, "pclk_asyncaxi_cam1", "div_pclk_cam0_50",
+                        ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ASYNCAXI_3AA1, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50",
+                        ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ASYNCAXI_3AA0, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50",
+                        ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ASYNCAXI_LITE_D, "pclk_asyncaxi_lite_d",
+                        "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
+                        12, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ASYNCAXI_LITE_B, "pclk_asyncaxi_lite_b",
+                        "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
+                        11, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ASYNCAXI_LITE_A, "pclk_asyncaxi_lite_a",
+                        "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
+                        10, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_PMU_CAM0, "pclk_pmu_cam0", "div_pclk_cam0_50",
+                        ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SYSREG_CAM0, "pclk_sysreg_cam0", "div_pclk_cam0_50",
+                        ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_CMU_CAM0_LOCAL, "pclk_cmu_cam0_local",
+                        "div_aclk_cam0_200", ENABLE_PCLK_CAM0,
+                        7, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_CSIS1, "pclk_csis1", "div_aclk_cam0_200",
+                        ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_CSIS0, "pclk_csis0", "div_aclk_cam0_200",
+                        ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_3AA1, "pclk_3aa1", "div_pclk_3aa1",
+                        ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_3AA0, "pclk_3aa0", "div_pclk_3aa0",
+                        ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_LITE_D, "pclk_lite_d", "div_pclk_lite_d",
+                        ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_LITE_B, "pclk_lite_b", "div_pclk_lite_b",
+                        ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_LITE_A, "pclk_lite_a", "div_pclk_lite_a",
+                        ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_SCLK_CAM0 */
+        GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4",
+                        "mout_phyclk_rxbyteclkhs0_s4_user",
+                        ENABLE_SCLK_CAM0, 8, 0, 0),
+        GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a",
+                        "mout_phyclk_rxbyteclkhs0_s2a_user",
+                        ENABLE_SCLK_CAM0, 7, 0, 0),
+        GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt",
+                        "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0),
+        GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1",
+                        "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0),
+        GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0",
+                        "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0),
+        GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0",
+                        "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0),
+        GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c",
+                        "div_sclk_pixelasync_lite_c",
+                        ENABLE_SCLK_CAM0, 2, 0, 0),
+        GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init",
+                        "div_sclk_pixelasync_lite_c_init",
+                        ENABLE_SCLK_CAM0, 1, 0, 0),
+        GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init",
+                        "div_sclk_pixelasync_lite_c",
+                        ENABLE_SCLK_CAM0, 0, 0, 0),
+};
+
+static struct samsung_cmu_info cam0_cmu_info __initdata = {
+        .mux_clks               = cam0_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(cam0_mux_clks),
+        .div_clks               = cam0_div_clks,
+        .nr_div_clks            = ARRAY_SIZE(cam0_div_clks),
+        .gate_clks              = cam0_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(cam0_gate_clks),
+        .fixed_clks             = cam0_fixed_clks,
+        .nr_fixed_clks          = ARRAY_SIZE(cam0_fixed_clks),
+        .nr_clk_ids             = CAM0_NR_CLK,
+        .clk_regs               = cam0_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(cam0_clk_regs),
+};
+
+static void __init exynos5433_cmu_cam0_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &cam0_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_cam0, "samsung,exynos5433-cmu-cam0",
+                exynos5433_cmu_cam0_init);
+
+/*
+ * Register offset definitions for CMU_CAM1
+ */
+#define MUX_SEL_CAM10                   0x0200
+#define MUX_SEL_CAM11                   0x0204
+#define MUX_SEL_CAM12                   0x0208
+#define MUX_ENABLE_CAM10                0x0300
+#define MUX_ENABLE_CAM11                0x0304
+#define MUX_ENABLE_CAM12                0x0308
+#define MUX_STAT_CAM10                  0x0400
+#define MUX_STAT_CAM11                  0x0404
+#define MUX_STAT_CAM12                  0x0408
+#define MUX_IGNORE_CAM11                0x0504
+#define DIV_CAM10                       0x0600
+#define DIV_CAM11                       0x0604
+#define DIV_STAT_CAM10                  0x0700
+#define DIV_STAT_CAM11                  0x0704
+#define ENABLE_ACLK_CAM10               0X0800
+#define ENABLE_ACLK_CAM11               0X0804
+#define ENABLE_ACLK_CAM12               0X0808
+#define ENABLE_PCLK_CAM1                0X0900
+#define ENABLE_SCLK_CAM1                0X0a00
+#define ENABLE_IP_CAM10                 0X0b00
+#define ENABLE_IP_CAM11                 0X0b04
+#define ENABLE_IP_CAM12                 0X0b08
+
+static unsigned long cam1_clk_regs[] __initdata = {
+        MUX_SEL_CAM10,
+        MUX_SEL_CAM11,
+        MUX_SEL_CAM12,
+        MUX_ENABLE_CAM10,
+        MUX_ENABLE_CAM11,
+        MUX_ENABLE_CAM12,
+        MUX_STAT_CAM10,
+        MUX_STAT_CAM11,
+        MUX_STAT_CAM12,
+        MUX_IGNORE_CAM11,
+        DIV_CAM10,
+        DIV_CAM11,
+        DIV_STAT_CAM10,
+        DIV_STAT_CAM11,
+        ENABLE_ACLK_CAM10,
+        ENABLE_ACLK_CAM11,
+        ENABLE_ACLK_CAM12,
+        ENABLE_PCLK_CAM1,
+        ENABLE_SCLK_CAM1,
+        ENABLE_IP_CAM10,
+        ENABLE_IP_CAM11,
+        ENABLE_IP_CAM12,
+};
+
+PNAME(mout_sclk_isp_uart_user_p)        = { "oscclk", "sclk_isp_uart_cam1", };
+PNAME(mout_sclk_isp_spi1_user_p)        = { "oscclk", "sclk_isp_spi1_cam1", };
+PNAME(mout_sclk_isp_spi0_user_p)        = { "oscclk", "sclk_isp_spi0_cam1", };
+
+PNAME(mout_aclk_cam1_333_user_p)        = { "oscclk", "aclk_cam1_333", };
+PNAME(mout_aclk_cam1_400_user_p)        = { "oscclk", "aclk_cam1_400", };
+PNAME(mout_aclk_cam1_552_user_p)        = { "oscclk", "aclk_cam1_552", };
+
+PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = { "oscclk",
+                                               "phyclk_rxbyteclkhs0_s2b_phy", };
+
+PNAME(mout_aclk_csis2_b_p)              = { "mout_aclk_csis2_a",
+                                            "mout_aclk_cam1_333_user", };
+PNAME(mout_aclk_csis2_a_p)              = { "mout_aclk_cam1_552_user",
+                                            "mout_aclk_cam1_400_user", };
+
+PNAME(mout_aclk_fd_b_p)                 = { "mout_aclk_fd_a",
+                                            "mout_aclk_cam1_333_user", };
+PNAME(mout_aclk_fd_a_p)                 = { "mout_aclk_cam1_552_user",
+                                            "mout_aclk_cam1_400_user", };
+
+PNAME(mout_aclk_lite_c_b_p)             = { "mout_aclk_lite_c_a",
+                                            "mout_aclk_cam1_333_user", };
+PNAME(mout_aclk_lite_c_a_p)             = { "mout_aclk_cam1_552_user",
+                                            "mout_aclk_cam1_400_user", };
+
+static struct samsung_fixed_rate_clock cam1_fixed_clks[] __initdata = {
+        FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL,
+                        CLK_IS_ROOT, 100000000),
+};
+
+static struct samsung_mux_clock cam1_mux_clks[] __initdata = {
+        /* MUX_SEL_CAM10 */
+        MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user",
+                        mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1),
+        MUX(CLK_MOUT_SCLK_ISP_SPI1_USER, "mout_sclk_isp_spi1_user",
+                        mout_sclk_isp_spi1_user_p, MUX_SEL_CAM10, 16, 1),
+        MUX(CLK_MOUT_SCLK_ISP_SPI0_USER, "mout_sclk_isp_spi0_user",
+                        mout_sclk_isp_spi0_user_p, MUX_SEL_CAM10, 12, 1),
+        MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user",
+                        mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1),
+        MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user",
+                        mout_aclk_cam1_400_user_p, MUX_SEL_CAM01, 4, 1),
+        MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user",
+                        mout_aclk_cam1_552_user_p, MUX_SEL_CAM01, 0, 1),
+
+        /* MUX_SEL_CAM11 */
+        MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER,
+                        "mout_phyclk_rxbyteclkhs0_s2b_user",
+                        mout_phyclk_rxbyteclkhs0_s2b_user_p,
+                        MUX_SEL_CAM11, 0, 1),
+
+        /* MUX_SEL_CAM12 */
+        MUX(CLK_MOUT_ACLK_CSIS2_B, "mout_aclk_csis2_b", mout_aclk_csis2_b_p,
+                        MUX_SEL_CAM12, 20, 1),
+        MUX(CLK_MOUT_ACLK_CSIS2_A, "mout_aclk_csis2_a", mout_aclk_csis2_a_p,
+                        MUX_SEL_CAM12, 16, 1),
+        MUX(CLK_MOUT_ACLK_FD_B, "mout_aclk_fd_b", mout_aclk_fd_b_p,
+                        MUX_SEL_CAM12, 12, 1),
+        MUX(CLK_MOUT_ACLK_FD_A, "mout_aclk_fd_a", mout_aclk_fd_a_p,
+                        MUX_SEL_CAM12, 8, 1),
+        MUX(CLK_MOUT_ACLK_LITE_C_B, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p,
+                        MUX_SEL_CAM12, 4, 1),
+        MUX(CLK_MOUT_ACLK_LITE_C_A, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p,
+                        MUX_SEL_CAM12, 0, 1),
+};
+
+static struct samsung_div_clock cam1_div_clks[] __initdata = {
+        /* DIV_CAM10 */
+        DIV(CLK_DIV_SCLK_ISP_WPWM, "div_sclk_isp_wpwm",
+                        "div_pclk_cam1_83", DIV_CAM10, 16, 2),
+        DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83",
+                        "mout_aclk_cam1_333_user", DIV_CAM10, 12, 2),
+        DIV(CLK_DIV_PCLK_CAM1_166, "div_pclk_cam1_166",
+                        "mout_aclk_cam1_333_user", DIV_CAM10, 8, 2),
+        DIV(CLK_DIV_PCLK_DBG_CAM1, "div_pclk_dbg_cam1",
+                        "mout_aclk_cam1_552_user", DIV_CAM10, 4, 3),
+        DIV(CLK_DIV_ATCLK_CAM1, "div_atclk_cam1", "mout_aclk_cam1_552_user",
+                        DIV_CAM10, 0, 3),
+
+        /* DIV_CAM11 */
+        DIV(CLK_DIV_ACLK_CSIS2, "div_aclk_csis2", "mout_aclk_csis2_b",
+                        DIV_CAM11, 16, 3),
+        DIV(CLK_DIV_PCLK_FD, "div_pclk_fd", "div_aclk_fd", DIV_CAM11, 12, 2),
+        DIV(CLK_DIV_ACLK_FD, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11, 8, 3),
+        DIV(CLK_DIV_PCLK_LITE_C, "div_pclk_lite_c", "div_aclk_lite_c",
+                        DIV_CAM11, 4, 2),
+        DIV(CLK_DIV_ACLK_LITE_C, "div_aclk_lite_c", "mout_aclk_lite_c_b",
+                        DIV_CAM11, 0, 3),
+};
+
+static struct samsung_gate_clock cam1_gate_clks[] __initdata = {
+        /* ENABLE_ACLK_CAM10 */
+        GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user",
+                        ENABLE_ACLK_CAM10, 4, 0, 0),
+        GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd",
+                        ENABLE_ACLK_CAM10, 3, 0, 0),
+        GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c",
+                        ENABLE_ACLK_CAM10, 1, 0, 0),
+        GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2",
+                        ENABLE_ACLK_CAM10, 0, 0, 0),
+
+        /* ENABLE_ACLK_CAM11 */
+        GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd",
+                        ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAPBS_FD, "aclk_asyncapbs_fd", "div_pclk_cam1_166",
+                        ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAPBM_LITE_C, "aclk_asyncapbm_lite_c",
+                        "div_pclk_lite_c", ENABLE_ACLK_CAM11,
+                        27, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAPBS_LITE_C, "aclk_asyncapbs_lite_c",
+                        "div_pclk_cam1_166", ENABLE_ACLK_CAM11,
+                        26, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2, "aclk_asyncahbs_sfrisp2h2",
+                        "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
+                        25, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1, "aclk_asyncahbs_sfrisp2h1",
+                        "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
+                        24, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_CA5, "aclk_asyncaxim_ca5",
+                        "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
+                        23, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_CA5, "aclk_asyncaxis_ca5",
+                        "mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11,
+                        22, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_ISPX2, "aclk_asyncaxis_ispx2",
+                        "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
+                        21, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_ISPX1, "aclk_asyncaxis_ispx1",
+                        "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
+                        20, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_ISPX0, "aclk_asyncaxis_ispx0",
+                        "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
+                        19, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_ISPEX, "aclk_asyncaxim_ispex",
+                        "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
+                        18, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_ISP3P, "aclk_asyncaxim_isp3p",
+                        "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
+                        17, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_ISP3P, "aclk_asyncaxis_isp3p",
+                        "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
+                        16, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_FD, "aclk_asyncaxim_fd",
+                        "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
+                        15, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_FD, "aclk_asyncaxis_fd", "div_aclk_fd",
+                        ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_LITE_C, "aclk_asyncaxim_lite_c",
+                        "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
+                        13, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_LITE_C, "aclk_asyncaxis_lite_c",
+                        "div_aclk_lite_c", ENABLE_ACLK_CAM11,
+                        12, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB2APB_ISP5P, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83",
+                        ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB2APB_ISP3P, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83",
+                        ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXI2APB_ISP3P, "aclk_axi2apb_isp3p",
+                        "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
+                        9, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB_SFRISP2H, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83",
+                        ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXI_ISP_HX_R, "aclk_axi_isp_hx_r", "div_pclk_cam1_166",
+                        ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXI_ISP_CX_R, "aclk_axi_isp_cx_r", "div_pclk_cam1_166",
+                        ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXI_ISP_HX, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user",
+                        ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXI_ISP_CX, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user",
+                        ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_XIU_ISPX, "aclk_xiu_ispx", "mout_aclk_cam1_333_user",
+                        ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_XIU_ISPEX, "aclk_xiu_ispex", "mout_aclk_cam1_400_user",
+                        ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_CAM1NP_333, "aclk_cam1np_333", "mout_aclk_cam1_333_user",
+                        ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_CAM1ND_400, "aclk_cam1nd_400", "mout_aclk_cam1_400_user",
+                        ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_ACLK_CAM12 */
+        GATE(CLK_ACLK_SMMU_ISPCPU, "aclk_smmu_ispcpu",
+                        "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
+                        10, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SMMU_FD, "aclk_smmu_fd", "mout_aclk_cam1_400_user",
+                        ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SMMU_LITE_C, "aclk_smmu_lite_c",
+                        "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
+                        8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_ISP3P, "aclk_bts_isp3p", "mout_aclk_cam1_400_user",
+                        ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_FD, "aclk_bts_fd", "mout_aclk_cam1_400_user",
+                        ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_LITE_C, "aclk_bts_lite_c", "mout_aclk_cam1_400_user",
+                        ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHBDN_SFRISP2H, "aclk_ahbdn_sfrisp2h",
+                        "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
+                        4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHBDN_ISP5P, "aclk_aclk-shbdn_isp5p",
+                        "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
+                        3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXIUS_ISP3P, "aclk_axius_isp3p",
+                        "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
+                        2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXIUS_FD, "aclk_axius_fd", "mout_aclk_cam1_400_user",
+                        ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXIUS_LITE_C, "aclk_axius_lite_c",
+                        "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
+                        0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_PCLK_CAM1 */
+        GATE(CLK_PCLK_SMMU_ISPCPU, "pclk_smmu_ispcpu", "div_pclk_cam1_166",
+                        ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SMMU_FD, "pclk_smmu_fd", "div_pclk_cam1_166",
+                        ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SMMU_LITE_C, "pclk_smmu_lite_c", "div_pclk_cam1_166",
+                        ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_ISP3P, "pclk_bts_isp3p", "div_pclk_cam1_83",
+                        ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_FD, "pclk_bts_fd", "div_pclk_cam1_83",
+                        ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_LITE_C, "pclk_bts_lite_c", "div_pclk_cam1_83",
+                        ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ASYNCAXIM_CA5, "pclk_asyncaxim_ca5", "div_pclk_cam1_166",
+                        ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ASYNCAXIM_ISPEX, "pclk_asyncaxim_ispex",
+                        "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
+                        20, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ASYNCAXIM_ISP3P, "pclk_asyncaxim_isp3p",
+                        "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
+                        19, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ASYNCAXIM_FD, "pclk_asyncaxim_fd", "div_pclk_cam1_83",
+                        ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ASYNCAXIM_LITE_C, "pclk_asyncaxim_lite_c",
+                        "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
+                        17, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_PMU_CAM1, "pclk_pmu_cam1", "div_pclk_cam1_83",
+                        ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SYSREG_CAM1, "pclk_sysreg_cam1", "div_pclk_cam1_83",
+                        ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_CMU_CAM1_LOCAL, "pclk_cmu_cam1_local",
+                        "div_pclk_cam1_166", ENABLE_PCLK_CAM1,
+                        14, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ISP_MCTADC, "pclk_isp_mctadc", "div_pclk_cam1_83",
+                        ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ISP_WDT, "pclk_isp_wdt", "div_pclk_cam1_83",
+                        ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ISP_PWM, "pclk_isp_pwm", "div_pclk_cam1_83",
+                        ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ISP_UART, "pclk_isp_uart", "div_pclk_cam1_83",
+                        ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ISP_MCUCTL, "pclk_isp_mcuctl", "div_pclk_cam1_83",
+                        ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ISP_SPI1, "pclk_isp_spi1", "div_pclk_cam1_83",
+                        ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ISP_SPI0, "pclk_isp_spi0", "div_pclk_cam1_83",
+                        ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ISP_I2C2, "pclk_isp_i2c2", "div_pclk_cam1_83",
+                        ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ISP_I2C1, "pclk_isp_i2c1", "div_pclk_cam1_83",
+                        ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83",
+                        ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_wpwm", "div_pclk_cam1_83",
+                        ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd",
+                        ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_LITE_C, "pclk_lite_c", "div_pclk_lite_c",
+                        ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_CSIS2, "pclk_csis2", "div_pclk_cam1_166",
+                        ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0),
+
+        /* ENABLE_SCLK_CAM1 */
+        GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1,
+                        15, 0, 0),
+        GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1,
+                        14, 0, 0),
+        GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1,
+                        13, 0, 0),
+        GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1,
+                        12, 0, 0),
+        GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b",
+                        "mout_phyclk_rxbyteclkhs0_s2b_user",
+                        ENABLE_SCLK_CAM1, 11, 0, 0),
+        GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c",
+                        ENABLE_SCLK_CAM1, 10, 0, 0),
+        GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd",
+                        ENABLE_SCLK_CAM1, 9, 0, 0),
+        GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1",
+                        ENABLE_SCLK_CAM1, 7, 0, 0),
+        GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user",
+                        ENABLE_SCLK_CAM1, 6, 0, 0),
+        GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user",
+                        ENABLE_SCLK_CAM1, 5, 0, 0),
+        GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user",
+                        ENABLE_SCLK_CAM1, 4, 0, 0),
+        GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_wpwm", "div_sclk_isp_wpwm",
+                        ENABLE_SCLK_CAM1, 3, 0, 0),
+        GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1",
+                        ENABLE_SCLK_CAM1, 2, 0, 0),
+        GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1",
+                        ENABLE_SCLK_CAM1, 1, 0, 0),
+        GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user",
+                        ENABLE_SCLK_CAM1, 0, 0, 0),
+};
+
+static struct samsung_cmu_info cam1_cmu_info __initdata = {
+        .mux_clks               = cam1_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(cam1_mux_clks),
+        .div_clks               = cam1_div_clks,
+        .nr_div_clks            = ARRAY_SIZE(cam1_div_clks),
+        .gate_clks              = cam1_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(cam1_gate_clks),
+        .fixed_clks             = cam1_fixed_clks,
+        .nr_fixed_clks          = ARRAY_SIZE(cam1_fixed_clks),
+        .nr_clk_ids             = CAM1_NR_CLK,
+        .clk_regs               = cam1_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(cam1_clk_regs),
+};
+
+static void __init exynos5433_cmu_cam1_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &cam1_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_cam1, "samsung,exynos5433-cmu-cam1",
+                exynos5433_cmu_cam1_init);
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
index 72d97279eae1..49baf3831546 100644
--- a/drivers/clk/ti/apll.c
+++ b/drivers/clk/ti/apll.c
@@ -203,7 +203,7 @@ static void __init of_dra7_apll_setup(struct device_node *node)
         ad->control_reg = ti_clk_get_reg_addr(node, 0);
         ad->idlest_reg = ti_clk_get_reg_addr(node, 1);
 
-        if (!ad->control_reg || !ad->idlest_reg)
+        if (IS_ERR(ad->control_reg) || IS_ERR(ad->idlest_reg))
                 goto cleanup;
 
         ad->idlest_mask = 0x1;
@@ -384,7 +384,8 @@ static void __init of_omap2_apll_setup(struct device_node *node)
         ad->autoidle_reg = ti_clk_get_reg_addr(node, 1);
         ad->idlest_reg = ti_clk_get_reg_addr(node, 2);
 
-        if (!ad->control_reg || !ad->autoidle_reg || !ad->idlest_reg)
+        if (IS_ERR(ad->control_reg) || IS_ERR(ad->autoidle_reg) ||
+            IS_ERR(ad->idlest_reg))
                 goto cleanup;
 
         clk = clk_register(NULL, &clk_hw->hw);
diff --git a/drivers/clk/ti/autoidle.c b/drivers/clk/ti/autoidle.c
index 8912ff80af34..e75c64c9e81c 100644
--- a/drivers/clk/ti/autoidle.c
+++ b/drivers/clk/ti/autoidle.c
@@ -119,7 +119,7 @@ int __init of_ti_clk_autoidle_setup(struct device_node *node)
         clk->name = node->name;
         clk->reg = ti_clk_get_reg_addr(node, 0);
 
-        if (!clk->reg) {
+        if (IS_ERR(clk->reg)) {
                 kfree(clk);
                 return -EINVAL;
         }
diff --git a/drivers/clk/ti/clk-3xxx-legacy.c b/drivers/clk/ti/clk-3xxx-legacy.c
index e0732a4c8f26..0b61548d569b 100644
--- a/drivers/clk/ti/clk-3xxx-legacy.c
+++ b/drivers/clk/ti/clk-3xxx-legacy.c
@@ -4320,7 +4320,6 @@ static struct ti_clk_alias omap3xxx_clks[] = {
         CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck),
         CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck),
         CLK(NULL, "sys_altclk", &sys_altclk),
-        CLK(NULL, "mcbsp_clks", &mcbsp_clks),
         CLK(NULL, "sys_clkout1", &sys_clkout1),
         CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck),
         CLK(NULL, "core_ck", &core_ck),
@@ -4369,8 +4368,6 @@ static struct ti_clk_alias omap3xxx_clks[] = {
         CLK(NULL, "i2c3_fck", &i2c3_fck),
         CLK(NULL, "i2c2_fck", &i2c2_fck),
         CLK(NULL, "i2c1_fck", &i2c1_fck),
-        CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
-        CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
         CLK(NULL, "core_48m_fck", &core_48m_fck),
         CLK(NULL, "mcspi4_fck", &mcspi4_fck),
         CLK(NULL, "mcspi3_fck", &mcspi3_fck),
@@ -4409,8 +4406,6 @@ static struct ti_clk_alias omap3xxx_clks[] = {
         CLK(NULL, "uart1_ick", &uart1_ick),
         CLK(NULL, "gpt11_ick", &gpt11_ick),
         CLK(NULL, "gpt10_ick", &gpt10_ick),
-        CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
-        CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
         CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
         CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
         CLK(NULL, "omapctrl_ick", &omapctrl_ick),
@@ -4467,15 +4462,22 @@ static struct ti_clk_alias omap3xxx_clks[] = {
         CLK(NULL, "gpt4_ick", &gpt4_ick),
         CLK(NULL, "gpt3_ick", &gpt3_ick),
         CLK(NULL, "gpt2_ick", &gpt2_ick),
+        CLK(NULL, "mcbsp_clks", &mcbsp_clks),
+        CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
         CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
         CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
         CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
-        CLK(NULL, "mcbsp4_ick", &mcbsp2_ick),
+        CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
+        CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
+        CLK(NULL, "mcbsp2_ick", &mcbsp2_ick),
         CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
-        CLK(NULL, "mcbsp2_ick", &mcbsp4_ick),
+        CLK(NULL, "mcbsp4_ick", &mcbsp4_ick),
+        CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
+        CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
         CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
         CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
         CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
+        CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
         CLK(NULL, "emu_src_mux_ck", &emu_src_mux_ck),
         CLK("etb", "emu_src_ck", &emu_src_ck),
         CLK(NULL, "emu_src_mux_ck", &emu_src_mux_ck),
diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c
index 383a06e49b09..757636d166cf 100644
--- a/drivers/clk/ti/clk-3xxx.c
+++ b/drivers/clk/ti/clk-3xxx.c
@@ -34,7 +34,6 @@ static struct ti_dt_clk omap3xxx_clks[] = {
         DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"),
         DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"),
         DT_CLK(NULL, "sys_altclk", "sys_altclk"),
-        DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
         DT_CLK(NULL, "sys_clkout1", "sys_clkout1"),
         DT_CLK(NULL, "dpll1_ck", "dpll1_ck"),
         DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"),
@@ -82,8 +81,6 @@ static struct ti_dt_clk omap3xxx_clks[] = {
         DT_CLK(NULL, "i2c3_fck", "i2c3_fck"),
         DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
         DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
-        DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
-        DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
         DT_CLK(NULL, "core_48m_fck", "core_48m_fck"),
         DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"),
         DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
@@ -122,10 +119,6 @@ static struct ti_dt_clk omap3xxx_clks[] = {
         DT_CLK(NULL, "uart1_ick", "uart1_ick"),
         DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
         DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
-        DT_CLK("omap-mcbsp.5", "ick", "mcbsp5_ick"),
-        DT_CLK("omap-mcbsp.1", "ick", "mcbsp1_ick"),
-        DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
-        DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
         DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
         DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"),
         DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"),
@@ -179,15 +172,17 @@ static struct ti_dt_clk omap3xxx_clks[] = {
         DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
         DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
         DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
-        DT_CLK("omap-mcbsp.2", "ick", "mcbsp2_ick"),
-        DT_CLK("omap-mcbsp.3", "ick", "mcbsp3_ick"),
-        DT_CLK("omap-mcbsp.4", "ick", "mcbsp4_ick"),
-        DT_CLK(NULL, "mcbsp4_ick", "mcbsp2_ick"),
+        DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
+        DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
+        DT_CLK(NULL, "mcbsp2_ick", "mcbsp2_ick"),
         DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
-        DT_CLK(NULL, "mcbsp2_ick", "mcbsp4_ick"),
+        DT_CLK(NULL, "mcbsp4_ick", "mcbsp4_ick"),
+        DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
+        DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
         DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
         DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
         DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
+        DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
         DT_CLK("etb", "emu_src_ck", "emu_src_ck"),
         DT_CLK(NULL, "emu_src_ck", "emu_src_ck"),
         DT_CLK(NULL, "pclk_fck", "pclk_fck"),
diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
index 4f4c87751db5..581db7711f51 100644
--- a/drivers/clk/ti/clk-44xx.c
+++ b/drivers/clk/ti/clk-44xx.c
@@ -249,17 +249,6 @@ static struct ti_dt_clk omap44xx_clks[] = {
         DT_CLK("usbhs_tll", "usbtll_fck", "dummy_ck"),
         DT_CLK("omap_wdt", "ick", "dummy_ck"),
         DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
-        DT_CLK("omap_timer.1", "timer_sys_ck", "sys_clkin_ck"),
-        DT_CLK("omap_timer.2", "timer_sys_ck", "sys_clkin_ck"),
-        DT_CLK("omap_timer.3", "timer_sys_ck", "sys_clkin_ck"),
-        DT_CLK("omap_timer.4", "timer_sys_ck", "sys_clkin_ck"),
-        DT_CLK("omap_timer.9", "timer_sys_ck", "sys_clkin_ck"),
-        DT_CLK("omap_timer.10", "timer_sys_ck", "sys_clkin_ck"),
-        DT_CLK("omap_timer.11", "timer_sys_ck", "sys_clkin_ck"),
-        DT_CLK("omap_timer.5", "timer_sys_ck", "syc_clk_div_ck"),
-        DT_CLK("omap_timer.6", "timer_sys_ck", "syc_clk_div_ck"),
-        DT_CLK("omap_timer.7", "timer_sys_ck", "syc_clk_div_ck"),
-        DT_CLK("omap_timer.8", "timer_sys_ck", "syc_clk_div_ck"),
         DT_CLK("4a318000.timer", "timer_sys_ck", "sys_clkin_ck"),
         DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin_ck"),
         DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin_ck"),
diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
index 14160b223548..96c69a335975 100644
--- a/drivers/clk/ti/clk-54xx.c
+++ b/drivers/clk/ti/clk-54xx.c
@@ -208,17 +208,17 @@ static struct ti_dt_clk omap54xx_clks[] = {
         DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
         DT_CLK("omap_wdt", "ick", "dummy_ck"),
         DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
-        DT_CLK("omap_timer.1", "sys_ck", "sys_clkin"),
-        DT_CLK("omap_timer.2", "sys_ck", "sys_clkin"),
-        DT_CLK("omap_timer.3", "sys_ck", "sys_clkin"),
-        DT_CLK("omap_timer.4", "sys_ck", "sys_clkin"),
-        DT_CLK("omap_timer.9", "sys_ck", "sys_clkin"),
-        DT_CLK("omap_timer.10", "sys_ck", "sys_clkin"),
-        DT_CLK("omap_timer.11", "sys_ck", "sys_clkin"),
-        DT_CLK("omap_timer.5", "sys_ck", "dss_syc_gfclk_div"),
-        DT_CLK("omap_timer.6", "sys_ck", "dss_syc_gfclk_div"),
-        DT_CLK("omap_timer.7", "sys_ck", "dss_syc_gfclk_div"),
-        DT_CLK("omap_timer.8", "sys_ck", "dss_syc_gfclk_div"),
+        DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin"),
+        DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin"),
+        DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin"),
+        DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin"),
+        DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin"),
+        DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin"),
+        DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin"),
+        DT_CLK("40138000.timer", "timer_sys_ck", "dss_syc_gfclk_div"),
+        DT_CLK("4013a000.timer", "timer_sys_ck", "dss_syc_gfclk_div"),
+        DT_CLK("4013c000.timer", "timer_sys_ck", "dss_syc_gfclk_div"),
+        DT_CLK("4013e000.timer", "timer_sys_ck", "dss_syc_gfclk_div"),
         { .node_name = NULL },
 };
 
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index ee32f4deebf4..5d2217ae4478 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -289,17 +289,21 @@ static struct ti_dt_clk dra7xx_clks[] = {
         DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
         DT_CLK("omap_wdt", "ick", "dummy_ck"),
         DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
-        DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin2"),
-        DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin2"),
-        DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin2"),
-        DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin2"),
-        DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin2"),
-        DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin2"),
-        DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin2"),
+        DT_CLK("4ae18000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+        DT_CLK("48032000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+        DT_CLK("48034000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+        DT_CLK("48036000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+        DT_CLK("4803e000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+        DT_CLK("48086000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+        DT_CLK("48088000.timer", "timer_sys_ck", "timer_sys_clk_div"),
         DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"),
         DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"),
         DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"),
         DT_CLK("48826000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+        DT_CLK("48828000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+        DT_CLK("4882a000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+        DT_CLK("4882c000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+        DT_CLK("4882e000.timer", "timer_sys_ck", "timer_sys_clk_div"),
         DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
         { .node_name = NULL },
 };
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index e22b95646e09..0ebe5c51062b 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -103,7 +103,8 @@ int __init ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
  * @index: register index from the clock node
  *
  * Builds clock register address from device tree information. This
- * is a struct of type clk_omap_reg.
+ * is a struct of type clk_omap_reg. Returns a pointer to the register
+ * address, or a pointer error value in failure.
  */
 void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index)
 {
@@ -121,14 +122,14 @@ void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index)
 
         if (i == CLK_MAX_MEMMAPS) {
                 pr_err("clk-provider not found for %s!\n", node->name);
-                return NULL;
+                return ERR_PTR(-ENOENT);
         }
 
         reg->index = i;
 
         if (of_property_read_u32_index(node, "reg", index, &val)) {
                 pr_err("%s must have reg[%d]!\n", node->name, index);
-                return NULL;
+                return ERR_PTR(-EINVAL);
         }
 
         reg->offset = val;
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
index 6211893c0980..ff5f117950a9 100644
--- a/drivers/clk/ti/divider.c
+++ b/drivers/clk/ti/divider.c
@@ -530,8 +530,8 @@ static int __init ti_clk_divider_populate(struct device_node *node,
         u32 val;
 
         *reg = ti_clk_get_reg_addr(node, 0);
-        if (!*reg)
-                return -EINVAL;
+        if (IS_ERR(*reg))
+                return PTR_ERR(*reg);
 
         if (!of_property_read_u32(node, "ti,bit-shift", &val))
                 *shift = val;
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index 81dc4698dc41..11478a501c30 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -390,18 +390,18 @@ static void __init of_ti_dpll_setup(struct device_node *node,
 #endif
         } else {
                 dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
-                if (!dd->idlest_reg)
+                if (IS_ERR(dd->idlest_reg))
                         goto cleanup;
 
                 dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
         }
 
-        if (!dd->control_reg || !dd->mult_div1_reg)
+        if (IS_ERR(dd->control_reg) || IS_ERR(dd->mult_div1_reg))
                 goto cleanup;
 
         if (dd->autoidle_mask) {
                 dd->autoidle_reg = ti_clk_get_reg_addr(node, 3);
-                if (!dd->autoidle_reg)
+                if (IS_ERR(dd->autoidle_reg))
                         goto cleanup;
         }
 
diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c
index 6ef89639a9f6..ffcd8e09e85b 100644
--- a/drivers/clk/ti/fapll.c
+++ b/drivers/clk/ti/fapll.c
@@ -11,19 +11,27 @@
 
 #include <linux/clk-provider.h>
 #include <linux/delay.h>
-#include <linux/slab.h>
 #include <linux/err.h>
+#include <linux/math64.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/clk/ti.h>
-#include <asm/div64.h>
 
 /* FAPLL Control Register PLL_CTRL */
+#define FAPLL_MAIN_MULT_N_SHIFT 16
+#define FAPLL_MAIN_DIV_P_SHIFT  8
 #define FAPLL_MAIN_LOCK         BIT(7)
 #define FAPLL_MAIN_PLLEN        BIT(3)
 #define FAPLL_MAIN_BP           BIT(2)
 #define FAPLL_MAIN_LOC_CTL      BIT(0)
 
+#define FAPLL_MAIN_MAX_MULT_N   0xffff
+#define FAPLL_MAIN_MAX_DIV_P    0xff
+#define FAPLL_MAIN_CLEAR_MASK   \
+        ((FAPLL_MAIN_MAX_MULT_N << FAPLL_MAIN_MULT_N_SHIFT) | \
+         (FAPLL_MAIN_DIV_P_SHIFT << FAPLL_MAIN_DIV_P_SHIFT) | \
+         FAPLL_MAIN_LOC_CTL)
+
 /* FAPLL powerdown register PWD */
 #define FAPLL_PWD_OFFSET        4
 
@@ -49,6 +57,10 @@
 /* Synthesizer frequency register */
 #define SYNTH_LDFREQ            BIT(31)
 
+#define SYNTH_PHASE_K           8
+#define SYNTH_MAX_INT_DIV       0xf
+#define SYNTH_MAX_DIV_M         0xff
+
 struct fapll_data {
         struct clk_hw hw;
         void __iomem *base;
@@ -79,13 +91,56 @@ static bool ti_fapll_clock_is_bypass(struct fapll_data *fd)
                 return !!(v & FAPLL_MAIN_BP);
 }
 
+static void ti_fapll_set_bypass(struct fapll_data *fd)
+{
+        u32 v = readl_relaxed(fd->base);
+
+        if (fd->bypass_bit_inverted)
+                v &= ~FAPLL_MAIN_BP;
+        else
+                v |= FAPLL_MAIN_BP;
+        writel_relaxed(v, fd->base);
+}
+
+static void ti_fapll_clear_bypass(struct fapll_data *fd)
+{
+        u32 v = readl_relaxed(fd->base);
+
+        if (fd->bypass_bit_inverted)
+                v |= FAPLL_MAIN_BP;
+        else
+                v &= ~FAPLL_MAIN_BP;
+        writel_relaxed(v, fd->base);
+}
+
+static int ti_fapll_wait_lock(struct fapll_data *fd)
+{
+        int retries = FAPLL_MAX_RETRIES;
+        u32 v;
+
+        while ((v = readl_relaxed(fd->base))) {
+                if (v & FAPLL_MAIN_LOCK)
+                        return 0;
+
+                if (retries-- <= 0)
+                        break;
+
+                udelay(1);
+        }
+
+        pr_err("%s failed to lock\n", fd->name);
+
+        return -ETIMEDOUT;
+}
+
 static int ti_fapll_enable(struct clk_hw *hw)
 {
         struct fapll_data *fd = to_fapll(hw);
         u32 v = readl_relaxed(fd->base);
 
-        v |= (1 << FAPLL_MAIN_PLLEN);
+        v |= FAPLL_MAIN_PLLEN;
         writel_relaxed(v, fd->base);
+        ti_fapll_wait_lock(fd);
 
         return 0;
 }
@@ -95,7 +150,7 @@ static void ti_fapll_disable(struct clk_hw *hw)
         struct fapll_data *fd = to_fapll(hw);
         u32 v = readl_relaxed(fd->base);
 
-        v &= ~(1 << FAPLL_MAIN_PLLEN);
+        v &= ~FAPLL_MAIN_PLLEN;
         writel_relaxed(v, fd->base);
 }
 
@@ -104,7 +159,7 @@ static int ti_fapll_is_enabled(struct clk_hw *hw)
         struct fapll_data *fd = to_fapll(hw);
         u32 v = readl_relaxed(fd->base);
 
-        return v & (1 << FAPLL_MAIN_PLLEN);
+        return v & FAPLL_MAIN_PLLEN;
 }
 
 static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw,
@@ -141,12 +196,85 @@ static u8 ti_fapll_get_parent(struct clk_hw *hw)
         return 0;
 }
 
+static int ti_fapll_set_div_mult(unsigned long rate,
+                                 unsigned long parent_rate,
+                                 u32 *pre_div_p, u32 *mult_n)
+{
+        /*
+         * So far no luck getting decent clock with PLL divider,
+         * PLL does not seem to lock and the signal does not look
+         * right. It seems the divider can only be used together
+         * with the multiplier?
+         */
+        if (rate < parent_rate) {
+                pr_warn("FAPLL main divider rates unsupported\n");
+                return -EINVAL;
+        }
+
+        *mult_n = rate / parent_rate;
+        if (*mult_n > FAPLL_MAIN_MAX_MULT_N)
+                return -EINVAL;
+        *pre_div_p = 1;
+
+        return 0;
+}
+
+static long ti_fapll_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *parent_rate)
+{
+        u32 pre_div_p, mult_n;
+        int error;
+
+        if (!rate)
+                return -EINVAL;
+
+        error = ti_fapll_set_div_mult(rate, *parent_rate,
+                                      &pre_div_p, &mult_n);
+        if (error)
+                return error;
+
+        rate = *parent_rate / pre_div_p;
+        rate *= mult_n;
+
+        return rate;
+}
+
+static int ti_fapll_set_rate(struct clk_hw *hw, unsigned long rate,
+                             unsigned long parent_rate)
+{
+        struct fapll_data *fd = to_fapll(hw);
+        u32 pre_div_p, mult_n, v;
+        int error;
+
+        if (!rate)
+                return -EINVAL;
+
+        error = ti_fapll_set_div_mult(rate, parent_rate,
+                                      &pre_div_p, &mult_n);
+        if (error)
+                return error;
+
+        ti_fapll_set_bypass(fd);
+        v = readl_relaxed(fd->base);
+        v &= ~FAPLL_MAIN_CLEAR_MASK;
+        v |= pre_div_p << FAPLL_MAIN_DIV_P_SHIFT;
+        v |= mult_n << FAPLL_MAIN_MULT_N_SHIFT;
+        writel_relaxed(v, fd->base);
+        if (ti_fapll_is_enabled(hw))
+                ti_fapll_wait_lock(fd);
+        ti_fapll_clear_bypass(fd);
+
+        return 0;
+}
+
 static struct clk_ops ti_fapll_ops = {
         .enable = ti_fapll_enable,
         .disable = ti_fapll_disable,
         .is_enabled = ti_fapll_is_enabled,
         .recalc_rate = ti_fapll_recalc_rate,
         .get_parent = ti_fapll_get_parent,
+        .round_rate = ti_fapll_round_rate,
+        .set_rate = ti_fapll_set_rate,
 };
 
 static int ti_fapll_synth_enable(struct clk_hw *hw)
@@ -204,7 +332,7 @@ static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw,
         /*
          * Synth frequency integer and fractional divider.
          * Note that the phase output K is 8, so the result needs
-         * to be multiplied by 8.
+         * to be multiplied by SYNTH_PHASE_K.
          */
         if (synth->freq) {
                 u32 v, synth_int_div, synth_frac_div, synth_div_freq;
@@ -215,14 +343,138 @@ static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw,
                 synth_div_freq = (synth_int_div * 10000000) + synth_frac_div;
                 rate *= 10000000;
                 do_div(rate, synth_div_freq);
-                rate *= 8;
+                rate *= SYNTH_PHASE_K;
         }
 
-        /* Synth ost-divider M */
-        synth_div_m = readl_relaxed(synth->div) & 0xff;
-        do_div(rate, synth_div_m);
+        /* Synth post-divider M */
+        synth_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
 
-        return rate;
+        return DIV_ROUND_UP_ULL(rate, synth_div_m);
+}
+
+static unsigned long ti_fapll_synth_get_frac_rate(struct clk_hw *hw,
+                                                  unsigned long parent_rate)
+{
+        struct fapll_synth *synth = to_synth(hw);
+        unsigned long current_rate, frac_rate;
+        u32 post_div_m;
+
+        current_rate = ti_fapll_synth_recalc_rate(hw, parent_rate);
+        post_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
+        frac_rate = current_rate * post_div_m;
+
+        return frac_rate;
+}
+
+static u32 ti_fapll_synth_set_frac_rate(struct fapll_synth *synth,
+                                        unsigned long rate,
+                                        unsigned long parent_rate)
+{
+        u32 post_div_m, synth_int_div = 0, synth_frac_div = 0, v;
+
+        post_div_m = DIV_ROUND_UP_ULL((u64)parent_rate * SYNTH_PHASE_K, rate);
+        post_div_m = post_div_m / SYNTH_MAX_INT_DIV;
+        if (post_div_m > SYNTH_MAX_DIV_M)
+                return -EINVAL;
+        if (!post_div_m)
+                post_div_m = 1;
+
+        for (; post_div_m < SYNTH_MAX_DIV_M; post_div_m++) {
+                synth_int_div = DIV_ROUND_UP_ULL((u64)parent_rate *
+                                                 SYNTH_PHASE_K *
+                                                 10000000,
+                                                 rate * post_div_m);
+                synth_frac_div = synth_int_div % 10000000;
+                synth_int_div /= 10000000;
+
+                if (synth_int_div <= SYNTH_MAX_INT_DIV)
+                        break;
+        }
+
+        if (synth_int_div > SYNTH_MAX_INT_DIV)
+                return -EINVAL;
+
+        v = readl_relaxed(synth->freq);
+        v &= ~0x1fffffff;
+        v |= (synth_int_div & SYNTH_MAX_INT_DIV) << 24;
+        v |= (synth_frac_div & 0xffffff);
+        v |= SYNTH_LDFREQ;
+        writel_relaxed(v, synth->freq);
+
+        return post_div_m;
+}
+
+static long ti_fapll_synth_round_rate(struct clk_hw *hw, unsigned long rate,
+                                      unsigned long *parent_rate)
+{
+        struct fapll_synth *synth = to_synth(hw);
+        struct fapll_data *fd = synth->fd;
+        unsigned long r;
+
+        if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
+                return -EINVAL;
+
+        /* Only post divider m available with no fractional divider? */
+        if (!synth->freq) {
+                unsigned long frac_rate;
+                u32 synth_post_div_m;
+
+                frac_rate = ti_fapll_synth_get_frac_rate(hw, *parent_rate);
+                synth_post_div_m = DIV_ROUND_UP(frac_rate, rate);
+                r = DIV_ROUND_UP(frac_rate, synth_post_div_m);
+                goto out;
+        }
+
+        r = *parent_rate * SYNTH_PHASE_K;
+        if (rate > r)
+                goto out;
+
+        r = DIV_ROUND_UP_ULL(r, SYNTH_MAX_INT_DIV * SYNTH_MAX_DIV_M);
+        if (rate < r)
+                goto out;
+
+        r = rate;
+out:
+        return r;
+}
+
+static int ti_fapll_synth_set_rate(struct clk_hw *hw, unsigned long rate,
+                                   unsigned long parent_rate)
+{
+        struct fapll_synth *synth = to_synth(hw);
+        struct fapll_data *fd = synth->fd;
+        unsigned long frac_rate, post_rate = 0;
+        u32 post_div_m = 0, v;
+
+        if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
+                return -EINVAL;
+
+        /* Produce the rate with just post divider M? */
+        frac_rate = ti_fapll_synth_get_frac_rate(hw, parent_rate);
+        if (frac_rate < rate) {
+                if (!synth->freq)
+                        return -EINVAL;
+        } else {
+                post_div_m = DIV_ROUND_UP(frac_rate, rate);
+                if (post_div_m && (post_div_m <= SYNTH_MAX_DIV_M))
+                        post_rate = DIV_ROUND_UP(frac_rate, post_div_m);
+                if (!synth->freq && !post_rate)
+                        return -EINVAL;
+        }
+
+        /* Need to recalculate the fractional divider? */
+        if ((post_rate != rate) && synth->freq)
+                post_div_m = ti_fapll_synth_set_frac_rate(synth,
+                                                          rate,
+                                                          parent_rate);
+
+        v = readl_relaxed(synth->div);
+        v &= ~SYNTH_MAX_DIV_M;
+        v |= post_div_m;
+        v |= SYNTH_LDMDIV1;
+        writel_relaxed(v, synth->div);
+
+        return 0;
 }
 
 static struct clk_ops ti_fapll_synt_ops = {
@@ -230,6 +482,8 @@ static struct clk_ops ti_fapll_synt_ops = {
         .disable = ti_fapll_synth_disable,
         .is_enabled = ti_fapll_synth_is_enabled,
         .recalc_rate = ti_fapll_synth_recalc_rate,
+        .round_rate = ti_fapll_synth_round_rate,
+        .set_rate = ti_fapll_synth_set_rate,
 };
 
 static struct clk * __init ti_fapll_synth_setup(struct fapll_data *fd,
diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c
index d493307b73f4..0c6fdfcd5f93 100644
--- a/drivers/clk/ti/gate.c
+++ b/drivers/clk/ti/gate.c
@@ -225,7 +225,7 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node,
 
         if (ops != &omap_gate_clkdm_clk_ops) {
                 reg = ti_clk_get_reg_addr(node, 0);
-                if (!reg)
+                if (IS_ERR(reg))
                         return;
 
                 if (!of_property_read_u32(node, "ti,bit-shift", &val))
@@ -264,7 +264,7 @@ _of_ti_composite_gate_clk_setup(struct device_node *node,
                 return;
 
         gate->enable_reg = ti_clk_get_reg_addr(node, 0);
-        if (!gate->enable_reg)
+        if (IS_ERR(gate->enable_reg))
                 goto cleanup;
 
         of_property_read_u32(node, "ti,bit-shift", &val);
diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c
index 265d91f071c5..c76230d8dd04 100644
--- a/drivers/clk/ti/interface.c
+++ b/drivers/clk/ti/interface.c
@@ -111,7 +111,7 @@ static void __init _of_ti_interface_clk_setup(struct device_node *node,
         u32 val;
 
         reg = ti_clk_get_reg_addr(node, 0);
-        if (!reg)
+        if (IS_ERR(reg))
                 return;
 
         if (!of_property_read_u32(node, "ti,bit-shift", &val))
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
index 728e253606bc..5cdeed538b08 100644
--- a/drivers/clk/ti/mux.c
+++ b/drivers/clk/ti/mux.c
@@ -210,7 +210,7 @@ static void of_mux_clk_setup(struct device_node *node)
 
         reg = ti_clk_get_reg_addr(node, 0);
 
-        if (!reg)
+        if (IS_ERR(reg))
                 goto cleanup;
 
         of_property_read_u32(node, "ti,bit-shift", &shift);
@@ -283,7 +283,7 @@ static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
 
         mux->reg = ti_clk_get_reg_addr(node, 0);
 
-        if (!mux->reg)
+        if (IS_ERR(mux->reg))
                 goto cleanup;
 
         if (!of_property_read_u32(node, "ti,bit-shift", &val))
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
new file mode 100644
index 000000000000..5bd80d5ecd0f
--- /dev/null
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -0,0 +1,1403 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Chanwoo Choi <cw00.choi@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H
+#define _DT_BINDINGS_CLOCK_EXYNOS5433_H
+
+/* CMU_TOP */
+#define CLK_FOUT_ISP_PLL                1
+#define CLK_FOUT_AUD_PLL                2
+
+#define CLK_MOUT_AUD_PLL                10
+#define CLK_MOUT_ISP_PLL                11
+#define CLK_MOUT_AUD_PLL_USER_T         12
+#define CLK_MOUT_MPHY_PLL_USER          13
+#define CLK_MOUT_MFC_PLL_USER           14
+#define CLK_MOUT_BUS_PLL_USER           15
+#define CLK_MOUT_ACLK_HEVC_400          16
+#define CLK_MOUT_ACLK_CAM1_333          17
+#define CLK_MOUT_ACLK_CAM1_552_B        18
+#define CLK_MOUT_ACLK_CAM1_552_A        19
+#define CLK_MOUT_ACLK_ISP_DIS_400       20
+#define CLK_MOUT_ACLK_ISP_400           21
+#define CLK_MOUT_ACLK_BUS0_400          22
+#define CLK_MOUT_ACLK_MSCL_400_B        23
+#define CLK_MOUT_ACLK_MSCL_400_A        24
+#define CLK_MOUT_ACLK_GSCL_333          25
+#define CLK_MOUT_ACLK_G2D_400_B         26
+#define CLK_MOUT_ACLK_G2D_400_A         27
+#define CLK_MOUT_SCLK_JPEG_C            28
+#define CLK_MOUT_SCLK_JPEG_B            29
+#define CLK_MOUT_SCLK_JPEG_A            30
+#define CLK_MOUT_SCLK_MMC2_B            31
+#define CLK_MOUT_SCLK_MMC2_A            32
+#define CLK_MOUT_SCLK_MMC1_B            33
+#define CLK_MOUT_SCLK_MMC1_A            34
+#define CLK_MOUT_SCLK_MMC0_D            35
+#define CLK_MOUT_SCLK_MMC0_C            36
+#define CLK_MOUT_SCLK_MMC0_B            37
+#define CLK_MOUT_SCLK_MMC0_A            38
+#define CLK_MOUT_SCLK_SPI4              39
+#define CLK_MOUT_SCLK_SPI3              40
+#define CLK_MOUT_SCLK_UART2             41
+#define CLK_MOUT_SCLK_UART1             42
+#define CLK_MOUT_SCLK_UART0             43
+#define CLK_MOUT_SCLK_SPI2              44
+#define CLK_MOUT_SCLK_SPI1              45
+#define CLK_MOUT_SCLK_SPI0              46
+#define CLK_MOUT_ACLK_MFC_400_C         47
+#define CLK_MOUT_ACLK_MFC_400_B         48
+#define CLK_MOUT_ACLK_MFC_400_A         49
+#define CLK_MOUT_SCLK_ISP_SENSOR2       50
+#define CLK_MOUT_SCLK_ISP_SENSOR1       51
+#define CLK_MOUT_SCLK_ISP_SENSOR0       52
+#define CLK_MOUT_SCLK_ISP_UART          53
+#define CLK_MOUT_SCLK_ISP_SPI1          54
+#define CLK_MOUT_SCLK_ISP_SPI0          55
+#define CLK_MOUT_SCLK_PCIE_100          56
+#define CLK_MOUT_SCLK_UFSUNIPRO         57
+#define CLK_MOUT_SCLK_USBHOST30         58
+#define CLK_MOUT_SCLK_USBDRD30          59
+#define CLK_MOUT_SCLK_SLIMBUS           60
+#define CLK_MOUT_SCLK_SPDIF             61
+#define CLK_MOUT_SCLK_AUDIO1            62
+#define CLK_MOUT_SCLK_AUDIO0            63
+#define CLK_MOUT_SCLK_HDMI_SPDIF        64
+
+#define CLK_DIV_ACLK_FSYS_200           100
+#define CLK_DIV_ACLK_IMEM_SSSX_266      101
+#define CLK_DIV_ACLK_IMEM_200           102
+#define CLK_DIV_ACLK_IMEM_266           103
+#define CLK_DIV_ACLK_PERIC_66_B         104
+#define CLK_DIV_ACLK_PERIC_66_A         105
+#define CLK_DIV_ACLK_PERIS_66_B         106
+#define CLK_DIV_ACLK_PERIS_66_A         107
+#define CLK_DIV_SCLK_MMC1_B             108
+#define CLK_DIV_SCLK_MMC1_A             109
+#define CLK_DIV_SCLK_MMC0_B             110
+#define CLK_DIV_SCLK_MMC0_A             111
+#define CLK_DIV_SCLK_MMC2_B             112
+#define CLK_DIV_SCLK_MMC2_A             113
+#define CLK_DIV_SCLK_SPI1_B             114
+#define CLK_DIV_SCLK_SPI1_A             115
+#define CLK_DIV_SCLK_SPI0_B             116
+#define CLK_DIV_SCLK_SPI0_A             117
+#define CLK_DIV_SCLK_SPI2_B             118
+#define CLK_DIV_SCLK_SPI2_A             119
+#define CLK_DIV_SCLK_UART2              120
+#define CLK_DIV_SCLK_UART1              121
+#define CLK_DIV_SCLK_UART0              122
+#define CLK_DIV_SCLK_SPI4_B             123
+#define CLK_DIV_SCLK_SPI4_A             124
+#define CLK_DIV_SCLK_SPI3_B             125
+#define CLK_DIV_SCLK_SPI3_A             126
+#define CLK_DIV_SCLK_I2S1               127
+#define CLK_DIV_SCLK_PCM1               128
+#define CLK_DIV_SCLK_AUDIO1             129
+#define CLK_DIV_SCLK_AUDIO0             130
+#define CLK_DIV_ACLK_GSCL_111           131
+#define CLK_DIV_ACLK_GSCL_333           132
+#define CLK_DIV_ACLK_HEVC_400           133
+#define CLK_DIV_ACLK_MFC_400            134
+#define CLK_DIV_ACLK_G2D_266            135
+#define CLK_DIV_ACLK_G2D_400            136
+#define CLK_DIV_ACLK_G3D_400            137
+#define CLK_DIV_ACLK_BUS0_400           138
+#define CLK_DIV_ACLK_BUS1_400           139
+#define CLK_DIV_SCLK_PCIE_100           140
+#define CLK_DIV_SCLK_USBHOST30          141
+#define CLK_DIV_SCLK_UFSUNIPRO          142
+#define CLK_DIV_SCLK_USBDRD30           143
+#define CLK_DIV_SCLK_JPEG               144
+#define CLK_DIV_ACLK_MSCL_400           145
+#define CLK_DIV_ACLK_ISP_DIS_400        146
+#define CLK_DIV_ACLK_ISP_400            147
+#define CLK_DIV_ACLK_CAM0_333           148
+#define CLK_DIV_ACLK_CAM0_400           149
+#define CLK_DIV_ACLK_CAM0_552           150
+#define CLK_DIV_ACLK_CAM1_333           151
+#define CLK_DIV_ACLK_CAM1_400           152
+#define CLK_DIV_ACLK_CAM1_552           153
+#define CLK_DIV_SCLK_ISP_UART           154
+#define CLK_DIV_SCLK_ISP_SPI1_B         155
+#define CLK_DIV_SCLK_ISP_SPI1_A         156
+#define CLK_DIV_SCLK_ISP_SPI0_B         157
+#define CLK_DIV_SCLK_ISP_SPI0_A         158
+#define CLK_DIV_SCLK_ISP_SENSOR2_B      159
+#define CLK_DIV_SCLK_ISP_SENSOR2_A      160
+#define CLK_DIV_SCLK_ISP_SENSOR1_B      161
+#define CLK_DIV_SCLK_ISP_SENSOR1_A      162
+#define CLK_DIV_SCLK_ISP_SENSOR0_B      163
+#define CLK_DIV_SCLK_ISP_SENSOR0_A      164
+
+#define CLK_ACLK_PERIC_66               200
+#define CLK_ACLK_PERIS_66               201
+#define CLK_ACLK_FSYS_200               202
+#define CLK_SCLK_MMC2_FSYS              203
+#define CLK_SCLK_MMC1_FSYS              204
+#define CLK_SCLK_MMC0_FSYS              205
+#define CLK_SCLK_SPI4_PERIC             206
+#define CLK_SCLK_SPI3_PERIC             207
+#define CLK_SCLK_UART2_PERIC            208
+#define CLK_SCLK_UART1_PERIC            209
+#define CLK_SCLK_UART0_PERIC            210
+#define CLK_SCLK_SPI2_PERIC             211
+#define CLK_SCLK_SPI1_PERIC             212
+#define CLK_SCLK_SPI0_PERIC             213
+#define CLK_SCLK_SPDIF_PERIC            214
+#define CLK_SCLK_I2S1_PERIC             215
+#define CLK_SCLK_PCM1_PERIC             216
+#define CLK_SCLK_SLIMBUS                217
+#define CLK_SCLK_AUDIO1                 218
+#define CLK_SCLK_AUDIO0                 219
+#define CLK_ACLK_G2D_266                220
+#define CLK_ACLK_G2D_400                221
+#define CLK_ACLK_G3D_400                222
+#define CLK_ACLK_IMEM_SSX_266           223
+#define CLK_ACLK_BUS0_400               224
+#define CLK_ACLK_BUS1_400               225
+#define CLK_ACLK_IMEM_200               226
+#define CLK_ACLK_IMEM_266               227
+#define CLK_SCLK_PCIE_100_FSYS          228
+#define CLK_SCLK_UFSUNIPRO_FSYS         229
+#define CLK_SCLK_USBHOST30_FSYS         230
+#define CLK_SCLK_USBDRD30_FSYS          231
+#define CLK_ACLK_GSCL_111               232
+#define CLK_ACLK_GSCL_333               233
+#define CLK_SCLK_JPEG_MSCL              234
+#define CLK_ACLK_MSCL_400               235
+#define CLK_ACLK_MFC_400                236
+#define CLK_ACLK_HEVC_400               237
+#define CLK_ACLK_ISP_DIS_400            238
+#define CLK_ACLK_ISP_400                239
+#define CLK_ACLK_CAM0_333               240
+#define CLK_ACLK_CAM0_400               241
+#define CLK_ACLK_CAM0_552               242
+#define CLK_ACLK_CAM1_333               243
+#define CLK_ACLK_CAM1_400               244
+#define CLK_ACLK_CAM1_552               245
+#define CLK_SCLK_ISP_SENSOR2            246
+#define CLK_SCLK_ISP_SENSOR1            247
+#define CLK_SCLK_ISP_SENSOR0            248
+#define CLK_SCLK_ISP_MCTADC_CAM1        249
+#define CLK_SCLK_ISP_UART_CAM1          250
+#define CLK_SCLK_ISP_SPI1_CAM1          251
+#define CLK_SCLK_ISP_SPI0_CAM1          252
+#define CLK_SCLK_HDMI_SPDIF_DISP        253
+
+#define TOP_NR_CLK                      254
+
+/* CMU_CPIF */
+#define CLK_FOUT_MPHY_PLL               1
+
+#define CLK_MOUT_MPHY_PLL               2
+
+#define CLK_DIV_SCLK_MPHY               10
+
+#define CLK_SCLK_MPHY_PLL               11
+#define CLK_SCLK_UFS_MPHY               11
+
+#define CPIF_NR_CLK                     12
+
+/* CMU_MIF */
+#define CLK_FOUT_MEM0_PLL               1
+#define CLK_FOUT_MEM1_PLL               2
+#define CLK_FOUT_BUS_PLL                3
+#define CLK_FOUT_MFC_PLL                4
+#define CLK_DOUT_MFC_PLL                5
+#define CLK_DOUT_BUS_PLL                6
+#define CLK_DOUT_MEM1_PLL               7
+#define CLK_DOUT_MEM0_PLL               8
+
+#define CLK_MOUT_MFC_PLL_DIV2           10
+#define CLK_MOUT_BUS_PLL_DIV2           11
+#define CLK_MOUT_MEM1_PLL_DIV2          12
+#define CLK_MOUT_MEM0_PLL_DIV2          13
+#define CLK_MOUT_MFC_PLL                14
+#define CLK_MOUT_BUS_PLL                15
+#define CLK_MOUT_MEM1_PLL               16
+#define CLK_MOUT_MEM0_PLL               17
+#define CLK_MOUT_CLK2X_PHY_C            18
+#define CLK_MOUT_CLK2X_PHY_B            19
+#define CLK_MOUT_CLK2X_PHY_A            20
+#define CLK_MOUT_CLKM_PHY_C             21
+#define CLK_MOUT_CLKM_PHY_B             22
+#define CLK_MOUT_CLKM_PHY_A             23
+#define CLK_MOUT_ACLK_MIFNM_200         24
+#define CLK_MOUT_ACLK_MIFNM_400         25
+#define CLK_MOUT_ACLK_DISP_333_B        26
+#define CLK_MOUT_ACLK_DISP_333_A        27
+#define CLK_MOUT_SCLK_DECON_VCLK_C      28
+#define CLK_MOUT_SCLK_DECON_VCLK_B      29
+#define CLK_MOUT_SCLK_DECON_VCLK_A      30
+#define CLK_MOUT_SCLK_DECON_ECLK_C      31
+#define CLK_MOUT_SCLK_DECON_ECLK_B      32
+#define CLK_MOUT_SCLK_DECON_ECLK_A      33
+#define CLK_MOUT_SCLK_DECON_TV_ECLK_C   34
+#define CLK_MOUT_SCLK_DECON_TV_ECLK_B   35
+#define CLK_MOUT_SCLK_DECON_TV_ECLK_A   36
+#define CLK_MOUT_SCLK_DSD_C             37
+#define CLK_MOUT_SCLK_DSD_B             38
+#define CLK_MOUT_SCLK_DSD_A             39
+#define CLK_MOUT_SCLK_DSIM0_C           40
+#define CLK_MOUT_SCLK_DSIM0_B           41
+#define CLK_MOUT_SCLK_DSIM0_A           42
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_C   46
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_B   47
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_A   48
+#define CLK_MOUT_SCLK_DSIM1_C           49
+#define CLK_MOUT_SCLK_DSIM1_B           50
+#define CLK_MOUT_SCLK_DSIM1_A           51
+
+#define CLK_DIV_SCLK_HPM_MIF            55
+#define CLK_DIV_ACLK_DREX1              56
+#define CLK_DIV_ACLK_DREX0              57
+#define CLK_DIV_CLK2XPHY                58
+#define CLK_DIV_ACLK_MIF_266            59
+#define CLK_DIV_ACLK_MIFND_133          60
+#define CLK_DIV_ACLK_MIF_133            61
+#define CLK_DIV_ACLK_MIFNM_200          62
+#define CLK_DIV_ACLK_MIF_200            63
+#define CLK_DIV_ACLK_MIF_400            64
+#define CLK_DIV_ACLK_BUS2_400           65
+#define CLK_DIV_ACLK_DISP_333           66
+#define CLK_DIV_ACLK_CPIF_200           67
+#define CLK_DIV_SCLK_DSIM1              68
+#define CLK_DIV_SCLK_DECON_TV_VCLK      69
+#define CLK_DIV_SCLK_DSIM0              70
+#define CLK_DIV_SCLK_DSD                71
+#define CLK_DIV_SCLK_DECON_TV_ECLK      72
+#define CLK_DIV_SCLK_DECON_VCLK         73
+#define CLK_DIV_SCLK_DECON_ECLK         74
+#define CLK_DIV_MIF_PRE                 75
+
+#define CLK_CLK2X_PHY1                  80
+#define CLK_CLK2X_PHY0                  81
+#define CLK_CLKM_PHY1                   82
+#define CLK_CLKM_PHY0                   83
+#define CLK_RCLK_DREX1                  84
+#define CLK_RCLK_DREX0                  85
+#define CLK_ACLK_DREX1_TZ               86
+#define CLK_ACLK_DREX0_TZ               87
+#define CLK_ACLK_DREX1_PEREV            88
+#define CLK_ACLK_DREX0_PEREV            89
+#define CLK_ACLK_DREX1_MEMIF            90
+#define CLK_ACLK_DREX0_MEMIF            91
+#define CLK_ACLK_DREX1_SCH              92
+#define CLK_ACLK_DREX0_SCH              93
+#define CLK_ACLK_DREX1_BUSIF            94
+#define CLK_ACLK_DREX0_BUSIF            95
+#define CLK_ACLK_DREX1_BUSIF_RD         96
+#define CLK_ACLK_DREX0_BUSIF_RD         97
+#define CLK_ACLK_DREX1                  98
+#define CLK_ACLK_DREX0                  99
+#define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX   100
+#define CLK_ACLK_ASYNCAXIS_ATLAS_MIF    101
+#define CLK_ACLK_ASYNCAXIM_ATLAS_MIF    102
+#define CLK_ACLK_ASYNCAXIS_MIF_IMEM     103
+#define CLK_ACLK_ASYNCAXIS_NOC_P_CCI    104
+#define CLK_ACLK_ASYNCAXIM_NOC_P_CCI    105
+#define CLK_ACLK_ASYNCAXIS_CP1          106
+#define CLK_ACLK_ASYNCAXIM_CP1          107
+#define CLK_ACLK_ASYNCAXIS_CP0          108
+#define CLK_ACLK_ASYNCAXIM_CP0          109
+#define CLK_ACLK_ASYNCAXIS_DREX1_3      110
+#define CLK_ACLK_ASYNCAXIM_DREX1_3      111
+#define CLK_ACLK_ASYNCAXIS_DREX1_1      112
+#define CLK_ACLK_ASYNCAXIM_DREX1_1      113
+#define CLK_ACLK_ASYNCAXIS_DREX1_0      114
+#define CLK_ACLK_ASYNCAXIM_DREX1_0      115
+#define CLK_ACLK_ASYNCAXIS_DREX0_3      116
+#define CLK_ACLK_ASYNCAXIM_DREX0_3      117
+#define CLK_ACLK_ASYNCAXIS_DREX0_1      118
+#define CLK_ACLK_ASYNCAXIM_DREX0_1      119
+#define CLK_ACLK_ASYNCAXIS_DREX0_0      120
+#define CLK_ACLK_ASYNCAXIM_DREX0_0      121
+#define CLK_ACLK_AHB2APB_MIF2P          122
+#define CLK_ACLK_AHB2APB_MIF1P          123
+#define CLK_ACLK_AHB2APB_MIF0P          124
+#define CLK_ACLK_IXIU_CCI               125
+#define CLK_ACLK_XIU_MIFSFRX            126
+#define CLK_ACLK_MIFNP_133              127
+#define CLK_ACLK_MIFNM_200              128
+#define CLK_ACLK_MIFND_133              129
+#define CLK_ACLK_MIFND_400              130
+#define CLK_ACLK_CCI                    131
+#define CLK_ACLK_MIFND_266              132
+#define CLK_ACLK_PPMU_DREX1S3           133
+#define CLK_ACLK_PPMU_DREX1S1           134
+#define CLK_ACLK_PPMU_DREX1S0           135
+#define CLK_ACLK_PPMU_DREX0S3           136
+#define CLK_ACLK_PPMU_DREX0S1           137
+#define CLK_ACLK_PPMU_DREX0S0           138
+#define CLK_ACLK_BTS_APOLLO             139
+#define CLK_ACLK_BTS_ATLAS              140
+#define CLK_ACLK_ACE_SEL_APOLL          141
+#define CLK_ACLK_ACE_SEL_ATLAS          142
+#define CLK_ACLK_AXIDS_CCI_MIFSFRX      143
+#define CLK_ACLK_AXIUS_ATLAS_CCI        144
+#define CLK_ACLK_AXISYNCDNS_CCI         145
+#define CLK_ACLK_AXISYNCDN_CCI          146
+#define CLK_ACLK_AXISYNCDN_NOC_D        147
+#define CLK_ACLK_ASYNCACEM_APOLLO_CCI   148
+#define CLK_ACLK_ASYNCACEM_ATLAS_CCI    149
+#define CLK_ACLK_ASYNCAPBS_MIF_CSSYS    150
+#define CLK_ACLK_BUS2_400               151
+#define CLK_ACLK_DISP_333               152
+#define CLK_ACLK_CPIF_200               153
+#define CLK_PCLK_PPMU_DREX1S3           154
+#define CLK_PCLK_PPMU_DREX1S1           155
+#define CLK_PCLK_PPMU_DREX1S0           156
+#define CLK_PCLK_PPMU_DREX0S3           157
+#define CLK_PCLK_PPMU_DREX0S1           158
+#define CLK_PCLK_PPMU_DREX0S0           159
+#define CLK_PCLK_BTS_APOLLO             160
+#define CLK_PCLK_BTS_ATLAS              161
+#define CLK_PCLK_ASYNCAXI_NOC_P_CCI     162
+#define CLK_PCLK_ASYNCAXI_CP1           163
+#define CLK_PCLK_ASYNCAXI_CP0           164
+#define CLK_PCLK_ASYNCAXI_DREX1_3       165
+#define CLK_PCLK_ASYNCAXI_DREX1_1       166
+#define CLK_PCLK_ASYNCAXI_DREX1_0       167
+#define CLK_PCLK_ASYNCAXI_DREX0_3       168
+#define CLK_PCLK_ASYNCAXI_DREX0_1       169
+#define CLK_PCLK_ASYNCAXI_DREX0_0       170
+#define CLK_PCLK_MIFSRVND_133           171
+#define CLK_PCLK_PMU_MIF                172
+#define CLK_PCLK_SYSREG_MIF             173
+#define CLK_PCLK_GPIO_ALIVE             174
+#define CLK_PCLK_ABB                    175
+#define CLK_PCLK_PMU_APBIF              176
+#define CLK_PCLK_DDR_PHY1               177
+#define CLK_PCLK_DREX1                  178
+#define CLK_PCLK_DDR_PHY0               179
+#define CLK_PCLK_DREX0                  180
+#define CLK_PCLK_DREX0_TZ               181
+#define CLK_PCLK_DREX1_TZ               182
+#define CLK_PCLK_MONOTONIC_CNT          183
+#define CLK_PCLK_RTC                    184
+#define CLK_SCLK_DSIM1_DISP             185
+#define CLK_SCLK_DECON_TV_VCLK_DISP     186
+#define CLK_SCLK_FREQ_DET_BUS_PLL       187
+#define CLK_SCLK_FREQ_DET_MFC_PLL       188
+#define CLK_SCLK_FREQ_DET_MEM0_PLL      189
+#define CLK_SCLK_FREQ_DET_MEM1_PLL      190
+#define CLK_SCLK_DSIM0_DISP             191
+#define CLK_SCLK_DSD_DISP               192
+#define CLK_SCLK_DECON_TV_ECLK_DISP     193
+#define CLK_SCLK_DECON_VCLK_DISP        194
+#define CLK_SCLK_DECON_ECLK_DISP        195
+#define CLK_SCLK_HPM_MIF                196
+#define CLK_SCLK_MFC_PLL                197
+#define CLK_SCLK_BUS_PLL                198
+#define CLK_SCLK_BUS_PLL_APOLLO         199
+#define CLK_SCLK_BUS_PLL_ATLAS          200
+
+#define MIF_NR_CLK                      201
+
+/* CMU_PERIC */
+#define CLK_PCLK_SPI2                   1
+#define CLK_PCLK_SPI1                   2
+#define CLK_PCLK_SPI0                   3
+#define CLK_PCLK_UART2                  4
+#define CLK_PCLK_UART1                  5
+#define CLK_PCLK_UART0                  6
+#define CLK_PCLK_HSI2C3                 7
+#define CLK_PCLK_HSI2C2                 8
+#define CLK_PCLK_HSI2C1                 9
+#define CLK_PCLK_HSI2C0                 10
+#define CLK_PCLK_I2C7                   11
+#define CLK_PCLK_I2C6                   12
+#define CLK_PCLK_I2C5                   13
+#define CLK_PCLK_I2C4                   14
+#define CLK_PCLK_I2C3                   15
+#define CLK_PCLK_I2C2                   16
+#define CLK_PCLK_I2C1                   17
+#define CLK_PCLK_I2C0                   18
+#define CLK_PCLK_SPI4                   19
+#define CLK_PCLK_SPI3                   20
+#define CLK_PCLK_HSI2C11                21
+#define CLK_PCLK_HSI2C10                22
+#define CLK_PCLK_HSI2C9                 23
+#define CLK_PCLK_HSI2C8                 24
+#define CLK_PCLK_HSI2C7                 25
+#define CLK_PCLK_HSI2C6                 26
+#define CLK_PCLK_HSI2C5                 27
+#define CLK_PCLK_HSI2C4                 28
+#define CLK_SCLK_SPI4                   29
+#define CLK_SCLK_SPI3                   30
+#define CLK_SCLK_SPI2                   31
+#define CLK_SCLK_SPI1                   32
+#define CLK_SCLK_SPI0                   33
+#define CLK_SCLK_UART2                  34
+#define CLK_SCLK_UART1                  35
+#define CLK_SCLK_UART0                  36
+#define CLK_ACLK_AHB2APB_PERIC2P        37
+#define CLK_ACLK_AHB2APB_PERIC1P        38
+#define CLK_ACLK_AHB2APB_PERIC0P        39
+#define CLK_ACLK_PERICNP_66             40
+#define CLK_PCLK_SCI                    41
+#define CLK_PCLK_GPIO_FINGER            42
+#define CLK_PCLK_GPIO_ESE               43
+#define CLK_PCLK_PWM                    44
+#define CLK_PCLK_SPDIF                  45
+#define CLK_PCLK_PCM1                   46
+#define CLK_PCLK_I2S1                   47
+#define CLK_PCLK_ADCIF                  48
+#define CLK_PCLK_GPIO_TOUCH             49
+#define CLK_PCLK_GPIO_NFC               50
+#define CLK_PCLK_GPIO_PERIC             51
+#define CLK_PCLK_PMU_PERIC              52
+#define CLK_PCLK_SYSREG_PERIC           53
+#define CLK_SCLK_IOCLK_SPI4             54
+#define CLK_SCLK_IOCLK_SPI3             55
+#define CLK_SCLK_SCI                    56
+#define CLK_SCLK_SC_IN                  57
+#define CLK_SCLK_PWM                    58
+#define CLK_SCLK_IOCLK_SPI2             59
+#define CLK_SCLK_IOCLK_SPI1             60
+#define CLK_SCLK_IOCLK_SPI0             61
+#define CLK_SCLK_IOCLK_I2S1_BCLK        62
+#define CLK_SCLK_SPDIF                  63
+#define CLK_SCLK_PCM1                   64
+#define CLK_SCLK_I2S1                   65
+
+#define CLK_DIV_SCLK_SCI                70
+#define CLK_DIV_SCLK_SC_IN              71
+
+#define PERIC_NR_CLK                    72
+
+/* CMU_PERIS */
+#define CLK_PCLK_HPM_APBIF              1
+#define CLK_PCLK_TMU1_APBIF             2
+#define CLK_PCLK_TMU0_APBIF             3
+#define CLK_PCLK_PMU_PERIS              4
+#define CLK_PCLK_SYSREG_PERIS           5
+#define CLK_PCLK_CMU_TOP_APBIF          6
+#define CLK_PCLK_WDT_APOLLO             7
+#define CLK_PCLK_WDT_ATLAS              8
+#define CLK_PCLK_MCT                    9
+#define CLK_PCLK_HDMI_CEC               10
+#define CLK_ACLK_AHB2APB_PERIS1P        11
+#define CLK_ACLK_AHB2APB_PERIS0P        12
+#define CLK_ACLK_PERISNP_66             13
+#define CLK_PCLK_TZPC12                 14
+#define CLK_PCLK_TZPC11                 15
+#define CLK_PCLK_TZPC10                 16
+#define CLK_PCLK_TZPC9                  17
+#define CLK_PCLK_TZPC8                  18
+#define CLK_PCLK_TZPC7                  19
+#define CLK_PCLK_TZPC6                  20
+#define CLK_PCLK_TZPC5                  21
+#define CLK_PCLK_TZPC4                  22
+#define CLK_PCLK_TZPC3                  23
+#define CLK_PCLK_TZPC2                  24
+#define CLK_PCLK_TZPC1                  25
+#define CLK_PCLK_TZPC0                  26
+#define CLK_PCLK_SECKEY_APBIF           27
+#define CLK_PCLK_CHIPID_APBIF           28
+#define CLK_PCLK_TOPRTC                 29
+#define CLK_PCLK_CUSTOM_EFUSE_APBIF     30
+#define CLK_PCLK_ANTIRBK_CNT_APBIF      31
+#define CLK_PCLK_OTP_CON_APBIF          32
+#define CLK_SCLK_ASV_TB                 33
+#define CLK_SCLK_TMU1                   34
+#define CLK_SCLK_TMU0                   35
+#define CLK_SCLK_SECKEY                 36
+#define CLK_SCLK_CHIPID                 37
+#define CLK_SCLK_TOPRTC                 38
+#define CLK_SCLK_CUSTOM_EFUSE           39
+#define CLK_SCLK_ANTIRBK_CNT            40
+#define CLK_SCLK_OTP_CON                41
+
+#define PERIS_NR_CLK                    42
+
+/* CMU_FSYS */
+#define CLK_MOUT_ACLK_FSYS_200_USER     1
+#define CLK_MOUT_SCLK_MMC2_USER         2
+#define CLK_MOUT_SCLK_MMC1_USER         3
+#define CLK_MOUT_SCLK_MMC0_USER         4
+#define CLK_MOUT_SCLK_UFS_MPHY_USER     5
+#define CLK_MOUT_SCLK_PCIE_100_USER     6
+#define CLK_MOUT_SCLK_UFSUNIPRO_USER    7
+#define CLK_MOUT_SCLK_USBHOST30_USER    8
+#define CLK_MOUT_SCLK_USBDRD30_USER     9
+#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER        10
+#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER         11
+#define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER                12
+#define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER           13
+#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER             14
+#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER          15
+#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER          16
+#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER           17
+#define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER                     18
+#define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER                     19
+#define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER                     20
+#define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER                     21
+#define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER                    22
+#define CLK_MOUT_SCLK_MPHY                                      23
+
+#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY                 25
+#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY                26
+#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY               27
+#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY              28
+#define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY                    29
+#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY                   30
+#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY                 31
+#define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY                      32
+#define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY                           33
+#define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY                           34
+#define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY                           35
+#define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY                           36
+#define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY                          37
+
+#define CLK_ACLK_PCIE                   50
+#define CLK_ACLK_PDMA1                  51
+#define CLK_ACLK_TSI                    52
+#define CLK_ACLK_MMC2                   53
+#define CLK_ACLK_MMC1                   54
+#define CLK_ACLK_MMC0                   55
+#define CLK_ACLK_UFS                    56
+#define CLK_ACLK_USBHOST20              57
+#define CLK_ACLK_USBHOST30              58
+#define CLK_ACLK_USBDRD30               59
+#define CLK_ACLK_PDMA0                  60
+#define CLK_SCLK_MMC2                   61
+#define CLK_SCLK_MMC1                   62
+#define CLK_SCLK_MMC0                   63
+#define CLK_PDMA1                       64
+#define CLK_PDMA0                       65
+#define CLK_ACLK_XIU_FSYSPX             66
+#define CLK_ACLK_AHB_USBLINKH1          67
+#define CLK_ACLK_SMMU_PDMA1             68
+#define CLK_ACLK_BTS_PCIE               69
+#define CLK_ACLK_AXIUS_PDMA1            70
+#define CLK_ACLK_SMMU_PDMA0             71
+#define CLK_ACLK_BTS_UFS                72
+#define CLK_ACLK_BTS_USBHOST30          73
+#define CLK_ACLK_BTS_USBDRD30           74
+#define CLK_ACLK_AXIUS_PDMA0            75
+#define CLK_ACLK_AXIUS_USBHS            76
+#define CLK_ACLK_AXIUS_FSYSSX           77
+#define CLK_ACLK_AHB2APB_FSYSP          78
+#define CLK_ACLK_AHB2AXI_USBHS          79
+#define CLK_ACLK_AHB_USBLINKH0          80
+#define CLK_ACLK_AHB_USBHS              81
+#define CLK_ACLK_AHB_FSYSH              82
+#define CLK_ACLK_XIU_FSYSX              83
+#define CLK_ACLK_XIU_FSYSSX             84
+#define CLK_ACLK_FSYSNP_200             85
+#define CLK_ACLK_FSYSND_200             86
+#define CLK_PCLK_PCIE_CTRL              87
+#define CLK_PCLK_SMMU_PDMA1             88
+#define CLK_PCLK_PCIE_PHY               89
+#define CLK_PCLK_BTS_PCIE               90
+#define CLK_PCLK_SMMU_PDMA0             91
+#define CLK_PCLK_BTS_UFS                92
+#define CLK_PCLK_BTS_USBHOST30          93
+#define CLK_PCLK_BTS_USBDRD30           94
+#define CLK_PCLK_GPIO_FSYS              95
+#define CLK_PCLK_PMU_FSYS               96
+#define CLK_PCLK_SYSREG_FSYS            97
+#define CLK_SCLK_PCIE_100               98
+#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK  99
+#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK   100
+#define CLK_PHYCLK_UFS_RX1_SYMBOL               101
+#define CLK_PHYCLK_UFS_RX0_SYMBOL               102
+#define CLK_PHYCLK_UFS_TX1_SYMBOL               103
+#define CLK_PHYCLK_UFS_TX0_SYMBOL               104
+#define CLK_PHYCLK_USBHOST20_PHY_HSIC1          105
+#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI     106
+#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK       107
+#define CLK_PHYCLK_USBHOST20_PHY_FREECLK        108
+#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK    109
+#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK     110
+#define CLK_SCLK_MPHY                   111
+#define CLK_SCLK_UFSUNIPRO              112
+#define CLK_SCLK_USBHOST30              113
+#define CLK_SCLK_USBDRD30               114
+
+#define FSYS_NR_CLK                     115
+
+/* CMU_G2D */
+#define CLK_MUX_ACLK_G2D_266_USER       1
+#define CLK_MUX_ACLK_G2D_400_USER       2
+
+#define CLK_DIV_PCLK_G2D                3
+
+#define CLK_ACLK_SMMU_MDMA1             4
+#define CLK_ACLK_BTS_MDMA1              5
+#define CLK_ACLK_BTS_G2D                6
+#define CLK_ACLK_ALB_G2D                7
+#define CLK_ACLK_AXIUS_G2DX             8
+#define CLK_ACLK_ASYNCAXI_SYSX          9
+#define CLK_ACLK_AHB2APB_G2D1P          10
+#define CLK_ACLK_AHB2APB_G2D0P          11
+#define CLK_ACLK_XIU_G2DX               12
+#define CLK_ACLK_G2DNP_133              13
+#define CLK_ACLK_G2DND_400              14
+#define CLK_ACLK_MDMA1                  15
+#define CLK_ACLK_G2D                    16
+#define CLK_ACLK_SMMU_G2D               17
+#define CLK_PCLK_SMMU_MDMA1             18
+#define CLK_PCLK_BTS_MDMA1              19
+#define CLK_PCLK_BTS_G2D                20
+#define CLK_PCLK_ALB_G2D                21
+#define CLK_PCLK_ASYNCAXI_SYSX          22
+#define CLK_PCLK_PMU_G2D                23
+#define CLK_PCLK_SYSREG_G2D             24
+#define CLK_PCLK_G2D                    25
+#define CLK_PCLK_SMMU_G2D               26
+
+#define G2D_NR_CLK                      27
+
+/* CMU_DISP */
+#define CLK_FOUT_DISP_PLL                               1
+
+#define CLK_MOUT_DISP_PLL                               2
+#define CLK_MOUT_SCLK_DSIM1_USER                        3
+#define CLK_MOUT_SCLK_DSIM0_USER                        4
+#define CLK_MOUT_SCLK_DSD_USER                          5
+#define CLK_MOUT_SCLK_DECON_TV_ECLK_USER                6
+#define CLK_MOUT_SCLK_DECON_VCLK_USER                   7
+#define CLK_MOUT_SCLK_DECON_ECLK_USER                   8
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_USER                9
+#define CLK_MOUT_ACLK_DISP_333_USER                     10
+#define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER       11
+#define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER        12
+#define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER       13
+#define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER        14
+#define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER          15
+#define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER         16
+#define CLK_MOUT_SCLK_DSIM0                             17
+#define CLK_MOUT_SCLK_DECON_TV_ECLK                     18
+#define CLK_MOUT_SCLK_DECON_VCLK                        19
+#define CLK_MOUT_SCLK_DECON_ECLK                        20
+#define CLK_MOUT_SCLK_DSIM1_B_DISP                      21
+#define CLK_MOUT_SCLK_DSIM1_A_DISP                      22
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP              23
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP              24
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP              25
+
+#define CLK_DIV_SCLK_DSIM1_DISP                         30
+#define CLK_DIV_SCLK_DECON_TV_VCLK_DISP                 31
+#define CLK_DIV_SCLK_DSIM0_DISP                         32
+#define CLK_DIV_SCLK_DECON_TV_ECLK_DISP                 33
+#define CLK_DIV_SCLK_DECON_VCLK_DISP                    34
+#define CLK_DIV_SCLK_DECON_ECLK_DISP                    35
+#define CLK_DIV_PCLK_DISP                               36
+
+#define CLK_ACLK_DECON_TV                               40
+#define CLK_ACLK_DECON                                  41
+#define CLK_ACLK_SMMU_TV1X                              42
+#define CLK_ACLK_SMMU_TV0X                              43
+#define CLK_ACLK_SMMU_DECON1X                           44
+#define CLK_ACLK_SMMU_DECON0X                           45
+#define CLK_ACLK_BTS_DECON_TV_M3                        46
+#define CLK_ACLK_BTS_DECON_TV_M2                        47
+#define CLK_ACLK_BTS_DECON_TV_M1                        48
+#define CLK_ACLK_BTS_DECON_TV_M0                        49
+#define CLK_ACLK_BTS_DECON_NM4                          50
+#define CLK_ACLK_BTS_DECON_NM3                          51
+#define CLK_ACLK_BTS_DECON_NM2                          52
+#define CLK_ACLK_BTS_DECON_NM1                          53
+#define CLK_ACLK_BTS_DECON_NM0                          54
+#define CLK_ACLK_AHB2APB_DISPSFR2P                      55
+#define CLK_ACLK_AHB2APB_DISPSFR1P                      56
+#define CLK_ACLK_AHB2APB_DISPSFR0P                      57
+#define CLK_ACLK_AHB_DISPH                              58
+#define CLK_ACLK_XIU_TV1X                               59
+#define CLK_ACLK_XIU_TV0X                               60
+#define CLK_ACLK_XIU_DECON1X                            61
+#define CLK_ACLK_XIU_DECON0X                            62
+#define CLK_ACLK_XIU_DISP1X                             63
+#define CLK_ACLK_XIU_DISPNP_100                         64
+#define CLK_ACLK_DISP1ND_333                            65
+#define CLK_ACLK_DISP0ND_333                            66
+#define CLK_PCLK_SMMU_TV1X                              67
+#define CLK_PCLK_SMMU_TV0X                              68
+#define CLK_PCLK_SMMU_DECON1X                           69
+#define CLK_PCLK_SMMU_DECON0X                           70
+#define CLK_PCLK_BTS_DECON_TV_M3                        71
+#define CLK_PCLK_BTS_DECON_TV_M2                        72
+#define CLK_PCLK_BTS_DECON_TV_M1                        73
+#define CLK_PCLK_BTS_DECON_TV_M0                        74
+#define CLK_PCLK_BTS_DECONM4                            75
+#define CLK_PCLK_BTS_DECONM3                            76
+#define CLK_PCLK_BTS_DECONM2                            77
+#define CLK_PCLK_BTS_DECONM1                            78
+#define CLK_PCLK_BTS_DECONM0                            79
+#define CLK_PCLK_MIC1                                   80
+#define CLK_PCLK_PMU_DISP                               81
+#define CLK_PCLK_SYSREG_DISP                            82
+#define CLK_PCLK_HDMIPHY                                83
+#define CLK_PCLK_HDMI                                   84
+#define CLK_PCLK_MIC0                                   85
+#define CLK_PCLK_DSIM1                                  86
+#define CLK_PCLK_DSIM0                                  87
+#define CLK_PCLK_DECON_TV                               88
+#define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8                 89
+#define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0                  90
+#define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1                   91
+#define CLK_SCLK_RGB_TV_VCLK_TO_MIC1                    92
+#define CLK_SCLK_DSIM1                                  93
+#define CLK_SCLK_DECON_TV_VCLK                          94
+#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8                 95
+#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0                  96
+#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO                    97
+#define CLK_PHYCLK_HDMI_PIXEL                           98
+#define CLK_SCLK_RGB_VCLK_TO_SMIES                      99
+#define CLK_SCLK_FREQ_DET_DISP_PLL                      100
+#define CLK_SCLK_RGB_VCLK_TO_DSIM0                      101
+#define CLK_SCLK_RGB_VCLK_TO_MIC0                       102
+#define CLK_SCLK_DSD                                    103
+#define CLK_SCLK_HDMI_SPDIF                             104
+#define CLK_SCLK_DSIM0                                  105
+#define CLK_SCLK_DECON_TV_ECLK                          106
+#define CLK_SCLK_DECON_VCLK                             107
+#define CLK_SCLK_DECON_ECLK                             108
+#define CLK_SCLK_RGB_VCLK                               109
+#define CLK_SCLK_RGB_TV_VCLK                            110
+
+#define DISP_NR_CLK                                     111
+
+/* CMU_AUD */
+#define CLK_MOUT_AUD_PLL_USER                           1
+#define CLK_MOUT_SCLK_AUD_PCM                           2
+#define CLK_MOUT_SCLK_AUD_I2S                           3
+
+#define CLK_DIV_ATCLK_AUD                               4
+#define CLK_DIV_PCLK_DBG_AUD                            5
+#define CLK_DIV_ACLK_AUD                                6
+#define CLK_DIV_AUD_CA5                                 7
+#define CLK_DIV_SCLK_AUD_SLIMBUS                        8
+#define CLK_DIV_SCLK_AUD_UART                           9
+#define CLK_DIV_SCLK_AUD_PCM                            10
+#define CLK_DIV_SCLK_AUD_I2S                            11
+
+#define CLK_ACLK_INTR_CTRL                              12
+#define CLK_ACLK_AXIDS2_LPASSP                          13
+#define CLK_ACLK_AXIDS1_LPASSP                          14
+#define CLK_ACLK_AXI2APB1_LPASSP                        15
+#define CLK_ACLK_AXI2APH_LPASSP                         16
+#define CLK_ACLK_SMMU_LPASSX                            17
+#define CLK_ACLK_AXIDS0_LPASSP                          18
+#define CLK_ACLK_AXI2APB0_LPASSP                        19
+#define CLK_ACLK_XIU_LPASSX                             20
+#define CLK_ACLK_AUDNP_133                              21
+#define CLK_ACLK_AUDND_133                              22
+#define CLK_ACLK_SRAMC                                  23
+#define CLK_ACLK_DMAC                                   24
+#define CLK_PCLK_WDT1                                   25
+#define CLK_PCLK_WDT0                                   26
+#define CLK_PCLK_SFR1                                   27
+#define CLK_PCLK_SMMU_LPASSX                            28
+#define CLK_PCLK_GPIO_AUD                               29
+#define CLK_PCLK_PMU_AUD                                30
+#define CLK_PCLK_SYSREG_AUD                             31
+#define CLK_PCLK_AUD_SLIMBUS                            32
+#define CLK_PCLK_AUD_UART                               33
+#define CLK_PCLK_AUD_PCM                                34
+#define CLK_PCLK_AUD_I2S                                35
+#define CLK_PCLK_TIMER                                  36
+#define CLK_PCLK_SFR0_CTRL                              37
+#define CLK_ATCLK_AUD                                   38
+#define CLK_PCLK_DBG_AUD                                39
+#define CLK_SCLK_AUD_CA5                                40
+#define CLK_SCLK_JTAG_TCK                               41
+#define CLK_SCLK_SLIMBUS_CLKIN                          42
+#define CLK_SCLK_AUD_SLIMBUS                            43
+#define CLK_SCLK_AUD_UART                               44
+#define CLK_SCLK_AUD_PCM                                45
+#define CLK_SCLK_I2S_BCLK                               46
+#define CLK_SCLK_AUD_I2S                                47
+
+#define AUD_NR_CLK                                      48
+
+/* CMU_BUS{0|1|2} */
+#define CLK_DIV_PCLK_BUS_133                            1
+
+#define CLK_ACLK_AHB2APB_BUSP                           2
+#define CLK_ACLK_BUSNP_133                              3
+#define CLK_ACLK_BUSND_400                              4
+#define CLK_PCLK_BUSSRVND_133                           5
+#define CLK_PCLK_PMU_BUS                                6
+#define CLK_PCLK_SYSREG_BUS                             7
+
+#define CLK_MOUT_ACLK_BUS2_400_USER                     8  /* Only CMU_BUS2 */
+#define CLK_ACLK_BUS2BEND_400                           9  /* Only CMU_BUS2 */
+#define CLK_ACLK_BUS2RTND_400                           10 /* Only CMU_BUS2 */
+
+#define BUSx_NR_CLK                                     11
+
+/* CMU_G3D */
+#define CLK_FOUT_G3D_PLL                                1
+
+#define CLK_MOUT_ACLK_G3D_400                           2
+#define CLK_MOUT_G3D_PLL                                3
+
+#define CLK_DIV_SCLK_HPM_G3D                            4
+#define CLK_DIV_PCLK_G3D                                5
+#define CLK_DIV_ACLK_G3D                                6
+#define CLK_ACLK_BTS_G3D1                               7
+#define CLK_ACLK_BTS_G3D0                               8
+#define CLK_ACLK_ASYNCAPBS_G3D                          9
+#define CLK_ACLK_ASYNCAPBM_G3D                          10
+#define CLK_ACLK_AHB2APB_G3DP                           11
+#define CLK_ACLK_G3DNP_150                              12
+#define CLK_ACLK_G3DND_600                              13
+#define CLK_ACLK_G3D                                    14
+#define CLK_PCLK_BTS_G3D1                               15
+#define CLK_PCLK_BTS_G3D0                               16
+#define CLK_PCLK_PMU_G3D                                17
+#define CLK_PCLK_SYSREG_G3D                             18
+#define CLK_SCLK_HPM_G3D                                19
+
+#define G3D_NR_CLK                                      20
+
+/* CMU_GSCL */
+#define CLK_MOUT_ACLK_GSCL_111_USER                     1
+#define CLK_MOUT_ACLK_GSCL_333_USER                     2
+
+#define CLK_ACLK_BTS_GSCL2                              3
+#define CLK_ACLK_BTS_GSCL1                              4
+#define CLK_ACLK_BTS_GSCL0                              5
+#define CLK_ACLK_AHB2APB_GSCLP                          6
+#define CLK_ACLK_XIU_GSCLX                              7
+#define CLK_ACLK_GSCLNP_111                             8
+#define CLK_ACLK_GSCLRTND_333                           9
+#define CLK_ACLK_GSCLBEND_333                           10
+#define CLK_ACLK_GSD                                    11
+#define CLK_ACLK_GSCL2                                  12
+#define CLK_ACLK_GSCL1                                  13
+#define CLK_ACLK_GSCL0                                  14
+#define CLK_ACLK_SMMU_GSCL0                             15
+#define CLK_ACLK_SMMU_GSCL1                             16
+#define CLK_ACLK_SMMU_GSCL2                             17
+#define CLK_PCLK_BTS_GSCL2                              18
+#define CLK_PCLK_BTS_GSCL1                              19
+#define CLK_PCLK_BTS_GSCL0                              20
+#define CLK_PCLK_PMU_GSCL                               21
+#define CLK_PCLK_SYSREG_GSCL                            22
+#define CLK_PCLK_GSCL2                                  23
+#define CLK_PCLK_GSCL1                                  24
+#define CLK_PCLK_GSCL0                                  25
+#define CLK_PCLK_SMMU_GSCL0                             26
+#define CLK_PCLK_SMMU_GSCL1                             27
+#define CLK_PCLK_SMMU_GSCL2                             28
+
+#define GSCL_NR_CLK                                     29
+
+/* CMU_APOLLO */
+#define CLK_FOUT_APOLLO_PLL                             1
+
+#define CLK_MOUT_APOLLO_PLL                             2
+#define CLK_MOUT_BUS_PLL_APOLLO_USER                    3
+#define CLK_MOUT_APOLLO                                 4
+
+#define CLK_DIV_CNTCLK_APOLLO                           5
+#define CLK_DIV_PCLK_DBG_APOLLO                         6
+#define CLK_DIV_ATCLK_APOLLO                            7
+#define CLK_DIV_PCLK_APOLLO                             8
+#define CLK_DIV_ACLK_APOLLO                             9
+#define CLK_DIV_APOLLO2                                 10
+#define CLK_DIV_APOLLO1                                 11
+#define CLK_DIV_SCLK_HPM_APOLLO                         12
+#define CLK_DIV_APOLLO_PLL                              13
+
+#define CLK_ACLK_ATBDS_APOLLO_3                         14
+#define CLK_ACLK_ATBDS_APOLLO_2                         15
+#define CLK_ACLK_ATBDS_APOLLO_1                         16
+#define CLK_ACLK_ATBDS_APOLLO_0                         17
+#define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS                18
+#define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS                19
+#define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS                20
+#define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS                21
+#define CLK_ACLK_ASYNCACES_APOLLO_CCI                   22
+#define CLK_ACLK_AHB2APB_APOLLOP                        23
+#define CLK_ACLK_APOLLONP_200                           24
+#define CLK_PCLK_ASAPBMST_CSSYS_APOLLO                  25
+#define CLK_PCLK_PMU_APOLLO                             26
+#define CLK_PCLK_SYSREG_APOLLO                          27
+#define CLK_CNTCLK_APOLLO                               28
+#define CLK_SCLK_HPM_APOLLO                             29
+#define CLK_SCLK_APOLLO                                 30
+
+#define APOLLO_NR_CLK                                   31
+
+/* CMU_ATLAS */
+#define CLK_FOUT_ATLAS_PLL                              1
+
+#define CLK_MOUT_ATLAS_PLL                              2
+#define CLK_MOUT_BUS_PLL_ATLAS_USER                     3
+#define CLK_MOUT_ATLAS                                  4
+
+#define CLK_DIV_CNTCLK_ATLAS                            5
+#define CLK_DIV_PCLK_DBG_ATLAS                          6
+#define CLK_DIV_ATCLK_ATLASO                            7
+#define CLK_DIV_PCLK_ATLAS                              8
+#define CLK_DIV_ACLK_ATLAS                              9
+#define CLK_DIV_ATLAS2                                  10
+#define CLK_DIV_ATLAS1                                  11
+#define CLK_DIV_SCLK_HPM_ATLAS                          12
+#define CLK_DIV_ATLAS_PLL                               13
+
+#define CLK_ACLK_ATB_AUD_CSSYS                          14
+#define CLK_ACLK_ATB_APOLLO3_CSSYS                      15
+#define CLK_ACLK_ATB_APOLLO2_CSSYS                      16
+#define CLK_ACLK_ATB_APOLLO1_CSSYS                      17
+#define CLK_ACLK_ATB_APOLLO0_CSSYS                      18
+#define CLK_ACLK_ASYNCAHBS_CSSYS_SSS                    19
+#define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX                   20
+#define CLK_ACLK_ASYNCACES_ATLAS_CCI                    21
+#define CLK_ACLK_AHB2APB_ATLASP                         22
+#define CLK_ACLK_ATLASNP_200                            23
+#define CLK_PCLK_ASYNCAPB_AUD_CSSYS                     24
+#define CLK_PCLK_ASYNCAPB_ISP_CSSYS                     25
+#define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS                  26
+#define CLK_PCLK_PMU_ATLAS                              27
+#define CLK_PCLK_SYSREG_ATLAS                           28
+#define CLK_PCLK_SECJTAG                                29
+#define CLK_CNTCLK_ATLAS                                30
+#define CLK_SCLK_FREQ_DET_ATLAS_PLL                     31
+#define CLK_SCLK_HPM_ATLAS                              32
+#define CLK_TRACECLK                                    33
+#define CLK_CTMCLK                                      34
+#define CLK_HCLK_CSSYS                                  35
+#define CLK_PCLK_DBG_CSSYS                              36
+#define CLK_PCLK_DBG                                    37
+#define CLK_ATCLK                                       38
+#define CLK_SCLK_ATLAS                                  39
+
+#define ATLAS_NR_CLK                                    40
+
+/* CMU_MSCL */
+#define CLK_MOUT_SCLK_JPEG_USER                         1
+#define CLK_MOUT_ACLK_MSCL_400_USER                     2
+#define CLK_MOUT_SCLK_JPEG                              3
+
+#define CLK_DIV_PCLK_MSCL                               4
+
+#define CLK_ACLK_BTS_JPEG                               5
+#define CLK_ACLK_BTS_M2MSCALER1                         6
+#define CLK_ACLK_BTS_M2MSCALER0                         7
+#define CLK_ACLK_AHB2APB_MSCL0P                         8
+#define CLK_ACLK_XIU_MSCLX                              9
+#define CLK_ACLK_MSCLNP_100                             10
+#define CLK_ACLK_MSCLND_400                             11
+#define CLK_ACLK_JPEG                                   12
+#define CLK_ACLK_M2MSCALER1                             13
+#define CLK_ACLK_M2MSCALER0                             14
+#define CLK_ACLK_SMMU_M2MSCALER0                        15
+#define CLK_ACLK_SMMU_M2MSCALER1                        16
+#define CLK_ACLK_SMMU_JPEG                              17
+#define CLK_PCLK_BTS_JPEG                               18
+#define CLK_PCLK_BTS_M2MSCALER1                         19
+#define CLK_PCLK_BTS_M2MSCALER0                         20
+#define CLK_PCLK_PMU_MSCL                               21
+#define CLK_PCLK_SYSREG_MSCL                            22
+#define CLK_PCLK_JPEG                                   23
+#define CLK_PCLK_M2MSCALER1                             24
+#define CLK_PCLK_M2MSCALER0                             25
+#define CLK_PCLK_SMMU_M2MSCALER0                        26
+#define CLK_PCLK_SMMU_M2MSCALER1                        27
+#define CLK_PCLK_SMMU_JPEG                              28
+#define CLK_SCLK_JPEG                                   29
+
+#define MSCL_NR_CLK                                     30
+
+/* CMU_MFC */
+#define CLK_MOUT_ACLK_MFC_400_USER                      1
+
+#define CLK_DIV_PCLK_MFC                                2
+
+#define CLK_ACLK_BTS_MFC_1                              3
+#define CLK_ACLK_BTS_MFC_0                              4
+#define CLK_ACLK_AHB2APB_MFCP                           5
+#define CLK_ACLK_XIU_MFCX                               6
+#define CLK_ACLK_MFCNP_100                              7
+#define CLK_ACLK_MFCND_400                              8
+#define CLK_ACLK_MFC                                    9
+#define CLK_ACLK_SMMU_MFC_1                             10
+#define CLK_ACLK_SMMU_MFC_0                             11
+#define CLK_PCLK_BTS_MFC_1                              12
+#define CLK_PCLK_BTS_MFC_0                              13
+#define CLK_PCLK_PMU_MFC                                14
+#define CLK_PCLK_SYSREG_MFC                             15
+#define CLK_PCLK_MFC                                    16
+#define CLK_PCLK_SMMU_MFC_1                             17
+#define CLK_PCLK_SMMU_MFC_0                             18
+
+#define MFC_NR_CLK                                      19
+
+/* CMU_HEVC */
+#define CLK_MOUT_ACLK_HEVC_400_USER                     1
+
+#define CLK_DIV_PCLK_HEVC                               2
+
+#define CLK_ACLK_BTS_HEVC_1                             3
+#define CLK_ACLK_BTS_HEVC_0                             4
+#define CLK_ACLK_AHB2APB_HEVCP                          5
+#define CLK_ACLK_XIU_HEVCX                              6
+#define CLK_ACLK_HEVCNP_100                             7
+#define CLK_ACLK_HEVCND_400                             8
+#define CLK_ACLK_HEVC                                   9
+#define CLK_ACLK_SMMU_HEVC_1                            10
+#define CLK_ACLK_SMMU_HEVC_0                            11
+#define CLK_PCLK_BTS_HEVC_1                             12
+#define CLK_PCLK_BTS_HEVC_0                             13
+#define CLK_PCLK_PMU_HEVC                               14
+#define CLK_PCLK_SYSREG_HEVC                            15
+#define CLK_PCLK_HEVC                                   16
+#define CLK_PCLK_SMMU_HEVC_1                            17
+#define CLK_PCLK_SMMU_HEVC_0                            18
+
+#define HEVC_NR_CLK                                     19
+
+/* CMU_ISP */
+#define CLK_MOUT_ACLK_ISP_DIS_400_USER                  1
+#define CLK_MOUT_ACLK_ISP_400_USER                      2
+
+#define CLK_DIV_PCLK_ISP_DIS                            3
+#define CLK_DIV_PCLK_ISP                                4
+#define CLK_DIV_ACLK_ISP_D_200                          5
+#define CLK_DIV_ACLK_ISP_C_200                          6
+
+#define CLK_ACLK_ISP_D_GLUE                             7
+#define CLK_ACLK_SCALERP                                8
+#define CLK_ACLK_3DNR                                   9
+#define CLK_ACLK_DIS                                    10
+#define CLK_ACLK_SCALERC                                11
+#define CLK_ACLK_DRC                                    12
+#define CLK_ACLK_ISP                                    13
+#define CLK_ACLK_AXIUS_SCALERP                          14
+#define CLK_ACLK_AXIUS_SCALERC                          15
+#define CLK_ACLK_AXIUS_DRC                              16
+#define CLK_ACLK_ASYNCAHBM_ISP2P                        17
+#define CLK_ACLK_ASYNCAHBM_ISP1P                        18
+#define CLK_ACLK_ASYNCAXIS_DIS1                         19
+#define CLK_ACLK_ASYNCAXIS_DIS0                         20
+#define CLK_ACLK_ASYNCAXIM_DIS1                         21
+#define CLK_ACLK_ASYNCAXIM_DIS0                         22
+#define CLK_ACLK_ASYNCAXIM_ISP2P                        23
+#define CLK_ACLK_ASYNCAXIM_ISP1P                        24
+#define CLK_ACLK_AHB2APB_ISP2P                          25
+#define CLK_ACLK_AHB2APB_ISP1P                          26
+#define CLK_ACLK_AXI2APB_ISP2P                          27
+#define CLK_ACLK_AXI2APB_ISP1P                          28
+#define CLK_ACLK_XIU_ISPEX1                             29
+#define CLK_ACLK_XIU_ISPEX0                             30
+#define CLK_ACLK_ISPND_400                              31
+#define CLK_ACLK_SMMU_SCALERP                           32
+#define CLK_ACLK_SMMU_3DNR                              33
+#define CLK_ACLK_SMMU_DIS1                              34
+#define CLK_ACLK_SMMU_DIS0                              35
+#define CLK_ACLK_SMMU_SCALERC                           36
+#define CLK_ACLK_SMMU_DRC                               37
+#define CLK_ACLK_SMMU_ISP                               38
+#define CLK_ACLK_BTS_SCALERP                            39
+#define CLK_ACLK_BTS_3DR                                40
+#define CLK_ACLK_BTS_DIS1                               41
+#define CLK_ACLK_BTS_DIS0                               42
+#define CLK_ACLK_BTS_SCALERC                            43
+#define CLK_ACLK_BTS_DRC                                44
+#define CLK_ACLK_BTS_ISP                                45
+#define CLK_PCLK_SMMU_SCALERP                           46
+#define CLK_PCLK_SMMU_3DNR                              47
+#define CLK_PCLK_SMMU_DIS1                              48
+#define CLK_PCLK_SMMU_DIS0                              49
+#define CLK_PCLK_SMMU_SCALERC                           50
+#define CLK_PCLK_SMMU_DRC                               51
+#define CLK_PCLK_SMMU_ISP                               52
+#define CLK_PCLK_BTS_SCALERP                            53
+#define CLK_PCLK_BTS_3DNR                               54
+#define CLK_PCLK_BTS_DIS1                               55
+#define CLK_PCLK_BTS_DIS0                               56
+#define CLK_PCLK_BTS_SCALERC                            57
+#define CLK_PCLK_BTS_DRC                                58
+#define CLK_PCLK_BTS_ISP                                59
+#define CLK_PCLK_ASYNCAXI_DIS1                          60
+#define CLK_PCLK_ASYNCAXI_DIS0                          61
+#define CLK_PCLK_PMU_ISP                                62
+#define CLK_PCLK_SYSREG_ISP                             63
+#define CLK_PCLK_CMU_ISP_LOCAL                          64
+#define CLK_PCLK_SCALERP                                65
+#define CLK_PCLK_3DNR                                   66
+#define CLK_PCLK_DIS_CORE                               67
+#define CLK_PCLK_DIS                                    68
+#define CLK_PCLK_SCALERC                                69
+#define CLK_PCLK_DRC                                    70
+#define CLK_PCLK_ISP                                    71
+#define CLK_SCLK_PIXELASYNCS_DIS                        72
+#define CLK_SCLK_PIXELASYNCM_DIS                        73
+#define CLK_SCLK_PIXELASYNCS_SCALERP                    74
+#define CLK_SCLK_PIXELASYNCM_ISPD                       75
+#define CLK_SCLK_PIXELASYNCS_ISPC                       76
+#define CLK_SCLK_PIXELASYNCM_ISPC                       77
+
+#define ISP_NR_CLK                                      78
+
+/* CMU_CAM0 */
+#define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY                 1
+#define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY                2
+
+#define CLK_MOUT_ACLK_CAM0_333_USER                     3
+#define CLK_MOUT_ACLK_CAM0_400_USER                     4
+#define CLK_MOUT_ACLK_CAM0_552_USER                     5
+#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER            6
+#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER           7
+#define CLK_MOUT_ACLK_LITE_D_B                          8
+#define CLK_MOUT_ACLK_LITE_D_A                          9
+#define CLK_MOUT_ACLK_LITE_B_B                          10
+#define CLK_MOUT_ACLK_LITE_B_A                          11
+#define CLK_MOUT_ACLK_LITE_A_B                          12
+#define CLK_MOUT_ACLK_LITE_A_A                          13
+#define CLK_MOUT_ACLK_CAM0_400                          14
+#define CLK_MOUT_ACLK_CSIS1_B                           15
+#define CLK_MOUT_ACLK_CSIS1_A                           16
+#define CLK_MOUT_ACLK_CSIS0_B                           17
+#define CLK_MOUT_ACLK_CSIS0_A                           18
+#define CLK_MOUT_ACLK_3AA1_B                            19
+#define CLK_MOUT_ACLK_3AA1_A                            20
+#define CLK_MOUT_ACLK_3AA0_B                            21
+#define CLK_MOUT_ACLK_3AA0_A                            22
+#define CLK_MOUT_SCLK_LITE_FREECNT_C                    23
+#define CLK_MOUT_SCLK_LITE_FREECNT_B                    24
+#define CLK_MOUT_SCLK_LITE_FREECNT_A                    25
+#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B               26
+#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A               27
+#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B          28
+#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A          29
+
+#define CLK_DIV_PCLK_CAM0_50                            30
+#define CLK_DIV_ACLK_CAM0_200                           31
+#define CLK_DIV_ACLK_CAM0_BUS_400                       32
+#define CLK_DIV_PCLK_LITE_D                             33
+#define CLK_DIV_ACLK_LITE_D                             34
+#define CLK_DIV_PCLK_LITE_B                             35
+#define CLK_DIV_ACLK_LITE_B                             36
+#define CLK_DIV_PCLK_LITE_A                             37
+#define CLK_DIV_ACLK_LITE_A                             38
+#define CLK_DIV_ACLK_CSIS1                              39
+#define CLK_DIV_ACLK_CSIS0                              40
+#define CLK_DIV_PCLK_3AA1                               41
+#define CLK_DIV_ACLK_3AA1                               42
+#define CLK_DIV_PCLK_3AA0                               43
+#define CLK_DIV_ACLK_3AA0                               44
+#define CLK_DIV_SCLK_PIXELASYNC_LITE_C                  45
+#define CLK_DIV_PCLK_PIXELASYNC_LITE_C                  46
+#define CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT             47
+
+#define CLK_ACLK_CSIS1                                  50
+#define CLK_ACLK_CSIS0                                  51
+#define CLK_ACLK_3AA1                                   52
+#define CLK_ACLK_3AA0                                   53
+#define CLK_ACLK_LITE_D                                 54
+#define CLK_ACLK_LITE_B                                 55
+#define CLK_ACLK_LITE_A                                 56
+#define CLK_ACLK_AHBSYNCDN                              57
+#define CLK_ACLK_AXIUS_LITE_D                           58
+#define CLK_ACLK_AXIUS_LITE_B                           59
+#define CLK_ACLK_AXIUS_LITE_A                           60
+#define CLK_ACLK_ASYNCAPBM_3AA1                         61
+#define CLK_ACLK_ASYNCAPBS_3AA1                         62
+#define CLK_ACLK_ASYNCAPBM_3AA0                         63
+#define CLK_ACLK_ASYNCAPBS_3AA0                         64
+#define CLK_ACLK_ASYNCAPBM_LITE_D                       65
+#define CLK_ACLK_ASYNCAPBS_LITE_D                       66
+#define CLK_ACLK_ASYNCAPBM_LITE_B                       67
+#define CLK_ACLK_ASYNCAPBS_LITE_B                       68
+#define CLK_ACLK_ASYNCAPBM_LITE_A                       69
+#define CLK_ACLK_ASYNCAPBS_LITE_A                       70
+#define CLK_ACLK_ASYNCAXIM_ISP0P                        71
+#define CLK_ACLK_ASYNCAXIM_3AA1                         72
+#define CLK_ACLK_ASYNCAXIS_3AA1                         73
+#define CLK_ACLK_ASYNCAXIM_3AA0                         74
+#define CLK_ACLK_ASYNCAXIS_3AA0                         75
+#define CLK_ACLK_ASYNCAXIM_LITE_D                       76
+#define CLK_ACLK_ASYNCAXIS_LITE_D                       77
+#define CLK_ACLK_ASYNCAXIM_LITE_B                       78
+#define CLK_ACLK_ASYNCAXIS_LITE_B                       79
+#define CLK_ACLK_ASYNCAXIM_LITE_A                       80
+#define CLK_ACLK_ASYNCAXIS_LITE_A                       81
+#define CLK_ACLK_AHB2APB_ISPSFRP                        82
+#define CLK_ACLK_AXI2APB_ISP0P                          83
+#define CLK_ACLK_AXI2AHB_ISP0P                          84
+#define CLK_ACLK_XIU_IS0X                               85
+#define CLK_ACLK_XIU_ISP0EX                             86
+#define CLK_ACLK_CAM0NP_276                             87
+#define CLK_ACLK_CAM0ND_400                             88
+#define CLK_ACLK_SMMU_3AA1                              89
+#define CLK_ACLK_SMMU_3AA0                              90
+#define CLK_ACLK_SMMU_LITE_D                            91
+#define CLK_ACLK_SMMU_LITE_B                            92
+#define CLK_ACLK_SMMU_LITE_A                            93
+#define CLK_ACLK_BTS_3AA1                               94
+#define CLK_ACLK_BTS_3AA0                               95
+#define CLK_ACLK_BTS_LITE_D                             96
+#define CLK_ACLK_BTS_LITE_B                             97
+#define CLK_ACLK_BTS_LITE_A                             98
+#define CLK_PCLK_SMMU_3AA1                              99
+#define CLK_PCLK_SMMU_3AA0                              100
+#define CLK_PCLK_SMMU_LITE_D                            101
+#define CLK_PCLK_SMMU_LITE_B                            102
+#define CLK_PCLK_SMMU_LITE_A                            103
+#define CLK_PCLK_BTS_3AA1                               104
+#define CLK_PCLK_BTS_3AA0                               105
+#define CLK_PCLK_BTS_LITE_D                             106
+#define CLK_PCLK_BTS_LITE_B                             107
+#define CLK_PCLK_BTS_LITE_A                             108
+#define CLK_PCLK_ASYNCAXI_CAM1                          109
+#define CLK_PCLK_ASYNCAXI_3AA1                          110
+#define CLK_PCLK_ASYNCAXI_3AA0                          111
+#define CLK_PCLK_ASYNCAXI_LITE_D                        112
+#define CLK_PCLK_ASYNCAXI_LITE_B                        113
+#define CLK_PCLK_ASYNCAXI_LITE_A                        114
+#define CLK_PCLK_PMU_CAM0                               115
+#define CLK_PCLK_SYSREG_CAM0                            116
+#define CLK_PCLK_CMU_CAM0_LOCAL                         117
+#define CLK_PCLK_CSIS1                                  118
+#define CLK_PCLK_CSIS0                                  119
+#define CLK_PCLK_3AA1                                   120
+#define CLK_PCLK_3AA0                                   121
+#define CLK_PCLK_LITE_D                                 122
+#define CLK_PCLK_LITE_B                                 123
+#define CLK_PCLK_LITE_A                                 124
+#define CLK_PHYCLK_RXBYTECLKHS0_S4                      125
+#define CLK_PHYCLK_RXBYTECLKHS0_S2A                     126
+#define CLK_SCLK_LITE_FREECNT                           127
+#define CLK_SCLK_PIXELASYNCM_3AA1                       128
+#define CLK_SCLK_PIXELASYNCM_3AA0                       129
+#define CLK_SCLK_PIXELASYNCS_3AA0                       130
+#define CLK_SCLK_PIXELASYNCM_LITE_C                     131
+#define CLK_SCLK_PIXELASYNCM_LITE_C_INIT                132
+#define CLK_SCLK_PIXELASYNCS_LITE_C_INIT                133
+
+#define CAM0_NR_CLK                                     134
+
+/* CMU_CAM1 */
+#define CLK_PHYCLK_RXBYTEECLKHS0_S2B                    1
+
+#define CLK_MOUT_SCLK_ISP_UART_USER                     2
+#define CLK_MOUT_SCLK_ISP_SPI1_USER                     3
+#define CLK_MOUT_SCLK_ISP_SPI0_USER                     4
+#define CLK_MOUT_ACLK_CAM1_333_USER                     5
+#define CLK_MOUT_ACLK_CAM1_400_USER                     6
+#define CLK_MOUT_ACLK_CAM1_552_USER                     7
+#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER           8
+#define CLK_MOUT_ACLK_CSIS2_B                           9
+#define CLK_MOUT_ACLK_CSIS2_A                           10
+#define CLK_MOUT_ACLK_FD_B                              11
+#define CLK_MOUT_ACLK_FD_A                              12
+#define CLK_MOUT_ACLK_LITE_C_B                          13
+#define CLK_MOUT_ACLK_LITE_C_A                          14
+
+#define CLK_DIV_SCLK_ISP_WPWM                           15
+#define CLK_DIV_PCLK_CAM1_83                            16
+#define CLK_DIV_PCLK_CAM1_166                           17
+#define CLK_DIV_PCLK_DBG_CAM1                           18
+#define CLK_DIV_ATCLK_CAM1                              19
+#define CLK_DIV_ACLK_CSIS2                              20
+#define CLK_DIV_PCLK_FD                                 21
+#define CLK_DIV_ACLK_FD                                 22
+#define CLK_DIV_PCLK_LITE_C                             23
+#define CLK_DIV_ACLK_LITE_C                             24
+
+#define CLK_ACLK_ISP_GIC                                25
+#define CLK_ACLK_FD                                     26
+#define CLK_ACLK_LITE_C                                 27
+#define CLK_ACLK_CSIS2                                  28
+#define CLK_ACLK_ASYNCAPBM_FD                           29
+#define CLK_ACLK_ASYNCAPBS_FD                           30
+#define CLK_ACLK_ASYNCAPBM_LITE_C                       31
+#define CLK_ACLK_ASYNCAPBS_LITE_C                       32
+#define CLK_ACLK_ASYNCAHBS_SFRISP2H2                    33
+#define CLK_ACLK_ASYNCAHBS_SFRISP2H1                    34
+#define CLK_ACLK_ASYNCAXIM_CA5                          35
+#define CLK_ACLK_ASYNCAXIS_CA5                          36
+#define CLK_ACLK_ASYNCAXIS_ISPX2                        37
+#define CLK_ACLK_ASYNCAXIS_ISPX1                        38
+#define CLK_ACLK_ASYNCAXIS_ISPX0                        39
+#define CLK_ACLK_ASYNCAXIM_ISPEX                        40
+#define CLK_ACLK_ASYNCAXIM_ISP3P                        41
+#define CLK_ACLK_ASYNCAXIS_ISP3P                        42
+#define CLK_ACLK_ASYNCAXIM_FD                           43
+#define CLK_ACLK_ASYNCAXIS_FD                           44
+#define CLK_ACLK_ASYNCAXIM_LITE_C                       45
+#define CLK_ACLK_ASYNCAXIS_LITE_C                       46
+#define CLK_ACLK_AHB2APB_ISP5P                          47
+#define CLK_ACLK_AHB2APB_ISP3P                          48
+#define CLK_ACLK_AXI2APB_ISP3P                          49
+#define CLK_ACLK_AHB_SFRISP2H                           50
+#define CLK_ACLK_AXI_ISP_HX_R                           51
+#define CLK_ACLK_AXI_ISP_CX_R                           52
+#define CLK_ACLK_AXI_ISP_HX                             53
+#define CLK_ACLK_AXI_ISP_CX                             54
+#define CLK_ACLK_XIU_ISPX                               55
+#define CLK_ACLK_XIU_ISPEX                              56
+#define CLK_ACLK_CAM1NP_333                             57
+#define CLK_ACLK_CAM1ND_400                             58
+#define CLK_ACLK_SMMU_ISPCPU                            59
+#define CLK_ACLK_SMMU_FD                                60
+#define CLK_ACLK_SMMU_LITE_C                            61
+#define CLK_ACLK_BTS_ISP3P                              62
+#define CLK_ACLK_BTS_FD                                 63
+#define CLK_ACLK_BTS_LITE_C                             64
+#define CLK_ACLK_AHBDN_SFRISP2H                         65
+#define CLK_ACLK_AHBDN_ISP5P                            66
+#define CLK_ACLK_AXIUS_ISP3P                            67
+#define CLK_ACLK_AXIUS_FD                               68
+#define CLK_ACLK_AXIUS_LITE_C                           69
+#define CLK_PCLK_SMMU_ISPCPU                            70
+#define CLK_PCLK_SMMU_FD                                71
+#define CLK_PCLK_SMMU_LITE_C                            72
+#define CLK_PCLK_BTS_ISP3P                              73
+#define CLK_PCLK_BTS_FD                                 74
+#define CLK_PCLK_BTS_LITE_C                             75
+#define CLK_PCLK_ASYNCAXIM_CA5                          76
+#define CLK_PCLK_ASYNCAXIM_ISPEX                        77
+#define CLK_PCLK_ASYNCAXIM_ISP3P                        78
+#define CLK_PCLK_ASYNCAXIM_FD                           79
+#define CLK_PCLK_ASYNCAXIM_LITE_C                       80
+#define CLK_PCLK_PMU_CAM1                               81
+#define CLK_PCLK_SYSREG_CAM1                            82
+#define CLK_PCLK_CMU_CAM1_LOCAL                         83
+#define CLK_PCLK_ISP_MCTADC                             84
+#define CLK_PCLK_ISP_WDT                                85
+#define CLK_PCLK_ISP_PWM                                86
+#define CLK_PCLK_ISP_UART                               87
+#define CLK_PCLK_ISP_MCUCTL                             88
+#define CLK_PCLK_ISP_SPI1                               89
+#define CLK_PCLK_ISP_SPI0                               90
+#define CLK_PCLK_ISP_I2C2                               91
+#define CLK_PCLK_ISP_I2C1                               92
+#define CLK_PCLK_ISP_I2C0                               93
+#define CLK_PCLK_ISP_MPWM                               94
+#define CLK_PCLK_FD                                     95
+#define CLK_PCLK_LITE_C                                 96
+#define CLK_PCLK_CSIS2                                  97
+#define CLK_SCLK_ISP_I2C2                               98
+#define CLK_SCLK_ISP_I2C1                               99
+#define CLK_SCLK_ISP_I2C0                               100
+#define CLK_SCLK_ISP_PWM                                101
+#define CLK_PHYCLK_RXBYTECLKHS0_S2B                     102
+#define CLK_SCLK_LITE_C_FREECNT                         103
+#define CLK_SCLK_PIXELASYNCM_FD                         104
+#define CLK_SCLK_ISP_MCTADC                             105
+#define CLK_SCLK_ISP_UART                               106
+#define CLK_SCLK_ISP_SPI1                               107
+#define CLK_SCLK_ISP_SPI0                               108
+#define CLK_SCLK_ISP_MPWM                               109
+#define CLK_PCLK_DBG_ISP                                110
+#define CLK_ATCLK_ISP                                   111
+#define CLK_SCLK_ISP_CA5                                112
+
+#define CAM1_NR_CLK                                     113
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h b/include/dt-bindings/clock/qcom,gcc-msm8916.h
new file mode 100644
index 000000000000..e430f644dd6c
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8916.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright 2015 Linaro Limited
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8916_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8916_H
+
+#define GPLL0                                   0
+#define GPLL0_VOTE                              1
+#define BIMC_PLL                                2
+#define BIMC_PLL_VOTE                           3
+#define GPLL1                                   4
+#define GPLL1_VOTE                              5
+#define GPLL2                                   6
+#define GPLL2_VOTE                              7
+#define PCNOC_BFDCD_CLK_SRC                     8
+#define SYSTEM_NOC_BFDCD_CLK_SRC                9
+#define CAMSS_AHB_CLK_SRC                       10
+#define APSS_AHB_CLK_SRC                        11
+#define CSI0_CLK_SRC                            12
+#define CSI1_CLK_SRC                            13
+#define GFX3D_CLK_SRC                           14
+#define VFE0_CLK_SRC                            15
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC             16
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC             17
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC             18
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC             19
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC             20
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC             21
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC             22
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC             23
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC             24
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC             25
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC             26
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC             27
+#define BLSP1_UART1_APPS_CLK_SRC                28
+#define BLSP1_UART2_APPS_CLK_SRC                29
+#define CCI_CLK_SRC                             30
+#define CAMSS_GP0_CLK_SRC                       31
+#define CAMSS_GP1_CLK_SRC                       32
+#define JPEG0_CLK_SRC                           33
+#define MCLK0_CLK_SRC                           34
+#define MCLK1_CLK_SRC                           35
+#define CSI0PHYTIMER_CLK_SRC                    36
+#define CSI1PHYTIMER_CLK_SRC                    37
+#define CPP_CLK_SRC                             38
+#define CRYPTO_CLK_SRC                          39
+#define GP1_CLK_SRC                             40
+#define GP2_CLK_SRC                             41
+#define GP3_CLK_SRC                             42
+#define BYTE0_CLK_SRC                           43
+#define ESC0_CLK_SRC                            44
+#define MDP_CLK_SRC                             45
+#define PCLK0_CLK_SRC                           46
+#define VSYNC_CLK_SRC                           47
+#define PDM2_CLK_SRC                            48
+#define SDCC1_APPS_CLK_SRC                      49
+#define SDCC2_APPS_CLK_SRC                      50
+#define APSS_TCU_CLK_SRC                        51
+#define USB_HS_SYSTEM_CLK_SRC                   52
+#define VCODEC0_CLK_SRC                         53
+#define GCC_BLSP1_AHB_CLK                       54
+#define GCC_BLSP1_SLEEP_CLK                     55
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK             56
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK             57
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK             58
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK             59
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK             60
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK             61
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK             62
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK             63
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK             64
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK             65
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK             66
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK             67
+#define GCC_BLSP1_UART1_APPS_CLK                68
+#define GCC_BLSP1_UART2_APPS_CLK                69
+#define GCC_BOOT_ROM_AHB_CLK                    70
+#define GCC_CAMSS_CCI_AHB_CLK                   71
+#define GCC_CAMSS_CCI_CLK                       72
+#define GCC_CAMSS_CSI0_AHB_CLK                  73
+#define GCC_CAMSS_CSI0_CLK                      74
+#define GCC_CAMSS_CSI0PHY_CLK                   75
+#define GCC_CAMSS_CSI0PIX_CLK                   76
+#define GCC_CAMSS_CSI0RDI_CLK                   77
+#define GCC_CAMSS_CSI1_AHB_CLK                  78
+#define GCC_CAMSS_CSI1_CLK                      79
+#define GCC_CAMSS_CSI1PHY_CLK                   80
+#define GCC_CAMSS_CSI1PIX_CLK                   81
+#define GCC_CAMSS_CSI1RDI_CLK                   82
+#define GCC_CAMSS_CSI_VFE0_CLK                  83
+#define GCC_CAMSS_GP0_CLK                       84
+#define GCC_CAMSS_GP1_CLK                       85
+#define GCC_CAMSS_ISPIF_AHB_CLK                 86
+#define GCC_CAMSS_JPEG0_CLK                     87
+#define GCC_CAMSS_JPEG_AHB_CLK                  88
+#define GCC_CAMSS_JPEG_AXI_CLK                  89
+#define GCC_CAMSS_MCLK0_CLK                     90
+#define GCC_CAMSS_MCLK1_CLK                     91
+#define GCC_CAMSS_MICRO_AHB_CLK                 92
+#define GCC_CAMSS_CSI0PHYTIMER_CLK              93
+#define GCC_CAMSS_CSI1PHYTIMER_CLK              94
+#define GCC_CAMSS_AHB_CLK                       95
+#define GCC_CAMSS_TOP_AHB_CLK                   96
+#define GCC_CAMSS_CPP_AHB_CLK                   97
+#define GCC_CAMSS_CPP_CLK                       98
+#define GCC_CAMSS_VFE0_CLK                      99
+#define GCC_CAMSS_VFE_AHB_CLK                   100
+#define GCC_CAMSS_VFE_AXI_CLK                   101
+#define GCC_CRYPTO_AHB_CLK                      102
+#define GCC_CRYPTO_AXI_CLK                      103
+#define GCC_CRYPTO_CLK                          104
+#define GCC_OXILI_GMEM_CLK                      105
+#define GCC_GP1_CLK                             106
+#define GCC_GP2_CLK                             107
+#define GCC_GP3_CLK                             108
+#define GCC_MDSS_AHB_CLK                        109
+#define GCC_MDSS_AXI_CLK                        110
+#define GCC_MDSS_BYTE0_CLK                      111
+#define GCC_MDSS_ESC0_CLK                       112
+#define GCC_MDSS_MDP_CLK                        113
+#define GCC_MDSS_PCLK0_CLK                      114
+#define GCC_MDSS_VSYNC_CLK                      115
+#define GCC_MSS_CFG_AHB_CLK                     116
+#define GCC_OXILI_AHB_CLK                       117
+#define GCC_OXILI_GFX3D_CLK                     118
+#define GCC_PDM2_CLK                            119
+#define GCC_PDM_AHB_CLK                         120
+#define GCC_PRNG_AHB_CLK                        121
+#define GCC_SDCC1_AHB_CLK                       122
+#define GCC_SDCC1_APPS_CLK                      123
+#define GCC_SDCC2_AHB_CLK                       124
+#define GCC_SDCC2_APPS_CLK                      125
+#define GCC_GTCU_AHB_CLK                        126
+#define GCC_JPEG_TBU_CLK                        127
+#define GCC_MDP_TBU_CLK                         128
+#define GCC_SMMU_CFG_CLK                        129
+#define GCC_VENUS_TBU_CLK                       130
+#define GCC_VFE_TBU_CLK                         131
+#define GCC_USB2A_PHY_SLEEP_CLK                 132
+#define GCC_USB_HS_AHB_CLK                      133
+#define GCC_USB_HS_SYSTEM_CLK                   134
+#define GCC_VENUS0_AHB_CLK                      135
+#define GCC_VENUS0_AXI_CLK                      136
+#define GCC_VENUS0_VCODEC0_CLK                  137
+
+#endif
diff --git a/include/dt-bindings/reset/qcom,gcc-msm8916.h b/include/dt-bindings/reset/qcom,gcc-msm8916.h
new file mode 100644
index 000000000000..3d90410f09c7
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,gcc-msm8916.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2015 Linaro Limited
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_MSM_GCC_8916_H
+#define _DT_BINDINGS_RESET_MSM_GCC_8916_H
+
+#define GCC_BLSP1_BCR                   0
+#define GCC_BLSP1_QUP1_BCR              1
+#define GCC_BLSP1_UART1_BCR             2
+#define GCC_BLSP1_QUP2_BCR              3
+#define GCC_BLSP1_UART2_BCR             4
+#define GCC_BLSP1_QUP3_BCR              5
+#define GCC_BLSP1_QUP4_BCR              6
+#define GCC_BLSP1_QUP5_BCR              7
+#define GCC_BLSP1_QUP6_BCR              8
+#define GCC_IMEM_BCR                    9
+#define GCC_SMMU_BCR                    10
+#define GCC_APSS_TCU_BCR                11
+#define GCC_SMMU_XPU_BCR                12
+#define GCC_PCNOC_TBU_BCR               13
+#define GCC_PRNG_BCR                    14
+#define GCC_BOOT_ROM_BCR                15
+#define GCC_CRYPTO_BCR                  16
+#define GCC_SEC_CTRL_BCR                17
+#define GCC_AUDIO_CORE_BCR              18
+#define GCC_ULT_AUDIO_BCR               19
+#define GCC_DEHR_BCR                    20
+#define GCC_SYSTEM_NOC_BCR              21
+#define GCC_PCNOC_BCR                   22
+#define GCC_TCSR_BCR                    23
+#define GCC_QDSS_BCR                    24
+#define GCC_DCD_BCR                     25
+#define GCC_MSG_RAM_BCR                 26
+#define GCC_MPM_BCR                     27
+#define GCC_SPMI_BCR                    28
+#define GCC_SPDM_BCR                    29
+#define GCC_MM_SPDM_BCR                 30
+#define GCC_BIMC_BCR                    31
+#define GCC_RBCPR_BCR                   32
+#define GCC_TLMM_BCR                    33
+#define GCC_USB_HS_BCR                  34
+#define GCC_USB2A_PHY_BCR               35
+#define GCC_SDCC1_BCR                   36
+#define GCC_SDCC2_BCR                   37
+#define GCC_PDM_BCR                     38
+#define GCC_SNOC_BUS_TIMEOUT0_BCR       39
+#define GCC_PCNOC_BUS_TIMEOUT0_BCR      40
+#define GCC_PCNOC_BUS_TIMEOUT1_BCR      41
+#define GCC_PCNOC_BUS_TIMEOUT2_BCR      42
+#define GCC_PCNOC_BUS_TIMEOUT3_BCR      43
+#define GCC_PCNOC_BUS_TIMEOUT4_BCR      44
+#define GCC_PCNOC_BUS_TIMEOUT5_BCR      45
+#define GCC_PCNOC_BUS_TIMEOUT6_BCR      46
+#define GCC_PCNOC_BUS_TIMEOUT7_BCR      47
+#define GCC_PCNOC_BUS_TIMEOUT8_BCR      48
+#define GCC_PCNOC_BUS_TIMEOUT9_BCR      49
+#define GCC_MMSS_BCR                    50
+#define GCC_VENUS0_BCR                  51
+#define GCC_MDSS_BCR                    52
+#define GCC_CAMSS_PHY0_BCR              53
+#define GCC_CAMSS_CSI0_BCR              54
+#define GCC_CAMSS_CSI0PHY_BCR           55
+#define GCC_CAMSS_CSI0RDI_BCR           56
+#define GCC_CAMSS_CSI0PIX_BCR           57
+#define GCC_CAMSS_PHY1_BCR              58
+#define GCC_CAMSS_CSI1_BCR              59
+#define GCC_CAMSS_CSI1PHY_BCR           60
+#define GCC_CAMSS_CSI1RDI_BCR           61
+#define GCC_CAMSS_CSI1PIX_BCR           62
+#define GCC_CAMSS_ISPIF_BCR             63
+#define GCC_CAMSS_CCI_BCR               64
+#define GCC_CAMSS_MCLK0_BCR             65
+#define GCC_CAMSS_MCLK1_BCR             66
+#define GCC_CAMSS_GP0_BCR               67
+#define GCC_CAMSS_GP1_BCR               68
+#define GCC_CAMSS_TOP_BCR               69
+#define GCC_CAMSS_MICRO_BCR             70
+#define GCC_CAMSS_JPEG_BCR              71
+#define GCC_CAMSS_VFE_BCR               72
+#define GCC_CAMSS_CSI_VFE0_BCR          73
+#define GCC_OXILI_BCR                   74
+#define GCC_GMEM_BCR                    75
+#define GCC_CAMSS_AHB_BCR               76
+#define GCC_MDP_TBU_BCR                 77
+#define GCC_GFX_TBU_BCR                 78
+#define GCC_GFX_TCU_BCR                 79
+#define GCC_MSS_TBU_AXI_BCR             80
+#define GCC_MSS_TBU_GSS_AXI_BCR         81
+#define GCC_MSS_TBU_Q6_AXI_BCR          82
+#define GCC_GTCU_AHB_BCR                83
+#define GCC_SMMU_CFG_BCR                84
+#define GCC_VFE_TBU_BCR                 85
+#define GCC_VENUS_TBU_BCR               86
+#define GCC_JPEG_TBU_BCR                87
+#define GCC_PRONTO_TBU_BCR              88
+#define GCC_SMMU_CATS_BCR               89
+
+#endif
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 8381bbfbc308..68c16a6bedb3 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -125,6 +125,19 @@ int clk_set_phase(struct clk *clk, int degrees);
  */
 int clk_get_phase(struct clk *clk);
 
+/**
+ * clk_is_match - check if two clk's point to the same hardware clock
+ * @p: clk compared against q
+ * @q: clk compared against p
+ *
+ * Returns true if the two struct clk pointers both point to the same hardware
+ * clock node. Put differently, returns true if struct clk *p and struct clk *q
+ * share the same struct clk_core object.
+ *
+ * Returns false otherwise. Note that two NULL clks are treated as matching.
+ */
+bool clk_is_match(const struct clk *p, const struct clk *q);
+
 #else
 
 static inline long clk_get_accuracy(struct clk *clk)
@@ -142,6 +155,11 @@ static inline long clk_get_phase(struct clk *clk)
         return -ENOTSUPP;
 }
 
+static inline bool clk_is_match(const struct clk *p, const struct clk *q)
+{
+        return p == q;
+}
+
 #endif
 
 /**
diff --git a/include/trace/events/clk.h b/include/trace/events/clk.h
new file mode 100644
index 000000000000..758607226bfd
--- /dev/null
+++ b/include/trace/events/clk.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM clk
+
+#if !defined(_TRACE_CLK_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_CLK_H
+
+#include <linux/tracepoint.h>
+
+struct clk_core;
+
+DECLARE_EVENT_CLASS(clk,
+
+        TP_PROTO(struct clk_core *core),
+
+        TP_ARGS(core),
+
+        TP_STRUCT__entry(
+                __string(        name,           core->name       )
+        ),
+
+        TP_fast_assign(
+                __assign_str(name, core->name);
+        ),
+
+        TP_printk("%s", __get_str(name))
+);
+
+DEFINE_EVENT(clk, clk_enable,
+
+        TP_PROTO(struct clk_core *core),
+
+        TP_ARGS(core)
+);
+
+DEFINE_EVENT(clk, clk_enable_complete,
+
+        TP_PROTO(struct clk_core *core),
+
+        TP_ARGS(core)
+);
+
+DEFINE_EVENT(clk, clk_disable,
+
+        TP_PROTO(struct clk_core *core),
+
+        TP_ARGS(core)
+);
+
+DEFINE_EVENT(clk, clk_disable_complete,
+
+        TP_PROTO(struct clk_core *core),
+
+        TP_ARGS(core)
+);
+
+DEFINE_EVENT(clk, clk_prepare,
+
+        TP_PROTO(struct clk_core *core),
+
+        TP_ARGS(core)
+);
+
+DEFINE_EVENT(clk, clk_prepare_complete,
+
+        TP_PROTO(struct clk_core *core),
+
+        TP_ARGS(core)
+);
+
+DEFINE_EVENT(clk, clk_unprepare,
+
+        TP_PROTO(struct clk_core *core),
+
+        TP_ARGS(core)
+);
+
+DEFINE_EVENT(clk, clk_unprepare_complete,
+
+        TP_PROTO(struct clk_core *core),
+
+        TP_ARGS(core)
+);
+
+DECLARE_EVENT_CLASS(clk_rate,
+
+        TP_PROTO(struct clk_core *core, unsigned long rate),
+
+        TP_ARGS(core, rate),
+
+        TP_STRUCT__entry(
+                __string(        name,           core->name                )
+                __field(unsigned long,           rate                      )
+        ),
+
+        TP_fast_assign(
+                __assign_str(name, core->name);
+                __entry->rate = rate;
+        ),
+
+        TP_printk("%s %lu", __get_str(name), (unsigned long)__entry->rate)
+);
+
+DEFINE_EVENT(clk_rate, clk_set_rate,
+
+        TP_PROTO(struct clk_core *core, unsigned long rate),
+
+        TP_ARGS(core, rate)
+);
+
+DEFINE_EVENT(clk_rate, clk_set_rate_complete,
+
+        TP_PROTO(struct clk_core *core, unsigned long rate),
+
+        TP_ARGS(core, rate)
+);
+
+DECLARE_EVENT_CLASS(clk_parent,
+
+        TP_PROTO(struct clk_core *core, struct clk_core *parent),
+
+        TP_ARGS(core, parent),
+
+        TP_STRUCT__entry(
+                __string(        name,           core->name                )
+                __string(        pname,          parent->name              )
+        ),
+
+        TP_fast_assign(
+                __assign_str(name, core->name);
+                __assign_str(pname, parent->name);
+        ),
+
+        TP_printk("%s %s", __get_str(name), __get_str(pname))
+);
+
+DEFINE_EVENT(clk_parent, clk_set_parent,
+
+        TP_PROTO(struct clk_core *core, struct clk_core *parent),
+
+        TP_ARGS(core, parent)
+);
+
+DEFINE_EVENT(clk_parent, clk_set_parent_complete,
+
+        TP_PROTO(struct clk_core *core, struct clk_core *parent),
+
+        TP_ARGS(core, parent)
+);
+
+DECLARE_EVENT_CLASS(clk_phase,
+
+        TP_PROTO(struct clk_core *core, int phase),
+
+        TP_ARGS(core, phase),
+
+        TP_STRUCT__entry(
+                __string(        name,           core->name                )
+                __field(          int,           phase                     )
+        ),
+
+        TP_fast_assign(
+                __assign_str(name, core->name);
+                __entry->phase = phase;
+        ),
+
+        TP_printk("%s %d", __get_str(name), (int)__entry->phase)
+);
+
+DEFINE_EVENT(clk_phase, clk_set_phase,
+
+        TP_PROTO(struct clk_core *core, int phase),
+
+        TP_ARGS(core, phase)
+);
+
+DEFINE_EVENT(clk_phase, clk_set_phase_complete,
+
+        TP_PROTO(struct clk_core *core, int phase),
+
+        TP_ARGS(core, phase)
+);
+
+#endif /* _TRACE_CLK_H */
+
+/* This part must be outside protection */
+#include <trace/define_trace.h>
diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
index 75870c0ea2c9..91eb3aef7f02 100644
--- a/sound/soc/fsl/fsl_spdif.c
+++ b/sound/soc/fsl/fsl_spdif.c
@@ -1049,7 +1049,7 @@ static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
                                 enum spdif_txrate index, bool round)
 {
         const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 };
-        bool is_sysclk = clk == spdif_priv->sysclk;
+        bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk);
         u64 rate_ideal, rate_actual, sub;
         u32 sysclk_dfmin, sysclk_dfmax;
         u32 txclk_df, sysclk_df, arate;
@@ -1143,7 +1143,7 @@ static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
                         spdif_priv->txclk_src[index], rate[index]);
         dev_dbg(&pdev->dev, "use txclk df %d for %dHz sample rate\n",
                         spdif_priv->txclk_df[index], rate[index]);
-        if (spdif_priv->txclk[index] == spdif_priv->sysclk)
+        if (clk_is_match(spdif_priv->txclk[index], spdif_priv->sysclk))
                 dev_dbg(&pdev->dev, "use sysclk df %d for %dHz sample rate\n",
                                 spdif_priv->sysclk_df[index], rate[index]);
         dev_dbg(&pdev->dev, "the best rate for %dHz sample rate is %dHz\n",
diff --git a/sound/soc/kirkwood/kirkwood-i2s.c b/sound/soc/kirkwood/kirkwood-i2s.c
index def7d8260c4e..d19483081f9b 100644
--- a/sound/soc/kirkwood/kirkwood-i2s.c
+++ b/sound/soc/kirkwood/kirkwood-i2s.c
@@ -579,7 +579,7 @@ static int kirkwood_i2s_dev_probe(struct platform_device *pdev)
                 if (PTR_ERR(priv->extclk) == -EPROBE_DEFER)
                         return -EPROBE_DEFER;
         } else {
-                if (priv->extclk == priv->clk) {
+                if (clk_is_match(priv->extclk, priv->clk)) {
                         devm_clk_put(&pdev->dev, priv->extclk);
                         priv->extclk = ERR_PTR(-EINVAL);
                 } else {