aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--drivers/gpu/drm/i915/intel_display.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5ccd18f62e43..b1de6cb74803 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7298,7 +7298,7 @@ void intel_enable_clock_gating(struct drm_device *dev)
7298 _3D_CHICKEN2_WM_READ_PIPELINED); 7298 _3D_CHICKEN2_WM_READ_PIPELINED);
7299 } 7299 }
7300 7300
7301 if (IS_GEN6(dev)) { 7301 if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
7302 I915_WRITE(WM3_LP_ILK, 0); 7302 I915_WRITE(WM3_LP_ILK, 0);
7303 I915_WRITE(WM2_LP_ILK, 0); 7303 I915_WRITE(WM2_LP_ILK, 0);
7304 I915_WRITE(WM1_LP_ILK, 0); 7304 I915_WRITE(WM1_LP_ILK, 0);
@@ -7560,6 +7560,13 @@ static void intel_init_display(struct drm_device *dev)
7560 } else if (IS_IVYBRIDGE(dev)) { 7560 } else if (IS_IVYBRIDGE(dev)) {
7561 /* FIXME: detect B0+ stepping and use auto training */ 7561 /* FIXME: detect B0+ stepping and use auto training */
7562 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; 7562 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7563 if (SNB_READ_WM0_LATENCY()) {
7564 dev_priv->display.update_wm = sandybridge_update_wm;
7565 } else {
7566 DRM_DEBUG_KMS("Failed to read display plane latency. "
7567 "Disable CxSR\n");
7568 dev_priv->display.update_wm = NULL;
7569 }
7563 } else 7570 } else
7564 dev_priv->display.update_wm = NULL; 7571 dev_priv->display.update_wm = NULL;
7565 } else if (IS_PINEVIEW(dev)) { 7572 } else if (IS_PINEVIEW(dev)) {