diff options
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 147 |
1 files changed, 75 insertions, 72 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index c7554f057366..0e8af6309160 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h | |||
| @@ -111,66 +111,6 @@ | |||
| 111 | */ | 111 | */ |
| 112 | #define CP0_TX39_CACHE $7 | 112 | #define CP0_TX39_CACHE $7 |
| 113 | 113 | ||
| 114 | /* | ||
| 115 | * Coprocessor 1 (FPU) register names | ||
| 116 | */ | ||
| 117 | #define CP1_REVISION $0 | ||
| 118 | #define CP1_STATUS $31 | ||
| 119 | |||
| 120 | /* | ||
| 121 | * FPU Status Register Values | ||
| 122 | */ | ||
| 123 | #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ | ||
| 124 | #define FPU_CSR_COND 0x00800000 /* $fcc0 */ | ||
| 125 | #define FPU_CSR_COND0 0x00800000 /* $fcc0 */ | ||
| 126 | #define FPU_CSR_COND1 0x02000000 /* $fcc1 */ | ||
| 127 | #define FPU_CSR_COND2 0x04000000 /* $fcc2 */ | ||
| 128 | #define FPU_CSR_COND3 0x08000000 /* $fcc3 */ | ||
| 129 | #define FPU_CSR_COND4 0x10000000 /* $fcc4 */ | ||
| 130 | #define FPU_CSR_COND5 0x20000000 /* $fcc5 */ | ||
| 131 | #define FPU_CSR_COND6 0x40000000 /* $fcc6 */ | ||
| 132 | #define FPU_CSR_COND7 0x80000000 /* $fcc7 */ | ||
| 133 | |||
| 134 | /* | ||
| 135 | * Bits 18 - 20 of the FPU Status Register will be read as 0, | ||
| 136 | * and should be written as zero. | ||
| 137 | */ | ||
| 138 | #define FPU_CSR_RSVD 0x001c0000 | ||
| 139 | |||
| 140 | /* | ||
| 141 | * X the exception cause indicator | ||
| 142 | * E the exception enable | ||
| 143 | * S the sticky/flag bit | ||
| 144 | */ | ||
| 145 | #define FPU_CSR_ALL_X 0x0003f000 | ||
| 146 | #define FPU_CSR_UNI_X 0x00020000 | ||
| 147 | #define FPU_CSR_INV_X 0x00010000 | ||
| 148 | #define FPU_CSR_DIV_X 0x00008000 | ||
| 149 | #define FPU_CSR_OVF_X 0x00004000 | ||
| 150 | #define FPU_CSR_UDF_X 0x00002000 | ||
| 151 | #define FPU_CSR_INE_X 0x00001000 | ||
| 152 | |||
| 153 | #define FPU_CSR_ALL_E 0x00000f80 | ||
| 154 | #define FPU_CSR_INV_E 0x00000800 | ||
| 155 | #define FPU_CSR_DIV_E 0x00000400 | ||
| 156 | #define FPU_CSR_OVF_E 0x00000200 | ||
| 157 | #define FPU_CSR_UDF_E 0x00000100 | ||
| 158 | #define FPU_CSR_INE_E 0x00000080 | ||
| 159 | |||
| 160 | #define FPU_CSR_ALL_S 0x0000007c | ||
| 161 | #define FPU_CSR_INV_S 0x00000040 | ||
| 162 | #define FPU_CSR_DIV_S 0x00000020 | ||
| 163 | #define FPU_CSR_OVF_S 0x00000010 | ||
| 164 | #define FPU_CSR_UDF_S 0x00000008 | ||
| 165 | #define FPU_CSR_INE_S 0x00000004 | ||
| 166 | |||
| 167 | /* Bits 0 and 1 of FPU Status Register specify the rounding mode */ | ||
| 168 | #define FPU_CSR_RM 0x00000003 | ||
| 169 | #define FPU_CSR_RN 0x0 /* nearest */ | ||
| 170 | #define FPU_CSR_RZ 0x1 /* towards zero */ | ||
| 171 | #define FPU_CSR_RU 0x2 /* towards +Infinity */ | ||
| 172 | #define FPU_CSR_RD 0x3 /* towards -Infinity */ | ||
| 173 | |||
| 174 | 114 | ||
| 175 | /* | 115 | /* |
| 176 | * Values for PageMask register | 116 | * Values for PageMask register |
| @@ -687,18 +627,6 @@ | |||
| 687 | #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1)) | 627 | #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1)) |
| 688 | 628 | ||
| 689 | /* | 629 | /* |
| 690 | * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. | ||
| 691 | */ | ||
| 692 | #define MIPS_FPIR_S (_ULCAST_(1) << 16) | ||
| 693 | #define MIPS_FPIR_D (_ULCAST_(1) << 17) | ||
| 694 | #define MIPS_FPIR_PS (_ULCAST_(1) << 18) | ||
| 695 | #define MIPS_FPIR_3D (_ULCAST_(1) << 19) | ||
| 696 | #define MIPS_FPIR_W (_ULCAST_(1) << 20) | ||
| 697 | #define MIPS_FPIR_L (_ULCAST_(1) << 21) | ||
| 698 | #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) | ||
| 699 | #define MIPS_FPIR_FREP (_ULCAST_(1) << 29) | ||
| 700 | |||
| 701 | /* | ||
| 702 | * Bits in the MIPS32 Memory Segmentation registers. | 630 | * Bits in the MIPS32 Memory Segmentation registers. |
| 703 | */ | 631 | */ |
| 704 | #define MIPS_SEGCFG_PA_SHIFT 9 | 632 | #define MIPS_SEGCFG_PA_SHIFT 9 |
| @@ -757,6 +685,81 @@ | |||
| 757 | #define MIPS_CDMMBASE_ADDR_SHIFT 11 | 685 | #define MIPS_CDMMBASE_ADDR_SHIFT 11 |
| 758 | #define MIPS_CDMMBASE_ADDR_START 15 | 686 | #define MIPS_CDMMBASE_ADDR_START 15 |
| 759 | 687 | ||
| 688 | |||
| 689 | /* | ||
| 690 | * Coprocessor 1 (FPU) register names | ||
| 691 | */ | ||
| 692 | #define CP1_REVISION $0 | ||
| 693 | #define CP1_STATUS $31 | ||
| 694 | |||
| 695 | |||
| 696 | /* | ||
| 697 | * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. | ||
| 698 | */ | ||
| 699 | #define MIPS_FPIR_S (_ULCAST_(1) << 16) | ||
| 700 | #define MIPS_FPIR_D (_ULCAST_(1) << 17) | ||
| 701 | #define MIPS_FPIR_PS (_ULCAST_(1) << 18) | ||
| 702 | #define MIPS_FPIR_3D (_ULCAST_(1) << 19) | ||
| 703 | #define MIPS_FPIR_W (_ULCAST_(1) << 20) | ||
| 704 | #define MIPS_FPIR_L (_ULCAST_(1) << 21) | ||
| 705 | #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) | ||
| 706 | #define MIPS_FPIR_FREP (_ULCAST_(1) << 29) | ||
| 707 | |||
| 708 | /* | ||
| 709 | * FPU Status Register Values | ||
| 710 | */ | ||
| 711 | #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ | ||
| 712 | #define FPU_CSR_COND 0x00800000 /* $fcc0 */ | ||
| 713 | #define FPU_CSR_COND0 0x00800000 /* $fcc0 */ | ||
| 714 | #define FPU_CSR_COND1 0x02000000 /* $fcc1 */ | ||
| 715 | #define FPU_CSR_COND2 0x04000000 /* $fcc2 */ | ||
| 716 | #define FPU_CSR_COND3 0x08000000 /* $fcc3 */ | ||
| 717 | #define FPU_CSR_COND4 0x10000000 /* $fcc4 */ | ||
| 718 | #define FPU_CSR_COND5 0x20000000 /* $fcc5 */ | ||
| 719 | #define FPU_CSR_COND6 0x40000000 /* $fcc6 */ | ||
| 720 | #define FPU_CSR_COND7 0x80000000 /* $fcc7 */ | ||
| 721 | |||
| 722 | /* | ||
| 723 | * Bits 18 - 20 of the FPU Status Register will be read as 0, | ||
| 724 | * and should be written as zero. | ||
| 725 | */ | ||
| 726 | #define FPU_CSR_RSVD 0x001c0000 | ||
| 727 | |||
| 728 | /* | ||
| 729 | * X the exception cause indicator | ||
| 730 | * E the exception enable | ||
| 731 | * S the sticky/flag bit | ||
| 732 | */ | ||
| 733 | #define FPU_CSR_ALL_X 0x0003f000 | ||
| 734 | #define FPU_CSR_UNI_X 0x00020000 | ||
| 735 | #define FPU_CSR_INV_X 0x00010000 | ||
| 736 | #define FPU_CSR_DIV_X 0x00008000 | ||
| 737 | #define FPU_CSR_OVF_X 0x00004000 | ||
| 738 | #define FPU_CSR_UDF_X 0x00002000 | ||
| 739 | #define FPU_CSR_INE_X 0x00001000 | ||
| 740 | |||
| 741 | #define FPU_CSR_ALL_E 0x00000f80 | ||
| 742 | #define FPU_CSR_INV_E 0x00000800 | ||
| 743 | #define FPU_CSR_DIV_E 0x00000400 | ||
| 744 | #define FPU_CSR_OVF_E 0x00000200 | ||
| 745 | #define FPU_CSR_UDF_E 0x00000100 | ||
| 746 | #define FPU_CSR_INE_E 0x00000080 | ||
| 747 | |||
| 748 | #define FPU_CSR_ALL_S 0x0000007c | ||
| 749 | #define FPU_CSR_INV_S 0x00000040 | ||
| 750 | #define FPU_CSR_DIV_S 0x00000020 | ||
| 751 | #define FPU_CSR_OVF_S 0x00000010 | ||
| 752 | #define FPU_CSR_UDF_S 0x00000008 | ||
| 753 | #define FPU_CSR_INE_S 0x00000004 | ||
| 754 | |||
| 755 | /* Bits 0 and 1 of FPU Status Register specify the rounding mode */ | ||
| 756 | #define FPU_CSR_RM 0x00000003 | ||
| 757 | #define FPU_CSR_RN 0x0 /* nearest */ | ||
| 758 | #define FPU_CSR_RZ 0x1 /* towards zero */ | ||
| 759 | #define FPU_CSR_RU 0x2 /* towards +Infinity */ | ||
| 760 | #define FPU_CSR_RD 0x3 /* towards -Infinity */ | ||
| 761 | |||
| 762 | |||
| 760 | #ifndef __ASSEMBLY__ | 763 | #ifndef __ASSEMBLY__ |
| 761 | 764 | ||
| 762 | /* | 765 | /* |