diff options
| -rw-r--r-- | arch/arm/boot/dts/sunxi.dtsi | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi index acf7777cf61f..dfbb98bbc4c2 100644 --- a/arch/arm/boot/dts/sunxi.dtsi +++ b/arch/arm/boot/dts/sunxi.dtsi | |||
| @@ -47,7 +47,7 @@ | |||
| 47 | 47 | ||
| 48 | osc24M: osc24M@01c20050 { | 48 | osc24M: osc24M@01c20050 { |
| 49 | #clock-cells = <0>; | 49 | #clock-cells = <0>; |
| 50 | compatible = "allwinner,sunxi-osc-clk"; | 50 | compatible = "allwinner,sun4i-osc-clk"; |
| 51 | reg = <0x01c20050 0x4>; | 51 | reg = <0x01c20050 0x4>; |
| 52 | clocks = <&osc24M_fixed>; | 52 | clocks = <&osc24M_fixed>; |
| 53 | }; | 53 | }; |
| @@ -60,7 +60,7 @@ | |||
| 60 | 60 | ||
| 61 | pll1: pll1@01c20000 { | 61 | pll1: pll1@01c20000 { |
| 62 | #clock-cells = <0>; | 62 | #clock-cells = <0>; |
| 63 | compatible = "allwinner,sunxi-pll1-clk"; | 63 | compatible = "allwinner,sun4i-pll1-clk"; |
| 64 | reg = <0x01c20000 0x4>; | 64 | reg = <0x01c20000 0x4>; |
| 65 | clocks = <&osc24M>; | 65 | clocks = <&osc24M>; |
| 66 | }; | 66 | }; |
| @@ -68,28 +68,28 @@ | |||
| 68 | /* dummy is 200M */ | 68 | /* dummy is 200M */ |
| 69 | cpu: cpu@01c20054 { | 69 | cpu: cpu@01c20054 { |
| 70 | #clock-cells = <0>; | 70 | #clock-cells = <0>; |
| 71 | compatible = "allwinner,sunxi-cpu-clk"; | 71 | compatible = "allwinner,sun4i-cpu-clk"; |
| 72 | reg = <0x01c20054 0x4>; | 72 | reg = <0x01c20054 0x4>; |
| 73 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | 73 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; |
| 74 | }; | 74 | }; |
| 75 | 75 | ||
| 76 | axi: axi@01c20054 { | 76 | axi: axi@01c20054 { |
| 77 | #clock-cells = <0>; | 77 | #clock-cells = <0>; |
| 78 | compatible = "allwinner,sunxi-axi-clk"; | 78 | compatible = "allwinner,sun4i-axi-clk"; |
| 79 | reg = <0x01c20054 0x4>; | 79 | reg = <0x01c20054 0x4>; |
| 80 | clocks = <&cpu>; | 80 | clocks = <&cpu>; |
| 81 | }; | 81 | }; |
| 82 | 82 | ||
| 83 | ahb: ahb@01c20054 { | 83 | ahb: ahb@01c20054 { |
| 84 | #clock-cells = <0>; | 84 | #clock-cells = <0>; |
| 85 | compatible = "allwinner,sunxi-ahb-clk"; | 85 | compatible = "allwinner,sun4i-ahb-clk"; |
| 86 | reg = <0x01c20054 0x4>; | 86 | reg = <0x01c20054 0x4>; |
| 87 | clocks = <&axi>; | 87 | clocks = <&axi>; |
| 88 | }; | 88 | }; |
| 89 | 89 | ||
| 90 | apb0: apb0@01c20054 { | 90 | apb0: apb0@01c20054 { |
| 91 | #clock-cells = <0>; | 91 | #clock-cells = <0>; |
| 92 | compatible = "allwinner,sunxi-apb0-clk"; | 92 | compatible = "allwinner,sun4i-apb0-clk"; |
| 93 | reg = <0x01c20054 0x4>; | 93 | reg = <0x01c20054 0x4>; |
| 94 | clocks = <&ahb>; | 94 | clocks = <&ahb>; |
| 95 | }; | 95 | }; |
| @@ -97,14 +97,14 @@ | |||
| 97 | /* dummy is pll62 */ | 97 | /* dummy is pll62 */ |
| 98 | apb1_mux: apb1_mux@01c20058 { | 98 | apb1_mux: apb1_mux@01c20058 { |
| 99 | #clock-cells = <0>; | 99 | #clock-cells = <0>; |
| 100 | compatible = "allwinner,sunxi-apb1-mux-clk"; | 100 | compatible = "allwinner,sun4i-apb1-mux-clk"; |
| 101 | reg = <0x01c20058 0x4>; | 101 | reg = <0x01c20058 0x4>; |
| 102 | clocks = <&osc24M>, <&dummy>, <&osc32k>; | 102 | clocks = <&osc24M>, <&dummy>, <&osc32k>; |
| 103 | }; | 103 | }; |
| 104 | 104 | ||
| 105 | apb1: apb1@01c20058 { | 105 | apb1: apb1@01c20058 { |
| 106 | #clock-cells = <0>; | 106 | #clock-cells = <0>; |
| 107 | compatible = "allwinner,sunxi-apb1-clk"; | 107 | compatible = "allwinner,sun4i-apb1-clk"; |
| 108 | reg = <0x01c20058 0x4>; | 108 | reg = <0x01c20058 0x4>; |
| 109 | clocks = <&apb1_mux>; | 109 | clocks = <&apb1_mux>; |
| 110 | }; | 110 | }; |