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-rw-r--r--arch/x86/kernel/cpu/perf_event_amd_ibs.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_amd_ibs.c b/arch/x86/kernel/cpu/perf_event_amd_ibs.c
index b14e71127c82..5a9f95b5cc26 100644
--- a/arch/x86/kernel/cpu/perf_event_amd_ibs.c
+++ b/arch/x86/kernel/cpu/perf_event_amd_ibs.c
@@ -473,11 +473,13 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
473 u64 *buf, *config, period; 473 u64 *buf, *config, period;
474 474
475 if (!test_bit(IBS_STARTED, pcpu->state)) { 475 if (!test_bit(IBS_STARTED, pcpu->state)) {
476 /* Catch spurious interrupts after stopping IBS: */ 476 /*
477 if (!test_and_clear_bit(IBS_STOPPING, pcpu->state)) 477 * Catch spurious interrupts after stopping IBS: After
478 return 0; 478 * disabling IBS there could be still incomming NMIs
479 rdmsrl(perf_ibs->msr, *ibs_data.regs); 479 * with samples that even have the valid bit cleared.
480 return (*ibs_data.regs & perf_ibs->valid_mask) ? 1 : 0; 480 * Mark all this NMIs as handled.
481 */
482 return test_and_clear_bit(IBS_STOPPING, pcpu->state) ? 1 : 0;
481 } 483 }
482 484
483 msr = hwc->config_base; 485 msr = hwc->config_base;